WO2020093265A1

WO2020093265A1 - Wafer, smart processor, and electrical device

Info

Publication number: WO2020093265A1
Application number: PCT/CN2018/114351
Authority: WO
Inventors: 杨帅; 郭函
Original assignee: 北京比特大陆科技有限公司
Priority date: 2018-11-07
Filing date: 2018-11-07
Publication date: 2020-05-14

Abstract

Provided are a wafer (10), a smart processor, and an electrical device; the wafer (10) has a first power supply region (101) and a second power supply region (102) arranged at intervals; the first power supply region (101) comprises a first solder pad (1011) and a second solder pad (1012); the second power supply region (102) comprises a second solder pad (1021) and a third solder pad (1022); the first solder pad (1011) in the first power supply region (101) is used as a power input terminal; the second solder pad (1012) in the first power supply region (101) is connected to the second solder pad (1021) in the second power supply region (102); the third solder pad (1022) in the second power supply region (102) is used as a ground terminal of the second power supply region (102); it is necessary only to use the first solder pad (1011) in the first power supply region (101) as a power input terminal and use the third solder pad (1022) in the second power supply region (102) as a ground terminal to supply power to the wafer (10); the arrangement described above reduces the number of solder pads connected to solder balls on a substrate (20), thus decreasing the number of solder balls on the substrate (20), simplifying the structure of the substrate and reducing production cost.

Description

Wafers, intelligent processors and electrical equipment

Technical field

This application relates to the field of electrical equipment, for example, to a wafer, intelligent processor and electrical equipment.

Background technique

The electrical equipment has a circuit board and an intelligent processor installed on the circuit board. The intelligent processor is electrically connected to the circuit on the circuit board.

In the prior art, an intelligent processor includes a wafer and a substrate. The wafer has a first power supply area and a second power supply area spaced apart. Each of the first power supply area and the second power supply area has a plurality of pads, and each A pad is electrically connected to a solder ball on the substrate; the substrate is connected to the circuit board, and the solder ball on the substrate is electrically connected to the circuit on the circuit board to realize the connection between the intelligent processor and the circuit board.

However, there are more pads on the wafer, which results in more solder balls connected to the pads on the substrate, resulting in a complicated structure of the intelligent processor and high production cost.

Summary of the invention

An embodiment of the present disclosure provides a wafer having a first power supply area and a second power supply area spaced apart, the first power supply area includes a first pad and a second pad, the first The second power supply area includes a second pad and a third pad. The first pad in the first power supply area serves as a power input terminal to supply power to the internal components of the first power supply area. Is connected to the second pad in the second power supply area, and the third pad in the second power supply area serves as the ground terminal of the second power supply area; the first power supply area Of the first pad is greater than the potential of the second pad in the first power supply area, and the potential of the second pad in the second power supply area is greater than the third pad in the second power supply area Electric potential.

For the wafer as described above, preferably, the wafer further includes a third power supply area, the third power supply area includes a third pad and a fourth pad, and the third pad in the third power supply area It is connected to the third pad in the second power supply area, the fourth pad in the third power supply area serves as a ground terminal, and the potential of the third pad in the third power supply area is greater than that of the third power supply The potential of the fourth pad in the area.

For the wafer as described above, preferably, the second power supply area is provided between the first power supply area and the third power supply area.

In the wafer as described above, preferably, the first power supply area includes at least a plurality of first pads and second pads, and the first pads in the plurality of first power supply areas are arranged parallel to each other A plurality of first vertical columns, and the second pads in the plurality of first power supply areas are arranged into a plurality of second vertical columns parallel to each other.

In the wafer as described above, preferably, the first vertical columns and the second vertical columns are alternately arranged.

In the wafer as described above, preferably, the second power supply area includes at least a plurality of second pads and third pads, and the second pads in the plurality of second power supply areas are arranged parallel to each other A plurality of third vertical columns, a plurality of third pads in the second power supply area are arranged into a plurality of parallel fourth vertical columns, and the third vertical columns and the fourth vertical columns are alternately arranged And each of the third vertical columns and one of the second vertical columns are arranged collinearly.

The wafer as described above, preferably, the wafer further includes a third power supply area, the third power supply area includes a plurality of third pads and a plurality of fourth pads; a plurality of the third power supply areas The third pads in the array are arranged in a plurality of fifth vertical columns parallel to each other, and the fourth pads in the plurality of third power supply areas are arranged in a plurality of sixth vertical columns parallel to each other, the fifth vertical columns It is alternately arranged with the sixth vertical column, and each fifth vertical column is arranged collinearly with one fourth vertical column.

For the wafer as described above, preferably, the internal components in the first power supply area, the internal components in the second power supply area, and the internal components in the third power supply include multiple computing cores.

For the wafer as described above, preferably, the second pad in the first power supply area serves as the ground terminal of the first power supply area, and the second pad in the second power supply area serves as the second Power input of the power supply area.

In the wafer as described above, preferably, the third pad in the second power supply area serves as the ground terminal of the second power supply area, and the third pad in the third power supply area serves as the third Power input of the power supply area.

An embodiment of the present disclosure also provides an intelligent processor, including a wafer, with a first power supply area and a second power supply area spaced apart on the wafer, the first power supply area including a first pad and a second solder Plate, the second power supply area includes a second pad and a third pad, and the first pad in the first power supply area serves as a power input terminal to supply power to the internal components of the first power supply area, the The second pad in the first power supply area is connected to the second pad in the second power supply area, and the third pad in the second power supply area serves as the ground terminal of the second power supply area; The potential of the first pad in the first power supply area is greater than the potential of the second pad in the first power supply area, and the potential of the second pad in the second power supply area is greater than the second power supply area The potential of the third pad.

In the smart processor as described above, preferably, the wafer further includes a third power supply area, the third power supply area includes a third pad and a fourth pad, and the third solder in the third power supply area The disk is connected to the third pad in the second power supply area, the fourth pad in the third power supply area serves as a ground terminal, and the potential of the third pad in the third power supply area is greater than the three The potential of the fourth pad in the power supply area.

In the smart processor as described above, preferably, the second power supply area is provided between the first power supply area and the third power supply area.

In the smart processor as described above, preferably, the first power supply area includes at least a plurality of first pads and second pads, and the plurality of first pads in the first power supply area are arranged to be mutually A plurality of parallel first vertical columns, and the second pads in the plurality of first power supply areas are arranged into a plurality of parallel second vertical columns.

In the smart processor as described above, preferably, the first vertical column and the second vertical column are alternately arranged.

In the smart processor as described above, preferably, the second power supply area includes at least a plurality of second pads and third pads, and the second pads of the plurality of second power supply areas are arranged to be mutually Parallel third vertical columns, the third pads in the plurality of second power supply areas are arranged into parallel fourth vertical columns, and the third vertical columns and the fourth vertical columns alternate And each of the third vertical columns and one of the second vertical columns are arranged collinearly.

In the smart processor as described above, preferably, the wafer further includes a third power supply area, and the third power supply area includes a plurality of third pads and a plurality of fourth pads; a plurality of the third power supplies The third pads in the area are arranged in parallel fifth vertical columns, and the fourth pads in the third power supply areas are arranged in parallel sixth vertical columns, and the fifth vertical columns The columns and the sixth vertical columns are alternately arranged, and each of the fifth vertical columns is arranged collinearly with one of the fourth vertical columns.

In the smart processor as described above, preferably, the internal components of the first power supply area, the internal components of the second power supply area, and the internal components of the third power supply area include multiple computing cores.

In the smart processor as described above, preferably, the second pad in the first power supply area serves as the ground terminal of the first power supply area, and the second pad in the second power supply area serves as the first The power input terminal of the power supply area.

In the smart processor as described above, preferably, the third pad in the second power supply area serves as the ground terminal of the second power supply area, and the third pad in the third power supply area serves as the first Three power input terminals in the power supply area.

As mentioned above, preferably, the intelligent processor further includes a substrate, the wafer is disposed on the substrate; the substrate is further provided with a first circuit, and the first power supply area The second pad and the second pad in the second power supply area are connected through the first circuit.

In the smart processor as described above, preferably, a second circuit is further provided on the substrate, and the third pad in the second power supply area and the third pad in the third power supply area pass through the Second circuit connection.

As described above, preferably, the intelligent processor further includes a packaging cover, the wafer is provided on a mounting surface of the substrate, the packaging cover is provided on the wafer, and the The mounting surface is connected.

In the above intelligent processor, preferably, the packaging cover is a plastic cover, a ceramic cover or a metal cover.

As described above, the intelligent processor is preferably a chip.

An embodiment of the present disclosure also provides an electrical device, including: the intelligent processor as described above.

In the wafer, the intelligent processor and the electrical equipment provided by the embodiments of the present disclosure, by using the first pad located in the first power supply area as a power input terminal, the second pad in the first power supply area and the second power supply area The second pad in the connection is connected, the third pad in the second power supply area is used as the ground terminal; only the first pad in the first power supply area is used as the power input terminal, and the second pad in the second power supply area The third pad is used as a ground terminal to supply power to the wafer; compared with all the pads on the wafer in the prior art and the solder ball connection on the substrate used to mount the wafer, the connection with the substrate is reduced The number of pads connected to the solder balls on the substrate can further reduce the number of solder balls on the substrate, thereby simplifying the structure of the substrate and reducing production costs.

BRIEF DESCRIPTION

One or more embodiments are exemplified by the corresponding drawings. These exemplary descriptions and the drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a proportional limitation, and among them:

1 is a schematic structural diagram of an intelligent processor provided by an embodiment of the present disclosure;

2 is a schematic structural diagram 1 of a wafer provided by an embodiment of the present disclosure;

FIG. 3 is a second schematic structural diagram of a wafer provided by an embodiment of the present disclosure.

Description of reference signs:

10. Wafer;

20. Substrate;

30. Encapsulation cover;

101. The first power supply area;

102. The second power supply area;

103. The third power supply area;

1011, the first pad in the first power supply area;

1012. The second pad in the first power supply area;

1021, the second pad in the second power supply area;

1022, the third pad in the second power supply area;

1031, the third pad in the third power supply area;

1032. The fourth pad in the third power supply area.

detailed description

In order to understand the features and technical contents of the embodiments of the present disclosure in more detail, the following describes the implementation of the embodiments of the present disclosure in detail with reference to the drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for convenience of explanation, various details are provided to provide a sufficient understanding of the disclosed embodiments. However, without these details, one or more embodiments can still be implemented. In other cases, to simplify the drawings, well-known structures and devices can be simplified.

Example 1

FIG. 2 is a first schematic structural view of a wafer provided by an embodiment of the present disclosure; FIG. 3 is a second structural schematic view of a wafer provided by an embodiment of the present disclosure.

Please refer to Figure 1 and Figure 2. This embodiment provides a wafer 10 having a first power supply area 101 and a second power supply area 102 spaced apart. The first power supply area 101 includes a first pad and a second pad, and a second power supply area 102 includes a second pad and a third pad. The first pad 1011 in the first power supply area serves as a power input terminal to supply power to the internal components in the first power supply area. The second pad 1012 in the first power supply area is The second pad 1021 in the second power supply area is connected, and the third pad 1022 in the second power supply area serves as the ground terminal of the second power supply area 102; the potential of the first pad 1011 in the first power supply area is greater than the first The potential of the second pad 1012 in the power supply area, the potential of the second pad 1021 in the second power supply area is greater than the potential of the third pad 1022 in the second power supply area.

In this embodiment, the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area may be metal sheets disposed on the wafer 10, and the same, the second pad in the second power supply area The pad 1021 and the third pad 1022 in the second power supply area are also metal sheets provided on the wafer 10.

In this embodiment, the first pad 1011 in the first power supply area is used as a power input terminal, and the first pad 1011 in the first power supply area can be connected to the power supply to the first pad 1011 in the first power supply area Provide a higher potential.

In this embodiment, the connection between the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area is an electrical connection. In a practical manner, a first copper sheet with a certain pattern is provided on the wafer 10, and the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area pass through the first Copper connection. In this embodiment, the third pad 1022 in the second power supply area serves as the ground terminal of the second power supply area 102, wherein the potential of the third pad 1022 in the second power supply area may be zero, or the The electric potential of the third pad 1022 is not zero, as long as the third pad 1022 in the second power supply area has a reference potential to ensure that the first pad 1011 in the first power supply area and the third in the second power supply area A certain voltage is required between the pads 1022, so that the wafer 10 can work normally.

In this embodiment, the second pad 1012 in the first power supply area serves as the ground terminal of the first power supply area 101, and the second pad 1021 in the second power supply area serves as the power input terminal of the second power supply area 102. During operation, there is a certain voltage between the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area, and the second pad 1021 in the second power supply area and the second power supply area There is a certain voltage between the third pad 1022 in the inner part, so that the inner parts of the first power supply area and the inner parts of the second power supply area can work normally.

In this embodiment, the internal components in the first power supply area are connected to the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area; The second pad 1021 in the second power supply area is connected to the third pad 1022 in the second power supply area. The potential of the first pad 1011 in the first power supply area is greater than the potential of the second pad 1012 in the first power supply area, and the potential of the second pad 1021 in the second power supply area is greater than the potential of the second power supply area. The electric potential of the three pads 1022 makes the internal components of the first power supply area and the internal components of the second power supply area share a part of the voltage.

Further, the divided voltages of the internal components of the first power supply area and the internal components of the second power supply area may be equal, that is, between the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area The voltage between them is equal to the voltage between the second pad 1021 in the second power supply area and the third pad 1022 in the second power supply area.

In the wafer provided in this embodiment, by using the first pad 1011 located in the first power supply area as a power input terminal, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area Connection, the third pad 1022 in the second power supply area serves as a ground terminal; only the first pad 1011 in the first power supply area serves as the power input terminal, and the third pad 1022 in the second power supply area As a ground terminal, the wafer 10 can be powered; compared with all the pads on the wafer in the prior art and the solder ball connection on the substrate for mounting the wafer, the soldering on the substrate is reduced The number of pads connected by the ball can further reduce the number of solder balls on the substrate, thereby simplifying the structure of the substrate and reducing the production cost.

In this embodiment, the wafer 10 further includes a third power supply area 103. The third power supply area 103 includes a third pad and a fourth pad. The third pad 1031 in the third power supply area and the second power supply area The third pad 1022 is connected, and the fourth pad 1032 in the third power supply area serves as a ground terminal. The potential of the third pad 1031 in the third power supply area is greater than the potential of the fourth pad 1032 in the third power supply area. The third pad 1031 in the third power supply area is connected to the third pad 1022 in the second power supply area, and the fourth pad 1032 in the third power supply area serves as a ground terminal, which can be The number of solder balls on the substrate of the wafer 10 in the power supply area to further simplify the structure of the substrate.

In a practical manner, a first copper sheet and a second copper sheet with a certain pattern are provided on the wafer 10, the second pad 1012 in the first power supply area and the second solder in the second power supply area The disk 1021 is connected by a first copper sheet; the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area are connected by a second copper plate.

In this embodiment, the second pad 1012 in the first power supply area serves as the ground terminal of the first power supply area 101, and the second pad 1021 in the second power supply area serves as the power input terminal of the second power supply area 102. The third pad 1022 in the second power supply area serves as a ground terminal of the second power supply area 102, and the third pad 1031 in the third power supply area serves as a power input terminal of the third power supply area 103. During operation, there is a certain voltage between the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area, and the second pad 1021 in the second power supply area and the second power supply area There is a certain voltage between the third pad 1022 in the inside, and there is a certain voltage between the third pad 1031 in the third power supply area and the fourth pad 1032 in the third power supply area, so that the The inner components, the inner components of the second power supply area, and the inner components of the third power supply area can all work normally.

Further, the divided voltages of the internal components of the first power supply area, the internal components of the second power supply area, and the internal components of the third power supply area are equal.

In this embodiment, the internal components in the first power supply area, the internal components in the second power supply area, and the internal components in the third power supply include multiple computing cores. In this embodiment, the calculation core is provided on the wafer 10 and has a certain logical structure. The calculation core is used for data processing, calculation, and other operations.

It is worth noting that the wafer 10 in this embodiment may also have four power supply areas, five power supply areas, etc .; correspondingly, each power supply area has internal components and pads connected to the internal components, one A pad in the power supply area is connected to a pad of the previous power supply area as a power input terminal of the power supply area, and another pad in the power supply area is used as a ground terminal of the power supply area and a pad of the next power supply area Pad connection, that is, the internal components in each power supply area are connected in series, so that only the first pad 1011 in the first power supply area is used as the power input terminal, and the last pad in the last power supply area is used as the ground terminal. Supply power to all internal components in the power supply area.

In this embodiment, the second power supply area 102 is disposed between the first power supply area 101 and the third power supply area 103. The second power supply area 102 is provided between the third power supply area 103 and the first power supply area 101, which can reduce the gap between the second pad 1021 in the second power supply area and the second pad 1012 in the first power supply area Distance, and the distance between the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area can be reduced.

In this embodiment, at least a plurality of first pads and second pads included in the first power supply area 101 are arranged, and the first pads 1011 in the plurality of first power supply areas are arranged in parallel first vertical columns The second pads 1021 in the plurality of first power supply areas are arranged in parallel second columns. The first vertical column and the second vertical column are alternately arranged. The second power supply area 102 includes a plurality of second pads and a plurality of third pads. The second pads 1021 in the plurality of second power supply areas are arranged in parallel third vertical columns, and the plurality of second power supplies The third pads 1022 in the area are arranged in several fourth vertical columns parallel to each other, and the third vertical columns and the fourth vertical columns are alternately arranged, and each third vertical column and one second vertical column are arranged collinearly.

Specifically, the first pads of the first vertical column are connected in parallel, the second pads of the second vertical column are connected in parallel, the second pads of the third vertical column are connected in parallel, and the third pads of the fourth vertical column are connected in parallel ; And the first pad of the first vertical column is connected to the power supply, the second pad of the second vertical column is connected to the second pad of the third vertical column, and the third pad of the fourth vertical column is grounded. Further, all the first pads located in the first power supply area 101 are connected in parallel, all the second pads located in the first power supply area 101 are connected in parallel, and all the second pads located in the second power supply area 102 are connected in parallel, located at All third pads in the second power supply area 102 are connected in parallel.

Specifically, the wafer 10 further includes a third power supply area 103, and the third power supply area 103 includes a plurality of third pads and a plurality of fourth pads; the third pads 1031 in the plurality of third power supply areas are arranged to be mutually Parallel fifth vertical columns, the fourth pads 1032 in the multiple third power supply areas are arranged into parallel sixth vertical columns, the fifth vertical columns and the sixth vertical columns are alternately arranged, and each Five vertical columns are arranged in line with a fourth vertical column.

In a practical manner, the first pads of the first vertical column are connected in parallel, the second pads of the second vertical column are connected in parallel, the second pads of the third vertical column are connected in parallel, and the fourth vertical columns are The third pads are connected in parallel, the third pads in the fifth column are connected in parallel, and the fourth pads in the sixth column are connected in parallel; and the first pads in the first column are connected to the power supply, and the second pads in the second column are soldered The disk is connected to the second pad of the third vertical column, the third pad of the fourth vertical column is connected to the third pad of the fifth vertical column, and the fourth pad of the sixth vertical column is grounded. Further, all first pads located in the first power supply area 101 are connected in parallel, all second pads located in the first power supply area 101 are connected in parallel, and all second pads located in the second power supply area 102 are connected in parallel, located in the first All third pads in the second power supply area 102 are connected in parallel, all third pads in the third power supply area 103 are connected in parallel, and all fourth pads in the third power supply area 103 are connected in parallel.

Example 2

FIG. 1 is a schematic structural diagram of an intelligent processor provided by an embodiment of the present disclosure. Please refer to FIGS. 1-3.

This embodiment provides an intelligent processor, including the wafer 10 as described above. The structure of the wafer 10 is substantially the same as that of the above-mentioned wafer 10, which will not be repeated here.

The smart processor provided in this embodiment further includes a substrate 20 on which the wafer is disposed; the substrate 20 is also provided with a first circuit, a second pad 1012 in the first power supply area and a second The two pads 1021 are connected through the first circuit.

The second pad 1012 in the first power supply area is connected to the second pad 1021 in the second power supply area through the first circuit on the substrate 20, which can be avoided compared with the first copper sheet provided on the wafer It is difficult to process the wafer 10 due to the large number of metal pieces placed on the wafer 10.

Further, a second circuit is further provided on the substrate 20, and the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area are connected by a second circuit. The connection between the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area can be achieved by the second circuit on the substrate 20, which can further avoid placing more metal on the wafer 10 The wafer 10 is difficult to process due to the wafer.

Further, the wafer 10 is mounted on the mounting surface of the substrate 20, and a corresponding soldering surface on the substrate 20 opposite to the mounting surface is provided with a first solder ball and a second solder ball, the first solder ball and the first power supply The first pad 1011 in the area is connected, the second solder ball is connected to the fourth pad 1032 in the third power supply area, the first solder ball is connected to the power supply, and the second solder ball is grounded to power the wafer 10.

Specifically, the substrate 20 may include at least two metal plates and an insulating plate between two adjacent metal plates, and the corresponding first circuit and second circuit may be formed on the same metal plate; of course, in order to avoid the same metal plate The circuit pattern is relatively complicated, and the first circuit and the second circuit can be located on different metal layers.

In a practical manner, the first circuit and the second circuit may be both provided on the metal plate of the substrate 20 near the mounting surface, or the first circuit and the second circuit are both provided on the metal plate of the substrate 20 near the bonding surface . When there are more than two metal plates on the substrate 20, the first circuit and the second circuit may be disposed on different metal plates between the metal plate near the mounting surface and the metal plate near the bonding surface; or the first circuit It is set on the metal plate close to the mounting surface, and the second circuit is set on the metal plate between the metal plate close to the mounting surface and the metal plate close to the bonding surface; or the first circuit is set on the metal plate close to the bonding surface And the second circuit is set on the metal plate between the metal plate close to the mounting surface and the metal plate close to the bonding surface; or the second circuit is set on the metal plate close to the mounting surface and the first circuit is set close to The metal plate between the metal plate on the mounting surface and the metal plate close to the bonding surface; or the second circuit is set on the metal plate near the bonding surface, and the first circuit is set on the metal plate close to the mounting surface and the close bonding The metal plate between the metal plates that meet. When there are more than three metal plates on the substrate 20, both the first circuit and the second circuit may be disposed between the metal plate near the mounting surface and the metal plate near the bonding surface, and the first circuit and the second circuit are located Different metal plates.

The first circuit and the second circuit in this embodiment are metal plates with certain patterns formed by patterning the metal plates. When the first circuit is located on the metal plate close to the mounting surface, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area can be directly connected to the first circuit when the first circuit is located On other metal plates, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area can be connected to the first circuit through the via; similarly, when the second circuit is located close to the installation On the metal plate on the surface, the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area can be directly connected to the second circuit. When the second circuit is located on another metal plate, The third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area may be connected to the second circuit through a via.

In this embodiment, the intelligent processor further includes a packaging cover 30, the wafer 10 is disposed on the mounting surface of the substrate 20, the packaging cover 30 is disposed on the wafer 10, and is connected to the mounting surface. The encapsulation cover 30 can seal the wafer 10, and at the same time, the encapsulation cover 30 can also protect the wafer 10 to prevent damage to the wafer 10 caused by contact of external objects with the wafer 10.

Further, the package cover 30 is a plastic cover, a ceramic cover or a metal cover.

The intelligent processor in this embodiment is a chip.

In other embodiments, an electrical device is also provided, including: the intelligent processor as described above.

When used in this application, although the terms "first", "second", etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without changing the meaning of the description, the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element" are consistently renamed and all occurrences of The "second component" can be renamed consistently. The first element and the second element are both elements, but they may not be the same element.

In addition, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no excessively detailed details are required to implement the described embodiments. Therefore, the above description of the embodiments is presented for explanation and description. The embodiments presented in the above description and the examples disclosed according to these embodiments are provided separately to add context and help to understand the described embodiments. The above description is not intended to be without omission or to limit the described embodiments to the precise form of this disclosure. Based on the above teachings, several modifications, choices and changes are possible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.

Claims

A wafer, characterized in that the wafer has a first power supply area and a second power supply area spaced apart, the first power supply area includes a first pad and a second pad, the second power supply The area includes a second pad and a third pad. The first pad in the first power supply area serves as a power input terminal to supply power to the internal components of the first power supply area. The second pad is connected to the second pad in the second power supply area, and the third pad in the second power supply area serves as the ground terminal of the second power supply area; The potential of one pad is greater than the potential of the second pad in the first power supply area, and the potential of the second pad in the second power supply area is greater than the potential of the third pad in the second power supply area .
The wafer according to claim 1, wherein the wafer further comprises a third power supply area, the third power supply area comprises a third pad and a fourth pad, and the third power supply area The third pad is connected to the third pad in the second power supply area, the fourth pad in the third power supply area serves as a ground terminal, and the potential of the third pad in the third power supply area is greater than The electric potential of the fourth pad in the three power supply areas.
The wafer according to claim 2, wherein the second power supply area is disposed between the first power supply area and the third power supply area.
The wafer according to claim 1, wherein the first power supply area includes at least a plurality of first pads and second pads, and a plurality of first pads in the first power supply area The first vertical columns are arranged parallel to each other, and the second pads in the plurality of first power supply areas are arranged into the second vertical columns parallel to each other.
The wafer according to claim 4, wherein the first vertical columns and the second vertical columns are alternately arranged.
The wafer according to claim 5, wherein the second power supply area includes at least a plurality of second pads and third pads, and a plurality of second pads in the second power supply area A plurality of third vertical columns arranged parallel to each other, a plurality of third pads in the second power supply area are arranged into a plurality of parallel fourth vertical columns, and the third vertical column and the fourth The vertical columns are alternately arranged, and each of the third vertical columns is arranged collinearly with one of the second vertical columns.
The wafer according to claim 6, wherein the wafer further comprises a third power supply area, the third power supply area comprises a plurality of third pads and a plurality of fourth pads; a plurality of the The third pads in the third power supply area are arranged in parallel fifth vertical columns, and the fourth pads in the third power supply areas are arranged in parallel sixth vertical columns. The fifth vertical column and the sixth vertical column are alternately arranged, and each fifth vertical column and one fourth vertical column are arranged collinearly.
The wafer according to claim 2, wherein the internal components of the first power supply area, the internal components of the second power supply area, and the internal components of the third power supply include multiple computing cores.
The wafer according to claim 1 or 2, wherein the second pad in the first power supply area serves as a ground terminal of the first power supply area, and the second solder in the second power supply area The disk serves as a power input end of the second power supply area.
The wafer according to claim 2, wherein the third pad in the second power supply area serves as the ground terminal of the second power supply area, and the third pad in the third power supply area serves as the ground A power input terminal of the third power supply area.
An intelligent processor, characterized by comprising a wafer, the wafer having a first power supply area and a second power supply area spaced apart, the first power supply area includes a first pad and a second pad, The second power supply area includes a second pad and a third pad. The first pad in the first power supply area serves as a power input terminal to supply power to internal components of the first power supply area. The second pad in the power supply area is connected to the second pad in the second power supply area, and the third pad in the second power supply area serves as the ground terminal of the second power supply area; the first The potential of the first pad in the power supply area is greater than the potential of the second pad in the first power supply area, and the potential of the second pad in the second power supply area is greater than the The potential of the three pads.
The intelligent processor according to claim 11, wherein the wafer further includes a third power supply area, the third power supply area includes a third pad and a fourth pad, and the third power supply area Is connected to the third pad in the second power supply area, the fourth pad in the third power supply area serves as a ground terminal, and the potential of the third pad in the third power supply area It is greater than the potential of the fourth pad in the three power supply regions.
The intelligent processor according to claim 12, wherein the second power supply area is provided between the first power supply area and the third power supply area.
The intelligent processor according to claim 11 or 12, wherein the first power supply area includes at least a plurality of first pads and second pads, and a plurality of One pad is arranged in several first vertical columns parallel to each other, and the second pads in the plurality of first power supply areas are arranged in several second vertical columns parallel to each other.
The intelligent processor according to claim 14, wherein the first vertical column and the second vertical column are alternately arranged.
The intelligent processor according to claim 15, wherein the second power supply area includes at least a plurality of second pads and third pads, and a plurality of second solders in the second power supply area The disks are arranged in parallel third vertical columns, the third pads in the second power supply area are arranged in parallel fourth vertical columns, and the third vertical column and the third vertical column Four vertical columns are alternately arranged, and each of the third vertical columns is arranged collinearly with one of the second vertical columns.
The intelligent processor according to claim 16, wherein the wafer further includes a third power supply area, the third power supply area includes a plurality of third pads and a plurality of fourth pads; The third pads in the third power supply area are arranged in parallel fifth vertical columns, and the fourth pads in the third power supply areas are arranged in parallel sixth vertical columns. The fifth vertical column and the sixth vertical column are alternately arranged, and each fifth vertical column is arranged collinearly with one fourth vertical column.
The intelligent processor according to claim 11, wherein the internal components of the first power supply area, the internal components of the second power supply area, and the internal components of the third power supply area include multiple computing cores.
The intelligent processor according to claim 11 or 12, wherein the second pad in the first power supply area serves as a ground terminal of the first power supply area, and the second pad in the second power supply area The pad serves as a power input end of the second power supply area.
The intelligent processor according to claim 12, wherein the third pad in the second power supply area serves as a ground terminal of the second power supply area, and the third pad in the third power supply area As a power input terminal of the third power supply area.
The intelligent processor according to claim 12, wherein the intelligent processor further comprises a substrate, the wafer is disposed on the substrate; the substrate is further provided with a first circuit, the first The second pad in the power supply area and the second pad in the second power supply area are connected by the first circuit.
The intelligent processor according to claim 21, wherein a second circuit is further provided on the substrate, the third pad in the second power supply area and the third solder in the third power supply area The disk is connected through the second circuit.
The intelligent processor according to claim 21, wherein the intelligent processor further comprises a packaging cover, the wafer is provided on a mounting surface of the substrate, and the packaging cover is provided on the wafer And connected to the mounting surface.
The intelligent processor according to claim 23, wherein the packaging cover is a plastic cover, a ceramic cover or a metal cover.
The intelligent processor according to claim 11, wherein the intelligent processor is a chip.
An electrical device, characterized by comprising: the intelligent processor according to any one of claims 11-25.