WO2020093277A1

WO2020093277A1 - Chip and electrical equipment

Info

Publication number: WO2020093277A1
Application number: PCT/CN2018/114390
Authority: WO
Inventors: 杨帅; 郭函
Original assignee: 北京比特大陆科技有限公司
Priority date: 2018-11-07
Filing date: 2018-11-07
Publication date: 2020-05-14

Abstract

A chip and electrical equipment. The chip comprises a substrate (20) and a wafer (10) mounted on the substrate (20); the wafer (10) is provided with a first power supply area (101) and a second power supply area (102) which are arranged at an interval; the first power supply area (101) comprises first bonding pads (1011) and second bonding pads (1012); the second power supply area (102) comprises second bonding pads (1021) and third bonding pads (1022); the wafer (10) is disposed on the mounting surface of the substrate (20); the substrate (20) comprises a bottom metal plate (205) away from the mounting surface, at least one middle metal plate arranged parallel to and spaced apart from the bottom metal plate (205), and an insulating plate disposed between adjacent metal plates; the bottom metal plate (205) is provided with power supply pins (2051), grounding pins (2052), and first power supply pins (2053); the second bonding pads (1012) in the first power supply area (101) are connected to the second bonding pads (1021) in the second power supply area (102) by means of a first circuit (2041) located on the middle metal plate, and the first circuit (2041) is electrically connected to the first power supply pins (2053) by means of a first connecting hole. The second bonding pads (1012) in the first power supply area (101) and the second bonding pads (1021) in the second power supply area (102) are connected to the first power supply pins (2053), so that the number of the power supply pins on the substrate (20) can be reduced, the structure of the chip is simplified, and the production costs of the chip are reduced.

Description

Chips and electrical equipment

Technical field

This application relates to the field of electrical equipment, such as a chip and electrical equipment.

Background technique

A circuit board and a chip mounted on the circuit board are provided in the electrical equipment, and the chip is electrically connected to the circuit on the circuit board.

In the prior art, the chip includes a wafer and a substrate, and the wafer has a first power supply area and a second power supply area spaced apart; each of the first power supply area and the second power supply area has a plurality of pads, and each The pad is electrically connected to a pin on the substrate, the substrate is connected to the circuit board, and the pins on the substrate are electrically connected to the circuit on the circuit board to realize the connection between the chip and the circuit board.

However, there are more pads on the wafer, which leads to more pins on the substrate, resulting in a complicated chip structure and high production cost.

Summary of the invention

An embodiment of the present disclosure provides a chip, including: a substrate and a wafer mounted on the substrate;

The wafer has a first power supply area and a second power supply area spaced apart, the first power supply area includes a first pad and a second pad, and the second power supply area includes a second pad and a third Pad

The wafer is disposed on a mounting surface on the substrate; the substrate includes a bottom metal plate facing away from the mounting surface, at least one intermediate metal plate disposed parallel to and spaced from the bottom metal plate, and disposed on Insulation plate between adjacent metal plates;

The bottom metal plate is provided with a power supply pin, a ground pin and a first power pin;

A first conductive hole and a second conductive hole penetrating the substrate are provided at intervals on the substrate, and an end of the first conductive hole facing the mounting surface is connected to the first pad in the first power supply area, The end of the first conductive hole facing away from the mounting surface is connected to the power supply pin; the end of the second conductive hole facing the mounting surface is connected to the third pad in the second power supply area. The end of the second conductive hole facing away from the mounting surface is connected to the ground pin; the second pad in the first power supply area and the second pad in the second power supply area are located between The first circuit on the intermediate metal plate is connected, and the first circuit is electrically connected to the first power pin through a first connection hole.

For the chip as described above, preferably, the wafer further includes a third power supply area, and the third power supply area is spaced apart from the first power supply area and the second power supply area, and the third power supply area It includes a third pad and a fourth pad; the fourth pad in the third power supply area is connected to the end of the second conductive hole facing the mounting surface, and the third solder in the third power supply area The disk and the third pad in the second power supply area are connected by a second circuit on the middle metal plate; the bottom metal plate is also provided with a second power pin, the second circuit The second power pin is electrically connected through the second connection hole.

For the chip as described above, preferably, the wafer further includes a fourth power supply area, and the fourth power supply area is spaced apart from the first power supply area, the second power supply area, and the third power supply area , The fourth power supply area includes a fourth pad and a fifth pad; the fifth pad in the fourth power supply area is connected to an end of the second conductive hole facing the mounting surface, the fourth The fourth pad in the power supply area and the fourth pad in the third power supply area are connected by a third circuit located on the middle metal plate; the bottom metal plate is also provided with a third power supply Pin, the second circuit is electrically connected to the third power pin through a third connection hole.

In the chip as described above, preferably, the power supply pin and the ground pin are provided in the middle of the bottom metal plate, the first power pin, the second power pin, and the first Three power pins are located at the edge of the bottom metal plate.

In the chip as described above, preferably, the intermediate metal plate includes a first intermediate metal plate disposed toward the wafer, and a second intermediate metal between the first intermediate metal plate and the bottom metal plate Board, the second circuit is provided on the first intermediate metal plate, and the first circuit and the third circuit are provided on the second intermediate metal plate.

In the chip as described above, preferably, a first solder resist layer is provided on the mounting surface of the substrate, and a second solder resist layer is provided on the bonding surface of the substrate opposite to the mounting surface.

In the chip as described above, preferably, the first solder resist layer and the second solder resist layer are both insulating layers.

As described above, preferably, the chip further includes a package cover, which is provided on the wafer and connected to the mounting surface.

For the above-mentioned chip, preferably, the packaging cover is a plastic cover or a ceramic cover or a metal cover.

An embodiment of the present disclosure also provides an electrical device, including: the chip as described above.

An embodiment of the present disclosure also provides a chip, including: a substrate and a wafer mounted on the substrate;

A first power supply area, a second power supply area, a third power supply area, and a fourth power supply area that are sequentially arranged on the wafer; the first power supply area includes a first pad and a second pad, and the second power supply The area includes a second pad and a three pad; the third power supply area includes a third pad and a fourth pad, and the fourth power supply area includes a fourth pad and a five pad;

The first pad in the first power supply area serves as a power input terminal, the second pad in the first power supply area is connected to the second pad in the second power supply area, and the first power supply area The second pad in the area serves as the ground terminal of the first power supply area; the second pad in the second power supply area serves as the power supply terminal of the second power supply area, and the third in the second power supply area The pad is connected to the third pad in the third power supply area, and the third pad in the second power supply area serves as the ground terminal of the second power supply area; the third in the third power supply area The pad serves as a power end of the third power supply area, the fourth pad in the third power supply area is connected to the fourth pad in the fourth power supply area, and the fourth pad in the third power supply area The pad serves as the ground terminal of the third power supply area; the fourth pad in the fourth power supply area serves as the power supply terminal of the fourth power supply area, and the fifth pad in the fourth power supply area serves as the first 4. The ground terminal of the power supply area;

The substrate includes a stacked first intermediate metal plate, a second intermediate metal plate, a bottom metal plate, and an insulating plate provided between adjacent metal plates, and the wafer is provided on a mounting surface on the substrate ;

The bottom metal plate is disposed away from the mounting surface and the bottom metal plate is provided with a power supply pin, a ground pin, a first power pin, a second power pin, and a third power pin;

Conductive holes are provided on the first intermediate metal plate and the second intermediate metal plate so that the power supply pin is connected to the first pad, the ground pin is connected to the fifth pad, and the first The power supply pin is connected to the second pad, the second power pin is connected to the third pad, and the third power pin is connected to the fourth pad.

In the chip as described above, preferably, the power supply pin and the ground pin are provided in the middle of the bottom metal plate; the first power pin, the second power pin, and the first Three power pins are provided at the edge of the bottom metal plate.

In the chip as described above, preferably, a first conductive hole and a second conductive hole penetrating the substrate are provided on the substrate at intervals, an end of the first conductive hole facing the mounting surface is connected to the first power supply The first pad in the area is connected, and the end of the first conductive hole facing away from the mounting surface is connected to the power supply pin; the end of the second conductive hole facing the mounting surface is connected to the fourth power supply area The fifth pad inside is connected, and the end of the second conductive hole facing away from the mounting surface is connected to the ground pin.

In the chip as described above, preferably, the first conductive hole and the second conductive hole are straight holes.

In the above-mentioned chip, preferably, the first conductive hole and the second conductive hole are plural.

In the chip described above, preferably, the first power pin is electrically connected to the second pad through the first connection hole, and the second power pin is electrically connected to the third pad through the second connection hole. The third power pin is electrically connected to the fourth pad through a third connection hole; the first connection hole, the second connection hole, and the third connection hole are all plural.

In the chip and electrical equipment provided by the embodiments of the present disclosure, the wafer has a first power supply area and a second power supply area spaced apart, the first power supply area includes a first pad and a second pad, and the second power supply area includes a second The pad and the third pad. The substrate includes a bottom metal plate facing away from the mounting surface, at least one intermediate metal plate disposed parallel to and spaced from the bottom metal plate, and an insulating plate disposed between adjacent metal plates. On the mounting surface of the substrate; the first pad in the first power supply area is connected to the power supply through the first conductive hole and the power supply pin on the substrate; the third pad in the second power supply area passes through the second conductive hole and the bottom layer The ground pin on the metal plate is connected; the second pad in the first power supply area is connected to the second pad in the second power supply area through the first circuit on the substrate, and the first circuit is connected to the second pad on the bottom metal plate A power pin connection; compared with all the pads in the prior art that are connected to the pin, the second pad in the first power supply area and the second pad in the second power supply area in this embodiment are both The first power pin connection can reduce the base The number of power pins on the board simplifies the structure of the chip and reduces the production cost of the chip.

BRIEF DESCRIPTION

One or more embodiments are exemplified by the corresponding drawings. These exemplary descriptions and the drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a proportional limitation, and among them:

FIG. 1 is a schematic structural diagram of a chip provided by this embodiment;

2 is a schematic structural diagram of a wafer in a chip provided by this embodiment;

3 is a schematic structural diagram of a substrate in a chip provided by this embodiment;

4 is a schematic structural diagram of a first intermediate metal plate in this embodiment;

5 is a schematic structural diagram of a second intermediate metal plate in this embodiment;

6 is a schematic structural diagram of a bottom metal plate in this embodiment.

Description of reference signs:

10. Wafer;

20. Substrate;

30. Encapsulation cover;

101. The first power supply area;

102. The second power supply area;

103. The third power supply area;

104. The fourth power supply area;

1011, the first pad in the first power supply area;

1012. The second pad in the first power supply area;

1021, the second pad in the second power supply area;

1022, the third pad in the second power supply area;

1031, the third pad in the third power supply area;

1032, the fourth pad in the third power supply area;

1041, the fourth pad in the fourth power supply area;

1042. The fifth pad in the fourth power supply area;

2051, power supply pin;

2052, ground pin;

2053, the first power pin;

2054, second power supply pin;

2055, the third power pin;

201. The first conductive hole;

202. Second conductive hole;

203. The first intermediate metal plate;

204. The second intermediate metal plate;

205. The bottom metal plate;

206. The first solder resist layer;

207. Second solder resist layer;

2041, the first circuit;

2031. Second circuit;

2042. The third circuit.

detailed description

In order to understand the features and technical contents of the embodiments of the present disclosure in more detail, the following describes the implementation of the embodiments of the present disclosure in detail with reference to the drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for convenience of explanation, various details are provided to provide a sufficient understanding of the disclosed embodiments. However, without these details, one or more embodiments can still be implemented. In other cases, to simplify the drawings, well-known structures and devices can be simplified.

1 is a schematic diagram of the structure of the chip provided in this embodiment; FIG. 2 is a schematic diagram of the structure of the wafer in the chip provided in this embodiment; FIG. 3 is a schematic diagram of the structure of the substrate in the chip provided in this embodiment; The structure diagram of the first middle metal plate in FIG. 5 is the structure diagram of the second middle metal plate in this embodiment. FIG. 6 is the structure diagram of the bottom metal plate in this embodiment.

Please refer to Figure 1-6. This embodiment provides a chip, including: a substrate 20 and a wafer 10 mounted on the substrate 20; the wafer 10 has a first power supply area 101 and a second power supply area 102 spaced apart, the first power supply area 101 includes a A pad and a second pad, the second power supply area 102 includes a second pad and a third pad; the wafer 10 is provided on a mounting surface on the substrate 20; the substrate 20 includes an underlying metal plate 205 facing away from the mounting surface, At least one intermediate metal plate disposed parallel to and spaced from the bottom metal plate 205, and an insulating plate provided between adjacent metal plates. The bottom metal plate 205 is provided with a power supply pin 2051, a ground pin 2052, and a first power supply Pin 2053; a first conductive hole 201 and a second conductive hole 202 penetrating through the substrate 20 are arranged at intervals on the substrate 20, an end of the first conductive hole 201 facing the mounting surface is connected to the first pad 1011 in the first power supply area, The end of the first conductive hole 201 facing away from the mounting surface is connected to the power supply pin 2051; the end of the second conductive hole 202 facing the mounting surface is connected to the third pad 1022 in the second power supply area, and the second conductive hole 202 facing away from the mounting surface One end is connected to the ground pin 2052 Connected; the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area are connected through a first circuit 2041 located on the middle metal plate, and the first circuit 2041 is connected through the first connection hole It is electrically connected to the first power pin 2053.

In this embodiment, the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area may be metal sheets provided on the wafer 10 or bumps made of other conductive materials; the same In addition, the second pad 1021 in the second power supply area and the third pad 1022 in the second power supply area are also metal sheets provided on the wafer 10 or bumps made of other conductive materials.

The power supply pin 2051 in this embodiment is connected to a power supply, which is located outside the wafer 10 and used to provide a higher potential to the first pad 1011 in the first power supply area through the power supply pin 2051 and the first conductive hole 201 installation.

In this embodiment, the third pad 1022 in the second power supply area is grounded, wherein the potential of the third pad 1022 in the second power supply area may be zero, or the potential of the third pad 1022 in the second power supply area is not Is zero, as long as the third pad 1022 in the second power supply area has a reference potential to ensure that there is a certain distance between the first pad 1011 in the first power supply area and the third pad in the second power supply area 102 The voltage is sufficient so that the wafer 10 can work normally.

In this embodiment, a computer core is provided in both the first power supply area 101 and the second power supply area 102. The first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area supply the first power supply The computer core in the area 101 supplies power. The second pad 1021 in the second power supply area and the third pad 1022 in the second power supply area supply power to the computer core in the second power supply area 102. The first pad 1011 in the first power supply area as the power supply terminal potential of the first power supply area 101 is greater than the potential of the second pad 1012 in the first power supply area, and the second pad 1021 in the second power supply area as the first The power supply terminal potential of the second power supply area 102 is greater than the potential of the third pad 1022 in the second power supply area, thereby supplying power to the computer cores in the first power supply area 101 and the second power supply area 102.

Further, the voltages obtained by the computer cores in the first power supply area 101 and the second power supply area 102 may be equal, that is, the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area The voltage between them is equal to the voltage between the second pad 1021 in the second power supply area and the third pad 1022 in the second power supply area.

In this embodiment, the first conductive hole 201 used to connect the first pad 1011 in the first power supply area and the power supply pin 2051 may be a via hole. Of course, the first conductive hole 201 may also include a through hole formed on the substrate 20 Hole, and a metal post penetrated in the through hole; the end of the first conductive hole 201 facing the mounting surface of the substrate 20 is connected to the first pad 1011 in the first power supply area, and the first conductive hole 201 is facing the mounting of the substrate 20 One end of the bonding surface opposite to the surface is connected to the power supply pin 2051. Similarly, the second conductive hole 202 may also be a via hole, or the second conductive hole 202 includes a through hole opened in the substrate 20, and a metal post penetrated in the through hole; the second conductive hole 202 faces the mounting surface One end is connected to the second pad 1021 in the second power supply area, and the end of the second guide hole facing the bonding surface is connected to the ground pin 2052.

In this embodiment, when the first circuit 2041 is located on the middle metal plate close to the mounting surface, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area may directly communicate with the first circuit 2041 connection; when the first circuit 2041 is located on another metal plate, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area may be connected to the first circuit 2041 through a via. The first circuit 2041 may be connected to the first power pin 2053 through the via between the middle metal plate and the bottom metal plate 205 where the first circuit 2041 is located, so as to connect the second pad 1012 and the second The signal on the second pad 1021 in the power supply area is transmitted to the first power supply pin 2053.

In the chip provided in this embodiment, the wafer 10 has a first power supply area 101 and a second power supply area 102 spaced apart. The first power supply area 101 includes a first pad and a second pad, and the second power supply area 102 includes a Two pads and a third pad, the substrate 20 includes a bottom metal plate 205 facing away from the mounting surface, at least one middle metal plate disposed parallel to and spaced from the bottom metal plate 205, and an insulating plate disposed between adjacent metal plates The wafer 10 is provided on the mounting surface of the substrate 20; the first pad 1011 in the first power supply area is connected to the power supply through the first conductive hole 201 and the power supply pin 2051 on the substrate 20; The three pads 1022 are connected to the ground pin 2052 on the bottom metal plate 205 through the second conductive hole 202; the second pad 1012 in the first power supply area is connected to the second power supply area through the first circuit 2041 on the substrate 20 The second pad 1021 is connected, and the first circuit 2041 is connected to the first power pin 2053 on the bottom metal plate 205; compared with all pads and pin connections in the prior art, the first in this embodiment The second pad 1012 in the power supply area and the second power supply area The second pads 1021 are connected to the first power pins 2053, which can reduce the number of power pins on the substrate 20, simplify the structure of the chip, and reduce the production cost of the chip.

In this embodiment, the wafer 10 further includes a third power supply area 103, which is spaced apart from the first power supply area 101 and the second power supply area 102. The third power supply area 103 includes a third pad and a fourth Pad; the fourth pad 1032 in the third power supply area is connected to the end of the second conductive hole 202 facing the mounting surface, the third pad 1031 in the third power supply area and the third pad 1022 in the second power supply area They are connected by a second circuit 2031 located on the middle metal plate; a second power pin 2054 is also provided on the bottom metal plate 205, and the second circuit 2031 is electrically connected to the second power pin 2054 through the second connection hole. The number of pins of a chip with three power supply areas can be reduced to further simplify the structure of the chip.

Specifically, the wafer 10 further includes a fourth power supply area 104, which is spaced apart from the first power supply area 101, the second power supply area 102, and the third power supply area 103. The fourth power supply area 104 includes a fourth solder Plate and fifth pad; the fifth pad 1042 in the fourth power supply area is connected to the end of the second conductive hole 202 facing the mounting surface, the fourth pad 1041 in the fourth power supply area and the third pad in the third power supply area The four pads 1032 are connected by a third circuit 2042 located on the middle metal plate; the bottom metal plate 205 is also provided with a third power pin 2055, and the second circuit 2031 is connected to the third power pin 2055 through the third connection hole Electrical connection.

The wafer 10 in this embodiment may also have five power supply areas, six power supply areas, etc .; correspondingly, each power supply area has a computer core and a pad connected to the computer core, and one power supply area serves as a power supply terminal. The pad is connected to the pad in the previous power supply area as the ground terminal. The pad in the power supply area is connected to the pad in the next power supply area as the power terminal, that is, the computer cores in the adjacent power supply area are connected in series, so that only the first The first pad 1011 in a power supply area is connected to the power supply pin 2051 through the first conductive hole 201, and the pad as the ground terminal in the last power supply area is connected to the ground pin 2052 through the second conductive hole 202. All computer cores in the power supply area provide power. In addition, the two adjacent power supply areas are connected by a circuit located on the middle metal plate, and each circuit is connected to a power pin on the bottom metal plate 205 to transmit the signal in the power supply area to the power pin.

With continued reference to FIG. 6, in this embodiment, the power supply pin 2051 and the ground pin 2052 are disposed in the middle of the bottom metal plate 205, and the first power pin 2053, the second power pin 2054, and the third power pin 2055 are located The edge of the bottom metal plate 205.

Specifically, with continued reference to FIG. 4, the second circuit 2031 for connecting the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area is provided on the first intermediate metal plate 203; The other pads on the wafer 10 are connected to other intermediate metal plates or pins through vias passing through the first intermediate metal plate 203.

5, the first circuit 2041 for connecting the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area is provided on the second intermediate metal plate 204, and at the same time, The third circuit 2042 connecting the fourth pad 1032 in the third power supply area and the fourth pad 1041 in the fourth power supply area is also disposed on the second intermediate metal layer 204.

Specifically, taking the bottom metal plate 205 as a rectangle, for example, there are multiple ground pins 2052 and power supply pins 2051, and the gaps are set in the middle of the bottom metal plate 205, the first power pin 2053, the second Both the power supply pin 2054 and the third power supply pin 2055 are located near one side of the bottom metal plate 205; of course, the first power supply pin 2053, the second power supply pin 2054, and the third power supply pin 2055 may be symmetrical Are provided on both edges of the bottom metal plate 205.

In a practical manner, there may be one intermediate metal plate, and the corresponding first circuit 2041, second circuit 2031, and third circuit 2042 are all disposed on the same intermediate metal plate, that is, the same intermediate metal plate is patterned To form a first circuit 2041, a second circuit 2031, and a third circuit 2042 with a certain pattern.

In this embodiment, the intermediate metal plate includes a first intermediate metal plate 203 disposed toward the wafer 10, and a second intermediate metal plate 204 between the first intermediate metal plate 203 and the bottom metal plate 205, and the second circuit 2031 is provided On the first intermediate metal plate 203, the first circuit 2041 and the third circuit 2042 are provided on the second intermediate metal plate 204.

Compared with that all circuits are arranged on the same intermediate metal plate, it is possible to avoid installing more circuits on the same intermediate metal plate, thereby simplifying the structure of the intermediate metal plate.

In this embodiment, the first power supply area 101 includes a plurality of first pads and a plurality of second pads, and the first pads 1011 in the plurality of first power supply areas are arranged in parallel first vertical columns. The second pads 1012 in the plurality of first power supply areas are arranged into a plurality of second vertical columns parallel to each other, and the first vertical columns and the second vertical columns are alternately arranged; the second power supply region 102 includes a plurality of second pads And a plurality of third pads, the second pads 1021 in the plurality of second power supply areas are arranged in parallel third vertical columns, and the third pads 1022 in the plurality of second power supply areas are arranged parallel to each other A number of fourth vertical columns, and the third vertical columns and the fourth vertical columns are alternately arranged, and each third vertical column is arranged collinearly with a second vertical column.

Specifically, the first pads of the first vertical column are connected in parallel, the second pads of the second vertical column are connected in parallel, the second pads of the third vertical column are connected in parallel, and the third pads of the fourth vertical column are connected in parallel ; And the first pad of the first vertical column is connected to the power supply pin 2051, the second pad of the second vertical column is connected to the second pad of the third vertical column, and the third pad of the fourth vertical column is grounded Pin 2052 is connected. Further, all the first pads located in the first power supply area 101 are connected in parallel, all the second pads located in the first power supply area 101 are connected in parallel, and all the second pads located in the second power supply area 102 are connected in parallel, located at All third pads in the second power supply area 102 are connected in parallel.

In this embodiment, the first solder resist layer 206 is provided on the mounting surface of the substrate 20, and the second solder resist layer 207 is provided on the bonding surface of the substrate 20 opposite to the mounting surface. Both the first solder resist layer 206 and the second solder resist layer 207 are insulating layers. Specifically, a first opening is provided on the first solder resist layer 206 corresponding to each pad. Similarly, the power supply pin 2051, the ground pin 2052, the first power pin 2053, the second power pin 2054, and the first The second solder resist layer 207 corresponding to the three power pins 2055 is provided with a second opening, so that welding is performed only at the first opening and the second opening, and the outer sides of the first opening and the second opening are not welded, which improves the chip Welding accuracy.

In this embodiment, the chip further includes a packaging cover 30, the wafer 10 is disposed on the mounting surface of the substrate 20, the packaging cover 30 is disposed on the wafer 10, and is connected to the mounting surface. The encapsulation cover 30 can seal the wafer 10, and at the same time, the encapsulation cover 30 can also protect the wafer 10 from damage caused by contact of the external object with the wafer 10.

Further, the package cover 30 is a plastic cover, a ceramic cover or a metal cover.

In other embodiments, an electrical device is also provided, including: the chip as described above.

Continue to refer to Figures 1-6. In other embodiments, a chip is further provided, including: a substrate 20 and a wafer 10 mounted on the substrate 20;

The first power supply area 101, the second power supply area 102, the third power supply area 103, and the fourth power supply area 104 provided on the wafer 10 in sequence; the first power supply area 101 includes a first pad and a second pad, and the second power supply The area 102 includes second and third pads; the third power supply area 103 includes third and fourth pads, and the fourth power supply area 104 includes fourth and fifth pads;

The first pad 1011 in the first power supply area serves as a power input terminal, the second pad 1012 in the first power supply area is connected to the second pad 1021 in the second power supply area, and the second solder in the first power supply area The disk 1012 serves as the ground terminal of the first power supply area 101; the second pad 1021 in the second power supply area serves as the power supply terminal of the second power supply area 102, the third pad 1022 in the second power supply area and the third power supply area The third pad 1031 is connected, the third pad 1022 in the second power supply area serves as the ground terminal of the second power supply area 102; the third pad 1031 in the third power supply area serves as the power supply terminal of the third power supply area 103, The fourth pad 1032 in the third power supply area is connected to the fourth pad 1041 in the fourth power supply area, and the fourth pad 1032 in the third power supply area serves as the ground terminal of the third power supply area 103; the fourth power supply area The fourth pad 1041 in the inside serves as the power terminal of the fourth power supply area 104, and the fifth pad 1042 in the fourth power supply area serves as the ground terminal of the fourth power supply area 104;

The substrate 20 includes a stacked first intermediate metal plate 203, a second intermediate metal plate 204, a bottom metal plate 205, and an insulating plate provided between adjacent metal plates. The wafer 10 is provided on the mounting surface of the substrate 20 ;

The bottom metal plate 205 is disposed away from the installation surface and the bottom metal plate 205 is provided with a power supply pin 2051, a ground pin 2052, a first power pin 2053, a second power pin 2054, and a third power pin 2055;

Conductive holes are provided on the first intermediate metal plate 203 and the second intermediate metal plate 204 so that the power supply pin 2051 is connected to the first pad, the ground pin 2052 is connected to the fifth pad, and the first power pin 2053 and the second Two pads are connected, the second power pin 2054 is connected to the third pad, and the third power pin 2055 is connected to the fourth pad.

Specifically, the power supply pin 2051 and the ground pin 2052 are provided in the middle of the bottom metal plate 205; the first power pin 2053, the second power pin 2054, and the third power pin 2055 are provided at the edge of the bottom metal plate 205 .

Specifically, a first conductive hole 201 and a second conductive hole 202 penetrating through the substrate 20 are provided on the substrate 20 at intervals. The end of the first conductive hole 201 facing the mounting surface is connected to the first pad 1011 in the first power supply area. The end of a conductive hole 201 facing away from the mounting surface is connected to the power supply pin 2051; the end of the second conductive hole 202 facing the mounting surface is connected to the fifth pad 1042 in the fourth power supply area, and the end of the second conductive hole 202 facing away from the mounting surface Connect to ground pin 2052.

Specifically, the first conductive hole 201 and the second conductive hole 202 are straight holes.

Specifically, there are a plurality of first conductive holes 201 and second conductive holes 202.

Specifically, the first power pin 2053 is electrically connected to the second pad through the first connection hole, the second power pin 2054 is electrically connected to the third pad through the second connection hole, and the third power pin 2055 is connected through the third The connection hole is electrically connected to the fourth pad; the first connection hole, the second connection hole, and the third connection hole are all plural.

When used in this application, although the terms "first", "second", etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without changing the meaning of the description, the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element" are consistently renamed and all occurrences of The "second component" can be renamed consistently. The first element and the second element are both elements, but they may not be the same element.

In addition, terminology is used in the above technical description to provide a thorough understanding of the described embodiments. However, no excessively detailed details are required to implement the described embodiments. Therefore, the above description of the embodiments is presented for explanation and description. The embodiments presented in the above description and the examples disclosed according to these embodiments are provided separately to add context and help to understand the described embodiments. The above description is not intended to be without omission or to limit the described embodiments to the precise form of this disclosure. Based on the above teachings, several modifications, choices and changes are possible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.

Claims

A chip characterized by comprising: a substrate and a wafer mounted on the substrate;

The wafer has a first power supply area and a second power supply area spaced apart, the first power supply area includes a first pad and a second pad, and the second power supply area includes a second pad and a third Pad

The wafer is disposed on a mounting surface on the substrate; the substrate includes a bottom metal plate facing away from the mounting surface, at least one intermediate metal plate disposed parallel to and spaced from the bottom metal plate, and disposed on Insulation plate between adjacent metal plates;

The bottom metal plate is provided with a power supply pin, a ground pin and a first power pin;

A first conductive hole and a second conductive hole penetrating the substrate are provided at intervals on the substrate, and an end of the first conductive hole facing the mounting surface is connected to the first pad in the first power supply area, The end of the first conductive hole facing away from the mounting surface is connected to the power supply pin; the end of the second conductive hole facing the mounting surface is connected to the third pad in the second power supply area. The end of the second conductive hole facing away from the mounting surface is connected to the ground pin; the second pad in the first power supply area and the second pad in the second power supply area are located between The first circuit on the intermediate metal plate is connected, and the first circuit is electrically connected to the first power pin through a first connection hole.
The chip according to claim 1, wherein the wafer further includes a third power supply area, and the third power supply area is spaced apart from the first power supply area and the second power supply area, the The third power supply area includes a third pad and a fourth pad; the fourth pad in the third power supply area is connected to an end of the second conductive hole facing the mounting surface, and the third power supply area The third pad of the second power supply area is connected to the third pad of the second power supply area through a second circuit on the middle metal plate; the bottom metal plate is also provided with a second power pin, so The second circuit is electrically connected to the second power pin through a second connection hole.
The chip according to claim 2, wherein the wafer further includes a fourth power supply area, the fourth power supply area and the first power supply area, the second power supply area, and the third power supply The arrangement of the interval, the fourth power supply area includes a fourth pad and a fifth pad; the fifth pad in the fourth power supply area is connected to the end of the second conductive hole facing the mounting surface, The fourth pad in the fourth power supply area and the fourth pad in the third power supply area are connected by a third circuit located on the middle metal plate; the bottom metal plate is also provided with A third power pin. The third circuit is electrically connected to the third power pin through a third connection hole.
The chip according to claim 3, wherein the power supply pin and the ground pin are disposed in the middle of the bottom metal plate, and the first power pin and the second power pin And the third power pin is located at the edge of the bottom metal plate.
The chip according to claim 3, characterized in that the intermediate metal plate includes a first intermediate metal plate disposed toward the wafer, and a portion between the first intermediate metal plate and the bottom metal plate A second intermediate metal plate, the second circuit is provided on the first intermediate metal plate, and the first circuit and the third circuit are provided on the second intermediate metal plate.
The chip according to claim 1, wherein a first solder resist layer is provided on the mounting surface of the substrate, and a second solder resist layer is provided on the bonding surface of the substrate opposite to the mounting surface .
The chip according to claim 6, wherein the first solder resist layer and the second solder resist layer are both insulating layers.
The chip according to claim 1, wherein the chip further comprises a packaging cover, the packaging cover is provided on the wafer and connected to the mounting surface.
The chip according to claim 8, wherein the packaging cover is a plastic cover, a ceramic cover or a metal cover.
An electric appliance, characterized by comprising: the chip according to any one of claims 1-9.
A chip characterized by comprising: a substrate and a wafer mounted on the substrate;

A first power supply area, a second power supply area, a third power supply area, and a fourth power supply area that are sequentially arranged on the wafer; the first power supply area includes a first pad and a second pad, and the second power supply The area includes a second pad and a three pad; the third power supply area includes a third pad and a fourth pad, and the fourth power supply area includes a fourth pad and a five pad;

The first pad in the first power supply area serves as a power input terminal, the second pad in the first power supply area is connected to the second pad in the second power supply area, and the first power supply area The second pad in the area serves as the ground terminal of the first power supply area; the second pad in the second power supply area serves as the power supply terminal of the second power supply area, and the third in the second power supply area The pad is connected to the third pad in the third power supply area, and the third pad in the second power supply area serves as the ground terminal of the second power supply area; the third in the third power supply area The pad serves as a power end of the third power supply area, the fourth pad in the third power supply area is connected to the fourth pad in the fourth power supply area, and the fourth pad in the third power supply area The pad serves as the ground terminal of the third power supply area; the fourth pad in the fourth power supply area serves as the power supply terminal of the fourth power supply area, and the fifth pad in the fourth power supply area serves as the first 4. The ground terminal of the power supply area;

The substrate includes a stacked first intermediate metal plate, a second intermediate metal plate, a bottom metal plate, and an insulating plate provided between adjacent metal plates, and the wafer is provided on a mounting surface on the substrate ;

The bottom metal plate is disposed away from the mounting surface and the bottom metal plate is provided with a power supply pin, a ground pin, a first power pin, a second power pin, and a third power pin;

Conductive holes are provided on the first intermediate metal plate and the second intermediate metal plate so that the power supply pin is connected to the first pad, the ground pin is connected to the fifth pad, and the first The power supply pin is connected to the second pad, the second power pin is connected to the third pad, and the third power pin is connected to the fourth pad.
The chip according to claim 11, wherein the power supply pin and the ground pin are provided in the middle of the bottom metal plate; the first power pin and the second power pin 3. The third power pin is disposed at the edge of the bottom metal plate.
The chip according to claim 11 or 12, wherein the substrate is provided with a first conductive hole and a second conductive hole penetrating the substrate at intervals, the first conductive hole facing an end of the mounting surface Connected to the first pad in the first power supply area, the end of the first conductive hole facing away from the mounting surface is connected to the power supply pin; the end of the second conductive hole facing the mounting surface is connected to A fifth pad in the fourth power supply area is connected, and an end of the second conductive hole facing away from the mounting surface is connected to the ground pin.
The chip according to claim 13, wherein the first conductive hole and the second conductive hole are straight holes.
The chip according to claim 14, wherein there are a plurality of first conductive holes and second conductive holes.
The chip according to claim 15, wherein the first power pin is electrically connected to the second pad through the first connection hole, and the second power pin is connected to the third pad through the second connection hole For electrical connection, the third power pin is electrically connected to the fourth pad through a third connection hole; the first connection hole, the second connection hole, and the third connection hole are all plural.