WO2020093266A1 - Tranche, processeur intelligent et équipement électrique - Google Patents

Tranche, processeur intelligent et équipement électrique Download PDF

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Publication number
WO2020093266A1
WO2020093266A1 PCT/CN2018/114356 CN2018114356W WO2020093266A1 WO 2020093266 A1 WO2020093266 A1 WO 2020093266A1 CN 2018114356 W CN2018114356 W CN 2018114356W WO 2020093266 A1 WO2020093266 A1 WO 2020093266A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
supply area
pad
pads
wafer
Prior art date
Application number
PCT/CN2018/114356
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English (en)
Chinese (zh)
Inventor
杨帅
郭函
Original Assignee
北京比特大陆科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京比特大陆科技有限公司 filed Critical 北京比特大陆科技有限公司
Priority to PCT/CN2018/114356 priority Critical patent/WO2020093266A1/fr
Publication of WO2020093266A1 publication Critical patent/WO2020093266A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This application relates to the field of electrical equipment, for example, to a wafer, intelligent processor and electrical equipment.
  • a circuit board and an intelligent processor installed on the circuit board are provided in the electrical equipment, and the intelligent processor is electrically connected to the circuit on the circuit board.
  • an intelligent processor includes a wafer and a substrate.
  • the wafer has a first power supply area and a second power supply area spaced apart.
  • Each of the first power supply area and the second power supply area has a plurality of pads, and each A pad is electrically connected to a solder ball on the substrate; the substrate is connected to the circuit board, and the solder ball on the substrate is electrically connected to the circuit on the circuit board to realize the connection between the intelligent processor and the circuit board.
  • An embodiment of the present disclosure provides a wafer having a first power supply area on the wafer, the first power supply area including a plurality of first pads and a plurality of second pads; the first power supply area The first pad of the first power supply area is connected in parallel, and the second pad of the first power supply area is connected in parallel, and the first pad in the first power supply area is used as a power input end of the first power supply area to supply power for the first The internal components of the area supply power; the second pad in the first power supply area serves as the ground terminal of the first power supply area.
  • the wafer has a second power supply area spaced apart from the first power supply area, the second power supply area includes a plurality of second pads and third pads, The second pads in the second power supply area are connected in parallel, and the third pads in the second power supply area are connected in parallel; and the second pads in the second power supply area are used as the power input end of the second power supply area To supply power to the internal components of the second power supply area; the third pad in the second power supply area serves as the ground terminal of the second power supply area.
  • the second pad in the first power supply area is connected to the second pad in the second power supply area.
  • the wafer further includes a third power supply area, and the third power supply area is spaced apart from the first power supply area and the second power supply area, and the third power supply The area includes a plurality of third pads and a plurality of fourth pads;
  • the third pads in the third power supply area are connected in parallel, and the fourth pads in the third power supply area are connected in parallel; and the third pad in the third power supply area serves as the power input end of the third power supply area To supply power to the internal components of the third power supply area; the fourth pad in the third power supply area serves as the ground terminal of the third power supply area.
  • the third pad in the third power supply area is connected to the third pad in the second power supply area.
  • the internal components of the first power supply area, the second power supply area, and the third power supply area include multiple computing cores.
  • An embodiment of the present disclosure also provides an intelligent processor, including: a substrate and a wafer mounted on the substrate;
  • the wafer has a first power supply area, the first power supply area includes a plurality of first pads and a plurality of second pads; the first pads in the first power supply area are connected in parallel, the first The second pads in the power supply area are connected in parallel, and the first pads in the first power supply area are used as the power input end of the first power supply area to supply power to the internal components of the first power supply area; the first power supply The second pad in the area serves as the ground terminal of the first power supply area.
  • the wafer has a second power supply area spaced apart from the first power supply area, and the second power supply area includes a plurality of second pads and third pads , The second pads in the second power supply area are connected in parallel, and the third pads in the second power supply area are connected in parallel; and the second pads in the second power supply area are used as the power input of the second power supply area Terminal to power the internal components of the second power supply area; the third pad in the second power supply area serves as the ground terminal of the second power supply area.
  • the second pad in the first power supply area is connected to the second pad in the second power supply area.
  • the wafer further includes a third power supply area, and the third power supply area is spaced apart from the first power supply area and the second power supply area.
  • the power supply area includes multiple third pads and multiple fourth pads;
  • the third pads in the third power supply area are connected in parallel, and the fourth pads in the third power supply area are connected in parallel; and the third pad in the third power supply area serves as the power input end of the third power supply area To supply power to the internal components of the third power supply area; the fourth pad in the third power supply area serves as the ground terminal of the third power supply area.
  • the third pad in the third power supply area is connected to the third pad in the second power supply area.
  • the internal components of the first power supply area, the second power supply area, and the third power supply area include multiple computing cores.
  • a first circuit is provided on the substrate, and the second pad in the first power supply area and the second pad in the second power supply area pass through the first One circuit connection.
  • a second circuit is further provided on the substrate, and the third pad in the second power supply area and the third pad in the third power supply area pass through the Second circuit connection.
  • the smart processor as described above, preferably, the smart processor further includes a packaging cover, the wafer is provided on a mounting surface of the substrate, the packaging cover is provided on the wafer, and the The mounting surface is connected.
  • the packaging cover is a plastic cover, a ceramic cover or a metal cover.
  • the intelligent processor is preferably a chip.
  • An embodiment of the present disclosure also provides an electrical device, including: the intelligent processor as described above.
  • the intelligent processor and the electrical equipment provided by the embodiments of the present disclosure, by connecting the first pads in the first power supply area in parallel and the second pads in the first power supply area in parallel, the first One pad can be connected to the power supply through one or several first solder balls on the substrate, and the second pad of the first power supply area can be grounded through one or several second solder balls, so that the first solder balls and the second solder balls
  • the number is less than the number of all pads in the first power supply area; compared with a solder ball corresponding to each pad in the first power supply area, the number of solder balls on the substrate is reduced, thereby simplifying the substrate
  • the structure reduces the production cost.
  • FIG. 1 is a schematic structural diagram of an intelligent processor provided by this embodiment
  • FIG. 2 is a schematic structural diagram of a wafer provided by this embodiment.
  • the first power supply area
  • FIG. 2 is a schematic structural diagram of a wafer provided by this embodiment.
  • This embodiment provides a wafer 10 having a first power supply area 101 on the wafer 10, the first power supply area 101 includes a plurality of first pads and a plurality of second pads; the first solder in the first power supply area
  • the disks 1011 are connected in parallel, the second pads 1012 in the first power supply area are connected in parallel, and the first pads 1011 in the first power supply area serve as the power input end of the first power supply area 101, and the second pads in the first power supply area 1012 serves as the ground terminal of the first power supply area.
  • the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area may be metal sheets disposed on the wafer 10.
  • the first pad 1011 in the first power supply area is used as a power input terminal, and the first pad 1011 in the first power supply area can be connected to the power supply to the first pad 1011 in the first power supply area Provide a higher potential.
  • the second pad 1012 in the first power supply area as the ground terminal may be that the potential of the second pad 1012 in the first power supply area is zero, and of course the second pad 1012 in the first power supply area may not be zero , As long as the second pad 1012 in the first power supply area has a certain reference potential, so that there is a certain voltage between the first pad 1011 in the first power supply area and the second pad 1012 in the first power supply area can.
  • the first power supply area 101 includes a plurality of first pads and a plurality of second pads, and the first pads 1011 in the plurality of first power supply areas are arranged in parallel to each other.
  • the second pads 1021 in the plurality of first power supply regions are arranged in parallel to each other, and the first vertical column and the second vertical column are alternately arranged.
  • the first pads 1011 in each first power supply area may be connected in parallel for each first vertical column of the first pad.
  • the second pads 1012 in the first power supply area may be connected in parallel The second pads of each second vertical column are connected in parallel.
  • the parallel connection of the first pads 1011 in the first power supply area may be parallel to all the first vertical pads.
  • the parallel connection of the second pads 1012 in the first power supply area may be all The second pads of the second vertical column are connected in parallel.
  • the first pad 1011 in the first power supply area may be connected in parallel through the first connection metal layer with a certain pattern on the wafer 10, and similarly, the second pad 1012 in the first power supply area may be The second connecting metal layer with a certain pattern on the wafer 10 is connected in parallel.
  • the wafer 10 in this embodiment is provided on the mounting surface of the substrate, and the first solder ball and the second solder ball are provided on the bonding surface of the substrate opposite to the mounting surface, and the first pad in the first power supply area 1011 is connected to the power source through the first solder ball, and the second pad 1012 in the first power supply area is grounded through the second solder ball.
  • the first pad 1011 in the first power supply area in parallel and the second pad 1012 in the first power supply area in parallel by connecting the first pad 1011 in the first power supply area in parallel and the second pad 1012 in the first power supply area in parallel, the first pad 1011 in the first power supply area can pass through One or several first solder balls on the substrate are connected to the power supply, and the second pad 1012 of the first power supply area may be grounded through one or several second solder balls, so that the number of first solder balls and second solder balls is less than The number of all pads in the first power supply area 101; compared with each solder pad in the first power supply area 101, the number of solder balls on the substrate is reduced, thereby simplifying the structure of the substrate 20 , Reducing production costs.
  • the wafer 10 has a second power supply area 102 spaced apart from the first power supply area 101.
  • the second power supply area 102 includes a plurality of second pads and a third pad.
  • the two pads 1021 are connected in parallel, and the third pads 1022 in the second power supply area are connected in parallel; and the second pads 1021 in the second power supply area serve as the power input end of the second power supply area 102 to be the internal components of the second power supply area Power supply; the third pad 1022 in the second power supply area serves as the ground terminal of the second power supply area 102.
  • the second pads 1021 in the plurality of second power supply areas are arranged in parallel third columns, and the third pads 1022 in the second power supply areas are arranged in parallel fourth positions.
  • the vertical column, the third vertical column and the fourth vertical column are alternately arranged.
  • the second pads 1021 in each second power supply area may be connected in parallel for each second vertical pad, and correspondingly, the third pads 1022 in the second power supply area may be connected in parallel
  • the third pads of each fourth vertical column may be connected in parallel.
  • the parallel connection of the second pads 1021 in each second power supply area may be parallel of all second vertical second pads.
  • the parallel connection of the third pads 1022 in the second power supply area may be All third pads 1022 in the second vertical column are connected in parallel.
  • the second pad 1021 in the second power supply area may be connected in parallel through a third connection metal layer with a certain pattern on the wafer 10, and similarly, the third pad 1022 in the second power supply area may be The fourth connection metal layer with a certain pattern on the wafer 10 is connected in parallel.
  • the second pad 1012 in the first power supply area is connected to the second pad 1021 in the second power supply area. Only the first pad 1011 in the first power supply area and the second pad 1022 in the second power supply area can supply power to the first power supply area 101 and the second power supply area 102, so as to further reduce the installation on the substrate 20 Number of solder balls.
  • the wafer 10 further includes a third power supply area 103, which is spaced apart from the first power supply area 101 and the second power supply area 102.
  • the third power supply area 103 includes a plurality of third pads and A plurality of fourth pads; the third pad 1031 in the third power supply area is connected in parallel, and the fourth pad 1032 in the third power supply area is connected in parallel; and the third pad 1031 in the third power supply area serves as the third power supply area
  • the power input terminal of 103 is used to supply power to the internal components of the third power supply area; the fourth pad 1032 in the third power supply area serves as the ground terminal of the third power supply area 103.
  • the third pads 1031 in the plurality of third power supply areas are arranged in a plurality of fifth vertical columns parallel to each other, and the fourth pads 1032 in the plurality of third power supply areas are arranged in a plurality of parallel sixth numbers. Vertical columns, fifth vertical columns and sixth vertical columns are alternately arranged.
  • the third pad 1031 in the third power supply area may be connected in parallel through the fifth connecting metal layer with a certain pattern on the wafer 10, and similarly, the fourth pad 1032 in the third power supply area may be The sixth connection metal layer with a certain pattern on the wafer 10 is connected in parallel.
  • the third pad 1031 in the third power supply area is connected to the third pad 1022 in the second power supply area. It is only necessary to supply power to the first power supply area 101, the second power supply area 102, and the third power supply area 103 through the first pad 1011 in the first power supply area and the fourth pad 1032 in the third power supply area, to The number of solder balls provided on the substrate 20 is further reduced.
  • the internal components in the first power supply area, the internal components in the second power supply area, and the internal components in the third power supply include multiple computing cores.
  • the calculation core is provided on the wafer 10 and has a certain logical structure. The calculation core is used for data processing, calculation, and other operations.
  • the wafer 10 in this embodiment may also have four power supply areas, five power supply areas, etc .; correspondingly, each power supply area has an internal component and a pad connected to the internal component.
  • the disk as the power input end of the power supply area is connected to a pad of the previous power supply area, and the other pad of the power supply area is connected to a pad of the next power supply area as the ground terminal of the power supply area, that is, each The internal components in the power supply area are connected in series, so that only the first pad 1011 in the first power supply area is used as the power input terminal, and the last pad in the last power supply area is used as the ground terminal.
  • the internal parts are powered.
  • FIG. 1 is a schematic structural diagram of an intelligent processor provided in this embodiment. Please refer to Figure 1 and Figure 2.
  • This embodiment provides an intelligent processor, including: a substrate 20 and a wafer 10 mounted on a substrate 02; wherein the structure of the wafer 10 is substantially the same as that of the above-mentioned wafer 10, which will not be repeated here.
  • a first circuit is provided on the substrate 20, and the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area are connected by the first circuit.
  • the first circuit on the substrate 20 realizes the connection between the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area, which can avoid crystals caused by placing more metal pieces on the wafer 10 Circle 10 is difficult to process.
  • a second circuit is further provided on the substrate 20, and the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area are connected by a second circuit.
  • the connection between the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area can be achieved by the second circuit on the substrate 20, which can further avoid placing more metal on the wafer 10
  • the wafer 10 is difficult to process due to the wafer.
  • the first circuit connects the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area, and connects all the second pads 1012 in the first power supply area and all the first The second pads 1021 in the second power supply area are connected in parallel; similarly, the second circuit connects the third pads 1022 in the second power supply area and the third pads 1031 in the third power supply area The third pads 1022 in the power supply area and the third pads 1031 in all third power supply areas are connected in parallel.
  • the substrate 20 may include at least two metal plates and an insulating plate between two adjacent metal plates, and the corresponding first circuit and second circuit may be formed on the same metal plate; of course, in order to avoid the same metal plate
  • the circuit pattern on the above is relatively complicated, and the first circuit and the second circuit can be located on different metal layers.
  • the first circuit and the second circuit may be both provided on the metal plate of the substrate 20 near the mounting surface, or the first circuit and the second circuit are both provided on the metal plate of the substrate 20 near the bonding surface.
  • the first circuit is provided on the metal plate close to the mounting surface, and the second circuit is provided on the metal between the metal plate close to the mounting surface and the metal plate close to the bonding surface Board; or the first circuit is set on the metal plate near the bonding surface, and the second circuit is set on the metal plate between the metal plate near the mounting surface and the metal plate near the bonding surface; or the second circuit is set On the metal plate close to the mounting surface, and the first circuit is set on the metal plate between the metal plate close to the mounting surface and the metal plate close to the bonding surface; or the second circuit is set on the metal plate close to the bonding surface And the first circuit is provided on the metal plate between the metal plate close to the mounting surface and the metal plate close to the bonding surface.
  • the first circuit and the second circuit in this embodiment are metal plates with certain patterns formed by patterning the metal plates.
  • the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area can be directly connected to the first circuit when the first circuit is located On other metal plates, the second pad 1012 in the first power supply area and the second pad 1021 in the second power supply area can be connected to the first circuit through the via; similarly, when the second circuit is located close to the installation On the metal plate on the surface, the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area can be directly connected to the second circuit.
  • the third pad 1022 in the second power supply area and the third pad 1031 in the third power supply area may be connected to the second circuit through a via.
  • the intelligent processor further includes a packaging cover 30, the wafer 10 is disposed on the mounting surface of the substrate 20, the packaging cover 30 is disposed on the wafer 10, and is connected to the mounting surface.
  • the encapsulation cover 30 can seal the wafer 10, and at the same time, the encapsulation cover 30 can also protect the wafer 10 to prevent damage to the wafer 10 caused by contact of external objects with the wafer 10.
  • the package cover 30 is a plastic cover, a ceramic cover or a metal cover.
  • the intelligent processor in this embodiment is a chip.
  • an electrical device including: the intelligent processor as described above.
  • first, second, etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element” are consistently renamed and all occurrences of The “second component” can be renamed consistently.
  • the first element and the second element are both elements, but they may not be the same element.

Abstract

L'invention concerne une tranche (10), un processeur intelligent et un équipement électrique. La tranche (10) est pourvue d'une première zone d'alimentation électrique (101). La première zone d'alimentation électrique (101) comprend une pluralité de premiers plots de connexion (1011) et une pluralité de seconds plots de connexion (1012). Les premiers plots de connexion (1011) dans la première zone d'alimentation électrique (101) sont connectés en parallèle, les seconds plots de connexion (1012) dans la première zone d'alimentation électrique (101) sont connectés en parallèle, les premiers plots de connexion (1011) dans la première zone d'alimentation électrique (101) servent d'extrémité d'entrée de puissance de la première zone d'alimentation électrique (101) et les deuxièmes plots de connexion (1012) dans la première zone d'alimentation électrique (101) servent d'extrémité de mise à la terre de la première zone d'alimentation électrique (101), de sorte que les premiers plots de connexion (1011) dans la première zone d'alimentation électrique (101) puissent être connectés à une alimentation électrique au moyen d'une ou de plusieurs premières billes de soudure sur un substrat (20) et les secondes plots de connexion (1012) dans la première zone d'alimentation électrique puissent être mis à la terre au moyen d'une ou de plusieurs secondes billes de soudure. Le nombre de premières billes de soudure et le nombre de secondes billes de soudure sont inférieurs au nombre de tous les plots de connexion dans la première zone d'alimentation électrique (101). Par comparaison avec le mode selon lequel chaque plot de connexion dans la première zone d'alimentation électrique (101) est pourvu de manière correspondante d'une bille de soudure, le nombre de billes de soudure sur le substrat (20) est réduit, la structure du substrat (20) est simplifiée et le coût de production est réduit.
PCT/CN2018/114356 2018-11-07 2018-11-07 Tranche, processeur intelligent et équipement électrique WO2020093266A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/CN2018/114356 WO2020093266A1 (fr) 2018-11-07 2018-11-07 Tranche, processeur intelligent et équipement électrique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/114356 WO2020093266A1 (fr) 2018-11-07 2018-11-07 Tranche, processeur intelligent et équipement électrique

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WO2020093266A1 true WO2020093266A1 (fr) 2020-05-14

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1754259A (zh) * 2003-02-26 2006-03-29 三洋电机株式会社 半导体集成电路装置及其电源布线方法
CN102891146A (zh) * 2011-07-22 2013-01-23 瑞萨电子株式会社 半导体器件
US8659144B1 (en) * 2011-12-15 2014-02-25 Marvell International Ltd. Power and ground planes in package substrate
WO2017203607A1 (fr) * 2016-05-24 2017-11-30 株式会社野田スクリーン Connecteur intermédiaire, dispositif à semi-conducteur équipé d'un connecteur intermédiaire et procédé de fabrication du connecteur intermédiaire

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1754259A (zh) * 2003-02-26 2006-03-29 三洋电机株式会社 半导体集成电路装置及其电源布线方法
CN102891146A (zh) * 2011-07-22 2013-01-23 瑞萨电子株式会社 半导体器件
US8659144B1 (en) * 2011-12-15 2014-02-25 Marvell International Ltd. Power and ground planes in package substrate
WO2017203607A1 (fr) * 2016-05-24 2017-11-30 株式会社野田スクリーン Connecteur intermédiaire, dispositif à semi-conducteur équipé d'un connecteur intermédiaire et procédé de fabrication du connecteur intermédiaire

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