WO2020087669A1 - 一种薄膜晶体管制备方法及薄膜晶体管 - Google Patents

一种薄膜晶体管制备方法及薄膜晶体管 Download PDF

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WO2020087669A1
WO2020087669A1 PCT/CN2018/120413 CN2018120413W WO2020087669A1 WO 2020087669 A1 WO2020087669 A1 WO 2020087669A1 CN 2018120413 W CN2018120413 W CN 2018120413W WO 2020087669 A1 WO2020087669 A1 WO 2020087669A1
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layer
igzo
channel
drain electrode
thin film
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French (fr)
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胡小波
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the invention relates to the technical field of semiconductor materials, in particular to a method for preparing a thin film transistor and a thin film transistor.
  • IGZO indium gallium zinc oxide
  • IGZO thin film transistors using indium gallium zinc oxide as the semiconductor channel layer material have the advantages of high mobility, good uniformity, transparency, and simple process.
  • Liquid crystal display Liquid Crystal driven by IGZO-TFT Display, LCD
  • organic light-emitting diodes Organic Light-Emitting Diode (OLED) panel
  • performance advantages such as high precision, low power consumption and high touch performance.
  • IGZO TFT device Coefficients such as field-effect mobility, switching current ratio, threshold voltage, and sub-threshold coefficient are all more excellent, so they are widely used as active layers of TFTs in active matrix liquid crystal displays (Active Matrix Liquid Crystal Display, AMLCD) and active matrix organic light-emitting diode (Active-matrix organic light-emitting diode, AMOLED).
  • active matrix liquid crystal displays Active Matrix Liquid Crystal Display, AMLCD
  • active matrix organic light-emitting diode Active-matrix organic light-emitting diode
  • IGZO devices are generally ESL mechanisms. Because IGZO is not resistant to Peroxyacetyl Nitrate (PAN) acid, it is easily etched by PAN acid. The etching rate can reach 105nm / min. An etch barrier layer is deposited on the IGZO for protection, which is generally silicon dioxide (SiO 2 ). In this way, a mask is needed to increase the production cost.
  • PAN Peroxyacetyl Nitrate
  • Embodiments of the present invention provide a method for preparing a thin film transistor and a thin film transistor.
  • a Ti etching barrier layer is formed above the IGZO channel without adding a photomask to protect The IGZO layer is not affected by the Al acid etching solution, improving the device characteristics of the thin film transistor.
  • the present application provides a method for manufacturing a thin film transistor, the method includes:
  • the source-drain electrode layer is a MoAlMo composite film layer
  • the method further includes:
  • O ion implantation treatment is performed on the Ti film in the channel of the IGZO layer, and a large amount of O ions are implanted into the Ti film layer;
  • the step of forming photoresist patterns with different area thicknesses on the source-drain electrode layer includes:
  • a half-tone mask is used to form photoresist patterns with different area thicknesses.
  • the step of sequentially forming the gate layer, the gate insulating layer and the indium gallium zinc oxide IGZO layer on the glass substrate includes:
  • a IGZO layer of indium gallium zinc oxide is deposited by a sputtering process, and a pattern is formed through a yellow light process and an etching process.
  • the photoresist of the IGZO layer channel is thinner than the photoresist at both ends.
  • the step of etching the periphery of the source-drain electrode layer includes:
  • Dry etching is performed with an etching solution containing F or PAN acid to etch the peripheral source and drain electrode layers.
  • the steps of removing the photoresist of the IGZO layer channel and etching the MoAlMo film layer in the channel and ensuring that the Ti film is not etched include:
  • the MoAlMo film layer in the channel of the IGZO layer is etched with PAN-free acid.
  • the thickness of the Ti film is 10 ⁇ ⁇ 100 ⁇ .
  • the thickness of the Ti film is 20 ⁇ ⁇ 80 ⁇ .
  • the annealing temperature is 200-400 ° C.
  • the annealing time is 30 min-120 min.
  • the present application provides a method for manufacturing a thin film transistor, the method includes:
  • the source-drain electrode layer is a MoAlMo composite film layer
  • the remaining photoresist on the glass substrate is removed, and the passivation layer and the pixel electrode layer are sequentially manufactured.
  • the method also included:
  • O ion implantation treatment is performed on the Ti film in the channel of the IGZO layer, and a large amount of O ions are implanted into the Ti film layer;
  • the glass substrate is annealed in an O 2 environment, so that Ti and O ions combine to form an insulating TiO 2 thin film.
  • the step of sequentially forming the gate layer, the gate insulating layer and the indium gallium zinc oxide IGZO layer on the glass substrate includes:
  • IGZO layer of indium gallium zinc oxide is deposited by sputtering process, and patterned by yellow process and etching process;
  • the step of forming photoresist patterns with different area thicknesses on the source-drain electrode layer includes:
  • a half-tone mask is used to form photoresist patterns with different area thicknesses.
  • the photoresist of the IGZO layer channel is thinner than the photoresist at both ends.
  • the step of etching the periphery of the source-drain electrode layer includes:
  • Dry etching is performed with an etching solution containing F or PAN acid to etch the peripheral source and drain electrode layers.
  • the steps of removing the photoresist of the IGZO layer channel and etching the MoAlMo film layer in the channel and ensuring that the Ti film is not etched include:
  • the MoAlMo film layer in the channel of the IGZO layer is etched with PAN-free acid.
  • the gate layer is an AlMo composite film layer.
  • the thickness of the Ti film is 10 ⁇ ⁇ 100 ⁇ .
  • the thickness of the Ti film is 20 ⁇ ⁇ 80 ⁇ .
  • the annealing temperature is 200-400 ° C.
  • the annealing time is 30 min-120 min.
  • the present application provides a thin film transistor, the thin film transistor includes:
  • the gate layer is prepared on the surface of the glass substrate
  • a gate insulating layer prepared on the surface of the glass substrate and covering the gate layer;
  • An IGZO layer prepared on the surface of the gate insulating layer
  • Ti film prepared on the surface of the gate insulating layer, located on both sides of the IGZO layer;
  • a source-drain electrode layer prepared on the surface of the Ti film, includes a source electrode layer and a drain electrode layer, and a channel region is formed between the source electrode layer and the drain electrode layer;
  • the pixel electrode layer is prepared on the surface of the drain electrode layer.
  • a gate layer, a gate insulating layer and an indium gallium zinc oxide IGZO layer are sequentially formed on a glass substrate; a Ti film is deposited on the IGZO layer, and then a source-drain electrode layer is deposited, and the source-drain electrode layer is MoAlMo Composite film layer; forming photoresist patterns with different thicknesses on the source and drain electrode layer, and etching the periphery of the source and drain electrode layer; removing the photoresist of the IGZO layer channel, etching the MoAlMo film layer in the channel, and To ensure that the Ti film is not etched; remove the remaining photoresist on the glass substrate, and proceed to fabricate the passivation layer and the pixel electrode layer in sequence.
  • the etching difference between the Ti film and the MoAlMo film layer is used to form a Ti etching barrier layer above the IGZO channel without increasing the photomask, which can protect the IGZO layer from the Al acid etching solution To improve the device characteristics of thin film transistors.
  • FIG. 1 is a schematic flowchart of an embodiment of a method for manufacturing a thin film transistor provided in an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor provided in an embodiment of the present invention
  • FIG. 3 is a schematic structural view of a method for manufacturing a thin film transistor provided in an embodiment of the present invention after a gate layer and a gate insulating layer are sequentially formed on a glass substrate;
  • FIG. 4 is a schematic structural view of a method for manufacturing a thin film transistor provided in an embodiment of the present invention after an IGZO layer is formed on a gate insulating layer;
  • FIG. 5 is a schematic structural view after depositing a Ti film on the IGZO layer and then depositing a source-drain electrode layer in a method for manufacturing a thin film transistor provided in an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a method for manufacturing a thin film transistor provided in an embodiment of the present invention after forming photoresist patterns with different thicknesses on a source-drain electrode layer;
  • FIG. 7 is a schematic structural view after etching the periphery of the source-drain electrode layer in a method for manufacturing a thin film transistor provided in an embodiment of the present invention
  • FIG. 8 is a schematic structural view after removing the photoresist of the IGZO layer channel and etching the MoAlMo film layer in the channel and ensuring that the Ti film is not etched in a method for manufacturing a thin film transistor provided in an embodiment of the present invention
  • FIG. 9 is a schematic structural view of a method for preparing a thin film transistor provided by an embodiment of the present invention after the Ti film in the IGZO layer is modified to form an insulating TiO 2 film;
  • FIG. 10 is a schematic structural view after removing the remaining photoresist on the glass substrate in a method for manufacturing a thin film transistor provided in an embodiment of the present invention
  • FIG. 11 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present invention.
  • Thin-film transistors are one of the types of field-effect transistors, which are roughly fabricated by depositing various thin films on the substrate, such as semiconductor active layers, dielectric layers, and metal electrode layers. Thin film transistors play a very important role in the performance of display devices.
  • FIG. 1 it is a schematic diagram of an embodiment of a method for manufacturing a thin film transistor in an embodiment of the present invention.
  • the method includes:
  • S101, a gate layer, a gate insulating layer, and an indium gallium zinc oxide IGZO layer are sequentially formed on the glass substrate.
  • the steps of sequentially forming the gate layer, the gate insulating layer, and the indium gallium zinc oxide IGZO layer on the glass substrate may further include: sequentially forming the gate layer and the gate insulating layer on the glass substrate; using a sputtering process An IGZO layer of indium gallium zinc oxide is deposited, and a pattern is formed through a yellow light process and an etching process.
  • the gate layer may be an AlMo composite film layer.
  • the yellow light process and the etching process are conventional technical means in the art, and the specific process here is not described in detail.
  • the source-drain electrode layer is a MoAlMo composite film layer.
  • Depositing a Ti film over the IGZO layer, and then depositing the source-drain electrode layer includes: depositing the Ti film by a sputtering process, and then depositing the source-drain electrode layer. Further, depositing the source-drain electrode layer includes sequentially depositing the source electrode layer and the drain electrode layer.
  • the thickness of the Ti film deposited on the IGZO layer is 10 ⁇ ⁇ 100 ⁇ . In some embodiments of the present invention, in order to avoid material waste and have a good etching barrier, the thickness of the Ti film deposited on the IGZO layer is preferably 20 ⁇ -80 ⁇ .
  • S103 Form a photoresist pattern with different area thicknesses on the source-drain electrode layer, and etch the periphery of the source-drain electrode layer.
  • the step of forming photoresist patterns with different area thicknesses on the source-drain electrode layer may further include: forming a photoresist pattern with different area thicknesses using a half-tone reticle through the yellow light manufacturing process. Further, the photoresist of the IGZO layer channel is thinner than the photoresist at both ends.
  • the step of etching the periphery of the source-drain electrode layer includes: performing dry etching with an etching solution containing F or PAN acid to etch the peripheral source-drain electrode layer.
  • the step of removing the photoresist of the IGZO layer channel, etching the MoAlMo film layer in the channel, and ensuring that the Ti film is not etched may further include: performing O 2 ashing process to remove the Describe the photoresist of the IGZO layer channel; etch the MoAlMo film layer in the IGZO layer channel with F-free PAN acid. Since the PAN acid without F can only etch the MoAlMo film, not Ti, the Ti film above the channel is retained.
  • the types and thicknesses of the film layers such as the passivation layer and the pixel electrode layer are not limited.
  • the steps of removing the remaining photoresist on the glass substrate and sequentially manufacturing the passivation layer and the pixel electrode layer reference may be made to the implementation in the prior art, which will not be described in detail here.
  • a gate layer, a gate insulating layer and an indium gallium zinc oxide IGZO layer are sequentially formed on a glass substrate; a Ti film is deposited on the IGZO layer, and then a source-drain electrode layer is deposited, and the source-drain electrode layer is MoAlMo Composite film layer; forming photoresist patterns with different thicknesses on the source and drain electrode layer, and etching the periphery of the source and drain electrode layer; removing the photoresist of the IGZO layer channel, etching the MoAlMo film layer in the channel, and To ensure that the Ti film is not etched; remove the remaining photoresist on the glass substrate, and proceed to fabricate the passivation layer and the pixel electrode layer in sequence.
  • the etching difference between the Ti film and the MoAlMo film layer is used to form a Ti etching barrier layer above the IGZO channel without increasing the photomask, which can protect the IGZO layer from the Al acid etching solution To improve the device characteristics of thin film transistors.
  • the oxygen absorption property of the Ti film can also be used to modify the Ti film in the channel into a TiO 2 film to improve the performance of the thin film transistor.
  • FIG. 2 it is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor of the present invention.
  • the method includes:
  • a gate layer, a gate insulating layer and an IGZO layer are sequentially formed on the glass substrate.
  • the steps of sequentially forming the gate layer 20, the gate insulating layer 30 and the indium gallium zinc oxide IGZO layer 40 on the glass substrate 10 may further include: sequentially on the glass substrate 10 A gate layer 20 and a gate insulating layer 30 are formed; an indium gallium zinc oxide IGZO layer 40 is deposited by a sputtering process, and patterned through a yellow light process and an etching process.
  • the gate layer 20 may be an AlMo composite film layer, and the insulating layer refers to a GI layer.
  • the GI layer is formed by a process in an LTPS called GI Deposition, that is, GI layer deposition.
  • the yellow light process and the etching process are conventional technical means in the art, and the specific process here is not described in detail.
  • the source-drain electrode layer is a MoAlMo composite film layer.
  • depositing a Ti film over the IGZO layer, and then depositing the source-drain electrode layer includes: depositing the Ti film 50 by a sputtering process, and then depositing the source-drain electrode layer 60. Further, depositing the source-drain electrode layer 60 includes depositing the source electrode layer 61 and the drain electrode layer 62 in sequence.
  • a Ti film 50 is deposited on the IGZO layer 40 to a thickness of 10 ⁇ -100 ⁇ . In some embodiments of the present invention, in order to avoid material waste and have a good etching barrier, the thickness of the Ti film 50 deposited on the IGZO layer 40 is preferably 20 ⁇ -80 ⁇ .
  • the step of forming photoresist patterns with different area thicknesses on the source-drain electrode layer may further include: forming a light with different area thicknesses using a half-tone mask through the yellow light process 70-resist pattern. Further, the photoresist 70 of the IGZO layer 40 channel is thinner than the photoresist at both ends.
  • the step of etching the periphery of the source-drain electrode layer includes: performing dry etching with an etching solution containing F or PAN acid to etch the peripheral source-drain electrode layer 60. As shown in FIG. 7, the periphery of both sides of the source-drain electrode layer 60 above the gate insulating layer is etched away.
  • the step of removing the photoresist 70 of the IGZO layer 40 channel, etching the MoAlMo film layer in the channel, and ensuring that the Ti film 50 is not etched may further include: performing O 2 Ashing treatment, removing the photoresist 70 of the IGZO layer 40 channel; etching the MoAlMo film layer in the IGZO layer 40 channel with F-free PAN acid. Since the PAN acid without F can only etch the MoAlMo film layer, not Ti, the 50 layer of Ti film above the channel is retained.
  • the glass substrate is annealed in an O 2 environment with an annealing temperature of 200 to 400 ° C. and a time of 30 min to 120 min; in this way, Ti and O ions are combined, and defects in the film layer are repaired, and the Ti film in the IGZO layer channel is changed
  • the formation of insulating TiO 2 film improves the performance of thin film transistor devices.
  • the Ti film 50 in the channel of the IGZO layer 40 is modified to form an insulating TiO 2 film 80, while the Ti films 50 on both sides of the IGZO layer remain.
  • the remaining photoresist 70 on the glass substrate 10 is removed, and the passivation layer 90 and the pixel electrode layer 100 are sequentially manufactured.
  • the types and thicknesses of the film layers such as the passivation layer and the pixel electrode layer are not limited.
  • the steps of removing the remaining photoresist on the glass substrate and sequentially manufacturing the passivation layer and the pixel electrode layer reference may be made to the implementation in the prior art, which will not be described in detail here.
  • An embodiment of the present invention further provides a thin film transistor.
  • the thin film transistor includes:
  • the gate layer 20 is prepared on the surface of the glass substrate 10;
  • the gate insulating layer 30 is prepared on the surface of the glass substrate 10 and covers the gate layer 20;
  • the IGZO layer 40 is prepared on the surface of the gate insulating layer 30;
  • Ti film 50 prepared on the surface of the gate insulating layer 30, is located on both sides of the IGZO layer 40;
  • the source-drain electrode layer 60 prepared on the surface of the Ti film 50, includes a source electrode layer 61 and a drain electrode layer 62, and a channel region is formed between the source electrode layer 61 and the drain electrode layer 62;
  • the pixel electrode layer 100 is prepared on the surface of the drain electrode layer 60.
  • the thin film transistor further includes:
  • the TiO 2 thin film layer 80 is prepared on the surface of the IGZO layer 40 and covered by the passivation layer 90.

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Abstract

本发明实施例公开了一种薄膜晶体管制备方法及薄膜晶体管。该方法包括：在玻璃基板上形成栅极层、栅极绝缘层和IGZO层；在IGZO层上沉积Ti膜、源漏电极层并形成光刻胶图案，刻蚀源漏电极层外围；去掉沟道的光刻胶，刻蚀沟道内MoAlMo膜层；去掉剩余光刻胶，进行钝化层、像素电极层的制作。本发明实施例中提高了薄膜晶体管的器件特性。

Description

一种薄膜晶体管制备方法及薄膜晶体管 技术领域
本发明涉及半导体材料技术领域，具体涉及一种薄膜晶体管制备方法及薄膜晶体管。
 背景技术
IGZO(indium gallium zinc oxide) 为铟镓锌氧化物的缩写，以铟镓锌氧化物作为半导体沟道层材料的IGZO 薄膜晶体管有着迁移率高、均一性好、透明、工艺简单等优点。
由IGZO-TFT 驱动的液晶显示器（Liquid Crystal Display，LCD）和有机发光二极管（Organic Light-Emitting Diode, OLED）面板具有高精度、低功耗与高触控性能等诸多性能优势，其相对于传统非晶硅（a-Si）薄膜晶体管 (Thin Film Transistor，TFT)，IGZO TFT 器件在场效应迁移率、开关电流比、阀值电压以及亚阀值系数等方面的系数均表现更为优异，因此被作为TFT的有源层广泛应用于有源矩阵液晶显示器（Active Matrix Liquid Crystal Display，AMLCD）和有源矩阵有机发光二极体（Active-matrix organic light-emitting diode，AMOLED）中。
 技术问题
在常规的Al制程IGZO 器件一般为ESL机构，由于IGZO不耐过氧乙酰硝酸酯（Peroxyacetyl Nitrate，PAN）酸，极易被PAN酸刻蚀掉，刻蚀速率可以达到105nm/min，故需在IGZO上面沉积一层刻蚀阻挡层进行保护，一般为二氧化硅（SiO 2），如此需增加一道光罩从而增加了生产成本。
技术解决方案
本发明实施例提供一种薄膜晶体管制备方法及薄膜晶体管，利用Ti膜和MoAlMo膜层的刻蚀差异，在不增加光罩的前提下，在IGZO沟道上方形成Ti刻蚀阻挡层，可以保护IGZO层不受Al酸刻蚀液影响，提高薄膜晶体管的器件特性。
为解决上述问题，第一方面，本申请提供一种薄膜晶体管制备方法，该方法包括：
在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层；
在所述IGZO层之上沉积Ti膜，再沉积源漏电极层，所述源漏电极层为MoAlMo复合膜层；
在所述源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀所述源漏电极层的外围；
去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀；
将所述玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作；
其中，在去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层之后，将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作的步骤之前，所述方法还包括：
对所述IGZO层沟道内的Ti膜进行O离子注入处理，大量的O离子注入到Ti膜层里面；
将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜；
所述在所述源漏电极层之上形成区域厚度不同的光刻胶图案的步骤，包括：
经黄光制程用half-tone光罩，形成区域厚度不同的光刻胶图案。
进一步的，所述在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层的步骤，包括：
在玻璃基板上依次形成栅极层和栅极绝缘层；
用溅射工艺沉积铟镓锌氧化物IGZO层，并经黄光制程、刻蚀制程形成图案。
进一步的，所述IGZO层沟道的光刻胶比两端的光刻胶薄。
进一步的，所述刻蚀所述源漏电极层的外围的步骤，包括：
用含F的刻蚀液或PAN酸进行干法刻蚀，以刻蚀外围的源漏电极层。
进一步的，所述去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀的步骤，包括：
进行O 2灰化处理，去掉所述IGZO层沟道的光刻胶；
用不含F的PAN酸刻蚀所述IGZO层沟道内的MoAlMo膜层。
进一步的，所述Ti膜的厚度为10Å~100Å。
进一步的，所述Ti膜的厚度为20Å~80Å。
进一步的，所述将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜的步骤中，退火温度200~400℃，退火时间30min~120min。
第二方面，本申请提供一种薄膜晶体管制备方法，该方法包括：
在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层；
在所述IGZO层之上沉积Ti膜，再沉积源漏电极层，所述源漏电极层为MoAlMo复合膜层；
在所述源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀所述源漏电极层的外围；
去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀；
将所述玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作。
进一步的，在去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层之后，将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作的步骤之前，所述方法还包括：
对所述IGZO层沟道内的Ti膜进行O离子注入处理，大量的O离子注入到Ti膜层里面；
将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜。
进一步的，所述在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层的步骤，包括：
在玻璃基板上依次形成栅极层和栅极绝缘层；
用溅射工艺沉积铟镓锌氧化物IGZO层，并经黄光制程、刻蚀制程形成图案；
进一步的，所述在所述源漏电极层之上形成区域厚度不同的光刻胶图案的步骤，包括：
经黄光制程用half-tone光罩，形成区域厚度不同的光刻胶图案。
进一步的，其中，所述IGZO层沟道的光刻胶比两端的光刻胶薄。
进一步的，所述刻蚀所述源漏电极层的外围的步骤，包括：
用含F的刻蚀液或PAN酸进行干法刻蚀，以刻蚀外围的源漏电极层。
进一步的，所述去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀的步骤，包括：
进行O 2灰化处理，去掉所述IGZO层沟道的光刻胶；
用不含F的PAN酸刻蚀所述IGZO层沟道内的MoAlMo膜层。
进一步的，其中，所述栅极层为AlMo复合膜层。
进一步的，所述Ti膜的厚度为10Å~100Å。
进一步的，所述Ti膜的厚度为20Å~80Å。
进一步的，所述将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜的步骤中，退火温度200~400℃，退火时间30min~120min。
第二方面，本申请提供一种薄膜晶体管，所述薄膜晶体管包括：
玻璃基板；
栅极层，制备于所述玻璃基板表面；
栅极绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极层；
IGZO层，制备于所述栅极绝缘层表面；
Ti膜，制备于所述栅极绝缘层表面，位于所述IGZO层两侧；
源漏电极层，制备于所述Ti膜表面，包括源电极层和漏电极层，所述源电极层与所述漏电极层之间形成有沟道区域；
钝化层，包围所述源漏电极层；
像素电极层，制备于漏电极层表面。
 有益效果
本发明实施例方法在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层；在IGZO层之上沉积Ti膜，再沉积源漏电极层，源漏电极层为MoAlMo复合膜层；在源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀源漏电极层的外围；去掉IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀；将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作。本发明实施例中利用Ti膜和MoAlMo膜层的刻蚀差异，在不增加光罩的前提下，在IGZO沟道上方形成Ti刻蚀阻挡层，可以保护IGZO层不受Al酸刻蚀液影响，提高薄膜晶体管的器件特性。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例中提供的一种薄膜晶体管制备方法的一个实施例流程示意图；
图2是本发明实施例中提供的一种薄膜晶体管制备方法的另一个实施例流程示意图；
图3是本发明实施例中提供的一种薄膜晶体管制备方法中在玻璃基板上依次形成栅极层、栅极绝缘层后的结构示意图；
图4是本发明实施例中提供的一种薄膜晶体管制备方法中在栅极绝缘层形成IGZO层后的结构示意图；
图5是本发明实施例中提供的一种薄膜晶体管制备方法中在IGZO层之上沉积Ti膜，再沉积源漏电极层之后的结构示意图；
图6是本发明实施例中提供的一种薄膜晶体管制备方法中在源漏电极层之上形成区域厚度不同的光刻胶图案之后的结构示意图；
图7是本发明实施例中提供的一种薄膜晶体管制备方法中刻蚀源漏电极层的外围后的结构示意图；
图8是本发明实施例中提供的一种薄膜晶体管制备方法中去掉IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀之后的结构示意图；
图9是本发明实施例中提供的一种薄膜晶体管制备方法中IGZO层沟道内Ti膜改性形成了绝缘TiO 2薄膜之后的结构示意图；
图10是本发明实施例中提供的一种薄膜晶体管制备方法中将玻璃基板上剩余的光刻胶去掉之后的结构示意图；
图11是本发明实施例中提供的薄膜晶体管的结构示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
薄膜晶体管（Thin-film transistor，TFT）是场效应晶体管的种类之一，大略的制作方式是在基板上沉积各种不同的薄膜，如半导体主动层、介电层和金属电极层等。薄膜晶体管对显示器件的工作性能具有十分重要的作用.
如图1所示，为本发明实施例中薄膜晶体管制备方法的一个实施例示意图，该方法包括：
S101、在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层。
具体的，在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层的步骤可以进一步包括：在玻璃基板上依次形成栅极层和栅极绝缘层；用溅射工艺沉积铟镓锌氧化物IGZO层，并经黄光制程、刻蚀制程形成图案。其中，栅极层可以为AlMo复合膜层。另外，黄光制程和刻蚀制程均为本领域惯用技术手段，此处具体过程不在详细描述。
S102、在IGZO层之上沉积Ti膜，再沉积源漏电极层。
其中，源漏电极层为MoAlMo复合膜层。在IGZO层之上沉积Ti膜，再沉积源漏电极层包括：用溅射工艺沉Ti膜，再沉积源漏电极层。进一步的，沉积源漏电极层包括依次沉积源电极层和漏电极层。在IGZO层之上沉积Ti膜厚度为10Å~100Å。在本发明一些实施例中，为了避免材料浪费的同时具有良好的刻蚀阻挡作用，在IGZO层之上沉积Ti膜厚度优选为20Å~80Å。
S103、在源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀源漏电极层的外围。
其中，所述在所述源漏电极层之上形成区域厚度不同的光刻胶图案的步骤，进一步可以包括：经黄光制程用half-tone光罩，形成区域厚度不同的光刻胶图案。进一步的，所述IGZO层沟道的光刻胶比两端的光刻胶薄。
另外，进一步的，所述刻蚀所述源漏电极层的外围的步骤，包括：用含F的刻蚀液或PAN酸进行干法刻蚀，以刻蚀外围的源漏电极层。
S104、去掉IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀。
本发明实施例中，该去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀的步骤可以进一步包括：进行O 2灰化处理，去掉所述IGZO层沟道的光刻胶；用不含F的PAN酸刻蚀IGZO层沟道内的MoAlMo膜层。由于不含F的PAN酸只能刻蚀MoAlMo膜层，不能刻蚀Ti，故沟道上方的Ti膜层得到保留。
S105、将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作。
本发明实施例中，钝化层、像素电极层等各膜层类型和厚度不做限定。此外，将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作的步骤可以参考现有技术中的实现方式，此处不再详细描述。
本发明实施例方法在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层；在IGZO层之上沉积Ti膜，再沉积源漏电极层，源漏电极层为MoAlMo复合膜层；在源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀源漏电极层的外围；去掉IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀；将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作。本发明实施例中利用Ti膜和MoAlMo膜层的刻蚀差异，在不增加光罩的前提下，在IGZO沟道上方形成Ti刻蚀阻挡层，可以保护IGZO层不受Al酸刻蚀液影响，提高薄膜晶体管的器件特性。
在本发明另一些实施例中，在去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层之后，玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作的步骤之前，还可以利用Ti膜的吸氧特性，将沟道内的Ti膜改性成为TiO 2薄膜，以提升薄膜晶体管的性能。
具体的，如图2所示，为本发明薄膜晶体管制备方法的另一个实施例流程示意图，该方法包括：
S201、在玻璃基板上依次形成栅极层、栅极绝缘层和IGZO层。
具体的，如图3，图4所示，在玻璃基板10上依次形成栅极层20、栅极绝缘层30和铟镓锌氧化物IGZO层40的步骤可以进一步包括：在玻璃基板10上依次形成栅极层20和栅极绝缘层30；用溅射工艺沉积铟镓锌氧化物IGZO层40，并经黄光制程、刻蚀制程形成图案。其中，栅极层20可以为AlMo复合膜层，绝缘层指的是GI层，GI层通过一个LTPS中的工艺，叫GI Deposition也就是GI层沉积形成。另外，黄光制程和刻蚀制程均为本领域惯用技术手段，此处具体过程不在详细描述。
S202、在IGZO层之上沉积Ti膜，再沉积源漏电极层。
其中，源漏电极层为MoAlMo复合膜层。如图5所示，在IGZO层之上沉积Ti膜，再沉积源漏电极层包括：用溅射工艺沉Ti膜50，再沉积源漏电极层60。进一步的，沉积源漏电极层60包括依次沉积源电极层61和漏电极层62。在IGZO层40之上沉积Ti膜50厚度为10Å~100Å。在本发明一些实施例中，为了避免材料浪费的同时具有良好的刻蚀阻挡作用，在IGZO层40之上沉积Ti膜50厚度优选为20Å~80Å。
S203、在源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀所述源漏电极层的外围。
其中，如图6所示，在所述源漏电极层之上形成区域厚度不同的光刻胶图案的步骤，进一步可以包括：经黄光制程用half-tone光罩，形成区域厚度不同的光刻胶70图案。进一步的，所述IGZO层40沟道的光刻胶70比两端的光刻胶薄。
另外，进一步的，所述刻蚀所述源漏电极层的外围的步骤，包括：用含F的刻蚀液或PAN酸进行干法刻蚀，以刻蚀外围的源漏电极层60。如图7所示，栅极绝缘层上方的源漏电极层60两边外围被刻蚀掉了。
S204、去掉IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀。
本发明实施例中，如图8所示，该去掉IGZO层40沟道的光刻胶70，刻蚀沟道内MoAlMo膜层，并保证Ti膜50不被刻蚀的步骤可以进一步包括：进行O 2灰化处理，去掉所述IGZO层40沟道的光刻胶70；用不含F的PAN酸刻蚀IGZO层40沟道内的MoAlMo膜层。由于不含F的PAN酸只能刻蚀MoAlMo膜层，不能刻蚀Ti，故沟道上方的Ti膜50层得到保留。
S205、对IGZO层沟道内的Ti膜进行O离子注入处理，大量的O离子注入到Ti膜层里面。
S206、将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜。
具体的将玻璃基板在O 2环境下进行退火处理，退火温度200~400℃，时间30min~120min；如此Ti和O离子结合，并修复了膜层内的缺陷，使IGZO层沟道内Ti膜改性形成了绝缘TiO 2薄膜，提升了薄膜晶体管器件性能。具体如图9所示， IGZO层40沟道内Ti膜50改性形成了绝缘TiO 2薄膜80，而IGZO层两边的Ti膜50仍保留。
S207、将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作。
如图10、11所示，在完成上述步骤后，将玻璃基板10上剩余的光刻胶70去掉，并依次进行钝化层90、像素电极层100的制作。
同样的，本发明实施例中，钝化层、像素电极层等各膜层类型和厚度不做限定。此外，将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作的步骤可以参考现有技术中的实现方式，此处不再详细描述。
本发明实施例中还提供一种薄膜晶体管，如图11所示，所述薄膜晶体管包括：
玻璃基板10；
栅极层20，制备于所述玻璃基板10表面；
栅极绝缘层30，制备于所述玻璃基板10表面，且覆盖所述栅极层20；
IGZO层40，制备于所述栅极绝缘层30表面；
Ti膜50，制备于所述栅极绝缘层30表面，位于所述IGZO层40两侧；
源漏电极层60，制备于所述Ti膜50表面，包括源电极层61和漏电极层62，所述源电极层61与所述漏电极层62之间形成有沟道区域；
钝化层90，包围所述源漏电极层60；
像素电极层100，制备于漏电极层60表面。
进一步的，所述薄膜晶体管还包括：
TiO 2薄膜层80，制备于所述IGZO层40表面，被所述钝化层90覆盖。
以上对本发明实施例所提供的一种薄膜晶体管制备方法及薄膜晶体管进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种薄膜晶体管制备方法，其中，所述方法包括：
    在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层；
    在所述IGZO层之上沉积Ti膜，再沉积源漏电极层，所述源漏电极层为MoAlMo复合膜层；
    在所述源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀所述源漏电极层的外围；
    去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀；
    将所述玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作；
    其中，在去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层之后，将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作的步骤之前，所述方法还包括：
    对所述IGZO层沟道内的Ti膜进行O离子注入处理，大量的O离子注入到Ti膜层里面；
    将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜；
    所述在所述源漏电极层之上形成区域厚度不同的光刻胶图案的步骤，包括：
    经黄光制程用half-tone光罩，形成区域厚度不同的光刻胶图案。
  2. 根据权利要求1所述的薄膜晶体管制备方法，其中，所述在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层的步骤，包括：
    在玻璃基板上依次形成栅极层和栅极绝缘层；
    用溅射工艺沉积铟镓锌氧化物IGZO层，并经黄光制程、刻蚀制程形成图案。
  3. 根据权利要求1所述的薄膜晶体管制备方法，其中，所述IGZO层沟道的光刻胶比两端的光刻胶薄。
  4. 根据权利要求1所述的薄膜晶体管制备方法，其中，所述刻蚀所述源漏电极层的外围的步骤，包括：
    用含F的刻蚀液或PAN酸进行干法刻蚀，以刻蚀外围的源漏电极层。
  5. 根据权利要求1所述的薄膜晶体管制备方法，其中，所述去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀的步骤，包括：
    进行O 2灰化处理，去掉所述IGZO层沟道的光刻胶；
    用不含F的PAN酸刻蚀所述IGZO层沟道内的MoAlMo膜层。
  6. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述Ti膜的厚度为10Å~100Å。
  7. 根据权利要求6所述的薄膜晶体管的制备方法，其中，所述Ti膜的厚度为20Å~80Å。
  8. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜的步骤中，退火温度200~400℃，退火时间30min~120min。
  9. 一种薄膜晶体管制备方法，其中，所述方法包括：
    在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层；
    在所述IGZO层之上沉积Ti膜，再沉积源漏电极层，所述源漏电极层为MoAlMo复合膜层；
    在所述源漏电极层之上形成区域厚度不同的光刻胶图案，并刻蚀所述源漏电极层的外围；
    去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀；
    将所述玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作。
  10. 根据权利要求9所述的薄膜晶体管制备方法，其中，在去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层之后，将玻璃基板上剩余的光刻胶去掉，并依次进行钝化层、像素电极层的制作的步骤之前，所述方法还包括：
    对所述IGZO层沟道内的Ti膜进行O离子注入处理，大量的O离子注入到Ti膜层里面；
    将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜。
  11. 根据权利要求9所述的薄膜晶体管制备方法，其中，所述在玻璃基板上依次形成栅极层、栅极绝缘层和铟镓锌氧化物IGZO层的步骤，包括：
    在玻璃基板上依次形成栅极层和栅极绝缘层；
    用溅射工艺沉积铟镓锌氧化物IGZO层，并经黄光制程、刻蚀制程形成图案。
  12. 根据要求9所述的薄膜晶体管制备方法，其中，所述在所述源漏电极层之上形成区域厚度不同的光刻胶图案的步骤，包括：
    经黄光制程用half-tone光罩，形成区域厚度不同的光刻胶图案。
  13. 根据权利要求12所述的薄膜晶体管制备方法，其中，所述IGZO层沟道的光刻胶比两端的光刻胶薄。
  14. 根据权利要求9所述的薄膜晶体管制备方法，其中，所述刻蚀所述源漏电极层的外围的步骤，包括：
    用含F的刻蚀液或PAN酸进行干法刻蚀，以刻蚀外围的源漏电极层。
  15. 根据权利要求9所述的薄膜晶体管制备方法，其中，所述去掉所述IGZO层沟道的光刻胶，刻蚀沟道内MoAlMo膜层，并保证Ti膜不被刻蚀的步骤，包括：
    进行O 2灰化处理，去掉所述IGZO层沟道的光刻胶；
    用不含F的PAN酸刻蚀所述IGZO层沟道内的MoAlMo膜层。
  16. 根据权利要求9所述的薄膜晶体管制备方法，其中，所述栅极层为AlMo复合膜层。
  17. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述Ti膜的厚度为10Å~100Å。
  18. 根据权利要求17所述的薄膜晶体管的制备方法，其中，所述Ti膜的厚度为20Å~80Å。
  19. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述将玻璃基板在O 2环境下进行退火处理，使得Ti和O离子结合形成绝缘TiO 2薄膜的步骤中，退火温度200~400℃，退火时间30min~120min。
  20. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    玻璃基板；
    栅极层，制备于所述玻璃基板表面；
    栅极绝缘层，制备于所述玻璃基板表面，且覆盖所述栅极层；
    IGZO层，制备于所述栅极绝缘层表面；
    Ti膜，制备于所述栅极绝缘层表面，位于所述IGZO层两侧；
    源漏电极层，制备于所述Ti膜表面，包括源电极层和漏电极层，所述源电极层与所述漏电极层之间形成有沟道区域；
    钝化层，包围所述源漏电极层；
    像素电极层，制备于漏电极层表面。
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