WO2020082940A1 - 一种飞跨电容的充电方法及装置 - Google Patents

一种飞跨电容的充电方法及装置 Download PDF

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Publication number
WO2020082940A1
WO2020082940A1 PCT/CN2019/106278 CN2019106278W WO2020082940A1 WO 2020082940 A1 WO2020082940 A1 WO 2020082940A1 CN 2019106278 W CN2019106278 W CN 2019106278W WO 2020082940 A1 WO2020082940 A1 WO 2020082940A1
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Prior art keywords
capacitor
voltage value
circuit
flying
set voltage
Prior art date
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PCT/CN2019/106278
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English (en)
French (fr)
Inventor
姜一鸣
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to AU2019367448A priority Critical patent/AU2019367448B9/en
Priority to EP19875633.0A priority patent/EP3780322B1/en
Publication of WO2020082940A1 publication Critical patent/WO2020082940A1/zh
Priority to US17/103,250 priority patent/US11463009B2/en

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    • H02J7/0072—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/44—Methods for charging or discharging
    • H02J7/0077—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4837—Flying capacitor converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/20—Charging or discharging characterised by the power electronics converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • the present application relates to the field of power electronics technology, and in particular, to a flying capacitor charging method and device.
  • a DC-DC converter circuit (DCDC circuit for short) is a circuit that boosts or reduces DC. Its input and output are DC. DCDC circuits are widely used in energy storage, electric vehicles, new energy, power systems, electronic computers and other fields.
  • the topological form of the DCDC circuit can be divided into two-level topology and multi-level topology according to the state of the output level.
  • the multi-level topology is relative to the traditional two-level topology.
  • the two-level topology means that the output level has only two states of 0 and 1.
  • the multi-level topology means that the output level has at least three states, such as output power. There are three states of level 1, 1/2 and 0 called three-level topology, and five states of output level 1, 3/4, 1/2, 1/4 and 0 are called five-level topology.
  • the multilevel topology circuit is divided into diode clamp type multilevel topology circuit, flying capacitor clamp type multilevel topology circuit and other forms.
  • FIG. 1 shows a flying capacitor clamp type three-level topology buck circuit.
  • the voltage of the flying capacitor Cfly is controlled to 1/2 * Vin, T1 and T4 are alternately turned on, and T2 and T3 are alternately turned on.
  • the flying capacitor Cfly needs to be charged to half of the input voltage Vin.
  • the charging circuit shown in FIG. 2 can be used to precharge the flying capacitor in the multilevel topology circuit.
  • This charging circuit can be regarded as another circuit independent of the multi-level topology circuit, and is only used for precharging the flying capacitor.
  • four resistors R1, R2, R3, and R4 and corresponding control switches form an RC network to charge the flying capacitor C. That is, close the four switches S1.1, S1.2, S2.1, and S2.2.
  • R1 and R4 are divided to obtain the upper end voltage Vp of the flying capacitor C, and R2 and R3 are divided.
  • Vp-Vn is the voltage across the capacitor.
  • the flying capacitor charging scheme provided in the prior art has the problems of high circuit cost and poor applicability of the scheme.
  • Embodiments of the present application provide a flying capacitor charging method and device, to provide a flying capacitor charging solution with a small board area, simple implementation, and strong applicability.
  • an embodiment of the present application provides a flying capacitor charging method.
  • the method is applied to a flying capacitor clamped multi-level topology circuit.
  • the multi-level topology circuit is connected to an input power supply through a first switch.
  • the topology circuit is connected to the output power supply through the second switch, and the multi-level topology circuit includes one or more flying capacitors; the first end of the first capacitor in the one or more flying capacitors and the first One electrode is connected, the second end of the first capacitor is connected to the second electrode of the second semiconductor switch tube, and the second electrode of the first semiconductor switch tube is connected to the first electrode of the second semiconductor switch tube through the second capacitor; wherein,
  • the first capacitor is any flying capacitor in one or more flying capacitors, and the second capacitor is an input capacitor, an output capacitor, or another flying capacitor other than the first capacitor in the one or more flying capacitors.
  • the method includes the following steps: closing the first semiconductor switch tube and the second semiconductor switch tube, so that the first capacitor and the second capacitor are connected in parallel; charging the first capacitor and the second capacitor to the first set voltage value; off Turn on the first semiconductor switch tube and the second semiconductor switch tube; charge the second capacitor to the second set voltage value.
  • the flying capacitor can be charged using the existing structure in the multi-level topology circuit.
  • the above scheme does not require an additional charging circuit for the flying capacitor Charging reduces costs and the applicability of the solution is strong.
  • the first capacitor is any flying capacitor
  • the second capacitor is an input capacitor, an output capacitor, or another flying capacitor, disconnecting the multilevel topology circuit from the input power supply and the output power supply After the connection is opened, the first capacitor and the second capacitor are charged to the ideal voltage value, respectively. After pre-charging all the flying capacitors in the multi-level circuit, all flying capacitors in the circuit can be charged to the ideal voltage value, so as to avoid the occurrence of semiconductor switching tubes due to excessive The problem of damage due to pressure.
  • the multilevel topology circuit may be a circuit used only for step-down or step-up only, or may be a buck-boost converter circuit.
  • charging can be started from the input side (that is, an external DC power source is connected in parallel at both ends of the input capacitor, or by slowing down
  • the resistor is connected to the input power supply to charge the flying capacitor
  • charging can also be started from the output side (that is, an external DC power source is connected in parallel at both ends of the output capacitor, or the flying capacitor is charged by connecting the output power to the output power through a slow-up resistor).
  • the flying capacitor and the input capacitor in the circuit will be charged first. Then, after the charging of one or more flying capacitors and the input capacitor is completed, the first switch can be closed; then, the multi-level topology circuit is adjusted to the normal working state, and the output capacitor is charged to the third set voltage value, The third set voltage value is the voltage value of the output power supply; finally, the second switch is closed.
  • the output capacitor can continue to be charged. After all flying capacitors, input capacitors, and output capacitors in the circuit are fully charged, the multi-level topology circuit can work normally.
  • the flying capacitor and the output capacitor in the circuit will be charged first. Then, after the charging of one or more flying capacitors and the output capacitor is completed, the second switch can be closed; then, the multi-level topology circuit is adjusted to the normal working state, and the input capacitor is charged to the fourth set voltage value, The fourth set voltage value is the voltage value of the input power supply; finally, the first switch is closed.
  • the input capacitor can be continuously charged. After all flying capacitors, input capacitors, and output capacitors in the circuit are fully charged, the multi-level topology circuit can work normally.
  • charging can be started from the input side or from the output side.
  • the multilevel topology circuit is a buck-boost converter circuit, and the first part of the flying capacitor
  • the capacitor is all flying capacitors in the buck circuit or boost circuit where the first capacitor is located; then, the multilevel topology circuit can be adjusted to a normal working state, and the output capacitor can be controlled to charge to the fifth set voltage value, the fifth Set the voltage value to the voltage value of the output power supply; and control the second part of the one or more flying capacitors to charge to their respective ideal voltage values; finally, close the second switch.
  • the output capacitor and the second part of the flying capacitor can be charged. After all flying capacitors, input capacitors, and output capacitors in the circuit are fully charged, the multi-level topology circuit can work normally.
  • the multilevel topology circuit is a buck-boost converter circuit, and the first part of the flying capacitor
  • the capacitance is all flying capacitors in the buck circuit or boost circuit where the first capacitor is located; then, the multi-level topology circuit can be adjusted to a normal working state, and the input capacitor is charged to the sixth set voltage value, the sixth Set the voltage value to the voltage value of the input power supply; and control the second part of the one or more flying capacitors to charge to their respective ideal voltage values; finally, close the first switch.
  • the input capacitor and the second part of the flying capacitor can continue to be charged. After all flying capacitors, input capacitors, and output capacitors in the circuit are fully charged, the multi-level topology circuit can work normally.
  • the first set voltage value is U * 1/2 N and the second set voltage value is U * 1/2 N-1 , where U is the voltage value of the input power supply or the output voltage Voltage value, N is a positive integer.
  • the first capacitor is charged to the first set voltage value, which may be implemented in any one of the following two ways: charging the first capacitor to the first set voltage through an external DC power supply Or, connect the input power or output power through the slow-start resistor to charge the first capacitor to the first set voltage value.
  • the external capacitor can be used to charge the first capacitor and the second capacitor, or the first capacitor and the second capacitor can be charged through the input power or output power connected to the slow-start resistor.
  • the external capacitor can be used to charge the first capacitor and the second capacitor, or the first capacitor and the second capacitor can be charged through the input power or output power connected to the slow-start resistor.
  • an external DC power supply for a multi-level topology with multiple parallel connections, only one external DC power supply can be used to charge the capacitors in the multi-path topology circuit, so as to achieve cost savings.
  • an embodiment of the present application provides a flying capacitor charging device, which includes a multi-level topology circuit and a controller.
  • the multi-level topology circuit is connected to the input power supply through the first switch, and the multi-level topology circuit is connected to the output power supply through the second switch.
  • the multi-level topology circuit contains one or more flying capacitors;
  • the first end of the first capacitor in the transcapacitor is connected to the first electrode of the first semiconductor switch, the second end of the first capacitor is connected to the second electrode of the second semiconductor switch, and the second The electrode is connected to the first electrode of the second semiconductor switch via a second capacitor; wherein, the first capacitor is any one of one or more flying capacitors, and the second capacitor is an input capacitor, an output capacitor, or one or The other flying capacitor of the plurality of flying capacitors except the first capacitor.
  • the controller is used to: close the first semiconductor switch tube and the second semiconductor switch tube, so that the first capacitor and the second capacitor are connected in parallel; charge the first capacitor and the second capacitor to the first set voltage value; open the first The semiconductor switch tube and the second semiconductor switch tube; charge the second capacitor to the second set voltage value.
  • the controller is also used to: after one or more flying capacitors and input capacitors are charged, close the first switch; adjust the multi-level topology circuit to a normal working state and control the output The capacitor is charged to the third set voltage value, and the third set voltage value is the voltage value of the output power supply; the second switch is closed.
  • the controller is also used to: after one or more flying capacitors and output capacitors are charged, close the second switch; adjust the multilevel topology circuit to a normal working state and control the input
  • the capacitor is charged to the fourth set voltage value, and the fourth set voltage value is the voltage value of the input power supply; the first switch is closed.
  • the controller is also used to close the first switch after the first part of the one or more flying capacitors and the input capacitors are fully charged; wherein, the multilevel topology circuit It is a buck-boost converter circuit.
  • the first part of the flying capacitor is all the flying capacitors in the buck circuit or boost circuit where the first capacitor is located; adjust the multilevel topology circuit to the normal working state, and control the output capacitor to charge
  • the fifth set voltage value, the fifth set voltage value is the voltage value of the output power supply; and, controls the second part of the one or more flying capacitors to charge to their respective ideal voltage values; close the second switch.
  • the controller is also used to close the second switch after the first part of the one or more flying capacitors and the output capacitor are fully charged; wherein, the multi-level topology circuit It is a buck-boost converter circuit.
  • the first part of the flying capacitor is all flying capacitors in the buck circuit or boost circuit where the first capacitor is located; adjust the multilevel topology circuit to the normal working state and control the input capacitor to charge
  • the sixth set voltage value, the sixth set voltage value is the voltage value of the input power supply; and, controls the second part of the one or more flying capacitors to charge to their respective ideal voltage values; close the first switch.
  • the first set voltage value may be U * 1/2 N
  • the second set voltage value may be U * 1/2 N-1 , where U is the voltage value of the input power supply or The voltage value of the output voltage, N is a positive integer.
  • the controller when the controller charges the first capacitor to the first set voltage value, it is specifically used to: charge the first capacitor to the first set voltage value through an external DC power supply; or, The slow-start resistor is connected to the input power supply or the output power supply to charge the first capacitor to the first set voltage value.
  • an embodiment of the present application provides a computer-readable storage medium having instructions stored therein, which when executed on a computer, causes the computer to perform the first aspect described above and various possible The method described in the design.
  • an embodiment of the present application further provides a computer program product containing instructions, which when executed on a computer, causes the computer to execute the method described in the first aspect and its various possible designs.
  • an embodiment of the present application further provides a computer chip, the chip is connected to a memory, the chip is used to read and execute a software program stored in the memory, and execute the first aspect and its various possibilities The method described in the design.
  • FIG. 1 is a schematic structural diagram of a flying capacitor clamp type three-level topology buck circuit provided by the prior art
  • FIG. 2 is a schematic structural diagram of a charging circuit provided by the prior art
  • FIG. 3 is a schematic diagram of voltages of various semiconductor switch tubes in a multilevel topology circuit provided by an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a first multi-level topology circuit provided by an embodiment of this application.
  • FIG. 5 is a schematic flowchart of a method for charging a flying capacitor provided by an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a second multi-level topology circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a third multi-level topology circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a fourth multi-level topology circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a fifth multilevel topology circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a sixth multi-level topology circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a flying capacitor charging device according to an embodiment of the present application.
  • the embodiments of the present application provide a flying capacitor charging method and device, which are used to provide a flying capacitor charging solution with a small board area, simple implementation, and strong applicability.
  • the method and the device are based on the same inventive concept. Since the principles of the method and the device to solve the problem are similar, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • the flying capacitor charging method provided by the embodiment of the present application can be applied to the three-level topology buck circuit shown in FIG. 4.
  • the circuit includes an input power source DC1, an output power source DC2, an input capacitor Cin, an output capacitor Cout, an inductance L, a flying capacitor Cfly, a first switch K1, a second switch K2, and four semiconductor switch tubes T1, T2, T3, T4 .
  • the semiconductor switching tube may be an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • IGBT insulated gate bipolar transistor
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • a buck circuit is formed by Cin, Cout, Cfly, L, T1, T2, T3, and T4.
  • the buck circuit is connected to DC1 through K1 and to the output power supply through K2.
  • the multilevel topology circuit contains a flying capacitor Cfly; the first end of Cfly is connected to the emitter of T1, the second end of Cfly is connected to the collector of T4, and the collector of T1 is connected to the emitter of T4 through Cin .
  • the emitter of T2 is connected to the collector of T3 and the first end of L
  • the collector of T2 is connected to the emitter of T1
  • the emitter of T3 is connected to the collector of T4
  • the first end of Cout is connected to L
  • the second end of Cout is connected to the emitter of T4.
  • K1 and K2 can be kept off. Then, close T1 and T4 to connect Cfly and Cin in parallel, and charge Cfly and Cin at the same time: after Cfly charging is completed, disconnect T1 and T4 and continue to charge Cin. After Cfly and Cin are charged, K1 can be closed to charge Cout. After all the capacitors in the circuit are charged, K2 can be closed to make the circuit work normally.
  • FIG. 4 is only a specific example of the topology structure to which the embodiments of the present application apply.
  • the flying capacitor charging scheme provided by the embodiments of the present application may be applicable to various multilevel topology circuits.
  • the multilevel topology circuits applicable to the embodiments of the present application all include circuit structures that conform to the similar connection relationships of Cfly, Cin, T1, and T4 in FIG. 4. Therefore, in various multilevel topological circuits, the solutions provided by the embodiments of the present application can be used to control the charging of capacitors such as Cfly and Cin, and the state of semiconductor switch tubes such as T1 and T4, so as to realize the flying in the circuit. Charging across the capacitor.
  • FIG. 5 it is a schematic flowchart of a flying capacitor charging method provided by an embodiment of the present application. This method is applied to multi-level topology circuits clamped by flying capacitors. Among them, the multi-level topology circuit is connected to the input power supply through the first switch, and the multi-level topology circuit is connected to the output power supply through the second switch.
  • the multi-level topology circuit contains one or more flying capacitors;
  • the first end of the first capacitor in the transcapacitor is connected to the first electrode of the first semiconductor switch, the second end of the first capacitor is connected to the second electrode of the second semiconductor switch, and the second The electrode is connected to the first electrode of the second semiconductor switch via a second capacitor; wherein, the first capacitor is any one of one or more flying capacitors, and the second capacitor is an input capacitor, an output capacitor, or one or The other flying capacitor of the plurality of flying capacitors except the first capacitor.
  • the method includes the following steps:
  • S501 Close the first semiconductor switch tube and the second semiconductor switch tube, so that the first capacitor and the second capacitor are connected in parallel.
  • the semiconductor switching tube may be an IGBT or a MOSFET. If the semiconductor switch in the embodiment of the present application is an IGBT, the first electrode may be an emitter and the second electrode may be a collector; if the semiconductor switch in the embodiment of the present application is a MOSFET, the first electrode may be a drain Electrode, the second electrode may be the source electrode.
  • the solution provided by the embodiments of the present application is used to precharge the flying capacitor before the multi-level topology circuit works normally.
  • the first switch and the second switch in the multi-level topology circuit may be normally open Switch, that is, the switch is in the off state by default. Therefore, when S501 is executed, the multi-level topology circuit has not been powered on, that is, the first switch and the second switch are in an off state.
  • charging the first capacitor means that the second capacitor is also charged.
  • the first capacitor is any flying capacitor in one or more flying capacitors
  • the second capacitor is an input capacitor, an output capacitor, or another flying capacitor other than the first capacitor in the one or more flying capacitors. Therefore, when the first capacitor and the second capacitor are connected in parallel, the two flying capacitors can be charged at the same time, or the input capacitor and the flying capacitor can be charged at the same time, or the output capacitor and the flying capacitor can be charged at the same time.
  • S502 Charge the first capacitor and the second capacitor to the first set voltage value.
  • the first set voltage value is the voltage value of the first capacitor in the normal working state.
  • the first set voltage value is 1/2 * Vin.
  • charging the first capacitor to the first set voltage value may be achieved in two ways as follows: In the first method, the first capacitor is charged to the first set voltage value through an external DC power supply; In two ways, the first capacitor is charged to the first set voltage value by connecting the slow start resistor to the input power supply or the output power supply.
  • the capacitor when charging the capacitor, the capacitor can be charged by an external DC power supply, or the input power or the output power supply connected to the slow-start resistor can be used to charge the capacitor.
  • the slow-start resistance mainly plays a role of current limiting to prevent the components in the circuit from being burned due to excessive current when powered on.
  • the slow-start resistor can also be called a current limiting resistor.
  • the multi-level topology circuit contains at least two flying capacitors.
  • the multi-level topology circuit may be a five-level topology circuit or a nine-level topology circuit. Topology circuit, etc.
  • S503 Disconnect the first semiconductor switch tube and the second semiconductor switch tube.
  • the first capacitor and the second capacitor are no longer in parallel relationship; subsequent charging of the second capacitor will not affect the voltage value of the first capacitor.
  • S504 Charge the second capacitor to the second set voltage value.
  • the second set voltage value is the voltage value of the second capacitor in the normal working state.
  • the flying capacitor Cfly is equivalent to the first capacitor, if the input capacitor Cin is equivalent to the second capacitor, the second set voltage value is Vin; if the output capacitor Cout is equivalent to the second capacitor , Then the second set voltage value is Vout.
  • the first set voltage value may be U * 1/2 N
  • the second set voltage value may be U * 1/2 N-1 , where U is the voltage value of the input power supply or the output voltage Voltage value, N is a positive integer.
  • U the voltage value of the input power supply or the output voltage Voltage value
  • N a positive integer.
  • the flying capacitor Cfly is equivalent to the first capacitor
  • the input capacitor Cin is equivalent to the second capacitor.
  • N 1 can be taken, and the first set voltage value can be 1/2 * Vin
  • the second set voltage value is Vin.
  • the flying capacitor shown in FIG. 5 can be charged to the first capacitor and the second capacitor method. That is to say, the embodiments of the present application are applicable to a variety of multi-level topology circuits, including but not limited to N-way parallel bidirectional buck-boost circuit, three-level bidirectional buck circuit, five-level topology circuit, nine-level topology circuit Wait.
  • the embodiments of the present application can be applied to the N-way parallel bidirectional buck-boost circuit shown in FIG. 6.
  • the flying capacitor Ca can be regarded as the first capacitor, the input capacitor Cin as the second capacitor, T1a as the first semiconductor switch, and T4a as the second semiconductor switch ; You can also consider the flying capacitor Cb as the first capacitor, the output capacitor Cout as the second capacitor, T1b as the first semiconductor switch, and T4b as the second semiconductor switch.
  • Cb and Cout can be charged by an external DC power supply when performing the method shown in FIG. 5, or Cb and Cout can be charged by the output power DC connected to the slow-start resistor source2
  • the embodiments of the present application can be applied to the three-level bidirectional BUCK circuit shown in FIG. 4.
  • the flying capacitor Cfly can be regarded as the first capacitor, the input capacitor Cin as the second capacitor, T1 as the first semiconductor switch, and T4 as the second semiconductor switch .
  • Cfly and Cin can be charged through an external DC power supply when performing the method shown in Figure 5, or Cfly and Cin can be charged through the input power source DC connected to the slow-start resistor. Or, you can charge Cfly and Cin through the output power DC2 source connected to the slow-start resistor. At this time, the output capacitor Cout is also charged.
  • the first switch K1 can be closed and the circuit shown in FIG. 4 can be adjusted to a normal working state, and Cout continues to be charged to an ideal voltage value. Then close the second switch, the circuit shown in Figure 4 can work normally.
  • the embodiments of the present application can be applied to the three-level bidirectional BOOST circuit shown in FIG. 7.
  • the flying capacitor Cfly can be regarded as the first capacitor, the output capacitor Cout as the second capacitor, T1 as the first semiconductor switch, and T4 as the second semiconductor switch .
  • Cfly and Cout can be charged by an external DC power supply when performing the method shown in Figure 5, or Cfly and Cout can be charged by the output power source DC2 connected to the slow-start resistor Or, you can charge Cfly and Cout through the input power DC1 connected to the slow-start resistor. At this time, the output capacitor Cin is also charged.
  • the second switch K2 can be closed and the circuit shown in FIG. 7 can be adjusted to a normal working state, and Cin continues to be charged to an ideal voltage value. Then the first switch K1, the circuit shown in FIG. 7 can work normally.
  • the embodiments of the present application can be applied to the five-level topology circuit shown in FIG. 8.
  • the flying capacitor Cfly1 can be regarded as the first capacitor
  • the flying capacitor Cfly2 can be regarded as the second capacitor.
  • T2 is the first semiconductor switch tube and T5 is the second semiconductor switch tube;
  • the flying capacitor Cfly2 may be regarded as the first capacitor
  • the input capacitor Cin may be regarded as the second capacitor.
  • T1 is the first semiconductor switch and T6 is the second semiconductor switch.
  • T1, T2, T5, and T6 can be closed at the same time, and Cfly1, Cfly2, and Cin can be simultaneously charged. After charging Cfly1 to 1/4 * Vin, you can disconnect T2 and T5, and then continue to charge Cfly2 and Cin. After charging Cfly2 to 1/2 * Vin, T1 and T6 can be disconnected. Then, continue to charge Cin.
  • the first switch K1 may be closed and the circuit shown in FIG. 8 may be adjusted to a normal working state, and Cout may continue to be charged to an ideal voltage value. Then, the second switch K2 is closed, and the circuit shown in FIG. 8 can work normally.
  • the multilevel topology circuit is the circuit shown in FIG. 4, FIG. 7 or FIG. 8 used only for step-down or step-up only, in specific implementation, charging can be started from the input side (That is, the external DC power supply is connected in parallel at both ends of the input capacitor, or is connected to the input power supply through the slow-down resistor to charge the flying capacitor), you can also start charging from the output side (that is, the external DC power supply is connected in parallel at both ends of the output capacitor, or Charge the flying capacitor by connecting the slow-rising resistor to the output power supply).
  • the first capacitor and the second capacitor may be charged by adding a DC power source on both sides of Cin, or the first capacitor and the second capacitor may be charged by adding a DC power source on both sides of Cout.
  • the flying capacitance and the input capacitance in the circuit Charging will be completed first.
  • the first switch can be closed; then, the multi-level topology circuit is adjusted to the normal working state to control the output capacitor charging To the third set voltage value, the third set voltage value is the voltage value of the output power supply; finally, the second switch is closed. At this time, the multilevel topology circuit can work normally.
  • the multi-level topology circuit is adjusted to a normal working state, that is, the on and off states of each semiconductor switch tube in the multi-level topology circuit are adjusted to the state during normal operation.
  • the flying capacitor and the output capacitor in the circuit will be completed first Charge.
  • the second switch After one or more flying capacitors (that is, all flying capacitors in the circuit) and the output capacitor are charged, close the second switch; then, adjust the multi-level topology circuit to a normal working state and control the input capacitor to charge
  • the fourth set voltage value, the fourth set voltage value is the voltage value of the input power supply; finally, the first switch is closed. At this time, the multilevel topology circuit can work normally.
  • the multilevel topology circuit is the BUCK-BOOST circuit (ie, buck-boost conversion circuit) shown in FIG. 6, in specific implementation, charging can be started from the input side or from the output side Start charging.
  • the BUCK-BOOST circuit ie, buck-boost conversion circuit
  • charging can be started from the input side or from the output side Start charging.
  • Ca and Cin can be charged by adding DC power sources on both sides of Cin, or Cb and Cout can be charged by adding DC power sources on both sides of Cout.
  • the multi-level topology circuit is adjusted to the normal working state to control the output capacitor charging
  • the fifth set voltage value is the voltage value of the output power supply; and, control the second part of the one or more flying capacitors to charge to their respective ideal voltage values; finally, Close the second switch.
  • the multilevel topology circuit can work normally.
  • the first flying capacitor is all flying capacitors in the BUCK circuit or the BOOST circuit where the first capacitor is located. If charging is started on the input side, in the example of FIG. 6, the first part of the flying capacitor contains only Ca.
  • the multilevel topology circuit can work normally.
  • the first flying capacitor is all flying capacitors in the BUCK circuit or BOOST circuit where the first capacitor is located. If charging is started on the output side, in the example of FIG. 6, the first part of the flying capacitor contains only Cb.
  • the flying structure can be charged using the existing structure in the multilevel topology circuit.
  • the solution provided by the embodiment of the present application does not require an additional charging circuit for the flying Charging across capacitors reduces costs and the applicability of the solution is strong.
  • the first capacitor is any flying capacitor
  • the second capacitor is an input capacitor, an output capacitor, or another flying capacitor, after disconnecting the multilevel topology circuit from the input power supply and the output power supply To charge the first capacitor and the second capacitor to the ideal voltage respectively.
  • an external DC power source may be used to charge the first capacitor and the second capacitor, or the input capacitor or the output power source connected to the slow-start resistor may be used to charge the first capacitor and the second capacitor.
  • an external DC power supply for a multi-level topology with multiple parallel connections (such as the topology shown in Figure 6), only one external DC power supply can be used to charge the capacitors in the multi-path topology circuit, thereby achieving cost savings the goal of.
  • Charging through the slow-start resistor because the slow-start resistor is an inherent device in a multilevel topology circuit, the flying capacitor can be charged without increasing the hardware cost.
  • the embodiments of the present application are applicable to various flying capacitor clamped multilevel topology circuits.
  • several specific circuit topologies of flying capacitor charging methods will be introduced through several specific examples.
  • the flying capacitors (that is, Ca and Cb) can be charged in the following manner.
  • the work of the power electronic power circuit needs to be controlled by the controller.
  • the flying capacitor pre-charging method provided by the embodiments of the present application can also be regarded as being controlled and executed by a controller independent of the multilevel topology circuit.
  • the power supply that powers the controller can be called an auxiliary power supply.
  • the auxiliary power supply can use a switching power supply circuit with a high voltage input and a low voltage such as 12V or 24V output.
  • S2 Use a DC power supply (such as a flyback power supply), connect the output of the power supply to the two ends of the output capacitor Cout, and charge the output capacitor Cout and the flying capacitor Cb connected in parallel.
  • the charging target value is the flying capacitor Cb
  • the voltage during normal operation is half of the DC source2 voltage.
  • S6 Buck-boost transmits normally.
  • the voltage of the input capacitor Cin is controlled by adjusting the state of each semiconductor switch tube.
  • the target value is slowly increased from 0 to DC1.
  • the voltage of Ca is controlled.
  • the target value is DC1. half.
  • the flying capacitor (ie Cfly) can be charged in the following manner.
  • S2 Use a DC power supply (such as a flyback power supply) to connect the output of the power supply to both ends of the input capacitor Cin to charge the input capacitor Cin and the flying capacitor Cfly connected in parallel.
  • the charging target value is the flying capacitor Cfly
  • the voltage during normal operation is half of the DC source1 voltage.
  • the input power DC1 connected to the slow-start resistor can also be used, as shown in FIG. 10.
  • the flying capacitor (ie Cfly) can be charged in the following manner.
  • S2 Use a DC power supply (such as a flyback power supply) to connect the output of the power supply to the two ends of the output capacitor Cout to charge three capacitors in parallel (ie Cin, Cfly and Cout).
  • the voltage during normal operation of the transcapacitor is half of the DC source1 voltage.
  • S6 The Buck circuit normally waves, and the voltage of the output capacitor Cout is controlled by adjusting the state of each semiconductor switch tube, and the target value is from DC source1 to DC source2.
  • Example 3 when charging the input capacitor Cin, the output capacitor Cout, and the flying capacitor Cfly, it can also be performed through the input power source DC2 connected to the slow-start resistor, which will not be repeated here.
  • the flying capacitor ie, Cfly
  • the flying capacitor can be charged in the following manner.
  • S2 Use a DC power supply (such as a flyback power supply), connect the output of the power supply to the two ends of the input capacitor Cin, charge the input capacitor Cin, the flying capacitor Cfly1 and the flying capacitor Cfly2 in parallel, the target value of the charging It is the voltage when the flying capacitor Cfly1 works normally, which is 1/4 of the DC source1 voltage.
  • a DC power supply such as a flyback power supply
  • the charging target value is the voltage during the normal operation of the flying capacitor Cfly2, which is half of the DC source1 voltage.
  • an embodiment of the present application further provides a flying capacitor charging device, which can be used to execute the flying capacitor charging method shown in FIG. 5.
  • the flying capacitor charging device 1100 includes a multi-level topology circuit 1101 and a controller 1102; wherein, the multi-level topology circuit is connected to the input power supply through the first switch, and the multi-level topology circuit is connected to the output through the second switch Power connection, the multilevel topology circuit 1101 includes one or more flying capacitors; the first end of the first capacitor in the one or more flying capacitors is connected to the first electrode of the first semiconductor switch, the first capacitor Is connected to the second electrode of the second semiconductor switch tube, and the second electrode of the first semiconductor switch tube is connected to the first electrode of the second semiconductor switch tube through the second capacitor; wherein, the first capacitor is one or more In any flying capacitor of the flying capacitors, the second capacitor is an input capacitor, an output capacitor, or another flying capacitor in addition to the first capacitor in one or more flying capacitors.
  • the controller 1102 is used to: close the first semiconductor switch tube and the second semiconductor switch tube to make the first capacitor and the second capacitor parallel; charge the first capacitor and the second capacitor to the first set voltage value; open The first semiconductor switch and the second semiconductor switch; charge the second capacitor to the second set voltage value.
  • the specific structure of the multilevel topology circuit 1101 is not limited in the embodiments of the present application. As long as the multi-level topology circuit 1101 includes the first capacitor, the second capacitor, the first semiconductor switch tube, and the second semiconductor switch tube, and their connection relationship satisfies the above description. Exemplarily, the multi-level topology circuit 1101 may be any of the multi-level topology circuits shown in FIGS. 1, 4, and 6 to 10.
  • the controller 1102 when charging the first capacitor to the first set voltage value, is specifically used to: charge the first capacitor to the first set voltage value through an external DC power supply; The input power or the output power is connected to charge the first capacitor to the first set voltage value.
  • the controller 1102 is also used to close the first switch after charging of one or more flying capacitors and input capacitors is completed Adjust the multi-level topology circuit 1101 to a normal working state, control the output capacitor to charge to a third set voltage value, the third set voltage value is the voltage value of the output power supply; close the second switch.
  • the controller 1102 is also used to close the second switch after charging of one or more flying capacitors and output capacitors is completed Adjust the multilevel topology circuit 1101 to a normal working state, control the input capacitor to charge to a fourth set voltage value, the fourth set voltage value is the voltage value of the input power supply; close the first switch.
  • the controller 1102 is also used to close the first switch after the first part of the one or more flying capacitors and the input capacitors are all charged ;
  • the multi-level topology circuit 1101 is a buck-boost converter circuit
  • the first part of the flying capacitor is all flying capacitors in the buck circuit or boost circuit where the first capacitor is located; adjust the multi-level topology circuit 1101 To the normal working state, control the output capacitor to charge to the fifth set voltage value, the fifth set voltage value is the voltage value of the output power supply; and, control the second part of one or more flying capacitors to charge separately To the respective ideal voltage value; close the second switch.
  • the controller 1102 is also used to close the second switch after the first part of the one or more flying capacitors and the output capacitor are fully charged ;
  • the multi-level topology circuit 1101 is a buck-boost converter circuit
  • the first part of the flying capacitor is all flying capacitors in the buck circuit or boost circuit where the first capacitor is located; adjust the multi-level topology circuit 1101 To the normal working state, control the input capacitor to charge to the sixth set voltage value, the sixth set voltage value is the voltage value of the input power supply; and, control the second part of one or more flying capacitors to charge separately To the respective ideal voltage value; close the first switch.
  • the first set voltage value is U * 1/2 N
  • the second set voltage value is U * 1/2 N-1
  • U is the voltage value of the input power supply or the voltage value of the output voltage
  • N is a positive integer
  • These computer program instructions may also be stored in a computer readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, the instructions The device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, which is executed on the computer or other programmable device
  • the instructions provide steps for implementing the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, computer, server or data center Transmit to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device including a server, a data center, and the like integrated with one or more available media.
  • the usable medium may be a magnetic medium (eg, floppy disk, hard disk, magnetic tape), optical medium (eg, DVD), or semiconductor medium (eg, solid state disk (SSD)), or the like.

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Abstract

本申请提供一种飞跨电容的充电方法及装置，应用于多电平拓扑电路中，以提供一种占板面积小、适用性强的飞跨电容充电方案。该电路通过第一开关与输入电源连接、通过第二开关与输出电源连接；电路中的飞跨电容中的第一电容的第一端与第一半导体开关管的第一电极连接、第二端与第二半导体开关管的第二电极连接，第一半导体开关管的第二电极通过第二电容与第二半导体开关管的第一电极连接；其中，第二电容为输入电容、输出电容或另一飞跨电容；方法包括：闭合第一半导体开关管和第二半导体开关管，使第一电容与第二电容并联；将第一电容与第二电容充电至第一设定电压值；断开第一半导体开关管和第二半导体开关管；将第二电容充电至第二设定电压值。

Description

一种飞跨电容的充电方法及装置
本申请要求于2018年10月24日提交中国专利局、申请号为201811244229.4、申请名称为“一种飞跨电容的充电方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电力电子技术领域，尤其涉及一种飞跨电容的充电方法及装置。
背景技术
直流-直流变换电路(简称DCDC电路)是一种将直流进行升压或降压的电路。其输入和输出均为直流。DCDC电路在储能、电动汽车、新能源、电力系统、电子计算机等领域都有广泛的应用。DCDC电路的拓扑形式按照输出电平的状态可以分为两电平拓扑和多电平拓扑两种。
多电平拓扑是相对传统的两电平拓扑来说的，两电平拓扑是指输出电平只有0和1两种状态，多电平拓扑是指输出电平至少有三种状态，例如输出电平有1、1/2和0三种状态则称为三电平拓扑，输出电平有1、3/4、1/2、1/4和0五种状态则称为五电平拓扑。此外，多电平拓扑电路又分为二极管钳位型多电平拓扑电路、飞跨电容钳位型多电平拓扑电路等形式。
示例性地，图1示出的为一种飞跨电容钳位型三电平拓扑降压电路。在图1所示的电路正常工作时，飞跨电容Cfly的电压控制为1/2*Vin，T1和T4交替导通，T2和T3交替导通。在该电路中，在输入电容Cin上电前(即该电路正常工作前)，需要将飞跨电容Cfly充电到输入电压Vin的一半。否则，由于Cout上的电压Vout＝0，那么T3和T4的电压就为0，同时上电瞬间飞跨Cfly电压Vfly＝0，即T2和T3的电压也都为0，那么只要输入端上电，Cin上的全部电压就加在了T1上，导致T1过压损坏。而如果在输入端上电之前飞跨电容Cfly被充电至输入电压Vin的一半，那么Cin上的电压则被T1和T2均分，此时T1和T2均不会因过压而损坏。具体地，在没有对飞跨电容Cfly进行预充电以及对飞跨电容Cfly进行预充电的情况下给输入端上电，图1中各个半导体开关管上的电压可以如图3所示。
因此如何在上电之前对飞跨电容进行预充电是一个亟需解决的问题。
实际应用中，无论飞跨电容钳位型多电平拓扑电路的具体拓扑形式是怎样的，在电路正常工作前均需对飞跨电容进行预充电。
现有技术中，可以采用图2所示的充电电路为多电平拓扑电路中的飞跨电容进行预充电。该充电电路可以视为独立于多电平拓扑电路的另一个电路，仅用于为飞跨电容进行预充电。如图2所示，用R1、R2、R3和R4四个电阻以及相应的控制开关组成RC网络给飞跨电容C充电。即，闭合四个开关S1.1、S1.2、S2.1和S2.2，当电路达到稳态后，R1与R4分压，得到飞跨电容C的上端电压Vp，R2和R3分压，得到飞跨电容C的下端电压Vn。Vp-Vn即为飞跨电容的电压。
采用图2所示的充电方案，需要额外的充电电路为飞跨电容充电，造成成本的增加。 此外，由于电阻功率与电压的平方成正比，对于低压系统，由于电压低，需要的电阻功率比较小，也不需要大量的电阻并联，所以该方案的成本较低、可靠性较高。而对于高压系统来说，如果需要较快地充电，则需要大功率的电阻或者大量电阻并联，这将会导致电阻的占板面积过大。另外，对于多路拓扑并联的高压系统，系统功率较大，飞跨电容数量较多，需要的电阻数量就更多。因而图2所示方案的适用性不强。
综上，现有技术中提供的飞跨电容充电方案中，存在电路成本高且方案适用性不强的问题。
发明内容
本申请实施例提供一种飞跨电容的充电方法及装置，用以提供一种占板面积小、实现简单、适用性较强的飞跨电容充电方案。
第一方面，本申请实施例提供一种飞跨电容充电方法，该方法应用于飞跨电容钳位的多电平拓扑电路，多电平拓扑电路通过第一开关与输入电源连接，多电平拓扑电路通过第二开关与输出电源连接，多电平拓扑电路中包含一个或多个飞跨电容；一个或多个飞跨电容中的第一电容的第一端与第一半导体开关管的第一电极连接，第一电容的第二端与第二半导体开关管的第二电极连接，第一半导体开关管的第二电极通过第二电容与第二半导体开关管的第一电极连接；其中，第一电容为一个或多个飞跨电容中的任一飞跨电容，第二电容为输入电容、输出电容或者一个或多个飞跨电容中除第一电容之外的另一个飞跨电容。
具体地，该方法包括如下步骤：闭合第一半导体开关管和第二半导体开关管，使第一电容与第二电容并联；将第一电容与第二电容充电至第一设定电压值；断开第一半导体开关管和第二半导体开关管；将第二电容充电至第二设定电压值。
采用第一方面提供的飞跨电容充电方法，可利用多电平拓扑电路中的现有结构为飞跨电容进行充电，与现有技术相比，采用上述方案无需额外的充电电路为飞跨电容充电，降低了成本，且方案的适用性较强。此外，在第一方面提供的方法中，第一电容为任一飞跨电容，第二电容为输入电容、输出电容或者另一个飞跨电容，将多电平拓扑电路与输入电源和输出电源断开连接后，分别将第一电容和第二电容充电至理想电压值。对多电平电路中的所有飞跨电容上述方法进行预充电后，电路中的所有飞跨电容均可充电至理想电压值，从而避免出现多电平拓扑电路上电时，半导体开关管由于过压而损坏的问题。
在本申请实施例中，多电平拓扑电路可以是仅用于降压或者仅用于升压的电路，也可以是升降压式变换电路。
若多电平拓扑电路为仅用于降压或者仅用于升压的电路，在具体实现时，既可以从输入侧启动充电(即外接直流电源并联在输入电容的两端，或者通过缓起电阻与输入电源连接为飞跨电容充电)，也可以从输出侧启动充电(即外接直流电源并联在输出电容的两端，或者通过缓起电阻与输出电源连接为飞跨电容充电)。
无论从输入侧启动充电还是从输出侧启动充电，对于降压电路来说，通过执行第一方面提供的方法，电路中的飞跨电容和输入电容会先完成充电。那么，在一个或多个飞跨电容以及输入电容均充电完成后，可闭合第一开关；然后，将多电平拓扑电路调整至正常工作状态，控制输出电容充电至第三设定电压值，第三设定电压值为输出电源的电压值；最后，闭合第二开关。
采用上述方案，在降压电路中的飞跨电容和输入电容均完成充电后，可以继续对输出 电容进行充电。待电路中的所有飞跨电容、输入电容以及输出电容均完成充电后，多电平拓扑电路即可正常工作。
无论从输入侧启动充电还是从输出侧启动充电，对于升压电路来说，通过执行第一方面提供的方法，电路中的飞跨电容和输出电容会先完成充电。那么，在一个或多个飞跨电容以及输出电容均充电完成后，可闭合第二开关；然后，将多电平拓扑电路调整至正常工作状态，控制输入电容充电至第四设定电压值，第四设定电压值为输入电源的电压值；最后，闭合第一开关。
采用上述方案，在升压电路中的飞跨电容和输出电容均完成充电后，可以继续对输入电容进行充电。待电路中的所有飞跨电容、输入电容以及输出电容均完成充电后，多电平拓扑电路即可正常工作。
若多电平拓扑电路为升降压式变换电路，在具体实现时，既可以从输入侧启动充电，也可以从输出侧启动充电。
若在输入侧启动充电，对于升降压式变换电路来说，通过执行第一方面提供的方法，电路中的部分飞跨电容和输入电容会先完成充电。那么，在一个或多个飞跨电容中的第一部分飞跨电容以及输入电容均充电完成后，可闭合第一开关；其中，多电平拓扑电路为升降压式变换电路，第一部分飞跨电容为第一电容所在的降压电路或升压电路中的所有飞跨电容；然后，可将多电平拓扑电路调整至正常工作状态，控制输出电容充电至第五设定电压值，第五设定电压值为输出电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；最后，闭合第二开关。
采用上述方案，若在输入侧启动充电，在升降压式变换电路中的第一部分飞跨电容和输入电容均完成充电后，可以继续对输出电容和第二部分飞跨电容进行充电。待电路中的所有飞跨电容、输入电容以及输出电容均完成充电后，多电平拓扑电路即可正常工作。
若在输出侧启动充电，对于升降压式变换电路来说，通过执行第一方面提供的方法，电路中的部分飞跨电容和输出电容会先完成充电。那么，在一个或多个飞跨电容中的第一部分飞跨电容以及输出电容均充电完成后，可闭合第二开关；其中，多电平拓扑电路为升降压式变换电路，第一部分飞跨电容为第一电容所在的降压电路或升压电路中的所有飞跨电容；然后，可将多电平拓扑电路调整至正常工作状态，控制输入电容充电至第六设定电压值，第六设定电压值为输入电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；最后，闭合第一开关。
采用上述方案，若在输出侧启动充电，在升降压式变换电路中的第一部分飞跨电容和输出电容均完成充电后，可以继续对输入电容和第二部分飞跨电容进行充电。待电路中的所有飞跨电容、输入电容以及输出电容均完成充电后，多电平拓扑电路即可正常工作。
在一种可能的设计中，第一设定电压值为U*1/2 N，第二设定电压值为U*1/2 N-1，其中，U为输入电源的电压值或输出电压的电压值，N为正整数。
在一种可能的设计中，将第一电容充电至第一设定电压值，具体可通过如下两种方式中的任一种实现：通过外接直流电源将第一电容充电至第一设定电压值；或者，通过缓启电阻与输入电源或输出电源连接，将第一电容充电至第一设定电压值。
采用上述方案，可采用外接直流电源对第一电容和第二电容充电，也可以通过与缓启电阻连接的输入电源或输出电源为对第一电容和第二电容充电。通过外接直流电源充电时，对于多路并联的多电平拓扑结构，可以仅采用一个外接直流电源为多路拓扑电路中的电容 进行充电，从而达到节约成本的目的。通过缓启电阻充电，由于缓启电阻为多电平拓扑电路中的固有器件，因而可以在不增加硬件成本的前提下对飞跨电容进行充电。
第二方面，本申请实施例提供一种飞跨电容充电装置，该装置包括多电平拓扑电路及控制器。其中，多电平拓扑电路通过第一开关与输入电源连接，多电平拓扑电路通过第二开关与输出电源连接，多电平拓扑电路中包含一个或多个飞跨电容；一个或多个飞跨电容中的第一电容的第一端与第一半导体开关管的第一电极连接，第一电容的第二端与第二半导体开关管的第二电极连接，第一半导体开关管的第二电极通过第二电容与第二半导体开关管的第一电极连接；其中，第一电容为一个或多个飞跨电容中的任一飞跨电容，第二电容为输入电容、输出电容或者一个或多个飞跨电容中除第一电容之外的另一个飞跨电容。
其中，控制器用于：闭合第一半导体开关管和第二半导体开关管，使第一电容与第二电容并联；将第一电容和第二电容充电至第一设定电压值；断开第一半导体开关管和第二半导体开关管；将第二电容充电至第二设定电压值。
在一种可能的设计中，该控制器还用于：在一个或多个飞跨电容以及输入电容均充电完成后，闭合第一开关；将多电平拓扑电路调整至正常工作状态，控制输出电容充电至第三设定电压值，第三设定电压值为输出电源的电压值；闭合第二开关。
在一种可能的设计中，该控制器还用于：在一个或多个飞跨电容以及输出电容均充电完成后，闭合第二开关；将多电平拓扑电路调整至正常工作状态，控制输入电容充电至第四设定电压值，第四设定电压值为输入电源的电压值；闭合第一开关。
在一种可能的设计中，该控制器还用于：在一个或多个飞跨电容中的第一部分飞跨电容以及输入电容均充电完成后，闭合第一开关；其中，多电平拓扑电路为升降压式变换电路，第一部分飞跨电容为第一电容所在的降压电路或升压电路中的所有飞跨电容；将多电平拓扑电路调整至正常工作状态，控制输出电容充电至第五设定电压值，第五设定电压值为输出电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；闭合第二开关。
在一种可能的设计中，该控制器还用于：在一个或多个飞跨电容中的第一部分飞跨电容以及输出电容均充电完成后，闭合第二开关；其中，多电平拓扑电路为升降压式变换电路，第一部分飞跨电容为第一电容所在的降压电路或升压电路中的所有飞跨电容；将多电平拓扑电路调整至正常工作状态，控制输入电容充电至第六设定电压值，第六设定电压值为输入电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；闭合第一开关。
在一种可能的设计中，第一设定电压值可以为U*1/2 N，第二设定电压值可以为U*1/2 N-1，其中，U为输入电源的电压值或输出电压的电压值，N为正整数。
在一种可能的设计中，该控制器在将第一电容充电至第一设定电压值时，具体用于：通过外接直流电源将第一电容充电至第一设定电压值；或者，通过缓启电阻与输入电源或输出电源连接，将第一电容充电至第一设定电压值。
第三方面，本申请实施例提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面及其各种可能的设计中所述的方法。
第四方面，本申请实施例还提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面及其各种可能的设计中所述的方法。
第五方面，本申请实施例还提供一种计算机芯片，所述芯片与存储器相连，所述芯片用于读取并执行所述存储器中存储的软件程序，执行上述第一方面及其各种可能的设计中所述的方法。
另外，第二方面至第五方面中任一种可能设计方式所带来的技术效果可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为现有技术提供的一种飞跨电容钳位型三电平拓扑降压电路的结构示意图；
图2为现有技术提供的一种充电电路的结构示意图；
图3为本申请实施例提供的一种多电平拓扑电路中各个半导体开关管的电压的示意图；
图4为本申请实施例提供的第一种多电平拓扑电路的结构示意图；
图5为本申请实施例提供的一种飞跨电容的充电方法的流程示意图；
图6为本申请实施例提供的第二种多电平拓扑电路的结构示意图；
图7为本申请实施例提供的第三种多电平拓扑电路的结构示意图；
图8为本申请实施例提供的第四种多电平拓扑电路的结构示意图；
图9为本申请实施例提供的第五种多电平拓扑电路的结构示意图；
图10为本申请实施例提供的第六种多电平拓扑电路的结构示意图；
图11为本申请实施例提供的一种飞跨电容的充电装置的结构示意图。
具体实施方式
基于上述问题，本申请实施例提供一种飞跨电容的充电方法及装置，用以提供一种占板面积小、实现简单、适用性较强的飞跨电容充电方案。其中，方法和装置是基于同一发明构思的，由于方法及装置解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
需要说明的是，本申请中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
下面，以图4为例对本申请实施例的应用场景进行简单介绍。
本申请实施例提供的飞跨电容充电方法可适用于图4所示的三电平拓扑降压电路。该电路包含输入电源DC source1、输出电源DC source2、输入电容Cin、输出电容Cout、电感L、飞跨电容Cfly第一开关K1、第二开关K2以及四个半导体开关管T1、T2、T3、T4。
其中，半导体开关管可以有多类型。例如，半导体开关管可以是绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)，也可以是金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)。下面以半导体开关管为IGBT为例介绍图4所示多电平拓扑电路中各个器件的连接关系。
在图4所示的电路中，由Cin、Cout、Cfly、L、T1、T2、T3和T4组成降压电路，降压电路通过K1与DC source1连接，通过K2与输出电源连接。该多电平拓扑电路中包含一个飞跨电容Cfly；Cfly的第一端与T1的发射极连接，Cfly的第二端与T4的集电极连接，T1的集电极通过Cin与T4的发射极连接。
此外，T2的发射极与T3的集电极以及L的第一端连接，T2的集电极与T1的发射极连接，T3的发射极与T4的集电极连接，Cout的第一端与L连接，Cout的第二端与T4的发射极连接。
在图4所示的电路中，在Cin上电前(即该电路正常工作前)，需要将Cfly充电至Vin的一半。否则，由于Cout上的电压Vout＝0，那么T3和T4的电压就为0，同时上电瞬间飞跨Cfly电压Vfly＝0，即T2和T3的电压也都为0，那么只要Cin上电，Cin上的全部电压就加在了T1上，导致T1过压损坏。而如果在输入端上电之前飞跨电容Cfly被充电至输入电压Vin的一半，那么Cin上的电压则被T1和T2均分，此时T1和T2均不会因过压而损坏。
本申请实施例提供的方案中，在该电路正常工作前，可以使K1和K2保持断开状态。然后，闭合T1和T4使Cfly和Cin并联，同时为Cfly和Cin充电：在Cfly充电完成后断开T1和T4，继续为Cin充电。在Cfly和Cin均充电完成后，可以闭合K1为Cout充电。待电路中的所有电容均充电完成后，即可闭合K2使电路正常工作。
需要说明的是，图4仅为本申请实施例所适用的拓扑结构的一个具体示例。实际实现时，本申请实施例提供的飞跨电容充电方案可适用于各种多电平拓扑电路。在本申请实施例适用的多电平拓扑电路中，均包含符合图4中Cfly、Cin、T1和T4类似连接关系的电路结构。因而，在各种多电平拓扑电路中，均可采用本申请实施例提供的方案来控制Cfly、Cin等电容的充电以及控制T1和T4等半导体开关管的状态，从而实现对电路中的飞跨电容进行充电。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
参见图5，为本申请实施例提供的一种飞跨电容的充电方法的流程示意图。该方法应用于飞跨电容钳位的多电平拓扑电路。其中，多电平拓扑电路通过第一开关与输入电源连接，多电平拓扑电路通过第二开关与输出电源连接，多电平拓扑电路中包含一个或多个飞跨电容；一个或多个飞跨电容中的第一电容的第一端与第一半导体开关管的第一电极连接，第一电容的第二端与第二半导体开关管的第二电极连接，第一半导体开关管的第二电极通过第二电容与第二半导体开关管的第一电极连接；其中，第一电容为一个或多个飞跨电容中的任一飞跨电容，第二电容为输入电容、输出电容或者一个或多个飞跨电容中除第一电容之外的另一个飞跨电容。
该方法包括如下步骤：
S501：闭合第一半导体开关管和第二半导体开关管，使第一电容与第二电容并联。
本申请实施例中，半导体开关管可以有多类型。例如，半导体开关管可以是IGBT，也可以是MOSFET。若本申请实施例中的半导体开关管为IGBT，则第一电极可以为发射极，第二电极可以为集电极；若本申请实施例中的半导体开关管为MOSFET，则第一电极可以为漏极，第二电极可以为源极。
需要说明的是，本申请实施例提供的方案用于在多电平拓扑电路正常工作之前对飞跨电容进行预充电，该多电平拓扑电路中的第一开关和第二开关可以为常开开关，即默认状态为断开状态的开关。因此，在执行S501时，多电平拓扑电路还未上电，即第一开关和第二开关处于断开状态。
当第一电容和第二电容并联时，若对第一电容进行充电，则相当于也对第二电容进行充电。第一电容为一个或多个飞跨电容中的任一飞跨电容，第二电容为输入电容、输出电容或者一个或多个飞跨电容中除第一电容之外的另一个飞跨电容，因而，当第一电容和第二电容并联时，可以同时对两个飞跨电容进行充电，或者同时对输入电容和飞跨电容进行充电，或者同时对输出电容和飞跨电容进行充电。
S502：将第一电容和第二电容充电至第一设定电压值。
其中，第一设定电压值为第一电容在正常工作状态下的电压值。例如，对于图1中的飞跨电容Cfly来说，第一设定电压值为1/2*Vin。
具体地，将所述第一电容充电至第一设定电压值，具体可通过如下两种方式实现：第一种方式，通过外接直流电源将第一电容充电至第一设定电压值；第二种方式，通过缓启电阻与输入电源或输出电源连接，将所述第一电容充电至第一设定电压值。
也就是说，在本申请实施例中，在为电容充电时，可以通过外接直流电源为电容充电，也可以通过与缓启电阻连接的输入电源或输出电源为电容充电。其中，在现有技术中，缓启电阻主要起到限流的作用，避免电路中的元器件在上电时因电流过大而被烧毁。实际应用中，缓启电阻也可称为限流电阻。
除了第一电容以外，在对电路中的其他电容(例如第二电容)进行充电时，也可采用上述两种方式中的任一种，后面将不再对充电方式做详细阐述。
如前所述，由于第一电容和第二电容并联，因而在对第一电容进行充电时，第二电容也被充电。假如第二电容为输入电容，则相当于对飞跨电容和输入电容一起充电；假如第二电容为输出电容，则相当于对飞跨电容和输出电容一起充电；假如第二电容为飞跨电容，则相当于对两个飞跨电容一起充电，此时，多电平拓扑电路中包含至少两个飞跨电容，示例性地，多电平拓扑电路可以是五电平拓扑电路、九电平拓扑电路等。
S503：断开第一半导体开关管和第二半导体开关管。
将第一半导体开关管和第二半导体开关管断开后，第一电容和第二电容不再是并联关系；后续再对第二电容充电，则不会影响第一电容的电压值。
S504：将第二电容充电至第二设定电压值。
其中，第二设定电压值为第二电容在正常工作状态下的电压值。例如，在图1所示的电路中，飞跨电容Cfly相当于第一电容，若输入电容Cin相当于第二电容，则第二设定电压值为Vin；若输出电容Cout相当于第二电容，则第二设定电压值为Vout。
在一个具体示例中，第一设定电压值可以为U*1/2 N，第二设定电压值可以为U*1/2 N-1，其中，U为输入电源的电压值或输出电压的电压值，N为正整数。例如，在图1的示例中，飞跨电容Cfly相当于第一电容，输入电容Cin相当于第二电容，此时可以取N＝1，则第一设定电压值可以为1/2*Vin，第二设定电压值为Vin。
在本申请实施例中，只要第一电容与第二电容通过第一半导体开关管和第二半导体开关管并联连接，即可对第一电容和第二电容执行图5所示的飞跨电容充电方法。也就是说，本申请实施例适用于多种多电平拓扑电路，包括但不限于N路并联的双向BUCK-BOOST电路、三电平双向BUCK电路、五电平拓扑电路、九电平拓扑电路等。
示例性地，本申请实施例可适用于图6所示的N路并联的双向BUCK-BOOST电路。在图6所示的电路中，可以将飞跨电容Ca视为第一电容，将输入电容Cin视为第二电容，将T1a视为第一半导体开关管，将T4a视为第二半导体开关管；也可以将飞跨电容Cb视 为第一电容，将输出电容Cout视为第二电容，将T1b视为第一半导体开关管，将T4b视为第二半导体开关管。
若Ca为第一电容、Cin为第二电容，则执行图5所示方法时可通过外接直流电源为Ca和Cin充电，也可以通过与缓启电阻连接的输入电源DC source1为Ca和Cin充电；在执行图5所示方法为Ca和Cin充电后，可闭合第一开关并将每个BUCK-BOOST电路调整至正常工作状态，继续将Cb和Cout充电至理想电压值。然后闭合第二开关，图6所示电路即可正常工作。
若Cb为第一电容、Cout为第二电容，则执行图5所示方法时可通过外接直流电源为Cb和Cout充电，也可以通过与缓启电阻连接的输出电源DC source2为Cb和Cout充电；在执行图5所示方法为Cb和Cout充电后，可闭合第二开关并将每个BUCK-BOOST电路调整至正常工作状态，继续将Ca和Cin充电至理想电压值。然后闭合第一开关，图6所示电路即可正常工作。
示例性地，本申请实施例可适用于图4所示的三电平双向BUCK电路。在图4所示的电路中，可以将飞跨电容Cfly视为第一电容，将输入电容Cin视为第二电容，将T1视为第一半导体开关管，将T4视为第二半导体开关管。
若Cfly为第一电容、Cin为第二电容，则执行图5所示方法时可通过外接直流电源为Cfly和Cin充电，也可以通过与缓启电阻连接的输入电源DC source1为Cfly和Cin充电；或者，也可以通过与缓启电阻连接的输出电源DC source2为Cfly和Cin充电，此时，输出电容Cout也被充电。在执行图5所示方法为Cfly和Cin充电后，可闭合第一开关K1并将图4所示电路调整至正常工作状态，继续将Cout充电至理想电压值。然后闭合第二开关，图4所示电路即可正常工作。
示例性地，本申请实施例可适用于图7所示的三电平双向BOOST电路。在图7所示的电路中，可以将飞跨电容Cfly视为第一电容，将输出电容Cout视为第二电容，将T1视为第一半导体开关管，将T4视为第二半导体开关管。
若Cfly为第一电容、Cout为第二电容，则执行图5所示方法时可通过外接直流电源为Cfly和Cout充电，也可以通过与缓启电阻连接的输出电源DC source2为Cfly和Cout充电；或者，也可以通过与缓启电阻连接的输入电源DC source1为Cfly和Cout充电，此时，输出电容Cin也被充电。在执行图5所示方法为Cfly和Cout充电后，可闭合第二开关K2并将图7所示电路调整至正常工作状态，继续将Cin充电至理想电压值。然后第一开关K1，图7所示电路即可正常工作。
示例性地，本申请实施例可适用于图8所示的五电平拓扑电路。在图8所示的电路中，可以将飞跨电容Cfly1视为第一电容，将飞跨电容Cfly2视为第二电容，此时T2为第一半导体开关管、T5为第二半导体开关管；在图8所示的电路中，也可以将飞跨电容Cfly2视为第一电容，将输入电容Cin视为第二电容，此时T1为第一半导体开关管、T6为第二半导体开关管。
具体实现时，可以将T1、T2、T5、T6同时闭合，此时可同时对Cfly1、Cfly2和Cin进行充电。将Cfly1充电至1/4*Vin后，可断开T2和T5，然后继续对Cfly2和Cin进行充电。将Cfly2充电至1/2*Vin后，可断开T1和T6。然后，继续为Cin进行充电。在执行图5所示方法为Cfly1、Cfly2和Cin充电后，可闭合第一开关K1并将图8所示电路调整至正常工作状态，继续将Cout充电至理想电压值。然后闭合第二开关K2，图8所示电路即可 正常工作。
本申请实施例中，若多电平拓扑电路为图4、图7或图8所示的仅用于降压或仅用于升压的电路，在具体实现时，既可以从输入侧启动充电(即外接直流电源并联在输入电容的两端，或者通过缓起电阻与输入电源连接为飞跨电容充电)，也可以从输出侧启动充电(即外接直流电源并联在输出电容的两端，或者通过缓起电阻与输出电源连接为飞跨电容充电)。例如，在图4所示的电路中，可以通过在Cin两侧加直流电源为第一电容和第二电容充电，也可以通过在Cout两侧加直流电源为第一电容和第二电容充电。
无论从输入侧启动充电还是从输出侧启动充电，对于降压电路(例如图4或图8所示的电路)来说，通过执行图5所示的方法，电路中的飞跨电容和输入电容会先完成充电。在一个或多个飞跨电容(即电路中的所有飞跨电容)以及输入电容均充电完成后，可闭合第一开关；然后，将多电平拓扑电路调整至正常工作状态，控制输出电容充电至第三设定电压值，第三设定电压值为输出电源的电压值；最后，闭合第二开关。此时该多电平拓扑电路即可正常工作。
其中，将多电平拓扑电路调整至正常工作状态，即将多电平拓扑电路中各个半导体开关管的导通和关断状态调整至正常工作时的状态。
无论从输入侧启动充电还是从输出侧启动充电，对于升压电路(例如图7所示的电路)来说，通过执行图5所示的方法，电路中的飞跨电容和输出电容会先完成充电。在一个或多个飞跨电容(即电路中的所有飞跨电容)以及输出电容均充电完成后，闭合第二开关；然后，将多电平拓扑电路调整至正常工作状态，控制输入电容充电至第四设定电压值，第四设定电压值为输入电源的电压值；最后，闭合第一开关。此时该多电平拓扑电路即可正常工作。
本申请实施例中，若多电平拓扑电路为图6所示的BUCK-BOOST电路(即升降压式变换电路)，在具体实现时，既可以从输入侧启动充电，也可以从输出侧启动充电。例如，在图6所示的电路中，可以通过在Cin两侧加直流电源为Ca和Cin充电，也可以通过在Cout两侧加直流电源为Cb和Cout充电。
若在输入侧启动充电，对于BUCK-BOOST电路来说，通过执行图5所示的方法，电路中的部分飞跨电容和输入电容会先完成充电。在电路中的一个或多个飞跨电容中的第一部分飞跨电容以及输入电容均充电完成后，可以闭合第一开关；然后，将多电平拓扑电路调整至正常工作状态，控制输出电容充电至第五设定电压值，第五设定电压值为输出电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；最后，闭合第二开关。此时该多电平拓扑电路即可正常工作。
其中，第一部分飞跨电容为第一电容所在的BUCK电路或BOOST电路中的所有飞跨电容。若在输入侧启动充电，则在图6的示例中，第一部分飞跨电容仅包含Ca。
若在输出侧启动充电，对于BUCK-BOOST电路(即升降压式变换电路)来说，通过执行图5所示的方法，电路中的部分飞跨电容和输出电容会先完成充电。在一个或多个飞跨电容中的第一部分飞跨电容以及输出电容均充电完成后，闭合第二开关；然后，将多电平拓扑电路调整至正常工作状态，控制输入电容充电至第六设定电压值，第六设定电压值为输入电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；然后，闭合第一开关。此时该多电平拓扑电路即可正常工作。
其中，第一部分飞跨电容为第一电容所在的BUCK电路或BOOST电路中的所有飞跨 电容。若在输出侧启动充电，则在图6的示例中，第一部分飞跨电容仅包含Cb。
采用本申请实施例提供的方案，可利用多电平拓扑电路中的现有结构为飞跨电容进行充电，与现有技术相比，采用本申请实施例提供的方案无需额外的充电电路为飞跨电容充电，降低了成本，且方案的适用性较强。此外，本申请实施例中，第一电容为任一飞跨电容，第二电容为输入电容、输出电容或者另一个飞跨电容，将多电平拓扑电路与输入电源和输出电源断开连接后，分别将第一电容和第二电容充电至理想电压值。对多电平电路中的所有飞跨电容执行图5所示方法进行预充电后，电路中的所有飞跨电容均可充电至理想电压值，从而避免出现多电平拓扑电路上电时，半导体开关管由于过压而损坏的问题。
此外，本申请实施例中，可采用外接直流电源对第一电容和第二电容充电，也可以通过与缓启电阻连接的输入电源或输出电源为对第一电容和第二电容充电。通过外接直流电源充电时，对于多路并联的多电平拓扑结构(例如图6所示的拓扑结构)，可以仅采用一个外接直流电源为多路拓扑电路中的电容进行充电，从而达到节约成本的目的。通过缓启电阻充电，由于缓启电阻为多电平拓扑电路中的固有器件，因而可以在不增加硬件成本的前提下对飞跨电容进行充电。
如前所述，本申请实施例适用于各种飞跨电容钳位的多电平拓扑电路。下面，将通过几个具体示例对几个具体的电路拓扑的飞跨电容充电方法进行介绍。
示例一
对于图6所示的多电平拓扑电路，可采用如下方式对飞跨电容(即Ca和Cb)进行充电。
通常，电力电子功率电路的工作需要由控制器来控制，本申请实施例提供的飞跨电容预充电方法也可以视为由独立于多电平拓扑电路的控制器控制执行。为控制器供电的电源可以称为辅助电源。通常，辅助电源可采用输入为高压、输出为12V或24V等低电压的开关电源电路。
S1：辅源接通后，控制闭合每一路拓扑中的开关器件T1b和T4b。将输出电容Cout与飞跨电容Cb并联起来。
S2：用一个直流电源(例如反激电源)，将该电源的输出接在输出电容Cout两端，对并联在一起的输出电容Cout和飞跨电容Cb充电，充电的目标值为飞跨电容Cb正常工作时的电压，即DC source2电压的一半。
S3：当飞跨电容达到目标值后，断开T1b和T4b，将飞跨电容Cb与输出电容Cout断开。
S4：继续对输出电容Cout充电，目标值为DC source2电压。
S5：达到目标值后，停止充电，输出电容Cout的电压与DC source2电压相等，K2两端没有电压差，直接将K2闭合。
S6：Buck-boost正常发波，通过调节各个半导体开关管的状态来控制输入电容Cin的电压，目标值从0到DC soruce1的电压缓慢增加；同时控制Ca的电压，目标值为DC soruce1电压的一半。
S7：当输入电容Cin的电压值达到DC soruce1的电压，飞跨电容Ca的电压值达到DC soruce1电压的一半时，K1两端没有电压差，直接将K1闭合。
此外，在示例一中，在对输出电容Cout和飞跨电容Cb进行充电时，还可通过与缓启 电阻连接的输出电源DC source2进行，如图9所示。
示例二
对于图4所示的多电平拓扑电路，可采用如下方式对飞跨电容(即Cfly)进行充电。
S1：辅源接通后，控制闭合拓扑电路中的开关器件T1和T4。将输入电容Cin与飞跨电容Cfly并联起来。
S2：用一个直流电源(例如反激电源)，将该电源的输出接在输入电容Cin两端，对并联在一起的输入电容Cin和飞跨电容Cfly充电，充电的目标值为飞跨电容Cfly正常工作时的电压，即DC source1电压的一半。
S3：当飞跨电容Cfly达到目标值后，断开T1和T4，将飞跨电容Cfly与输入电容Cin断开。
S4：继续对输入电容Cin充电，目标值为DC source1得电压。
S5：达到目标值后，停止充电，输入电容Cin的电压与DC source1电压相等，K1两端没有电压差，直接将K1闭合。
S6：Buck电路正常发波，通过调节各个半导体开关管的状态控制输出电容Cout的电压，目标值从0到DC soruce2的电压缓慢增加。
S7：当Cout电容电压达到DC soruce2的电压时，K2两端没有电压差，直接将K2闭合。
此外，在示例二中，在对输入电容Cin和飞跨电容Cfly进行充电时，还可通过与缓启电阻连接的输入电源DC source1进行，如图10所示。
示例三
对于图4所示的多电平拓扑电路，可采用如下方式对飞跨电容(即Cfly)进行充电。
S1：辅源接通后，控制闭合拓扑中的开关器件T1和T4。将输入电容Cin与飞跨电容Cfly并联起来。
S2：用一个直流电源(例如反激电源)，将该电源的输出接在输出电容Cout两端，对并联在一起的三个电容(即Cin、Cfly和Cout)充电，充电的目标值为飞跨电容正常工作时的电压，即DC source1电压的一半。
S3：当飞跨电容Cfly达到目标值后，将T1和T4断开。
S4：继续对输出电容Cout和输入电容Cin充电，目标值为DC source1电压。
S5：达到目标值后，停止充电，输入电容Cin的电压与DC source1电压相等，K1两端没有电压差，直接将K1闭合。
S6：Buck电路正常发波，通过调节各个半导体开关管的状态控制输出电容Cout的电压，目标值从DC source1到DC soruce2。
S7：当输出电容Cout的电压达到DC soruce2的电压时，K2两端没有电压差，直接将K2闭合。
此外，在示例三中，在对输入电容Cin、输出电容Cout和飞跨电容Cfly进行充电时，还可通过与缓启电阻连接的输入电源DC source2进行，此处不再赘述。
示例四
对于图8所示的多电平拓扑电路，可采用如下方式对飞跨电容(即Cfly)进行充电。
S1：辅源接通后，控制闭合拓扑中的开关器件T1、T2、T5、T6。将输入电容Cin与飞跨电容Cfly1、飞跨电容Cfly2并联起来。
S2：用一个直流电源(例如反激电源)，将该电源的输出接在输入电容Cin两端，对并联在一起的输入电容Cin、飞跨电容Cfly1和飞跨电容Cfly2充电，充电的目标值为飞跨电容Cfly1正常工作时的电压，即DC source1电压的1/4。
S3：当飞跨电容Cfly1达到目标值后，断开T2和T5，将飞跨电容Cfly1与输入电容Cin断开。此时飞跨电容Cfly2与输入电容Cin仍并联。
S4：继续对飞跨电容Cfly2和输入电容Cin充电，充电的目标值为飞跨电容Cfly2正常工作时的电压，即DC source1电压的一半。
S5：当飞跨电容Cfly2达到目标值后，断开T1和T6，将飞跨电容Cfly2与输入电容Cin断开。
S6：继续对输入电容Cin充电，目标值为DC source1的电压。
S7：达到目标值后，停止充电，输入电容Cin的电压与DC source1电压相等，K1两端没有电压差，直接将K1闭合。
S8：Buck电路正常发波，通过调节各个半导体开关管的状态控制输出电容Cout的电压，目标值从0到DC soruce2的电压缓慢增加。
S9：当Cout电容电压达到DC soruce2的电压时，K2两端没有电压差，直接将K2闭合。
基于同一发明构思，本申请实施例还提供一种飞跨电容充电装置，该装置可用于执行图5所示的飞跨电容的充电方法。
参见图11，该飞跨电容充电装置1100包括多电平拓扑电路1101及控制器1102；其中，多电平拓扑电路通过第一开关与输入电源连接，多电平拓扑电路通过第二开关与输出电源连接，多电平拓扑电路1101中包含一个或多个飞跨电容；一个或多个飞跨电容中的第一电容的第一端与第一半导体开关管的第一电极连接，第一电容的第二端与第二半导体开关管的第二电极连接，第一半导体开关管的第二电极通过第二电容与第二半导体开关管的第一电极连接；其中，第一电容为一个或多个飞跨电容中的任一飞跨电容，第二电容为输入电容、输出电容或者一个或多个飞跨电容中除第一电容之外的另一个飞跨电容。
其中，控制器1102用于：闭合第一半导体开关管和第二半导体开关管，使第一电容与第二电容并联；将第一电容和第二电容充电至第一设定电压值；断开第一半导体开关管和第二半导体开关管；将第二电容充电至第二设定电压值。
需要说明的是，本申请实施例中对多电平拓扑电路1101的具体结构不做限制。只要该多电平拓扑电路1101中包含第一电容、第二电容、第一半导体开关管和第二半导体开关管，且它们的连接关系满足上述描述即可。示例性地，多电平拓扑电路1101可以为图1、图4、图6～图10所示的任一多电平拓扑电路。
可选地，控制器1102在将第一电容充电至第一设定电压值时，具体用于：通过外接直流电源将第一电容充电至第一设定电压值；或者，通过缓启电阻与输入电源或输出电源连接，将第一电容充电至第一设定电压值。
当多电平拓扑电路1101为仅用于降压或者仅用于升压的电路时，控制器1102还用于：在一个或多个飞跨电容以及输入电容均充电完成后，闭合第一开关；将多电平拓扑电路1101调整至正常工作状态，控制输出电容充电至第三设定电压值，第三设定电压值为输出电源的电压值；闭合第二开关。
当多电平拓扑电路1101为仅用于降压或者仅用于升压的电路时，控制器1102还用于：在一个或多个飞跨电容以及输出电容均充电完成后，闭合第二开关；将多电平拓扑电路1101调整至正常工作状态，控制输入电容充电至第四设定电压值，第四设定电压值为输入电源的电压值；闭合第一开关。
当多电平拓扑电路1101为升降压式变换电路时，控制器1102还用于：在一个或多个飞跨电容中的第一部分飞跨电容以及输入电容均充电完成后，闭合第一开关；其中，多电平拓扑电路1101为升降压式变换电路，第一部分飞跨电容为第一电容所在的降压电路或升压电路中的所有飞跨电容；将多电平拓扑电路1101调整至正常工作状态，控制输出电容充电至第五设定电压值，第五设定电压值为输出电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；闭合第二开关。
当多电平拓扑电路1101为升降压式变换电路时，控制器1102还用于：在一个或多个飞跨电容中的第一部分飞跨电容以及输出电容均充电完成后，闭合第二开关；其中，多电平拓扑电路1101为升降压式变换电路，第一部分飞跨电容为第一电容所在的降压电路或升压电路中的所有飞跨电容；将多电平拓扑电路1101调整至正常工作状态，控制输入电容充电至第六设定电压值，第六设定电压值为输入电源的电压值；并，控制一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；闭合第一开关。
可选地，第一设定电压值为U*1/2 N，第二设定电压值为U*1/2 N-1，其中，U为输入电源的电压值或输出电压的电压值，N为正整数。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质 中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘solid state disk(SSD))等。

Claims (14)

  1. 一种飞跨电容充电方法，其特征在于，所述方法应用于飞跨电容钳位的多电平拓扑电路，所述多电平拓扑电路通过第一开关与输入电源连接，所述多电平拓扑电路通过第二开关与输出电源连接，所述多电平拓扑电路中包含一个或多个飞跨电容；所述一个或多个飞跨电容中的第一电容的第一端与第一半导体开关管的第一电极连接，所述第一电容的第二端与第二半导体开关管的第二电极连接，所述第一半导体开关管的第二电极通过第二电容与所述第二半导体开关管的第一电极连接；其中，所述第一电容为所述一个或多个飞跨电容中的任一飞跨电容，所述第二电容为输入电容、输出电容或者所述一个或多个飞跨电容中除所述第一电容之外的另一个飞跨电容；
    所述方法包括：
    闭合所述第一半导体开关管和所述第二半导体开关管，使所述第一电容与所述第二电容并联；
    将所述第一电容与第二电容充电至第一设定电压值；
    断开所述第一半导体开关管和所述第二半导体开关管；
    将所述第二电容充电至第二设定电压值。
  2. 如权利要求1所述的方法，其特征在于，还包括：
    在所述一个或多个飞跨电容以及所述输入电容均充电完成后，闭合所述第一开关；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输出电容充电至第三设定电压值，所述第三设定电压值为所述输出电源的电压值；
    闭合所述第二开关。
  3. 如权利要求1所述的方法，其特征在于，还包括：
    在所述一个或多个飞跨电容以及所述输出电容均充电完成后，闭合所述第二开关；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输入电容充电至第四设定电压值，所述第四设定电压值为所述输入电源的电压值；
    闭合所述第一开关。
  4. 如权利要求1所述的方法，其特征在于，还包括：
    在所述一个或多个飞跨电容中的第一部分飞跨电容以及所述输入电容均充电完成后，闭合所述第一开关；其中，所述多电平拓扑电路为升降压式变换电路，所述第一部分飞跨电容为所述第一电容所在的降压电路或升压电路中的所有飞跨电容；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输出电容充电至第五设定电压值，所述第五设定电压值为所述输出电源的电压值；并，控制所述一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；
    闭合所述第二开关。
  5. 如权利要求1所述的方法，其特征在于，还包括：
    在所述一个或多个飞跨电容中的第一部分飞跨电容以及所述输出电容均充电完成后，闭合所述第二开关；其中，所述多电平拓扑电路为升降压式变换电路，所述第一部分飞跨电容为所述第一电容所在的降压电路或升压电路中的所有飞跨电容；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输入电容充电至第六设定电压值，所述第六设定电压值为所述输入电源的电压值；并，控制所述一个或多个飞跨电容中 的第二部分飞跨电容分别充电至各自的理想电压值；
    闭合所述第一开关。
  6. 如权利要求1～5任一项所述的方法，其特征在于，所述第一设定电压值为U*1/2 N，所述第二设定电压值为U*1/2 N-1，其中，U为所述输入电源的电压值或所述输出电压的电压值，N为正整数。
  7. 如权利要求1～6任一项所述的方法，其特征在于，将所述第一电容充电至第一设定电压值，包括：
    通过外接直流电源将所述第一电容充电至第一设定电压值；或者，
    通过缓启电阻与所述输入电源或所述输出电源连接，将所述第一电容充电至第一设定电压值。
  8. 一种飞跨电容充电装置，其特征在于，包括多电平拓扑电路及控制器；其中，所述多电平拓扑电路通过第一开关与输入电源连接，所述多电平拓扑电路通过第二开关与输出电源连接，所述多电平拓扑电路中包含一个或多个飞跨电容；所述一个或多个飞跨电容中的第一电容的第一端与第一半导体开关管的第一电极连接，所述第一电容的第二端与第二半导体开关管的第二电极连接，所述第一半导体开关管的第二电极通过第二电容与所述第二半导体开关管的第一电极连接；其中，所述第一电容为所述一个或多个飞跨电容中的任一飞跨电容，所述第二电容为输入电容、输出电容或者所述一个或多个飞跨电容中除所述第一电容之外的另一个飞跨电容；
    所述控制器用于：
    闭合所述第一半导体开关管和所述第二半导体开关管，使所述第一电容与所述第二电容并联；
    将所述第一电容和第二电容充电至第一设定电压值；
    断开所述第一半导体开关管和所述第二半导体开关管；
    将所述第二电容充电至第二设定电压值。
  9. 如权利要求8所述的装置，其特征在于，所述控制器还用于：
    在所述一个或多个飞跨电容以及所述输入电容均充电完成后，闭合所述第一开关；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输出电容充电至第三设定电压值，所述第三设定电压值为所述输出电源的电压值；
    闭合所述第二开关。
  10. 如权利要求8所述的装置，其特征在于，所述控制器还用于：
    在所述一个或多个飞跨电容以及所述输出电容均充电完成后，闭合所述第二开关；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输入电容充电至第四设定电压值，所述第四设定电压值为所述输入电源的电压值；
    闭合所述第一开关。
  11. 如权利要求8所述的装置，其特征在于，所述控制器还用于：
    在所述一个或多个飞跨电容中的第一部分飞跨电容以及所述输入电容均充电完成后，闭合所述第一开关；其中，所述多电平拓扑电路为升降压式变换电路，所述第一部分飞跨电容为所述第一电容所在的降压电路或升压电路中的所有飞跨电容；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输出电容充电至第五设定电压值，所述第五设定电压值为所述输出电源的电压值；并，控制所述一个或多个飞跨电容中 的第二部分飞跨电容分别充电至各自的理想电压值；
    闭合所述第二开关。
  12. 如权利要求8所述的装置，其特征在于，所述控制器还用于：
    在所述一个或多个飞跨电容中的第一部分飞跨电容以及所述输出电容均充电完成后，闭合所述第二开关；其中，所述多电平拓扑电路为升降压式变换电路，所述第一部分飞跨电容为所述第一电容所在的降压电路或升压电路中的所有飞跨电容；
    将所述多电平拓扑电路调整至正常工作状态，控制所述输入电容充电至第六设定电压值，所述第六设定电压值为所述输入电源的电压值；并，控制所述一个或多个飞跨电容中的第二部分飞跨电容分别充电至各自的理想电压值；
    闭合所述第一开关。
  13. 如权利要求8～12任一项所述的装置，其特征在于，所述第一设定电压值为U*1/2 N，所述第二设定电压值为U*1/2 N-1，其中，U为所述输入电源的电压值或所述输出电压的电压值，N为正整数。
  14. 如权利要求8～13任一项所述的装置，其特征在于，所述控制器在将所述第一电容充电至第一设定电压值时，具体用于：
    通过外接直流电源将所述第一电容充电至第一设定电压值；或者，
    通过缓启电阻与所述输入电源或所述输出电源连接，将所述第一电容充电至第一设定电压值。
PCT/CN2019/106278 2018-10-24 2019-09-17 一种飞跨电容的充电方法及装置 WO2020082940A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114696609A (zh) * 2020-12-28 2022-07-01 圣邦微电子（北京）股份有限公司 电荷泵电路

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109617148B (zh) 2018-10-24 2020-08-07 华为技术有限公司 一种飞跨电容的充电方法及装置
US11881764B2 (en) * 2019-06-24 2024-01-23 General Electric Company Short-circuit protection systems and methods for flying capacitor based buck-boost converters
CN112491255B (zh) * 2019-09-12 2021-09-07 台达电子企业管理（上海）有限公司 均压电路、飞跨电容三电平变换器及设备
CN111030490B (zh) * 2019-12-18 2022-11-04 南京理工大学 一种升压型开关电容九电平逆变器
CN111049403B (zh) * 2019-12-18 2022-11-01 南京理工大学 一种升降压型开关电容九电平逆变器
WO2021134492A1 (zh) * 2019-12-31 2021-07-08 西门子股份公司 预充电电路、变流器以及预充电方法
CN113078815B (zh) * 2020-01-03 2022-04-15 台达电子工业股份有限公司 电源转换系统
CN113556029B (zh) * 2020-04-23 2023-02-28 台达电子企业管理（上海）有限公司 飞跨电容多电平端口失压保护电路
CN114079296B (zh) * 2020-07-31 2024-04-12 华为数字能源技术有限公司 电压转换电路、控制方法、dc/dc变换器以及设备
CN113054831B (zh) * 2021-04-30 2022-03-29 杰华特微电子股份有限公司 一种三电平开关电路
DE102021124195A1 (de) * 2021-09-20 2023-03-23 Dialog Semiconductor (Uk) Limited Effizienter hybrid- buck-boost- bzw. abwärts-aufwärts-wandler
CN116207976A (zh) * 2021-12-01 2023-06-02 澳门大学 一种降压电路及电源管理装置
US20230268835A1 (en) * 2022-02-22 2023-08-24 Cirrus Logic International Semiconductor Ltd. Power converters
CN115333211B (zh) * 2022-07-29 2024-04-30 重庆大学 一种电网侧供电混合式多电平变流器的软充电电路及方法
CN117318485A (zh) * 2023-08-10 2023-12-29 广州菲利斯太阳能科技有限公司 飞跨电容三电平Buckboost双向能量流动的控制方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102916603A (zh) * 2012-10-26 2013-02-06 哈尔滨东方报警设备开发有限公司 包含预充电电路的单相不对称多电平逆变器及其充电方法
CN204190608U (zh) * 2014-09-26 2015-03-04 徐州中矿大传动与自动化有限公司 一种五电平变频器预充电装置及控制装置
CN106230253A (zh) * 2016-09-09 2016-12-14 华为技术有限公司 升压功率变换电路和控制方法
US20180131271A1 (en) * 2016-11-08 2018-05-10 Delta Electronics,Inc. Precharge device and frequency converter
CN207542813U (zh) * 2017-10-30 2018-06-26 国电南瑞科技股份有限公司 一种储能式有轨电车的三电平充电装置
CN109617148A (zh) * 2018-10-24 2019-04-12 华为技术有限公司 一种飞跨电容的充电方法及装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090033293A1 (en) * 2007-08-01 2009-02-05 Intersil Americas Inc. Voltage converter with combined capacitive voltage divider, buck converter and battery charger
US20120153912A1 (en) * 2010-12-17 2012-06-21 Jeffrey Demski Controller for a Power Converter and Method of Operating the Same
CN104052278B (zh) * 2013-03-15 2018-10-16 马克西姆综合产品公司 多电平增压变换器拓扑、控制和软启动系统及方法
DE102014203159A1 (de) * 2014-02-21 2015-08-27 Airbus Operations Gmbh Brennstoffzellensystem in einem bipolaren Hochspannungsnetz und Verfahren zum Betreiben eines bipolaren Hochspannungsnetzes
CN105119512B (zh) 2015-09-23 2017-12-22 阳光电源股份有限公司 一种多电平逆变器及其应用电路的电容充电方法
CN105763037A (zh) 2016-05-16 2016-07-13 浙江工业大学 适用于三相电压型双向pwm变流器的预充电软启动电路
WO2018102689A1 (en) * 2016-12-01 2018-06-07 Integrated Device Technology, Inc. Battery charging system
US10554061B2 (en) * 2016-12-01 2020-02-04 Integrated Device Technology, Inc. Battery charging system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102916603A (zh) * 2012-10-26 2013-02-06 哈尔滨东方报警设备开发有限公司 包含预充电电路的单相不对称多电平逆变器及其充电方法
CN204190608U (zh) * 2014-09-26 2015-03-04 徐州中矿大传动与自动化有限公司 一种五电平变频器预充电装置及控制装置
CN106230253A (zh) * 2016-09-09 2016-12-14 华为技术有限公司 升压功率变换电路和控制方法
US20180131271A1 (en) * 2016-11-08 2018-05-10 Delta Electronics,Inc. Precharge device and frequency converter
CN207542813U (zh) * 2017-10-30 2018-06-26 国电南瑞科技股份有限公司 一种储能式有轨电车的三电平充电装置
CN109617148A (zh) * 2018-10-24 2019-04-12 华为技术有限公司 一种飞跨电容的充电方法及装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114696609A (zh) * 2020-12-28 2022-07-01 圣邦微电子（北京）股份有限公司 电荷泵电路

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