WO2020082448A1 - 一种闪存组件错误率调变核编译码速率节省耗电量的方法 - Google Patents

一种闪存组件错误率调变核编译码速率节省耗电量的方法 Download PDF

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WO2020082448A1
WO2020082448A1 PCT/CN2018/115509 CN2018115509W WO2020082448A1 WO 2020082448 A1 WO2020082448 A1 WO 2020082448A1 CN 2018115509 W CN2018115509 W CN 2018115509W WO 2020082448 A1 WO2020082448 A1 WO 2020082448A1
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matrix
check
decoding
coding
error rate
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French (fr)
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陈育鸣
李庭育
洪振洲
魏智汎
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江苏华存电子科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • the invention relates to the technical field of saving power consumption of the flash memory component error rate modulation core coding and decoding rate, in particular to a method for saving power consumption of the flash memory component error rate modulation core coding and decoding rate.
  • the design of the low-density parity check error correction code (LDPC) check digit generation and check unit of the current main control device adopts a single fixed check matrix, cooperates with the fixed check digit generation core and the data check verification core pipeline The design is also done at a fixed rate. In this way, it is impossible to effectively control the working mode of the generation and verification core of the main control terminal under different data error rates, so that it can save power consumption.
  • LDPC low-density parity check error correction code
  • the purpose of the present invention is to provide a flash memory device that operates in the most power-saving mode and effectively controls the power consumption generated and verified by the main control terminal Method to solve the problems raised in the background art above.
  • a method for saving power consumption of a flash memory component error rate modulation kernel coding and decoding rate includes the following steps:
  • a low-density parity control unit control unit inside the main control unit is provided with a main control chip on the system hardware, and the main control chip includes low-density parity check error correction
  • the controller is controlled by the data component, which is connected to the data component.
  • the main control chip includes a generation matrix, a check bit generation unit, a check matrix, and an error checking and correction unit.
  • the hardware of the step B system includes a low-density parity control unit controller and data component control.
  • the low-density parity control unit controller includes a generation matrix 1, a generation matrix 2, and check digit generation Unit, parity check matrix 1, parity check matrix 2, check error correction unit, the generator matrix 1 and the generator matrix 2 are respectively connected to a check bit generating unit, and the check bit generating unit is connected to the data component control, the check The matrix 1 and the check matrix 2 are respectively connected to an error checking and correction unit, and the error checking and correction unit is connected to the control of the data component, and the control of the data component is connected to the data component.
  • the operation status of the low-density parity check control unit in the main control system of the step C is not configured with multiple sets of matrix and dynamic matrix calling mechanisms, and the low-density parity check control unit controller includes a codeword coding period and a code Word decoding cycle.
  • the step C is to control the operation status of the internal low-density parity control unit, and configure multiple sets of matrix and dynamic matrix calling mechanisms.
  • the low-density parity control unit controller includes a codeword coding period A, codeword Coding cycle B, codeword coding cycle A, codeword coding cycle B, codeword coding cycle B, codeword coding cycle B, codeword decoding cycle, codeword decoding cycle B, decoding cycle B, decoding cycle B , Decoding cycle A, decoding cycle B.
  • the check bit generation and data verification unit design configure multiple sets of matrix storage space with different row weights, coupled with a unit that effectively monitors the read data error rate to detect the data error rate in a timely manner, Or according to different interval settings and component configurations, call different operation matrices and operation sequences so that the codec core can operate in the most power-saving mode as far as possible, so as to effectively control the power consumption of the main control end to generate and verify the core.
  • FIG. 1 is a schematic diagram of a low-density parity control unit inside a main control of the present invention
  • FIG. 2 is a schematic diagram of a low-density parity control unit in the main control of the present invention, configured with multiple sets of different operation matrices and operation sequences;
  • 3 is a schematic diagram of the operating status of the low-density parity check control unit inside the main control of the present invention, without multiple sets of matrix and dynamic matrix calling mechanism;
  • FIG. 4 is a schematic diagram of the operation status of the low-density parity control unit in the main control of the present invention, which is configured with multiple sets of matrix and dynamic matrix calling mechanism.
  • the present invention provides a technical solution: a method for saving power consumption of a flash memory component error rate modulation kernel coding and decoding rate, including the following steps:
  • the system hardware is provided with a main control chip.
  • the main control chip includes the low-density parity check error correction control on the main control chip
  • the controller and the data component control are connected to the data component control.
  • the main control chip includes a generation matrix, a check bit generation unit, a check matrix, and an error correction unit.
  • the system hardware includes a low-density parity control unit controller, and the data components are controlled in the low-density parity school.
  • the verification control unit includes a generation matrix 1, a generation matrix 2, a check digit generation unit, a check matrix 1, a check matrix 2, a check error correction unit in the generation matrix 1 and a generation matrix 2 and a check digit generation unit respectively.
  • the connection, the check bit generating unit and the data component control are connected to the check matrix 1 and the check matrix 2 are respectively connected to the check error correction unit, the check error correction unit is connected to the data component control, and the data component control is connected to the data component.
  • the controller includes codeword encoding cycle and codeword decoding cycle, the operation status of the low-density parity check control unit inside the main control, configuration of multiple sets of matrix and dynamic matrix calling mechanism, the low-density parity control unit controller includes Codeword coding cycle A, codeword coding cycle B, codeword coding cycle A, codeword coding cycle B, codeword coding cycle B, codeword coding cycle B, codeword decoding cycle, codeword decoding cycle B, translation Code period B, decoding period B, decoding period A, decoding period B.
  • Embodiment 1 Coordinate with the operation of the controller to select the corresponding matrix to perform the calculation, and select the most efficient operation mode for calculation and verification. Configuring the check matrix with different row weights represents different command cycles, but relatively also represents different Verification capability.
  • the current low-density parity check error correction code core operation method generally uses the effective value sequence or programming operation method in the matrix, and the ratio of the total effective value number in the matrix is approximately the line weight ratio: 5: 3, the codeword compilation code instruction cycle The approximate line weight ratio is 5: 3, and the calculated data throughput rate is the inverse ratio of the line weight value 3: 5, but the verification error correction ability is based on the line weight being higher.
  • the probability of correcting the number of error correction bits is 10: 7. Actual The number of correctable bits varies according to the arrangement of the matrix.
  • the check bit generation and data verification unit design configure multiple sets of matrix storage space with different row weights, coupled with a unit that effectively monitors the read data error rate to detect the data error rate in a timely manner, Or according to different interval settings and component configurations, call different operation matrices and operation sequences so that the codec core can operate in the most power-saving mode as far as possible, so as to effectively control the power consumption of the main control end to generate and verify the core.

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Abstract

一种闪存组件错误率调变核编译码速率节省耗电量的方法，包括以下步骤：A、透过系统软件程序与硬件自动管理；B、配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元适时检测数据错误率；C、根据不同区间设定与组件配置,调用不同运算矩阵与运算序列；D、配合控制器运作挑选对应的矩阵来做运算，选用最有效率的编解核运作方式进行计算。所述方法配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元以适时检测数据错误率，或者根据不同区间设定与组件配置，调用不同运算矩阵与运算序列使编解碼核都可以尽量在最省电模式下运作，达到有效控制主控端产生与校验核的耗电量之效用。

Description

一种闪存组件错误率调变核编译码速率节省耗电量的方法 技术领域
本发明涉及闪存组件错误率调变核编译码速率节省耗电量技术领域，具体为一种闪存组件错误率调变核编译码速率节省耗电量的方法。
背景技术
现行主控装置之低密度奇偶校验纠错码(LDPC)的校验位产生与校验单元设计,皆采用单一固定校验矩阵,配合固定的校验位产生核与数据检查校验核流水线的设计,也以固定的速率的方式做设计.如此一来便无法在不同数据错误率的情况下,有效控制主控端产生与校验核的工作模式,使其可以节省耗电量。
发明内容
本发明的目的在于提供一种在最省电模式下运作,达到有效控制主控端产生与校验核的耗电量之效的一种闪存组件错误率调变核编译码速率节省耗电量的方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种闪存组件错误率调变核编译码速率节省耗电量的方法,包括以下步骤：
A、透过系统软件程序与硬件自动管理；
B、配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元适时检测数据错误率；
C、根据不同区间设定与组件配置,调用不同运算矩阵与运算序列；
D、配合控制器运作挑选对应的矩阵来做运算，选用最有效率的编解核运作方式进行计算。
优选的，所述步骤A主控内部的低密度奇偶校验控制单元控制单元，系统硬件上设有主控芯片，所述主控芯片，所述主控芯片上包括低密度奇偶校验纠错控制器与数据组件控制，所述数据组件控制与数据组件连接。
优选的，所述主控芯片上包括生成矩阵，校验位产生单元，校验矩阵，检查纠错单元。
优选的，所述步骤B系统硬件上包括低密度奇偶校验控制单元控制器，数据组件控制，所述低密度奇偶校验控制单元控制器上包括生成矩阵1，生成矩阵2，校验位产生单元，校验矩阵1，校验矩阵2，检查纠错单元，所述生成矩阵1与生成矩阵2分别与校验位产生单元连接，校验位产生单元与数据组件控制连接，所述校验矩阵1与校验矩阵2分别与检查纠错单元连接，所述检查纠错单元与数据组件控制连接，所述数据组件控制与数据组件连接。
优选的，所述步骤C系统主控内部的低密度奇偶校验控制单元运作状况,未配置多组矩阵与动态矩阵调用机制，低密度奇偶校验控制单元控制器上包括码字编码周期与码字译码周期。
优选的，所述步骤C主控内部的低密度奇偶校验控制单元运作状况,配置多组矩阵与动态矩阵调用机制，低密度奇偶校验控制单元控制器上包括码字编码周期A，码字编码周期B，码字编码周期A，码字编码周期B，码字编码周期B，码字编码周期B，码字译码周期，码字译码周期B，译码周期B，译码周期B，译码周期A，译码周期B。
与现有技术相比，本发明的有益效果是：
在低密度奇偶校验纠错码的校验位产生与资料校验单元设计,配置多组不同行权重的矩阵储存空间,配上有效监测读取数据错误率的单元以适时检测数据错误率,或者根据不同区间设定与组件配置,调用不同运算矩阵与运算序列使编解碼核都可以尽量在最省电模式下运作,达到有效控制主控端产生与校验核的耗电量之效用。
附图说明
图1为本发明一个主控内部的低密度奇偶校验控制单元示意图；
图2为本发明主控内部的低密度奇偶校验控制单元,配置多组不同运算矩阵与运算序列示意图；
图3为本发明主控内部的低密度奇偶校验控制单元运作状况,未配置多组矩阵与动态矩阵调用机制示意图；
图4为本发明主控内部的低密度奇偶校验控制单元运作状况,配置多组矩阵与动态矩阵调用机制示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1,本发明提供一种技术方案：一种闪存组件错误率调变核编译码速率节省耗电量的方法,包括以下步骤：
A、透过系统软件程序与硬件自动管理；
B、配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元适时检测数据错误率；
C、根据不同区间设定与组件配置,调用不同运算矩阵与运算序列；
D、配合控制器运作挑选对应的矩阵来做运算，选用最有效率的编解核运作方式进行计算。
透过系统软件程序与硬件自动管理，主控内部的低密度奇偶校验控制单元控制单元，系统硬件上设有主控芯片在主控芯片在主控芯片上包括低密度奇偶校验纠错控制器与数据组件控制在数据组件控制与数据组件连接，主控芯片上包括生成矩阵，校验位产生单元，校验矩阵，检查纠错单元。
配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元适时检测数据错误率，系统硬件上包括低密度奇偶校验控制单元控制器，数据组件控制在低密度奇偶校验控制单元控制器上包括生成矩阵1，生成矩阵2，校验位产生单元，校验矩阵1，校验矩阵2，检查纠错单元在生成矩阵1与生成矩阵2分别与校验位产生单元连接，校验位产生单元与数据组件控制连接在校验矩阵1与校验矩阵2分别与检查纠错单元连接在检查纠错单元与数据组件控制连接在数据组件控制与数据组件连接。
根据不同区间设定与组件配置,调用不同运算矩阵与运算序列，系统主控内部的低密度奇偶校验控制单元运作状况,未配置多组矩阵与动态矩阵调用机制，低密度奇偶校验控制单元控制器上包括码字编码周期与码字译码周期，主控内部的低密度奇偶校验控制单元运作状况,配置多组矩阵与动态矩阵调用机制，低密度奇偶校验控制单元控制器上包括码字编码周期A，码字编码周期B，码字编码周期A，码字编码周期B，码字编码周期B，码字编码周期B， 码字译码周期，码字译码周期B，译码周期B，译码周期B，译码周期A，译码周期B。
实施例1：配合控制器运作挑选对应的矩阵来做运算，选用最有效率的编解核运作方式进行计算，配置不同行权重的校验矩阵代表着不同的指令周期,但相对也代表着不同的校验能力。
当行权重为5,其码字编解碼周期低于行权重低的矩阵。
当行权重为3,但校验能力高于行权重低的矩阵。
现行低密度奇偶校验纠错码核运作方式,大致上皆采用矩阵内有效值循序或编程运算方式,矩阵内总有效值数量比值约略为行权重比:5:3,码字编译码指令周期约略为行权重比值5:3,其运算之数据吞吐率为行权重值之反比3:5，但校验纠错能力则以行权重高着为优可纠错位数概率10:7，实际可纠错位元数依照矩阵排列不同而有所不同。
透过系统软件程序或硬件自动管理,依照实际运作状况,配合控制器运作挑选对应的矩阵来做运算,在错误位数低的需求下尽量使用行权重低的矩阵,在错误位高的需求下才使用行权重高的矩阵,选用最有效率的编解核运作方式,以有效降低主控端产生与校验核的耗电量。
本发明的有益效果是：
在低密度奇偶校验纠错码的校验位产生与资料校验单元设计,配置多组不同行权重的矩阵储存空间,配上有效监测读取数据错误率的单元以适时检测数据错误率,或者根据不同区间设定与组件配置,调用不同运算矩阵与运算序列使编解碼核都可以尽量在最省电模式下运作,达到有效控制主控端产生与校验核的耗电量之效用。尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人 员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (6)

  1. 一种闪存组件错误率调变核编译码速率节省耗电量的方法,其特征在于：包括以下步骤：
    A、透过系统软件程序与硬件自动管理；
    B、配置多组不同行权重的矩阵储存空间，配上有效监测读取数据错误率的单元适时检测数据错误率；
    C、根据不同区间设定与组件配置,调用不同运算矩阵与运算序列；
    D、配合控制器运作挑选对应的矩阵来做运算，选用最有效率的编解核运作方式进行计算。
  2. 根据权利要求1所述的一种闪存组件错误率调变核编译码速率节省耗电量的方法,其特征在于：所述步骤A主控内部的低密度奇偶校验控制单元控制单元，系统硬件上设有主控芯片，所述主控芯片，所述主控芯片上包括低密度奇偶校验纠错控制器与数据组件控制，所述数据组件控制与数据组件连接。
  3. 根据权利要求2所述的一种闪存组件错误率调变核编译码速率节省耗电量的方法,其特征在于：所述主控芯片上包括生成矩阵，校验位产生单元，校验矩阵，检查纠错单元。
  4. 根据权利要求1所述的一种闪存组件错误率调变核编译码速率节省耗电量的方法,其特征在于：所述步骤B系统硬件上包括低密度奇偶校验控制单元控制器，数据组件控制，所述低密度奇偶校验控制单元控制器上包括生成矩阵1，生成矩阵2，校验位产生单元，校验矩阵1，校验矩阵2，检查纠错单元，所述生成矩阵1与生成矩阵2分别与校验位产生单元连接，校验位产生单元与数据组件控制连接，所述校验矩阵1与校验矩阵2分别与检查纠错单元连接，所述检查纠错单元与数据组件控制连接，所述数据组 件控制与数据组件连接。
  5. 根据权利要求1所述的一种闪存组件错误率调变核编译码速率节省耗电量的方法,其特征在于：所述步骤C系统主控内部的低密度奇偶校验控制单元运作状况,未配置多组矩阵与动态矩阵调用机制，低密度奇偶校验控制单元控制器上包括码字编码周期与码字译码周期。
  6. 根据权利要求1所述的一种闪存组件错误率调变核编译码速率节省耗电量的方法,其特征在于：所述步骤C主控内部的低密度奇偶校验控制单元运作状况,配置多组矩阵与动态矩阵调用机制，低密度奇偶校验控制单元控制器上包括码字编码周期A，码字编码周期B，码字编码周期A，码字编码周期B，码字编码周期B，码字编码周期B，码字译码周期，码字译码周期B，译码周期B，译码周期B，译码周期A，译码周期B。
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