WO2020124980A1 - 应用于闪存控制器中的自适应polar码纠错码系统和方法 - Google Patents

应用于闪存控制器中的自适应polar码纠错码系统和方法 Download PDF

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WO2020124980A1
WO2020124980A1 PCT/CN2019/093278 CN2019093278W WO2020124980A1 WO 2020124980 A1 WO2020124980 A1 WO 2020124980A1 CN 2019093278 W CN2019093278 W CN 2019093278W WO 2020124980 A1 WO2020124980 A1 WO 2020124980A1
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flash memory
adaptive
error
polar code
decoding
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PCT/CN2019/093278
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French (fr)
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高美洲
孙大朋
郭泰�
裴永航
刘忞斋
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山东华芯半导体有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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  • the invention relates to a polar code error correction code system and method, in particular to an adaptive polar code error correction code system and method applied in a flash memory controller, and belongs to the field of flash memory storage control.
  • error correction codes are often used to enable the receiver to correct the error and obtain the correct signal when the signal transmission is incorrect.
  • Error correction codes can be used in many systems.
  • signal transmission may be interfered by channel effects and noise, which may cause the data stored in the flash memory storage device to be incorrect.
  • the data stored in the flash memory storage device is the data encoded by the error correction code device.
  • the error correction code is a necessary functional unit. With the emergence of new technology of memory, it is more and more advanced, the size of the memory unit is getting smaller and smaller, and the number of electrons is getting less and less, and the data stored in the memory unit is gradually increasing, causing the flash memory to be generated during the reading process. The probability of errors continues to increase, so it is especially necessary to use a suitable and strong error correction code decoding mechanism in the flash memory controller.
  • the key to measuring the quality of a flash memory controller is its adaptability, which can support multiple manufacturers and different processes of flash memory. Especially as the technology of the flash memory is more advanced and the volume is smaller, and the data stored by the flash memory storage unit is also increased, the probability of errors generated by the flash memory during reading is also increasing.
  • the error correction code decoding capability of the flash memory controller is an important factor in determining whether the flash memory controller is qualified. Therefore, it is an inevitable trend for flash memory controllers to have an adaptable error correction code.
  • Polar code (polarization code) is a polarization code based on the theory of channel polarization concept proposed by Arikan at the International Information Theory ISIT Conference in 2008. It is suitable for almost all channels, its performance is close to Shannon limit, and it has clear and simple encoding and decoding algorithms.
  • the decoding is simple and can be operated in parallel, suitable for hardware implementation.
  • the error correction performance that Polar codes can achieve exceeds the currently widely used Turbo codes and LDPC codes.
  • Polar code has huge application potential, and its application in the new generation of mobile communication field has been highly recognized by many parties.
  • the error correction capability of the error correction code in the flash memory control device also needs to be enhanced.
  • the main error correction code is the LDPC code.
  • the technical problem to be solved by the present invention is to provide an adaptive polar code error correction code system and method applied in a flash memory controller for improving the error correction capability of the error correction code of the flash memory, protecting the stability of the stored data and Improve flash memory life.
  • an adaptive polar code error correction code system applied in a flash memory controller, including a Polar code encoder, a Polar code generation matrix, an adaptive perceptron, and an error Detector, data processor, flash feature log unit, Polar code decoder and arbiter, Polar code encoder is connected between the host and the flash memory, and the Polar code encoder is connected to the Polar code generation matrix and adaptive sensor ,
  • the adaptive perceptron is connected to the flash characteristic log unit and the arbiter
  • the data processor is connected between the Polar code decoder and the flash memory
  • the Polar code decoder is connected to the adaptive perceptron
  • the data processor is connected to the flash characteristic log unit
  • the error detector is connected between the arbiter and the data processor, and the arbiter is connected to the Polar code decoder
  • the flash memory feature log unit stores the log content corresponding to the flash memory model, including the occurrence of flash memory at this time The probability of error and the number of flash block erasure
  • the error detector judges that the decoding fails according to the arbiter and outputs the decoding.
  • Data error the data processor processes the data read from the flash memory according to the flash characteristic log and weights it with an error detector, and finally outputs the maximum likelihood value of each bit of data.
  • the adaptive sensor verifies that the flash block is real.
  • the difference between the probability of an error occurring and the probability of an error occurring in the flash memory pre-stored in the log unit determines whether to adjust the channel offset probability value according to the relationship between the difference and the threshold, and generates a Polar code generation matrix according to the adjusted channel offset probability value.
  • the Polar code encoder encodes the data obtained from the host according to the adaptive sensor and Polar code generation matrix and then stores it in the flash memory; the adaptive sensor according to the flash block type, the probability of the flash block error and the flash block erasure The number of times to select the check matrix corresponding to the channel offset probability.
  • the Polar decoder performs decoding operations based on the check matrix and the maximum likelihood value output by the data processor.
  • the adaptive perceptron includes an information collector and an adaptive regulator.
  • the information collector collects real-time flash error rate, flash erase and write times, and flash characteristics log content.
  • the adaptive regulator is based on the information of the information collector. The principle of flash memory characteristics is adaptively adjusted.
  • the adaptive adjustment means that the adaptive regulator verifies the difference between the real-time flash error rate and the probability of repeated error of the flash content log content. If the difference is less than a preset threshold, the channel offset probability value remains unchanged, and if the difference is greater than the Set a threshold and adjust the channel offset probability value according to the real-time flash error rate.
  • the invention also discloses an adaptive polar code error correction code method applied in the flash memory controller, which includes an adaptive encoding process and an adaptive decoding process.
  • the adaptive encoding process includes the following steps: S11), adaptive sensor calibration Verify the difference between the probability of error that actually occurs in the flash memory block and the probability of the error that occurs in the flash memory pre-stored in the log unit, determine whether to adjust the channel offset probability value according to the relationship between the difference and the threshold, and generate the Polar code according to the adjusted channel offset probability value Generation matrix; S12), the data encoder encodes the codeword information according to the polar generation matrix; S13), stores the encoded data and the check code in the flash memory; the adaptive decoding process includes the following steps: S21), The data processor reads the code word information from the flash memory; S22), the data processor performs data processing according to the flash content log content and the detection result of the error detector to output the maximum likelihood value of each bit; S23), polar code The decoder decodes the polar code according to the maximum likelihood value, and
  • step S24 Use the arbiter to judge, if the decoding is successful, go to step S28, if the decoding is not successful, go to step S25, and feed back the number of errors to the adaptive sensor and error detector; S25) 1.
  • the decider judges whether the decoding is successful based on whether the decoded data and the check matrix are equal to 0. If it is equal to 0, the decoding is successful, and the number of successful correction errors is output. If it is not successful, it is not equal to 0, and the maximum energy is output. The number of corrections.
  • a method of applying an adaptive Polar code error correction code in a flash memory storage controller of the present invention is mainly aimed at improving the error correction capability of the error correction code of the flash memory, protecting the stability of stored data, and improving the flash memory Memory life.
  • Changing the Polar code into adaptive encoding and decoding improves the adaptability of the flash memory controller, and also greatly enhances the error correction capability of the flash memory controller, and at the same time improves the service life of the flash memory.
  • FIG. 1 is a functional block diagram of the storage controller device according to Embodiment 1;
  • FIG. 2 is a structural block diagram of an adaptive polar code error correction code system according to the present invention.
  • Figure 3 is a structural block diagram of an adaptive perceptron
  • Figure 4 is a flowchart of adaptive polar code decoding.
  • the polarization code is a linear block code, which is obtained by constructing a generator matrix. As long as the given code length N, the code structure is uniquely determined.
  • the polarization code is based on the phenomenon of channel polarization, which achieves its advantages while avoiding its shortcomings.
  • the transmission of message bits on the most reliable sub-channel is to increase the length, and the transmission of frozen bits on the least reliable sub-channel is to avoid the short.
  • Polarization codes have their own characteristics of algebraic coding and probabilistic coding. As long as the coding length of a polarized code is given, its coding structure is uniquely determined, and the coding process can be completed in the form of a generator matrix, which is consistent with the common thinking of algebraic coding.
  • Polarization codes use the process of channel combination and channel splitting to select specific coding schemes, and also use probabilistic algorithms when decoding.
  • Polar codes are constructed by introducing the concept of channel polarization.
  • Channel polarization is divided into two stages, namely channel association and channel splitting.
  • the symmetric capacity of each sub-channel will show a two-level differentiation trend: as the code length (that is, the number of joint channels) N increases, the capacity of some sub-channels tends to 1, while the capacity of other sub-channels The capacity tends to 0.
  • Polar uses this phenomenon of channel polarization to transmit message bits on K sub-channels with a capacity of 1 and transmit frozen bits on the remaining sub-channels (that is, fixed bits known to the sender and receiver, usually set to all zeros) ).
  • the code thus formed is the Polar code, and the code rate is K/N.
  • Polar codes When coding Polar codes, we must first distinguish the reliability of N split channels, that is, which belong to reliable channels and which belong to unreliable channels, and measure the reliability of each polarized channel. In the flash memory controller, different measurement methods are used along with the life cycle of the flash memory, and corresponding coding is performed. In the decoding of Polar codes, based on the serial offset decoding algorithm, only this type of decoding algorithm can make full use of the structure of the polarization code, and at the same time ensure that the capacity can be reached when the code length is long enough. The complexity of the Polar decoder is only O(NlogN) and the code length is approximately linear. This patent proposes an adaptive Polar code error correction code method applied in flash memory.
  • Polar code encoders can be implemented with various algorithms and coding devices with hardware and software architectures, and all can achieve the effects of the present invention.
  • the polarization channel metric of the Polar code encoder can be constructed using the Pap method, density evolution method, and deadly approximation method.
  • the rate-adaptive puncturing algorithm and quasi-uniform puncturing algorithm can be used to encode ,Encoded by hardware circuit, and implemented by software or hardware with processor to realize coding.
  • the Polar code decoder can be implemented by decoding devices of various algorithms and hardware and software architectures, and all can achieve the effect of the invention.
  • the Polar code decoding circuit may use a serial cancellation decoding algorithm, a serial cancellation list decoding algorithm, and a cyclic redundancy check-assisted cancellation list decoding algorithm, etc., and a decoding architecture implemented by a hardware circuit, or a combination of software or hardware
  • the processor implements decoding and other methods.
  • FIG. 1 is a simplified functional block diagram of an embodiment of a memory controller device of the present invention.
  • the flash memory controller contains an adaptive Polar code decoder.
  • the flash memory storage controller is mainly responsible for data reading and writing, data storage and other functions.
  • the flash memory controller obtains data from the host, and the data generated by the adaptive Polar code decoder for encoding operation is stored in the flash memory. If the host wants to obtain the data in the flash memory, the flash memory controller needs to be read from the flash memory, and the decoding operation is performed by the adaptive Polar code decoder to generate data input to the host.
  • FIG. 2 it is a structural block diagram of the adaptive polar code error correction code system described in this embodiment, including the adaptive Polar code error correction code, which is composed of a Polar code encoder, an adaptive perceptron, an error detector, and data processing.
  • the adaptive Polar code error correction code which is composed of a Polar code encoder, an adaptive perceptron, an error detector, and data processing.
  • Device flash memory feature log, Polar code decoder, Polar code generation matrix, and arbiter.
  • Polar code generation matrix is a matrix that has been verified and tested according to the life cycle of flash memory and application scenarios.
  • the Polar code generation matrix evaluates the reliability of the transmission channel based on the polarization channel reliability estimation.
  • After a lot of test flash memory we establish error models in different life cycles of the flash memory to determine the channel transfer probability.
  • the raw data stored in the flash memory is compared and counted with the data after the error, and the error situation of the flash memory life cycle is summarized. According to the test data, the wrong data types are fitted, such as Gaussian distribution, normal distribution, random distribution, and Poisson distribution. Wait. According to the above distribution, the channel offset probability in different life cycles of the flash memory can be established, which can better reflect the real flash memory channel situation and promote the high performance of Polar code decoding.
  • channel transfer probabilities in different life cycles of the flash memory based on the number of flashes of the flash memory block and the error rate. For example, the number of flash blocks is 500, and the probability of error is 0.5%-0.6%. At this time, the channel offset probability is 0.02%. If it exceeds a certain value in the probability interval, its channel offset probability will become larger or smaller. .
  • the flash feature log is a feature that is obtained after a long period of extensive testing of flash memory.
  • Each flash memory has its own unique log content.
  • the log content in the flash memory feature log unit includes the error models of the flash memory tested in different life cycles in advance, that is, the probability of the corresponding error of the flash memory under the following erasure times.
  • the arbiter judges whether the Polar code is successfully decoded and the number of data errors, and obtains the true error probability of the flash memory.
  • the adaptive sensor verifies the true error probability of the flash block and the flash memory pre-stored in the log unit. At this time, the difference in the probability of error occurrence depends on the relationship between the difference and the threshold to determine whether to adjust the channel offset probability value.
  • the Polar code generation matrix is generated according to the adjusted channel offset probability value.
  • the Polar code encoder is based on the adaptive sensor and The Polar code generation matrix encodes the data obtained from the host and stores it in the flash memory.
  • the error detector judges that the decoding fails according to the arbiter, and outputs the decoded data error.
  • the data processor processes the data read from the flash memory according to the flash memory characteristic log and uses the error detector to weight, and finally outputs each bit of data Maximum likelihood value, the adaptive sensor selects the check matrix corresponding to the channel offset probability according to the flash block type, the probability of the flash block error, and the flash block erase and write times.
  • the Polar decoder uses the check matrix and data processing The maximum likelihood value output by the device is decoded.
  • the data processor gives the maximum likelihood value according to the probability of an error in the flash memory block and the number of times the flash memory block is erased and the actual probability of the error occurred in the flash memory block, such as the probability of 0.5%-0.6% error in the flash memory block and the flash memory block
  • the number of erasure times is 500
  • the error probability of the real flash block is 0.55%
  • the maximum likelihood value in the Table is +5 or -5. If the error probability of the real flash block is 0.45%, the maximum likelihood value in the Table +7 or -7.
  • the adaptive sensor includes an information collector and an adaptive regulator.
  • the information collector collects real-time flash error rate, flash erase and write times, and flash memory characteristics log content.
  • the adaptive regulator is based on the information collector
  • the information is adaptively adjusted according to the principle of flash memory characteristics.
  • the adaptive adjustment means that the adaptive regulator verifies the difference between the real-time flash error rate and the probability of repeated error of the flash content log content. If the difference is less than the preset threshold, the channel offset probability value does not change, if the difference is greater than the preset threshold, Adjust the channel offset probability value according to the real-time flash error rate.
  • the generation matrix of Polar codes will be different when the channel offset probability is different.
  • This embodiment discloses an adaptive polar code error correction code method applied in a flash memory controller, and adaptively adjusts the number of error correction bits according to the error probability of data stored in the flash memory and different processes.
  • the adaptive Polar code error correction code of the present invention can automatically expand the number of error correction bits to improve the reliability of data and the service life of flash memory.
  • the adaptability of the invention of this patent is mainly reflected in the encoder and decoder of the Polar code, which automatically adjusts the number of error correction bits according to the error detector, thereby adjusting the encoding method and its decoding method.
  • the same flash erase and write times will have different probability of errors, and different manufacturers will also be different. Every manufacturer will test the probability of error occurrence of flash memory blocks of flash memory in different erasure times , Resulting in different Tables, resulting in different channel offset probabilities and different generation matrices of Polar codes.
  • the Table is stored in the flash memory characteristic log.
  • the adaptive perceptron generates different polar code generation matrices and check matrices according to the pre-stored table and the true error occurrence probability output by the decider, so as to achieve Error probability and adaptive adjustment by different processes.
  • the error detector detects that the decoding failed, and when Polar decoding is performed on this data again, it will trigger the data processor to adjust the maximum likelihood value related to the data, so that the channel offset probability is more reliable. As a result, the number of error correction bits changes, making the error correction capability stronger.
  • This embodiment is divided into an encoding process and a decoding process.
  • the specific process is as follows.
  • the adaptive sensor verifies the difference between the error probability of the actual occurrence of the flash memory block and the probability of the error of the flash memory pre-stored in the log unit, and determines whether to adjust the channel offset probability value according to the relationship between the difference and the threshold.
  • the channel offset probability value generates a Polar code generation matrix
  • the data encoder encodes the codeword information according to the polar generation matrix
  • the adaptive decoding process includes the following steps:
  • the data processor reads codeword information from the flash memory
  • the data processor performs data processing according to the flash memory characteristic log content and the detection result of the error detector to output the maximum likelihood value of each bit;
  • the polar code decoder decodes the polar code according to the maximum likelihood value, and then performs decoding judgment. If the decoding is successfully received, if it fails and does not reach a certain number of iterations, the Polar decoding iteration is continued, and if a certain number of iterations is reached, the decoding is not yet performed. If successful, proceed to the next judgment;
  • step S24 Use the decider to judge, if the decoding is successful, go to step S28, if the decoding is not successful, go to step S25, and feed back the number of errors that occurred to the adaptive sensor and error detector;
  • step S25 Decide whether to continue decoding. If the decoding is not continued, go to step S27. If the decoding continues, go to step S26;
  • step S26 start the error detector, the error detector outputs the decoded data error and feeds it back to the data processor, configure the parameters for decoding again, go to step S21;
  • the arbiter judges whether the decoding is successful based on whether the decoded data and the check matrix are equal to 0. If it is equal to 0, the decoding is successful, and the number of successful correction errors is output. If it is not successful, it is not equal to 0, and the maximum output The number of correctable errors.
  • the invention can improve the error correction capability of the error correction code of the flash memory, protect the stability of stored data, and increase the service life of the flash memory.
  • Changing the Polar code into adaptive encoding and decoding improves the adaptability of the flash memory controller, and also greatly enhances the error correction capability of the flash memory controller, and at the same time improves the service life of the flash memory.

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Abstract

一种应用闪存存储控制器中的自适应Polar码纠错码的系统和方法，主要针对提高闪存存储器的纠错码的纠错能力、保护存储数据的稳定性和提高闪存存储器使用寿命。对Polar码进行自适应的编、解码改善了闪存存储控制器的适应性，也大大增强了闪存存储控制器的纠错能力，同时提高了闪存存储器使用寿命。

Description

应用于闪存控制器中的自适应polar码纠错码系统和方法 技术领域
本发明涉及一种polar码纠错码系统和方法，具体是一种应用于闪存控制器中的自适应polar码纠错码系统和方法，属于闪存存储控制领域。
背景技术
在各种需要进行信号传输的应用中，常会采用纠错码，能使信号传输错误时接收端，得以更正错误而获得正确的信号。纠错码可以应用于许多系统中，在通信系统中，信号传输时可能会受到信道效应及噪声的干扰，从而造成闪存存储装置中所存储的数据已经不正确。闪存存储装置中所存储的数据是经过纠错码装置编码后的数据，对于闪存存储控制装置来说，纠错码是必需的一个功能单元。随着存储器的新的工艺出现，其越来越先进，存储器单元体积越来越小电子数越来越少，并且存储单元所存储的数据也逐渐在增加，造成闪存存储器在读取过程中产生的错误概率不断升高，因而闪存控制器中采用合适、较强的错误纠错码译码机制，尤其必要。
此外，衡量一个闪存存储控制器的好坏关键是它的适应性，它可以支持多个厂商和不同工艺的闪存存储器。尤其当闪存存储器的工艺越先进、体积越小，并且闪存存储单元存储的数据也增加，造成闪存存储器在读取时产生的错误概率也不断的增加。然而，闪存存储控制器的纠错码译码能力是决定闪存存储控制器是否合格的重要因素。因此，闪存存储控制器具有一个适应性强的纠错码是必然趋势需求。
Polar码(极化码)是Arikan于2008年在国际信息论ISIT会议上提出的一种基于信道极化概念理论的极化码。几乎适用于所有的信道，它的性能逼近香农限，且有明确而简单的编码及译码算法，译码简单且可实行并行操作，适合硬件实现。Polar码所能达到的纠错性能超过目前广泛使用的Turbo码、LDPC码。Polar码具有巨大的应用潜力，在新一代的移动通信领域应用，得到了多方高度认可。根据闪存存储装置的工艺越来越先进，闪存存储器控制装置中的纠错码的纠错能力也需要增强。在目前闪存存储器控制装置中，主要的纠错码是LDPC码，随着错误概率的增高，LDPC码的对空间要求及运算能力也逐渐增高；随着闪存存储工艺的提高，存储数据错误率增高，闪存在使用过程中，发生错误的概率逐渐增高，LDPC码解码延迟也逐渐增加，会影响用户的体验度，所以需要纠错能力更强、更灵活和适应性强的纠错码。所以下一代闪存存储控制装置中选择的Polar码来代替LDPC码是比较恰当的。
发明内容
本发明要解决的技术问题是提供一种应用于闪存控制器中的自适应polar码纠错码系统和方法，用于提高闪存存储器的纠错码的纠错能力、保护存储数据的稳定性和提高闪存存储器使用寿命。
为了解决所述技术问题，本发明采用的技术方案是：一种应用于闪存控制器中的自适应polar码纠错码系统，包括Polar码编码器、Polar码生成矩阵、自适应感知器、错误侦测器、数据处理器、闪存特性log单元、Polar码解码器和判决器，Polar码编码器连接于主机和闪存存储器之间，并且Polar码编码器与Polar码生成矩阵、自适应感知器相连，自适应感知器与闪存特性log单元、判决器相连，数据处理器连接于Polar码解码器与闪存存储器之间，Polar码解码器又与自适应感知器相连，数据处理器与闪存特性log单元相连，错误侦测器连接于判决器与数据处理器之间，判决器又与Polar码解码器相连；闪存特性log单元内存储有与闪存存储器型号相对应的log内容，包括闪存此时的发生错误的概率和闪存块擦写次数，判决器判断Polar码解码是否成功以及数据错误的位数，得出闪存存储器真实的发生的错率概率，错误侦测器根据判决器判断解码失败，输出解码的数据错误，数据处理器根据闪存特性log对从闪存读取的数据进行处理并利用错误侦测器进行加权，最后输出每位数据的最大似然值，自适应感知器校验闪存块真实的发生的错误概率与log单元预存的闪存此时的发生错误的概率的差异，根据差异与阈值的关系决定是否调整信道偏移概率值，根据调整后的信道偏移概率值生成Polar码生成矩阵，Polar码编码器根据自适应感知器和Polar码生成矩阵对从主机获取的数据进行编码处理然后存储至闪存存储器；自适应感知器根据根据闪存块类型、闪存块发生错误的概率和闪存块擦写次数来选择对应信道偏移概率的校验矩阵，Polar解码器根据校验矩阵、数据处理器输出的最大似然值进行解码运算。
进一步的，所述自适应感知器包括信息收集器和自适应调节器，信息收集器收集实时的闪存错误率、闪存擦写次数和闪存特性log内容，自适应调节器根据信息收集器的信息根据闪存特性原理进行自适应的调节。
进一步的，所述自适应调节指自适应调节器校验实时的闪存错误率与闪存特性log内容重错误概率的差异，如果差异小于预设阈值，信道偏移概率值不变，如果差异大于预设阈值，根据实时的闪存错误率调整信道偏移概率值。
本发明还公开了一种应用于闪存控制器中的自适应polar码纠错码方法，包括自适应编码流程和自适应解码流程，自适应编码流程包括以下步骤：S11)、自适应感知器校验闪存块真实发生的错误概率与log单元预存的闪存此时发生错误的概率的差异，根据差异与阈值 的关系决定是否调整信道偏移概率值，根据调整后的信道偏移概率值生成Polar码生成矩阵；S12)、数据编码器根据polar生成矩阵对码字信息进行相应编码；S13)、把编码完的数据及校验码存储到闪存存储器中；自适应解码流程包括以下步骤：S21)、数据处理器从闪存存储器中读取码字信息；S22)、数据处理器根据闪存特性log内容和错误侦测器的侦测结果进行数据处理输出每位的最大似然值；S23)、polar码解码器根据最大似然值进行polar码解码，然后进行解码判断，如果成功接收解码，如果失败且没有达到一定迭代次数，继续进行Polar解码迭代，如果达到一定迭代次数还没有解码成功则进入下一步判决；S24)、利用判决器进行判断，如果解码成功，转到步骤S28，如果解码不成功，转到步骤S25，同时把发生错误个数反馈给自适应感知器和错误侦测器；S25)、判决是否继续进行解码，如果不继续解码，转到步骤S27，如果继续解码，转到步骤S26；S26)、启动错误侦测器，错误侦测器输出解码的数据错误并反馈给数据处理器，配置好再次解码的参数，转到步骤S21；S27)、Polar码解码失败，结束解码过程；S28)、Polar码解码成功，结束解码过程。
进一步的，判决器根据解码数据与校验矩阵相乘是否等于0来判断是否解码成功，如果等于0，解码成功，输出成功纠正错误的个数，如果不成功是不等于0，输出最大的能纠错的个数。
本发明的有益效果：本发明的一种应用闪存存储控制器中的自适应Polar码纠错码的方法主要针对提高闪存存储器的纠错码的纠错能力、保护存储数据的稳定性和提高闪存存储器使用寿命。将Polar码变为自适应的编、解码改善了闪存存储控制器的适应性，也大大增强了闪存存储控制器的纠错能力，同时提高了闪存存储器使用寿命。
附图说明
图1为实施例1所述存储控制器装置的功能框图；
图2为本发明所述自适应polar码纠错码系统的结构框图；
图3为自适应感知器的结构框图；
图4为自适应polar码解码的流程图。
具体实施方式
下面结合附图和具体实施例对本发明作进一步的说明。
实施例1
本实施例中，首先对polar码的基本知识进行以下介绍。
极化码是一种线性分组码，通过构造生成矩阵而获得编码。只要给定码长N，编译码结构就唯一确定。极化码基于信道极化现象，做到了扬长而避短。在最可靠的子信道上传输 消息比特是为扬长，在最不可靠的子信道上传输冻结比特是为避短。极化码具备了代数编码和概率编码两者各自的特点。极化码只要给定编码长度，它的编译码结构就唯一确定了，而且可以通过生成矩阵的形式完成编码过程，这一点和代数编码的常见思维是一致的。极化码利用信道联合(Channel Combination)与信道分裂(Channel Splitting)的过程来选择具体的编码方案，而且在译码时也是采用概率算法。
Polar码是通过引入信道极化概念而构建的。信道极化分为两个阶段，分别是信道联合和信道分裂。通过信道的联合与分裂，各个子信道的对称容量将呈现两级分化的趋势：随着码长(也就是联合信道数)N的增加，一部分子信道的容量趋于1，而其余子信道的容量趋于0。Polar Code正是利用这一信道极化的现象，在容量趋于1的K个子信道上传输消息比特，在其余子信道上传输冻结比特(即收发双方已知的固定比特，通常设置为全零)。由此构成的编码即为Polar码，码率为K/N。在Polar码编码时，首先要区分出N个分裂信道的可靠程度，即哪些属于可靠信道，哪些属于不可靠信道，对各个极化信道的可靠性进行度量。在闪存存储控制器中，随着闪存的生命周期才用不同的度量方式，并进行相应的编码。在Polar码译码时，基于串行抵消译码算法，只有这类译码算法才能充分利用极化码的结构，并且同时保证在码长足够长时容量可达。Polar译码器的复杂度仅为O(NlogN)和码长呈近似线性的关系。本专利提出一种应用于闪存存储器中的自适应Polar码纠错码方法。
Polar码编码器可以采用各种算法及软硬件架构的编码装置实现，而都能够到达本发明之功效。例如，Polar码编码器的极化信道度量可以采用巴氏参数法、密度进化法和搞死近似法等来构造生成矩阵，可以采用速率适配的凿孔算法和准均匀凿孔算法等进行编码，以硬件电路实现的编码架构、以软件或硬件搭配处理器实现编码等方式实现。
Polar码解码器可以采用各种算法及软硬件架构的解码装置实现，而都能够达成本发明之功效。例如，Polar码解码电路可以采用串行抵消译码算法、串行抵消列表译码算法和循环冗余校验辅助的抵消列表译码算法等，以硬件电路实现的解码架构、以软件或硬件搭配处理器实现译码等方式实现。
图1为本发明的存储控制器装置的一个实施例简化后的功能框图。闪存存储控制器中包含自适应Polar码解码器。闪存存储控制器主要负责数据的读写和数据的存储及其它功能。闪存存储控制器从主机获得数据经过自适应Polar码解码器进行编码运算而产生的数据存储到闪存存储器中。如果主机想要获得闪存存储器中的数据需要闪存存储控制器来从闪存存储器中读取出来，经过自适应Polar码解码器进行解码运算而产生数据输入给主机。
如图2所示，为本实施例所述自适应polar码纠错码系统的结构框图，包括自适应 Polar码纠错码由Polar码编码器、自适应感知器、错误侦测器、数据处理器、闪存特性log、Polar码解码器、Polar码生成矩阵和判决器。
Polar码生成矩阵是经过验证、测试的生成矩阵，根据闪存的生命周期和应用场景而生成的矩阵。Polar码生成矩阵是根据极化信道可靠性估计来评估传输信道的可靠性，我们经过大量测试闪存建立闪存不同生命周期内的错误模型来确定信道转移概率。通过闪存存储的Raw数据来与发生错误后数据进行比对和统计，总结出闪存生命周期发生错误的情况，根据测试数据拟合错误数据类型，比如高斯分布、正态分布、随机分布和泊松分布等。根据上述分布可以建立闪存不同生命周期内信道偏移概率，更能反应真实的闪存信道情况，促使Polar码解码的性能很高。我们会根据闪存的存储块的擦写次数和发生的错误率，生成闪存不同生命周期内的信道转移概率。例如闪存块的擦写次数为500，发生错误的概率为0.5％-0.6％，此时信道偏移概率为0.02％，如果超出概率区间一定值，它的信道偏移概率会变大或变小。
闪存特性log是经过长时间大量测试闪存而得出的特性，每款闪存都有它独有的log内容。闪存特性log单元内的log内容包括事先测试的闪存不同生命周期内的错误模型，即闪存在以下擦写次数下对应的发生错误的概率。
编码时，判决器判断Polar码解码是否成功以及数据错误的位数，得出闪存存储器真实的发生的错率概率，自适应感知器校验闪存块真实的发生的错误概率与log单元预存的闪存此时的发生错误的概率的差异，根据差异与阈值的关系决定是否调整信道偏移概率值，根据调整后的信道偏移概率值生成Polar码生成矩阵，Polar码编码器根据自适应感知器和Polar码生成矩阵对从主机获取的数据进行编码处理然后存储至闪存存储器。
解码时，错误侦测器根据判决器判断解码失败，输出解码的数据错误，数据处理器根据闪存特性log对从闪存读取的数据进行处理并利用错误侦测器进行加权，最后输出每位数据的最大似然值，自适应感知器根据根据闪存块类型、闪存块发生错误的概率和闪存块擦写次数来选择对应信道偏移概率的校验矩阵，Polar解码器根据校验矩阵、数据处理器输出的最大似然值进行解码运算。
数据处理器根据闪存特性Log记录的闪存块发生错误的概率和闪存块擦写次数和闪存块实际发生错误概率给出最大似然值，例如闪存块发生错误的概率0.5％-0.6％和闪存块擦写次数500，真实闪存块发生错误概率为0.55％，在Table中的最大似然值为+5或-5，如果真实闪存块发生错误概率为0.45％，在Table中的最大似然值为+7或-7。数据处理其根据错误侦测器反馈的错误信息调整最大似然值，使信道偏移概率更可信，从而纠错位数发生改 变，使纠错能力更强些，并且提高了解码时间，减小解码延迟，提高了Polar码解码性能。
如图4所示，所述自适应感知器包括信息收集器和自适应调节器，信息收集器收集实时的闪存错误率、闪存擦写次数和闪存特性log内容，自适应调节器根据信息收集器的信息根据闪存特性原理进行自适应的调节。所述自适应调节指自适应调节器校验实时的闪存错误率与闪存特性log内容重错误概率的差异，如果差异小于预设阈值，信道偏移概率值不变，如果差异大于预设阈值，根据实时的闪存错误率调整信道偏移概率值。信道偏移概率不同Polar码的生成矩阵就会不同。
实施例2
本实施例公开一种应用于闪存控制器中的自适应polar码纠错码方法，根据闪存存储器存储数据的出错概率和不同工艺来进行自适应性调节纠错的位数。本发明的自适应Polar码纠错码可以自动扩展纠错位数来提高数据的可靠性及闪存存储器的使用寿命。本专利发明的自适应性主要体现在Polar码的编码器和解码器，它根据侦测错误器来自动调节纠错位数，从而调整编码方式及其解码方式。
闪存在不同工艺下，相同的闪存擦写次数，发生的错误的概率会不一样，不同厂商的也会不一样，每家厂商我们都会测试闪存的闪存块在不同擦写次数区间的发生错误概率，从而生成不一样的Table，从而导致信道偏移概率不一样，Polar码的生成矩阵也不一样。Table存储在闪存特性log内，在编码或者解码的过程中，由自适应感知器根据预存的table和判决器输出的真实的错误发生概率生成不同的polar码生成矩阵和校验矩阵，从而实现根据出错概率和不同工艺进行的自适应调节。
解码过程中，如果侦测错误器侦测出解码失败，等再一次对此数据进行Polar解码时，它会触发数据处理器调整数据相关的最大似然值，使信道偏移概率更可信，从而纠错位数发生改变，使纠错能力更强些。
本实施例分为编码流程和解码流程，具体流程如下。
S11)、自适应感知器校验闪存块真实发生的错误概率与log单元预存的闪存此时发生错误的概率的差异，根据差异与阈值的关系决定是否调整信道偏移概率值，根据调整后的信道偏移概率值生成Polar码生成矩阵；
S12)、数据编码器根据polar生成矩阵对码字信息进行相应编码；
S13)、把编码完的数据及校验码存储到闪存存储器中。
如图4所示，自适应解码流程包括以下步骤：
S21)、数据处理器从闪存存储器中读取码字信息；
S22)、数据处理器根据闪存特性log内容和错误侦测器的侦测结果进行数据处理输出每位的最大似然值；
S23)、polar码解码器根据最大似然值进行polar码解码，然后进行解码判断，如果成功接收解码，如果失败且没有达到一定迭代次数，继续进行Polar解码迭代，如果达到一定迭代次数还没有解码成功则进入下一步判决；
S24)、利用判决器进行判断，如果解码成功，转到步骤S28，如果解码不成功，转到步骤S25，同时把发生错误个数反馈给自适应感知器和错误侦测器；
S25)、判决是否继续进行解码，如果不继续解码，转到步骤S27，如果继续解码，转到步骤S26；
S26)、启动错误侦测器，错误侦测器输出解码的数据错误并反馈给数据处理器，配置好再次解码的参数，转到步骤S21；
S27)、Polar码解码失败，结束解码过程；
S28)、Polar码解码成功，结束解码过程。
本实施例中，判决器根据解码数据与校验矩阵相乘是否等于0来判断是否解码成功，如果等于0，解码成功，输出成功纠正错误的个数，如果不成功是不等于0，输出最大的能纠错的个数。
本发明可以提高闪存存储器的纠错码的纠错能力、保护存储数据的稳定性和提高闪存存储器使用寿命。将Polar码变为自适应的编、解码改善了闪存存储控制器的适应性，也大大增强了闪存存储控制器的纠错能力，同时提高了闪存存储器使用寿命。
以上描述的仅是本发明的基本原理和优选实施例，本领域技术人员根据本发明做出的改进和替换，属于本发明的保护范围。

Claims (5)

  1. 一种应用于闪存控制器中的自适应polar码纠错码系统，其特征在于：包括Polar码编码器、Polar码生成矩阵、自适应感知器、错误侦测器、数据处理器、闪存特性log单元、Polar码解码器和判决器，Polar码编码器连接于主机和闪存存储器之间，并且Polar码编码器与Polar码生成矩阵、自适应感知器相连，自适应感知器与闪存特性log单元、判决器相连，数据处理器连接于Polar码解码器与闪存存储器之间，Polar码解码器又与自适应感知器相连，数据处理器与闪存特性log单元相连，错误侦测器连接于判决器与数据处理器之间，判决器又与Polar码解码器相连；闪存特性log单元内存储有与闪存存储器型号相对应的log内容，包括闪存此时的发生错误的概率和闪存块擦写次数，判决器判断Polar码解码是否成功以及数据错误的位数，得出闪存存储器真实的发生的错率概率，错误侦测器根据判决器判断解码失败，输出解码的数据错误，数据处理器根据闪存特性log对从闪存读取的数据进行处理并利用错误侦测器进行加权，最后输出每位数据的最大似然值，自适应感知器校验闪存块真实的发生的错误概率与log单元预存的闪存此时的发生错误的概率的差异，根据差异与阈值的关系决定是否调整信道偏移概率值，根据调整后的信道偏移概率值生成Polar码生成矩阵，Polar码编码器根据自适应感知器和Polar码生成矩阵对从主机获取的数据进行编码处理然后存储至闪存存储器；自适应感知器根据根据闪存块类型、闪存块发生错误的概率和闪存块擦写次数来选择对应信道偏移概率的校验矩阵，Polar解码器根据校验矩阵、数据处理器输出的最大似然值进行解码运算。
  2. 根据权利要求1所述的应用于闪存控制器中的自适应polar码纠错码系统，其特征在于：所述自适应感知器包括信息收集器和自适应调节器，信息收集器收集实时的闪存错误率、闪存擦写次数和闪存特性log内容，自适应调节器根据信息收集器的信息根据闪存特性原理进行自适应的调节。
  3. 根据权利要求2所述的应用于闪存控制器中的自适应polar码纠错码系统，其特征在于：所述自适应调节指自适应调节器校验实时的闪存错误率与闪存特性log内容重错误概率的差异，如果差异小于预设阈值，信道偏移概率值不变，如果差异大于预设阈值，根据实时的闪存错误率调整信道偏移概率值。
  4. 一种应用于闪存控制器中的自适应polar码纠错码方法，其特征在于：包括自适应编码流程和自适应解码流程，自适应编码流程包括以下步骤：S11)、自适应感知器校验闪存块真实发生的错误概率与log单元预存的闪存此时发生错误的概率的差异，根据差异与阈值的关系决定是否调整信道偏移概率值，根据调整后的信道偏移概率值生成Polar码生成矩阵；S12)、数据编码器根据polar生成矩阵对码字信息进行相应编码；S13)、把编码完的数据及 校验码存储到闪存存储器中；自适应解码流程包括以下步骤：S21)、数据处理器从闪存存储器中读取码字信息；S22)、数据处理器根据闪存特性log内容和错误侦测器的侦测结果进行数据处理输出每位的最大似然值；S23)、polar码解码器根据最大似然值进行polar码解码，然后进行解码判断，如果成功接收解码，如果失败且没有达到一定迭代次数，继续进行Polar解码迭代，如果达到一定迭代次数还没有解码成功则进入下一步判决；S24)、利用判决器进行判断，如果解码成功，转到步骤S28，如果解码不成功，转到步骤S25，同时把发生错误个数反馈给自适应感知器和错误侦测器；S25)、判决是否继续进行解码，如果不继续解码，转到步骤S27，如果继续解码，转到步骤S26；S26)、启动错误侦测器，错误侦测器输出解码的数据错误并反馈给数据处理器，配置好再次解码的参数，转到步骤S21；S27)、Polar码解码失败，结束解码过程；S28)、Polar码解码成功，结束解码过程。
  5. 根据权利要求4所述的应用于闪存控制器中的自适应polar码纠错码方法，其特征在于：判决器根据解码数据与校验矩阵相乘是否等于0来判断是否解码成功，如果等于0，解码成功，输出成功纠正错误的个数，如果不成功是不等于0，输出最大的能纠错的个数。
PCT/CN2019/093278 2018-12-21 2019-06-27 应用于闪存控制器中的自适应polar码纠错码系统和方法 WO2020124980A1 (zh)

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