WO2020073857A1 - 过孔反焊盘形状的确定方法及印刷电路板 - Google Patents

过孔反焊盘形状的确定方法及印刷电路板 Download PDF

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Publication number
WO2020073857A1
WO2020073857A1 PCT/CN2019/109207 CN2019109207W WO2020073857A1 WO 2020073857 A1 WO2020073857 A1 WO 2020073857A1 CN 2019109207 W CN2019109207 W CN 2019109207W WO 2020073857 A1 WO2020073857 A1 WO 2020073857A1
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Prior art keywords
pad
diameter
layer
planar
via anti
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PCT/CN2019/109207
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English (en)
French (fr)
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孙跃
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中兴通讯股份有限公司
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Publication of WO2020073857A1 publication Critical patent/WO2020073857A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Definitions

  • the present application relates to, but is not limited to, the field of communications, and in particular, to a method for determining the shape of a via anti-pad and a printed circuit board.
  • Figure 1 is a schematic diagram of the components of the PCB according to the related art. As shown in Figure 1, an effective signal via is composed of four parts: via aperture, pad , Anti-pad and stump.
  • the second is SI technology considerations.
  • One of the key factors affecting signal integrity is the impedance continuity of the via, and the via impedance is related to the above four elements.
  • the impedance of a via is strongly related to its components. In actual processing, for certain PCB board material and board thickness, via hole diameter and pad size have certain restrictions.
  • FIG. 2 is a schematic diagram of the design of the traditional via anti pad in the related art.
  • the effect is indeed to increase the impedance value of the via, but in fact the overall impedance at the via is increased, and the part that has been large enough before (the part that does not want to be increased) is also forced to increase.
  • Fig. 3 is a schematic diagram of changes in via impedance caused by a design method in the related art. As shown in Fig. 3, it can be seen from the above that the traditional via design improves the impedance of the via as a whole. The part that does not need to increase the impedance has the defect that the impedance is further raised, which has a certain negative effect on the impedance continuity at the via.
  • Embodiments of the present application provide a method for determining the shape of a via anti-pad and a printed circuit board, so as to at least solve the problem of low impedance uniformity in vias in related technologies in related technologies.
  • a method for determining the shape of a via anti-pad includes: obtaining the position of a via hole residual pile in a PCB board of a via anti-pad to be laid out; according to the via The position of the stump determines the diameter of the via anti-pad of one or more plane layers of the PCB board.
  • a printed circuit board PCB board comprising: a plurality of planar layers, wherein the diameter of the via anti-pad of each planar layer, with each planar layer and The distance between the positions of the through-hole residual piles increases and decreases.
  • a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the above method embodiments during runtime.
  • an electronic device including a memory and a processor, the memory stores a computer program, the processor is configured to run the computer program to perform any of the above The steps in the method embodiment.
  • the position of the via hole residual pile in the PCB is obtained, and the diameters of the via anti-pads of multiple planar layers in the PCB board are determined according to the location of the residual pile.
  • the remaining piles all have an impact on the via impedance.
  • the above scheme is adopted to minimize the impact of the via pile residual pile on the via impedance, which solves the problem of low impedance consistency throughout the via in the related art, and ensures that the via impedance is relatively low High consistency.
  • FIG. 1 is a schematic diagram of components of a via of a PCB board according to the related art
  • FIG. 2 is a schematic diagram of a conventional via anti-pad design according to the related art
  • FIG. 3 is a schematic diagram of changes in via impedance caused by a design method in the related art
  • FIG. 4 is a flowchart of a method for determining the shape of a via anti-pad according to an embodiment of the present application
  • FIG. 5 is a schematic view of a design of a funnel-shaped via anti-pad according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a via anti-pad design according to specific embodiment 1;
  • FIG. 7 is a schematic view of a via anti-pad design according to specific embodiment 2;
  • FIG. 8 is a schematic comparison diagram of return loss of a via according to another embodiment of the present application.
  • FIG. 9 is a schematic diagram of via impedance comparison according to another embodiment of the present application.
  • FIG. 10 is a schematic diagram of a typical PCB stackup according to this application document.
  • Example 11 is a comparison diagram of return loss according to Example 2 of the present application.
  • Example 12 is a schematic diagram of impedance comparison according to Example 2 of the present application.
  • the technical solution of this application document can be used to design a PCB board.
  • the solution of this application document can be used to design the via anti-pad of each plane layer.
  • the method for determining the shape of the via anti-pad in this application file can be performed by a computer terminal, that is, the computer terminal first performs a simulation, calculates the via anti-pad of each planar layer, and subsequently manufactures the corresponding PCB board.
  • FIG. 4 is a flowchart of a method for determining the shape of a via anti-pad according to an embodiment of the present application. As shown in FIG. 4, the process includes The following steps:
  • Step S402 Obtain the position of the via stump in the PCB board of the via pad to be laid out;
  • step S404 the diameter of the via anti-pad of one or more planar layers of the PCB board is determined according to the position of the via stump.
  • the position of the via hole stump in the PCB is obtained, and the diameters of the via anti-pads of the multiple planar layers in the PCB board are determined according to the position of the via stump. Due to the via anti-pad and via stump All have an impact on the via impedance.
  • the above scheme is used to minimize the impact of the via hole residual pile on the via impedance, which solves the problem of low impedance consistency throughout the via in the related art and ensures that the via impedance is high consistency.
  • the size of the anti-pad, the position or length of the residual pile, both are factors that affect the via impedance.
  • determining the diameter of the via anti-pad of one or more plane layers of the PCB board according to the position of the via hole stump includes: determining between each plane layer and the position of the stump pile Distance; determine the diameter of the via anti-pad of each planar layer, which decreases as the distance increases.
  • the diameter and the distance may be inversely proportional.
  • determining the diameter of the via anti-pad of one or more planar layers of the PCB according to the position of the via stump includes: determining the two outlet layers A and B of the via, wherein , The A is the top layer or the bottom layer, the B is the inner layer, and there are residual piles on one side of the B; the via anti-pad diameter S1 of the adjacent planar layer of the A is determined by simulation; The diameter S2 of the via anti-pad of the adjacent planar layer on the B side; according to the S1 and S2, the diameter of the via anti-pad of each planar layer is determined.
  • the final shape of the via anti-pad layout designed in this embodiment may be a trapezoid, that is, the via anti-pad diameter near the residual pile is large, and the via anti-pad diameter decreases as the distance increases, and the final multilayer plane
  • the layer is trapezoidal.
  • the diameter of the via anti-pad of each planar layer is determined according to the distances between S1 and S2 and the planar layers between A and B.
  • determining the diameter of the via anti-pad of one or more planar layers of the PCB according to the position of the via stump includes: determining the two outlet layers C and D of the via, wherein , A and B are inner layers, and there are residual piles in both C and D; the diameter S4 of the via anti-pad of the adjacent planar layer on the side of C is determined by simulation, and the D is determined by simulation The via anti-pad diameter S5 of the adjacent planar layer on one side; the position of the intermediate planar layer is determined according to the length of the stub at C and D, and the diameter of the via anti-pad at the intermediate plane The shortest; the diameter S6 of the via anti-pad of the middle planar layer is determined by simulation; the diameter of the via anti-pad of each planar layer is determined according to the S4, S5 and S6.
  • the final via anti-pads of the plurality of planar layers have large diameters at both ends, and the via anti-pads of the middle planar layer have the smallest diameter, that is, two trapezoids.
  • the position of the intermediate plane layer is determined according to the ratio of the length of the residual pile at C and the length of the residual pile at D.
  • the diameter of the via anti-pad of each planar layer is determined according to the distances of the planar layers between S4, S5, and S6, and between C and D.
  • the bulk impedance forced to add most of the impedance is related to the strength of the residual pile left with a certain length after the back drilling of the via. There are three main points:
  • Increasing the counter pad can reduce the via capacitance and increase the impedance.
  • the via impedance at the stub increases, while the via impedance away from the stub increases. This method increases the via impedance to a certain extent, but the consistency of the via impedance cannot be guaranteed.
  • the present invention proposes a "funnel-shaped" via anti-pad
  • the influence of the residual pile digs anti-pads of different sizes on different plane layers, that is, the anti-pad near the residual pile is larger, and the farther away from the residual pile, the size of the anti-pad gradually decreases.
  • FIG. 5 is another embodiment according to the present application The design diagram of the anti-pad of the funnel-shaped via is shown in Figure 5. As the anti-pad near the residual pile is too large, the impedance of the via at the residual pile is increased; while the anti-pad away from the residual pile is small. It is ensured that the via impedance here does not become too large. This method can improve the return loss and impedance of the via, and ensure the consistency of the via impedance on the z-axis.
  • the via has two outlet layers A and B, A is a TOP or BOTTOM layer, and B is an inner layer.
  • the diameter S1 of the via anti-pad of the plane layer adjacent to the line layer A is determined by simulation, and the diameter S2, S3 of the via anti-pad of the plane layer adjacent to the line layer B is determined by simulation.
  • FIG. 6 is a schematic diagram of a via anti-pad design according to specific embodiment 1.
  • the via has two outlet layers A and B, and both A and B are inner layers.
  • the length of the residual pile at A is L1
  • the length of the residual pile at B is L2.
  • the diameters of the via anti-pads S1 and S2 of the plane layer adjacent to the line layer A are determined through simulation, and the diameters of the anti-pad vias S3 and S4 of the plane layer adjacent to the line layer B are determined through simulation.
  • FIG. 7 is a schematic view of a via anti-pad design according to a specific embodiment 2.
  • FIG. 8 is a comparison diagram of via return loss according to another embodiment of the present application. As shown in FIG. 8, via return echo of the initial situation (ori), traditional (ini) and “funnel” (opt) design methods Loss comparison.
  • FIG. 9 is a schematic diagram of via impedance comparison according to another embodiment of the present application. As shown in FIG. 9, the via impedances of the initial situation (ori), the traditional (ini) and the “funnel” (opt) design method are compared.
  • the anti-pads of vias dug near the stub are larger. The farther away from the stub, the size of the anti-pad will gradually decrease, and the shape will be similar to "funnel”.
  • FIG. 10 is a schematic diagram of a typical PCB stackup according to this application document. As shown in FIG. 10, a typical PCB stackup is shown.
  • the diameters of the via anti-pads S2 and S3 of the two adjacent planar layers (L13 and L15) of the trace layer L14 are determined by simulation.
  • Step three the distance from the TOP layer to the L13 layer is 68.8 mil, the diameter of the counter pad is 39.56 mil; the distance from the TOP layer to the L2 layer is 4.8 mil, and the diameter of the counter pad is 27.56 mil.
  • the distance from the TOP layer to other layers is L
  • the diameter of the reverse pad is S
  • step one the diameters of the via anti-pads S1 and S2 of the two adjacent planar layers (L2 and L4) of the trace layer L3 are determined by simulation.
  • the diameters of the via anti-pads S3 and S4 of the two adjacent planar layers (L13 and L15) of the trace layer L14 are determined by simulation to be 41.56mil.
  • Step 4 If the diameter of the anti-pad is L for L6 and L8, assuming that the distance from the TOP layer to L6 and L8 is L, the following equation is satisfied:
  • FIG. 11 is a comparison diagram of return loss according to Example 2 of the present application. As shown in FIG. 11, the return loss of the via in the initial case (ori), traditional (ini) and “funnel” (opt) design methods are given. Compared.
  • FIG. 12 is a schematic diagram of impedance comparison according to Example 2 of the present application. As shown in FIG. 12, the via impedances of the initial case (ori), traditional (ini) and “funnel” (opt) design methods are given.
  • the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases the former is Better implementation.
  • the technical solutions of the present application can essentially be embodied in the form of software products that contribute to the existing technology, and the computer software products are stored in a storage medium (such as ROM / RAM, magnetic disk,
  • the CD-ROM includes several instructions to enable a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the embodiments of the present application.
  • a printed circuit board PCB board comprising: a plurality of planar layers, wherein the diameter of the via anti-pad of each planar layer, with each planar layer and The distance between the positions of the through-hole residual piles increases and decreases.
  • the embodiments of the present application also provide a storage medium.
  • the above storage medium may be set to store program code for performing the following steps:
  • S2. Determine the diameter of the via anti-pad of one or more plane layers of the PCB board according to the position of the via stump.
  • the above storage medium may include, but is not limited to: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic Various media such as discs or optical discs that can store program codes.
  • An embodiment of the present application further provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to perform any step in any of the foregoing method embodiments.
  • the electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the processor, and the input-output device is connected to the processor.
  • the above processor may be configured to perform the following steps through a computer program:
  • S2. Determine the diameter of the via anti-pad of one or more plane layers of the PCB board according to the position of the via stump.
  • modules or steps of the present application can be implemented by a general-purpose computing device, they can be concentrated on a single computing device, or distributed in a network composed of multiple computing devices Above, optionally, they can be implemented with program code executable by the computing device, so that they can be stored in the storage device to be executed by the computing device, and in some cases, can be in a different order than here
  • the steps shown or described are performed, or they are made into individual integrated circuit modules respectively, or multiple modules or steps among them are made into a single integrated circuit module for implementation. In this way, this application is not limited to any specific combination of hardware and software.

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Abstract

一种过孔反焊盘形状的确定方法及印刷电路板，其中，该方法包括：获取PCB中的过孔残桩的位置，依据该残桩的位置确定PCB板中的多个平面层的过孔反焊盘的直径，由于过孔反焊盘和过孔残桩均对过孔阻抗存在影响，采用上述方案以尽量减少过孔残桩对过孔阻抗的影响，解决了相关技术中过孔各处的阻抗一致性低的问题，保证了过孔阻抗较高的一致性。

Description

过孔反焊盘形状的确定方法及印刷电路板 技术领域
本申请涉及但不限于通信领域，具体而言，涉及一种过孔反焊盘形状的确定方法及印刷电路板。
背景技术
在相关技术中，在印制电路板PCB板设计中，对于信号线因换层需要而使用的换层过孔或连接器的压接过孔设计时，会基于两方面考虑来完成这类过孔的设计：
一是加工工艺考虑，一般情况下，图1是根据相关技术中的PCB板的过孔组成部分示意图，如图1所示，一个有效的信号过孔由四部分组成：过孔孔径、焊盘、反焊盘和残桩。
二是SI技术考虑，影响信号完整性的关键因素之一就是过孔的阻抗连续性，而过孔阻抗与上述四要素均相关。
过孔的阻抗与其组成部分强相关。实际加工中，对于确定的PCB板板材及板厚，过孔孔径与焊盘的尺寸都有一定的限制要求。
为了解决过孔处阻抗不连续的问题，传统设计方法主要是对反焊盘进行挖大处理，来提高过孔处的阻抗，图2是根据相关技术中的传统过孔反焊盘设计示意图，其效果确实是提升了过孔的阻抗值，但实际上是过孔处的阻抗整体被提升了，其之前已经足够大的部分(不想被提高的部分)也被迫增大了。图3是根据相关技术中设计方式导致的的过孔阻抗的变化示意图，如图3所示，从上可以看出，传统过孔处的设计将过孔处的阻抗整体提高了，对于过孔中不需要增加阻抗的部分存在阻抗被进一步拉升的缺陷，从而对过孔处的阻抗连续性有着一定的负面影响。
针对相关技术中过孔各处的阻抗一致性低的问题，目前还没有有效的解决方案。
发明内容
本申请实施例提供了一种过孔反焊盘形状的确定方法及印刷电路板，以至少解决相关技术中相关技术中过孔各处的阻抗一致性低的问题。
根据本申请的一个实施例，提供了一种过孔反焊盘形状的确定方法，包括：在待布局过孔反焊盘的PCB板中，获取过孔残桩的位置；依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径。
根据本申请文件的另一个实施例，还提供了一种印刷电路板PCB板，包括：多个平面层，其中，每个平面层的过孔反焊盘的直径，随着每个平面层与过孔残桩位置之间的距离增大而减小。
根据本申请的又一个实施例，还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
根据本申请的又一个实施例，还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项方法实施例中的步骤。
通过本申请实施例，获取PCB中的过孔残桩的位置，依据该残桩的位置确定PCB板中的多个平面层的过孔反焊盘的直径，由于过孔反焊盘和过孔残桩均对过孔阻抗存在影响，采用上述方案以尽量减少过孔残桩对过孔阻抗的影响，解决了相关技术中过孔各处的阻抗一致性低的问题，保证了过孔阻抗较高的一致性。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1是根据相关技术中的PCB板的过孔组成部分示意图；
图2是根据相关技术中的传统过孔反焊盘设计示意图；
图3是根据相关技术中设计方式导致的的过孔阻抗的变化示意图；
图4是根据本申请实施例的过孔反焊盘形状的确定方法的流程图；
图5是根据本申请另一个实施例的漏斗形过孔反焊盘设计示意图；
图6是根据具体实施例1的过孔反焊盘设计示意图；
图7是根据具体实施例2的过孔反焊盘设计示意图；
图8是根据本申请另一个实施例的过孔回波损耗对比示意图；
图9是根据本申请另一个实施例的过孔阻抗对比示意图；
图10是根据本申请文件的一典型的PCB叠层的示意图；
图11是根据本申请例子2的回波损耗对比图；
图12是根据本申请例子2的阻抗对比示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本申请。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本申请文件的技术方案可以用于设计PCB板时，针对存在残桩的过孔，可以采用本申请文件的方案去设计每个平面层的过孔反焊盘。
可选地，本申请文件的过孔反焊盘形状的确定方法可以由计算机终端执行，即先有计算机终端进行仿真模拟，计算出每个平面层的过孔反焊盘，后续制作相应的PCB板。
实施例一
在本实施例中提供了一种过孔反焊盘形状的确定方法，图4是根据本申请实施例的过孔反焊盘形状的确定方法的流程图，如图4所示，该流程包括如下步骤：
步骤S402，在待布局过孔反焊盘的PCB板中，获取过孔残桩的位置；
步骤S404，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径。
通过上述步骤，获取PCB中的过孔残桩的位置，依据该残桩的位置确定PCB板中的多个平面层的过孔反焊盘的直径，由于过孔反焊盘和过孔残桩均对过孔阻抗存在影响，采用上述方案以尽量减少过孔残桩对过孔阻抗的影响，解决了相关技术中过孔各处的阻抗一致性低的问题，保证了过孔阻抗较高的一致性。
反焊盘的尺寸，残桩的位置或长短，二者是过孔阻抗的影响因素。
可选地，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径，包括：确定每个平面层与所述残桩的位置之间的距离；确定所述每个平面层的过孔反焊盘的直径，随着所述距离的增大而减小。
可选地，该直径与该距离可以成反比例关系。
可选地，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径，包括：确定所述过孔的两个出线层A和B，其中，所述A为顶层或底层，所述B为内层，所述B的一侧存在残桩；通过仿真确定所述A的相邻平面层的过孔反焊盘直径S1；通过仿真确定所述B一侧的相邻平面层的过孔反焊盘直径S2；依据所述S1和S2，确定出每个平面层的过孔反焊盘的直径。该实施例中设计的过孔的反焊盘布局最终形状可以是梯形，即离残桩近的过孔反焊盘直径大，随着距离增加过孔反焊盘直径减小，最终多层平面层呈现梯形。
可选地，依据所述S1和S2，以及所述A和B之间平面层彼此的距离，确定所述每个平面层的过孔反焊盘的直径。
可选地，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径，包括：确定所述过孔的两个出线层C和D，其中，所述A和所述B为内层，所述C和D均存在残桩；通过仿真确定所述C一侧的相邻平面层的过孔反焊盘直径S4,通过仿真确定所述D一侧的相邻平面层的过孔反焊盘直径S5；依据C处残桩长度和D处残桩长度，确定中间平面层的位置，其中，所述中间平面层的过孔反焊盘直径最短；通过仿真确定所述中间平面层的过孔反焊盘直径S6；依据所述S4、S5和S6，确定出每个平面层的过孔反焊盘的直径。本实施例中的方案，由于残桩位于两侧，则最终的多个平面层的过孔反焊盘呈现两端直径大，中间平面层的过孔反焊盘直径最小，即两个梯形。
可选地，依据C处残桩长度和D处残桩长度的比值，确定所述中间平面层的位置。
可选地，依据所述S4、S5和S6，以及所述C和D之间平面层彼此的距离，确定所述每个平面层的过孔反焊盘的直径。
下面结合本申请文件另一个实施例进行说明。
经过综合分析实际加工后的过孔模型，整体阻抗中被迫加大部分的阻抗与过孔背钻后留有一定长度的残桩强相关，主要有以下三点：
1)残桩的容性效应，拉低了过孔的阻抗；
2)残桩在过孔z轴上的影响并不是一致的，即残桩对过孔z轴上靠近自己的地方影响大，远离自己的地方影响小；
3)增大反焊盘可以降低过孔容性，提高阻抗。
若在所有平面层挖取较大的相同大小反焊盘，残桩处的过孔阻抗提高了，远离残桩处的过孔阻抗却偏大了。这种方法一定程度提高了过孔的阻抗，但是过孔阻抗的一致性却不能保证。
本发明所要解决的技术问题是：为了克服现有技术中的过孔处整体阻抗都被提升导致阻抗连续性受到影响的缺点，本发明提出了一种“漏斗形”过孔反焊盘，针对残桩的影响对不同平面层挖取不同大小的反焊盘，即残 桩附近的反焊盘偏大，越远离残桩，反焊盘大小逐渐缩小，图5是根据本申请另一个实施例的漏斗形过孔反焊盘设计示意图，如图5所示，由于残桩附近的反焊盘偏大，提高了残桩处过孔的阻抗；而远离残桩处的反焊盘偏小，保证了此处的过孔阻抗不至于变的太大。此种方法可以很好的改善过孔回损及阻抗，保证了过孔阻抗在z轴上的一致性。
具体实施例1，假设过孔有两个出线层A、B，A为TOP或BOTTOM层，B为内层。
通过仿真确定出线层A相邻平面层的过孔反焊盘直径S1，再通过仿真确定出线层B相邻平面层的过孔反焊盘直径S2、S3。
其他平面层反焊盘直径(如1、2、3)可通过S1、S2和它们在z轴上的位置线性的计算出，图6是根据具体实施例1的过孔反焊盘设计示意图。
具体实施例2，假设过孔有两个出线层A、B，A、B都为内层。A处残桩长度为L1，B处残桩长度为L2。通过仿真确定出线层A相邻平面层的过孔反焊盘直径S1、S2，再通过仿真确定出线层B相邻平面层的过孔反焊盘直径S3、S4。确定平面层2的位置(在过孔上应满足L1/L2＝L3/L4)，通过仿真确定平面层2的过孔反焊盘直径S5，其他平面层反焊盘直径(如1、3)可通过S2、S3、S5和它们在z轴上的位置线性的计算出。图7是根据具体实施例2的过孔反焊盘设计示意图。
图8是根据本申请另一个实施例的过孔回波损耗对比示意图，如图8所示，初始情况(ori)、传统(ini)与“漏斗形”(opt)设计方法的过孔回波损耗对比。
图9是根据本申请另一个实施例的过孔阻抗对比示意图，如图9所示，初始情况(ori)、传统(ini)与“漏斗形”(opt)设计方法的过孔阻抗对比。
在本申请文件的方案中，有以下两个特征：
1、在过孔反焊盘设计中，在不同平面层挖取不同大小的反焊盘。
2、在过孔反焊盘设计中，残桩附近挖取的过孔反焊盘偏大，越远离残桩，反焊盘大小逐渐缩小，形状类似“漏斗”。
为了使本发明的目的、技术方案及优点更加清楚的说明，下面结合附图，对本发明的具体设计方法做详细的说明：
图10是根据本申请文件的一典型的PCB叠层的示意图，如图10所示，展示了一个典型的PCB叠层。
例子1
假设有一高速差分信号从内层L14，经过过孔换层到TOP层扇出，过孔残桩长度8mil。
步骤一，先通过仿真确定TOP层相邻平面层(L2)过孔反焊盘直径S1＝27.56mil。
步骤二，再通过仿真确定走线层L14相邻两个平面层(L13、L15)的过孔反焊盘直径S2、S3＝39.56mil。
步骤三，从TOP层到L13层的距离为68.8mil，采用反焊盘的直径为39.56mil；从TOP层到L2层的距离为4.8mil，采用反焊盘的直径为27.56mil。假设从TOP层到其他层的距离为L，若采用反焊盘的直径为S，满足如下方程：
Figure PCTCN2019109207-appb-000001
经计算得到，其他层的反焊盘直径如下表1所示：
表1
平面层 从TOP层到相应层的距离/mil 反焊盘的直径/mil
L2 4.8 S 1＝27.56
L4 16 29.66
L6 27.2 31.76
L8 38.4 33.86
L9 44.6 35.02
L10 50.8 36.18
L11 57 37.34
L13 68.8 S 2＝39.56
L15 80 S 3＝39.56
例子1的回波损耗及阻抗对比如图8、9所示。
例子2
假设有一高速差分信号从内层L3，经过过孔换层到内层L14扇出。过孔残桩长度8mil。
步骤一，先通过仿真确定走线层L3相邻两个平面层(L2、L4)的过孔反焊盘直径S1、S2＝41.56mil。
步骤二，再通过仿真确定走线层L14相邻两个平面层(L13、L15)的过孔反焊盘直径S3、S4＝41.56mil。
步骤三，确定平面层2的位置，由于过孔两边的残桩都是8mil，因此，平面层2的位置应处于L3和L14中间位置。即从TOP层到相应层的距离处，而L9层的位置在44.6mil处，因此，平面层2为L9。然后通过仿真确定L9的过孔反焊盘直径S5＝27.56mil。
步骤四，若L6、L8采用反焊盘的直径为S，假设从TOP层到L6、L8的距离为L，满足如下方程：
Figure PCTCN2019109207-appb-000002
若L10、L11采用反焊盘的直径为S＇，假设从TOP层到L10、L11的距离为L＇，满足如下方程：
Figure PCTCN2019109207-appb-000003
经计算得到，其他层的反焊盘直径如下表2所示：
表2
平面层 从TOP层到相应层的距离/mil 反焊盘的直径/mil
L2 4.8 S 1＝41.56
L3 10.4 /
L4 16 S 2＝41.56
L6 27.2 36.08
L8 38.4 30.60
L9 44.6 S 5＝27.56
L10 50.8 31.15
L11 57 34.73
L13 68.8 S 3＝41.56
L14 74.4 /
L15 80 S 4＝41.56
图11是根据本申请例子2的回波损耗对比图，如图11所示，给出了初始情况(ori)、传统(ini)与“漏斗形”(opt)设计方法的过孔回波损耗对比。
图12是根据本申请例子2的阻抗对比示意图，如图12所示，给出了初始情况(ori)、传统(ini)与“漏斗形”(opt)设计方法的过孔阻抗对比。
采用本方案可以极大的提高过孔阻抗的一致性，减小过孔回波损耗和改善过孔阻抗。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
实施例二
根据本申请文件的另一个实施例，还提供了一种印刷电路板PCB板，包括：多个平面层，其中，每个平面层的过孔反焊盘的直径，随着每个平 面层与过孔残桩位置之间的距离增大而减小。
实施例三
本申请的实施例还提供了一种存储介质。可选地，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的程序代码：
S1，在待布局过孔反焊盘的PCB板中，获取过孔残桩的位置；
S2，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本申请的实施例还提供了一种电子装置，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
可选地，上述电子装置还可以包括传输装置以及输入输出设备，其中，该传输装置和上述处理器连接，该输入输出设备和上述处理器连接。
可选地，在本实施例中，上述处理器可以被设置为通过计算机程序执行以下步骤：
S1，在待布局过孔反焊盘的PCB板中，获取过孔残桩的位置；
S2，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本申请的各模块或各步骤 可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本申请不限制于任何特定的硬件和软件结合。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种过孔反焊盘形状的确定方法，包括：
    在待布局过孔反焊盘的PCB板中，获取过孔残桩的位置；
    依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径。
  2. 根据权利要求1所述的方法，其中，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径，包括：
    确定每个平面层与所述残桩的位置之间的距离；
    确定所述每个平面层的过孔反焊盘的直径，随着所述距离的增大而减小。
  3. 根据权利要求1所述的方法，其中，依据所述过孔残桩的位置确定所述PCB板一个或多个平面层的过孔反焊盘的直径，包括：
    确定所述过孔的两个出线层A和B，其中，所述A为顶层或底层，所述B为内层，所述B的一侧存在残桩；
    通过仿真确定所述A的相邻平面层的过孔反焊盘直径S1；
    通过仿真确定所述B一侧的相邻平面层的过孔反焊盘直径S2；
    依据所述S1和S2，确定出每个平面层的过孔反焊盘的直径。
  4. 根据权利要求3所述的方法，其中，依据所述S1和S2，确定出每个平面层的过孔反焊盘的直径，包括：
    依据所述S1和S2，以及所述A和B之间平面层彼此的距离，确定所述每个平面层的过孔反焊盘的直径。
  5. 根据权利要求1所述的方法，其中，依据所述过孔残桩的位 置确定所述PCB板一个或多个平面层的过孔反焊盘的直径，包括：
    确定所述过孔的两个出线层C和D，其中，所述A和所述B为内层，所述C和D均存在残桩；
    通过仿真确定所述C一侧的相邻平面层的过孔反焊盘直径S4,通过仿真确定所述D一侧的相邻平面层的过孔反焊盘直径S5；
    依据C处残桩长度和D处残桩长度，确定中间平面层的位置，其中，所述中间平面层的过孔反焊盘直径最短；
    通过仿真确定所述中间平面层的过孔反焊盘直径S6；
    依据所述S4、S5和S6，确定出每个平面层的过孔反焊盘的直径。
  6. 根据权利要求5所述的方法，其中，依据C处残桩长度和D处残桩长度，确定中间平面层的位置，包括：
    依据C处残桩长度和D处残桩长度的比值，确定所述中间平面层的位置。
  7. 根据权利要求5所述的方法，其中，依据所述S4、S5和S6，确定出每个平面层的过孔反焊盘的直径，包括：
    依据所述S4、S5和S6，以及所述C和D之间平面层彼此的距离，确定所述每个平面层的过孔反焊盘的直径。
  8. 一种印刷电路板PCB板，包括：
    多个平面层，其中，每个平面层的过孔反焊盘的直径，随着每个平面层与过孔残桩位置之间的距离增大而减小。
  9. 一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求1至7任一项中所 述的方法。
  10. 一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至7任一项中所述的方法。
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