WO2020073695A1 - 一种tft基板、显示面板及显示装置 - Google Patents

一种tft基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2020073695A1
WO2020073695A1 PCT/CN2019/093829 CN2019093829W WO2020073695A1 WO 2020073695 A1 WO2020073695 A1 WO 2020073695A1 CN 2019093829 W CN2019093829 W CN 2019093829W WO 2020073695 A1 WO2020073695 A1 WO 2020073695A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
electrode layer
insulating layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/093829
Other languages
English (en)
French (fr)
Inventor
肖辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2020073695A1 publication Critical patent/WO2020073695A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the technical field of display panels, in particular to a TFT substrate, a display panel and a display device.
  • the display device includes a display panel including a thin film transistor and a storage capacitor in each pixel area, where the storage capacitor is used to increase the charge storage amount of the pixel and maintain the pixel potential until the next scan period comes.
  • the inventor of the present application discovered in the long-term research and development that in the existing organic light-emitting display panel, due to the second layer metal used for VDD / Sense wiring, one of the electrode plates of the storage capacitor also uses the second layer metal. Due to the limited space of the layout and the short distance, the DD / Sense trace is easy to be short-circuited with the electrode plate of the storage capacitor, resulting in abnormal bright spots on the display panel.
  • the technical problem mainly solved by the present application is to provide a TFT substrate, a display panel and a display device to reduce the abnormal bright spots of the display panel and improve the display effect.
  • the TFT substrate includes at least a first thin film transistor and a storage capacitor provided on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode layer and a third electrode layer, the first electrode layer, the second electrode layer and the first
  • the three electrode layers are all provided in different layers from the source and drain layers of the first thin film transistor; wherein, the second electrode layer is provided between the first electrode layer and the third electrode layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, wherein the first electrode layer is disposed on the substrate; the buffer layer covers at least the first electrode layer; the second electrode layer is disposed on the buffer layer; the first The insulating layer covers at least the second electrode layer; the third electrode layer is disposed on the first insulating layer; wherein, the third electrode layer is disposed in the same layer as the first gate of the first thin film transistor.
  • the first thin film transistor further includes: a first common electrode line, which is disposed in the same layer as the first electrode layer and is covered by the buffer layer; a first active layer, which is disposed in the same layer as the second electrode layer, the first The active layer is covered by the first insulating layer; the first gate is disposed on the first insulating layer; the second insulating layer covers at least the first gate and the third electrode layer; the source and drain layers include the first source and the first The drain is disposed on the second insulating layer, and the first source and the first drain are connected to the first active layer through the first through hole.
  • the TFT substrate further includes: a passivation layer covering at least the first source electrode and the first drain electrode; a flat layer disposed on the passivation layer; an ITO layer disposed on the flat layer, the ITO layer passing through The two through holes are connected to the first source or the first drain.
  • the TFT substrate further includes: a pixel definition layer covering at least the ITO layer; a pixel cathode layer provided on the pixel definition layer and connected to the ITO layer through the third through hole.
  • the TFT substrate further includes a second thin film transistor.
  • the second thin film transistor includes: a second common electrode line, which is disposed in the same layer as the first common electrode line and is covered by the buffer layer; the second active layer, and the second An active layer is arranged in the same layer and is covered by the first insulating layer; the second gate is arranged between the first insulating layer and the second insulating layer; the second source and the second drain are arranged on the second insulating layer And corresponding to the second active layer, the second source electrode and the second drain electrode are connected to the second active layer through the fourth via hole.
  • the storage capacitor further includes a buffer layer, a first insulating layer, and a second insulating layer, wherein the first electrode layer is disposed on the buffer layer; the first insulating layer covers at least the first electrode layer; the second electrode layer is disposed On the first insulating layer, the second insulating layer covers at least the second electrode layer, and the second electrode layer is provided in the same layer as the first gate of the first thin film transistor; the third electrode layer is provided on the second insulating layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, wherein the first electrode layer is disposed on the substrate; the buffer layer covers at least the first electrode layer; the second electrode layer is disposed on the buffer layer; the first The insulating layer covers at least the second electrode layer; the third electrode layer is disposed on the first insulating layer.
  • the display panel includes a TFT substrate including at least a first thin film transistor and a storage capacitor provided on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode layer, and a A three-electrode layer, the first electrode layer, the second electrode layer, and the third electrode layer are all provided in different layers from the source-drain layer of the first thin film transistor; wherein, the second electrode layer is provided Between the first electrode layer and the third electrode layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, the first electrode layer is disposed on the substrate, the buffer layer covers at least the first electrode layer, and the second An electrode layer is provided on the buffer layer; the first insulating layer covers at least the second electrode layer; the third electrode layer is provided on the first insulating layer; wherein, the third electrode layer is The first gate of the first thin film transistor is arranged in the same layer.
  • the first thin film transistor further includes: a first common electrode line, which is disposed in the same layer as the first electrode layer and is covered by the buffer layer; a first active layer, and the second The electrode layers are arranged in the same layer, the first active layer is covered by the first insulating layer; the first gate is arranged on the first insulating layer; the second insulating layer covers at least the first gate And the third electrode layer; and the source-drain layer includes a first source electrode and a first drain electrode, which are disposed on the second insulating layer, and the first source electrode and the first drain electrode pass through The first through hole is connected to the first active layer.
  • the TFT substrate further includes: a passivation layer covering at least the first source electrode and the first drain electrode; a flat layer provided on the passivation layer; an ITO layer provided on the On the flat layer, the ITO layer is connected to the first source electrode or the first drain electrode through a second through hole.
  • the TFT substrate further includes: a pixel definition layer covering at least the ITO layer; a pixel cathode layer provided on the pixel definition layer and connected to the ITO layer through a third through hole.
  • the TFT substrate further includes a second thin film transistor
  • the second thin film transistor includes: a second common electrode line, which is disposed in the same layer as the first common electrode line and is covered by the buffer layer ;
  • the second active layer is provided in the same layer as the first active layer and is covered by the first insulating layer;
  • the second gate is provided between the first insulating layer and the second insulating layer;
  • the second source electrode and the second drain electrode are disposed on the second insulating layer and corresponding to the second active layer, and the second source electrode and the second drain electrode pass through the fourth through hole It is connected to the second active layer.
  • the storage capacitor further includes a buffer layer, a first insulating layer, and a second insulating layer, wherein the first electrode layer is disposed on the buffer layer; the first insulating layer covers at least The first electrode layer; the second electrode layer is disposed on the first insulating layer, the second insulating layer covers at least the second electrode layer, and the second electrode layer and the first film
  • the first gate of the transistor is arranged in the same layer; the third electrode layer is arranged on the second insulating layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, wherein the first electrode layer is disposed on the substrate; the buffer layer covers at least the first electrode layer, the A second electrode layer is provided on the buffer layer, the first insulating layer covers at least the second electrode layer; the third electrode layer is provided on the first insulating layer.
  • a display device includes a display panel including a TFT substrate, the TFT substrate includes at least a first thin film transistor and a storage capacitor disposed on the substrate, wherein the storage capacitor includes: a first An electrode layer, a second electrode layer and a third electrode layer, the first electrode layer, the second electrode layer and the third electrode layer are all provided in different layers from the source and drain layers of the first thin film transistor; Wherein, the second electrode layer is disposed between the first electrode layer and the third electrode layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, the first electrode layer is disposed on the substrate, the buffer layer covers at least the first electrode layer, and the second An electrode layer is provided on the buffer layer; the first insulating layer covers at least the second electrode layer; the third electrode layer is provided on the first insulating layer; wherein, the third electrode layer is The first gate of the first thin film transistor is arranged in the same layer.
  • the first thin film transistor further includes: a first common electrode line, which is disposed in the same layer as the first electrode layer and is covered by the buffer layer; a first active layer, and the second The electrode layers are arranged in the same layer, the first active layer is covered by the first insulating layer; the first gate is arranged on the first insulating layer; the second insulating layer covers at least the first gate And the third electrode layer; and the source-drain layer includes a first source electrode and a first drain electrode, which are disposed on the second insulating layer, and the first source electrode and the first drain electrode pass through The first through hole is connected to the first active layer.
  • the TFT substrate further includes: a passivation layer covering at least the first source electrode and the first drain electrode; a flat layer provided on the passivation layer; an ITO layer provided on the On the flat layer, the ITO layer is connected to the first source electrode or the first drain electrode through a second through hole.
  • the TFT substrate of the embodiments of the present application includes at least a first thin film transistor and a storage capacitor provided on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode Layer and third electrode layer, the first electrode layer, the second electrode layer and the third electrode layer are all provided in a different layer from the source and drain layers of the first thin film transistor; wherein, the second electrode layer is provided on the first electrode layer and the first Between three electrode layers.
  • the electrode layer of the storage capacitor and the source and drain layers of the first thin film transistor are provided in different layers. Therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (that is, the source or drain of the first thin film transistor Pole) separate, can avoid short circuit between the two, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • FIG. 1 is a schematic structural view of a TFT substrate
  • FIG. 2 is a schematic diagram of the pixel structure of the TFT substrate of the embodiment of FIG. 1;
  • FIG. 3 is an equivalent circuit diagram of the pixel structure of the embodiment of FIG. 2;
  • FIG. 4 is a schematic structural diagram of a first embodiment of a TFT substrate of the present application.
  • FIG. 5 is a schematic flow chart of the method for manufacturing a TFT substrate of the embodiment of FIG. 4;
  • FIG. 6 is another schematic flow chart of the method for manufacturing the TFT substrate of the embodiment of FIG. 4;
  • FIG. 7 is a schematic structural diagram of a second embodiment of a TFT substrate of the present application.
  • FIG. 8 is a schematic structural diagram of a third embodiment of a TFT substrate of the present application.
  • FIG. 9 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • FIG. 10 is a schematic structural diagram of an embodiment of a display device of the present application.
  • FIG. 1 is a schematic diagram of a TFT substrate
  • FIG. 2 is a schematic diagram of a pixel structure of the TFT substrate of the embodiment of FIG. 1
  • FIG. 3 is an equivalent circuit diagram of the pixel structure of the embodiment of FIG.
  • the VDD / Sense trace (normally high potential) 101 and the anode 102 of the pixel both use the second metal layer M2 trace, and at least the VDD / Sense trace 101 and one sub-pixel in the pixel are arranged next to each other.
  • the second metal layer M2 is likely to remain. Therefore, the VDD / Sense trace 101 and the anode 102 of the sub-pixel are short-circuited, thereby causing abnormal bright spots on the display panel.
  • FIG. 4 is a schematic structural diagram of a first embodiment of the TFT substrate of the present application.
  • the TFT substrate 401 includes at least a first thin film transistor 402 and a storage capacitor 403 disposed on the substrate 406, wherein the storage capacitor 403 includes: a first electrode layer 414, a second electrode layer 415, and a third electrode layer 416, An electrode layer 414, a second electrode layer 415, and a third electrode layer 416 are all disposed in different layers from the source / drain layer S1 / D1 of the first thin film transistor 402; wherein, the second electrode layer 415 is disposed on the first electrode layer 414 and Between the third electrode layers 416.
  • the first electrode layer 414, the second electrode layer 415, and the third electrode layer 416 are all arranged in different layers from the source / drain layer S1 / D1 of the first thin film transistor 402.
  • the second electrode layer 415 and the third electrode layer 416 are disposed on different layers from the source-drain layer S1 / D1 of the first thin film transistor 402.
  • the electrode layer of the storage capacitor and the source-drain layer of the first thin film transistor in this embodiment are provided in different layers, therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (ie, the first thin film transistor The source or the drain) are separated, which can avoid the short circuit between the two, thereby reducing the abnormal bright spots of the display panel and improving the display effect.
  • the storage capacitor 403 of this embodiment further includes a buffer layer 404 and a first insulating layer 405; wherein, the first electrode layer 414 is disposed on the substrate 406, the buffer layer 404 at least covers the first electrode layer 414, and the second electrode The layer 415 is disposed on the buffer layer 404, the first insulating layer 405 covers at least the second electrode layer 415, and the third electrode layer 416 is disposed on the first insulating layer 405, wherein the third electrode layer 416 and the first thin film transistor 402 A gate G1 is provided in the same layer.
  • the first electrode layer 414 is the common electrode line LS1
  • the second electrode layer 415 is the active layer AOS1
  • the third electrode layer 416 is the pixel anode layer M1.
  • the common electrode line LS1, the active layer AOS1 and the pixel anode layer M1 are correspondingly disposed, that is, the active layer AOS1 is located directly above the common electrode line LS1, and the pixel anode layer M1 is located directly above the active layer AOS1.
  • the electrode of the storage capacitor 403 in this embodiment has a three-layer structure, that is, the common electrode line LS1, the active layer AOS1, and the pixel anode layer M1, and none of these three electrode layers are connected to the first thin film transistor.
  • the source and drain layers S1 / D1 of 402 are provided in the same layer, therefore, the electrode layer of the storage capacitor 403 can be separated from the VDD / Sense trace (that is, the source / drain layer S1 / D1 of the first thin film transistor 402), which can avoid storage
  • the capacitor 403 is short-circuited with the VDD / Sense trace.
  • the first thin film transistor 402 of this embodiment further includes: a first common electrode line LS2, a first active layer AOS2, a second insulating layer 407, and a first source electrode S1 and a first drain electrode D1; wherein, the first A common electrode line LS2 is disposed in the same layer as the first electrode layer 414 (that is, the common electrode line LS1) and is covered by the buffer layer 404; the first active layer AOS2 and the second electrode layer 415 (that is, the active layer AOS1) are disposed in the same layer, And covered by the first insulating layer 405; the first gate G1 is disposed on the first insulating layer 405; the second insulating layer 407 at least covers the first gate G1 and the third electrode layer 416 (ie, the pixel anode layer M1); A source S1 and a first drain D1 are disposed on the second insulating layer 407, and the first source S1 and the first drain D1 are connected to the first active layer AOS2 through a
  • the first active layer AOS2 is a conductive channel between the first source S1 and the first drain D1.
  • the first common electrode line LS2, the first active layer AOS2 and the first gate G1 are correspondingly disposed, that is, the first active layer AOS2 is located directly above the first common electrode line LS2, and the first gate G1 is located in the first active layer Just above AOS2.
  • the TFT substrate 401 in this embodiment further includes: a passivation layer 408, a flat layer 409, and indium tin oxide (ITO, Indium Tin Oxides) layer 410; wherein, the passivation layer 408 covers at least the first source S1 and the first drain D1, the flat layer 409 is provided on the passivation layer 408, the ITO layer 410 is provided on the flat layer 409, and the ITO layer 410 It is connected to the first drain D1 through a second through hole (not marked in the figure).
  • ITO Indium Tin Oxides
  • the ITO layer 410 may also be connected to the first drain through the second through hole.
  • the TFT substrate 401 of this embodiment further includes: a pixel definition layer 411 and a pixel cathode layer 412; wherein, the pixel definition layer 411 at least covers the ITO layer 410, the pixel cathode layer 412 is disposed on the pixel definition layer 411, and passes the The three through holes (not marked in the figure) are connected to the ITO layer 410.
  • the TFT substrate 401 of this embodiment further includes: a second thin film transistor 413, and the second thin film transistor 413 includes: a second common electrode line LS3, a second active layer AOS3, a second gate G2, and a second source S2 And the second drain D2; wherein, the second common electrode line LS3 is arranged in the same layer as the first common electrode line LS2 and is covered by the buffer layer 404, and the second active layer AOS3 is arranged in the same layer as the first active layer AOS2 and is The first insulating layer covers 405, the second gate G2 is disposed between the first insulating layer 405 and the second insulating layer 407, the second source S2 and the second drain D2 are disposed on the second insulating layer 407, the second The source electrode S2 and the second drain electrode D2 are connected to the second active layer AOS3 through a fourth through hole (not shown).
  • the second active layer AOS3 is a conductive channel between the second source S2 and the second drain D2.
  • the second active layer AOS3 of this embodiment is disposed corresponding to the second common electrode line LS3, that is, the second active layer AOS3 is located directly above the second common electrode line LS3; the second gate G2 corresponds to the second active layer AOS3 It is provided that the second gate G2 is provided directly above the second active layer AOS3.
  • T1 is a driving thin film transistor, and T1 may specifically be an oxide thin film transistor; T2 is a switching thin film transistor, and T2 may specifically be a Low Temperature Poly-silicon (LTPS) thin film transistor.
  • LTPS Low Temperature Poly-silicon
  • the control terminal of T2 is connected to the scan line Scan, the first communication terminal of T2 is connected to the control terminal of T1, and the second communication terminal of T2 is connected to the data line Data;
  • the first communication terminal of T1 is connected to VDD Line connection, the second communication terminal of T1 is connected to the positive electrode of OLED, the negative electrode of OLED is grounded;
  • the first end of capacitor Cst is connected to the control terminal of T1, the second end of capacitor Cst is connected to the second terminal of T3, and the control of T3
  • the terminal is connected to the RD trace, and the first end of T3 is connected to the Sense trace.
  • T3 in FIG. 3 is not shown in FIGS. 1, 2 and 4 of this application.
  • the number of thin film transistors provided on the TFT substrate is not limited.
  • FIG. 5 is a schematic flowchart of a method for manufacturing a TFT substrate according to the embodiment of FIG. Specifically, the method of this embodiment includes the following steps:
  • Step S501 Prepare the substrate.
  • the substrate may be a glass substrate or a resin substrate, etc., which is not specifically limited.
  • Step S502 forming a common electrode line on the substrate.
  • Step S503 forming a buffer layer covering at least the common electrode line.
  • Step S504 forming an active layer on the buffer layer.
  • the active layer is provided corresponding to the common electrode line.
  • Step S505 forming a first insulating layer covering at least the active layer.
  • Step S506 forming a pixel anode layer and a first gate on the first insulating layer, wherein the pixel anode layer and the first gate are arranged in the same layer.
  • the pixel anode layer is provided corresponding to the active layer.
  • the method of this embodiment can complete the production of the storage capacitor in the TFT substrate.
  • the common electrode line, the active layer, and the pixel anode layer constitute a three-layer electrode structure of the storage capacitor.
  • the three electrode layers of the storage capacitor in this embodiment are not provided in the same layer as the source / drain layer S1 / D1 of the first thin film transistor, therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (ie the first thin film
  • the source / drain layers of the transistors (S1 / D1) are separated to avoid short-circuiting of storage capacitors and VDD / Sense traces, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • the present application further proposes a method for manufacturing a TFT substrate according to another embodiment. As shown in FIG. 6, the method of this embodiment is used to manufacture the TFT substrate shown in FIG.
  • the method of this embodiment includes the following steps:
  • Step S601 Prepare the substrate 406.
  • Step S602 forming a common electrode line LS1, a first common electrode line LS2, and a second common electrode line LS3 on the substrate 406.
  • Step S603 forming a buffer layer 404 covering at least the common electrode line LS1, the first common electrode line LS2, and the second common electrode line LS3.
  • Step S604 forming an active layer AOS1, a first active layer AOS2, and a second active layer AOS3 on the buffer layer 404.
  • the position of the active layer AOS1, the first active layer AOS2 and the second active layer AOS3 can be preset on the buffer layer 404 by wet etching to form a pattern to facilitate the active layer AOS1, the first active layer AOS2 and the second active layer AOS3 positioning.
  • the active layer AOS1 corresponds to the common electrode line LS1
  • the first active layer AOS2 corresponds to the first common electrode line LS2
  • the second active layer AOS3 corresponds to the second common electrode line LS3.
  • Step S605 forming a first insulating layer 405 covering at least the active layer AOS1, the first active layer AOS2, and the second active layer AOS3.
  • Step S606 forming a pixel anode layer M1, a first gate G1 and a second gate G2 on the first insulating layer 405, wherein the pixel anode layer M1 and the first gate G2 are disposed in the same layer.
  • the pixel anode layer M1 corresponds to the active layer AOS1
  • the first gate G1 corresponds to the first active layer AOS2
  • the second gate G2 corresponds to the second active layer AOS3.
  • Step S607 forming a second insulating layer 407 covering at least the pixel anode layer M1, the first gate G1, and the second gate G2.
  • Step S608 forming a first source S1, a first drain D1, a second source S2 and a second drain D2 on the second insulating layer 407.
  • Step S609 forming a plurality of first through holes penetrating the first insulating layer 405 and the second insulating layer 407, and connecting the first source S1 and the first drain D1 to the first active layer AOS2 through the first through holes, The second source electrode S2 and the second drain electrode D2 are connected to the second active layer AOS3 through the first via hole.
  • the method of this implementation further includes:
  • Step S610 forming a passivation layer 408 covering at least the first source S1, the first drain D1, the second source S2 and the second drain D2; forming a flat layer 409 on the passivation layer 408; An ITO layer 410 is formed thereon; a second through hole penetrating the passivation layer 408 and the flat layer 409 is formed, and the ITO layer 410 is connected to the first drain D1 through the second through hole.
  • the method of this implementation further includes:
  • Step S611 forming a pixel definition layer 411 covering at least the ITO layer 410; forming a pixel cathode layer 412 on the pixel definition layer 411; forming a third through hole in the pixel definition layer 411, passing the pixel cathode layer 412 through the third through hole Layer 410 is connected.
  • This application further proposes the TFT substrate of the second embodiment.
  • the difference between the TFT substrate 701 of this embodiment and the TFT substrate 401 of the above embodiment is that the first electrode layer 703 of the storage capacitor 702 of this embodiment is provided On the buffer layer 704; the first insulating layer 705 covers at least the first electrode layer 703; the second electrode layer 706 is disposed on the first insulating layer 705, the second insulating layer 707 covers at least the second electrode layer 706, and the second electrode layer 706 is provided in the same layer as the first gate G1 of the first thin film transistor 708; the third electrode layer 709 is provided on the second insulating layer 707.
  • the source / drain layer S1 / D1 of the first thin film transistor 708 of this embodiment is provided on the second insulating layer 707, in order to make the third electrode layer 709 and the source / drain layer S1 / D1 not in the same layer, the third The electrode layer 709 is provided on the passivation layer 710.
  • the first electrode layer 703 is an active layer AOS1
  • the second electrode layer 415 is a pixel anode layer M1
  • the third electrode layer 416 is an ITO layer.
  • the active layer AOS1, the pixel anode layer M1 and the ITO layer are provided correspondingly, that is, the pixel anode layer M1 is located directly above the active layer AOS1, and the ITO layer is located directly above the pixel anode layer M1.
  • none of the three electrode layers of the storage capacitor 702 of this embodiment are provided in the same layer as the source and drain layers S1 / D1 of the first thin film transistor 708, therefore, the electrode layer of the storage capacitor 702 can be Separated from the VDD / Sense trace (that is, the source / drain layer S1 / D1 of the first thin film transistor 708), the storage capacitor 702 can be prevented from being short-circuited with the VDD / Sense trace, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • the manufacturing method of the TFT substrate 701 in this embodiment is similar to the above embodiment, and will not be repeated here.
  • the present application further proposes a TFT substrate of a third embodiment.
  • the difference between the TFT substrate 801 of this embodiment and the TFT substrate 401 of the above embodiment is that the first electrode layer 803 of the storage capacitor 802 of this embodiment is provided On the substrate 804; the buffer layer 805 covers at least the first electrode layer 803; the second electrode layer 806 is provided on the buffer layer 805; the first insulating layer 807 covers at least the second electrode layer 806; the third electrode layer 808 is provided on the first insulation On layer 807.
  • the first insulating layer 807 of the present embodiment is equivalent to the second insulating layer of the above-mentioned embodiment.
  • the first electrode layer 803 is a common electrode line LS1
  • the second electrode layer 806 is an active layer AOS1
  • the third electrode layer 808 is an ITO layer.
  • the common electrode line LS1, the active layer AOS1 and the ITO layer are arranged correspondingly, that is, the active layer AOS1 is located directly above the common electrode line LS1, and the ITO layer is located directly above the active layer AOS1.
  • none of the three electrode layers of the storage capacitor 802 of this embodiment are provided in the same layer as the source / drain layer S1 / D1 of the first thin film transistor 809, therefore, the electrode layer of the storage capacitor 802 can be Separated from the VDD / Sense trace (that is, the source / drain layer S1 / D1 of the first thin film transistor 809), the storage capacitor 802 can be prevented from short-circuiting with the VDD / Sense trace, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • the manufacturing method of the TFT substrate 801 in this embodiment is similar to the above embodiment, and will not be repeated here.
  • FIG. 9 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • the display panel 901 of this embodiment includes a color filter substrate 902 and a TFT substrate 903, wherein the TFT substrate 903 is the TFT substrate of the foregoing embodiment, which is not described here.
  • the pixel anode layer of the storage capacitor and the first gate of the first thin film transistor in this embodiment can separate the pixel anode layer from the VDD trace (that is, the source or drain of the first thin film transistor), The short circuit of the pixel anode layer and the VDD trace can be avoided, thereby reducing the abnormal bright spots of the display panel and improving the display effect.
  • FIG. 10 is a schematic structural diagram of an embodiment of the display device of the present application.
  • the display device 1001 of this embodiment includes at least a display panel 1002.
  • the TFT substrate in the embodiment of the present application includes at least a first thin film transistor and a storage capacitor disposed on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode layer, and a third electrode layer, the first The electrode layer, the second electrode layer, and the third electrode layer are all disposed in a different layer from the source and drain layers of the first thin film transistor; wherein, the second electrode layer is disposed between the first electrode layer and the third electrode layer.
  • the electrode layer of the storage capacitor and the source and drain layers of the first thin film transistor are provided in different layers. Therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (that is, the source or drain of the first thin film transistor Pole) separate, can avoid short circuit between the two, which can reduce the abnormal bright spots of the display panel and improve the display effect.

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开了一种TFT基板、显示面板及显示装置。该TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，存储电容包括：第一电极层、第二电极层及第三电极层，第一电极层、第二电极层及第三电极层均与第一薄膜晶体管的源漏极层异层设置；其中，第二电极层设置在第一电极层及第三电极层之间。通过这种方式，能够减少显示面板的异常亮点，提升显示效果。

Description

一种TFT基板、显示面板及显示装置 技术领域
本申请涉及显示面板技术领域，特别是涉及一种TFT基板、显示面板及显示装置。
 背景技术
随着信息社会的发展，需要多种形式的用于显示图像的显示装置。近年来，诸如液晶显示器、等离子体显示面板以及有机发光显示装置到了广泛应用。显示装置包括显示面板，显示面板包括在各像素区域中的薄膜晶体管及存储电容，其中，存储电容用于增加像素的电荷存储量，在下一个扫描周期到来之前保持像素电位。
 技术问题
本申请的发明人在长期的研发中发现，现有的有机发光显示面板中，因VDD/Sense走线用的第二层金属，存储电容其中一个电极板用的也是第二层金属，两者因为版图空间限制，距离较近，所以DD/Sense走线易与存储电容的电极板短接，导致在显示面板出现异常亮点。
 技术解决方案
本申请主要解决的技术问题是提供一种TFT基板、显示面板及显示装置，以减少显示面板的异常亮点，提升显示效果。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种TFT基板。该TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，存储电容包括：第一电极层、第二电极层及第三电极层，第一电极层、第二电极层及第三电极层均与第一薄膜晶体管的源漏极层异层设置；其中，第二电极层设置在第一电极层及第三电极层之间。
在一实施例中，存储电容进一步包括缓冲层及第一绝缘层，其中，第一电极层设置在基板上；缓冲层至少覆盖第一电极层；第二电极层设置在缓冲层上；第一绝缘层至少覆盖第二电极层；第三电极层设置在第一绝缘层上；其中，第三电极层与第一薄膜晶体管的第一栅极同层设置。
在一实施例中，第一薄膜晶体管进一步包括：第一公共电极线，与第一电极层同层设置，且被缓冲层覆盖；第一活性层，与第二电极层同层设置，第一活性层被第一绝缘层覆盖；第一栅极设置在第一绝缘层上；第二绝缘层，至少覆盖第一栅极及第三电极层；源漏极层包括第一源极和第一漏极，设置在第二绝缘层上，第一源极和第一漏极通过第一通孔与第一活性层连接。
在一实施例中，TFT基板进一步包括：钝化层，至少覆盖第一源极和第一漏极；平坦层，设置在钝化层上；ITO层，设置在平坦层上，ITO层通过第二通孔与第一源极或第一漏极连接。
在一实施例中，TFT基板进一步包括：像素定义层，至少覆盖ITO层；像素阴极层，设置在像素定义层上，且通过第三通孔与ITO层连接。
在一实施例中，TFT基板进一步包括第二薄膜晶体管，第二薄膜晶体管包括：第二公共电极线，与第一公共电极线同层设置，且被缓冲层覆盖；第二活性层，与第一活性层同层设置，且被第一绝缘层覆盖；第二栅极，设置在第一绝缘层与第二绝缘层之间；第二源极和第二漏极，设置在第二绝缘层上，且与第二活性层的对应设置，第二源极和第二漏极通过第四通孔与第二活性层连接。
在一实施例中，存储电容进一步包括缓冲层、第一绝缘层及第二绝缘层，其中，第一电极层设置缓冲层上；第一绝缘层至少覆盖第一电极层；第二电极层设置在第一绝缘层上，第二绝缘层至少覆盖第二电极层，且第二电极层与第一薄膜晶体管的第一栅极同层设置；第三电极层设置在第二绝缘层上。
在一实施例中，存储电容进一步包括缓冲层及第一绝缘层，其中，第一电极层设置在基板上；缓冲层至少覆盖第一电极层；第二电极层设置在缓冲层上；第一绝缘层至少覆盖第二电极层；第三电极层设置在第一绝缘层上。
在一实施例中，显示面板包括TFT基板，所述TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，所述存储电容包括：第一电极层、第二电极层及第三电极层，所述第一电极层、所述第二电极层及所述第三电极层均与所述第一薄膜晶体管的源漏极层异层设置；其中，所述第二电极层设置在所述第一电极层及第三电极层之间。
在一实施例中，所述存储电容进一步包括缓冲层及第一绝缘层，所述第一电极层设置在所述基板上，所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上；其中，所述第三电极层与所述第一薄膜晶体管的第一栅极同层设置。
在一实施例中，所述第一薄膜晶体管进一步包括：第一公共电极线，与所述第一电极层同层设置，且被所述缓冲层覆盖；第一活性层，与所述第二电极层同层设置，所述第一活性层被所述第一绝缘层覆盖；所述第一栅极设置在所述第一绝缘层上；第二绝缘层，至少覆盖所述第一栅极及所述第三电极层；以及所述源漏极层包括第一源极和第一漏极，设置在所述第二绝缘层上，所述第一源极和所述第一漏极通过第一通孔与所述第一活性层连接。
在一实施例中，所述TFT基板进一步包括：钝化层，至少覆盖所述第一源极和所述第一漏极；平坦层，设置在所述钝化层上；ITO层，设置在所述平坦层上，所述ITO层通过第二通孔与所述第一源极或所述第一漏极连接。
在一实施例中，所述TFT基板进一步包括：像素定义层，至少覆盖所述ITO层；像素阴极层，设置在所述像素定义层上，且通过第三通孔与所述ITO层连接。
在一实施例中，所述TFT基板进一步包括第二薄膜晶体管，所述第二薄膜晶体管包括：第二公共电极线，与所述第一公共电极线同层设置，且被所述缓冲层覆盖；第二活性层，与所述第一活性层同层设置，且被所述第一绝缘层覆盖；第二栅极，设置在所述第一绝缘层与所述第二绝缘层之间；第二源极和第二漏极，设置在所述第二绝缘层上，且与所述第二活性层的对应设置，所述第二源极和所述第二漏极通过第四通孔与所述第二活性层连接。
在一实施例中，所述存储电容进一步包括缓冲层、第一绝缘层及第二绝缘层，其中，所述第一电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第一电极层；所述第二电极层设置在所述第一绝缘层上，所述第二绝缘层至少覆盖所述第二电极层，且所述第二电极层与所述第一薄膜晶体管的第一栅极同层设置；所述第三电极层设置在所述第二绝缘层上。
在一实施例中，所述存储电容进一步包括缓冲层及第一绝缘层，其中，所述第一电极层设置在所述基板上；所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上，所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上。
在一实施例中，种显示装置包括显示面板，所述显示面板包括TFT基板，所述TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，所述存储电容包括：第一电极层、第二电极层及第三电极层，所述第一电极层、所述第二电极层及所述第三电极层均与所述第一薄膜晶体管的源漏极层异层设置；其中，所述第二电极层设置在所述第一电极层及第三电极层之间。
在一实施例中，所述存储电容进一步包括缓冲层及第一绝缘层，所述第一电极层设置在所述基板上，所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上；其中，所述第三电极层与所述第一薄膜晶体管的第一栅极同层设置。
在一实施例中，所述第一薄膜晶体管进一步包括：第一公共电极线，与所述第一电极层同层设置，且被所述缓冲层覆盖；第一活性层，与所述第二电极层同层设置，所述第一活性层被所述第一绝缘层覆盖；所述第一栅极设置在所述第一绝缘层上；第二绝缘层，至少覆盖所述第一栅极及所述第三电极层；以及所述源漏极层包括第一源极和第一漏极，设置在所述第二绝缘层上，所述第一源极和所述第一漏极通过第一通孔与所述第一活性层连接。
在一实施例中，所述TFT基板进一步包括：钝化层，至少覆盖所述第一源极和所述第一漏极；平坦层，设置在所述钝化层上；ITO层，设置在所述平坦层上，所述ITO层通过第二通孔与所述第一源极或所述第一漏极连接。
 有益效果
本申请实施例的有益效果是：区别于现有技术，本申请实施例TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，存储电容包括：第一电极层、第二电极层及第三电极层，第一电极层、第二电极层及第三电极层均与第一薄膜晶体管的源漏极层异层设置；其中，第二电极层设置在第一电极层及第三电极层之间。通过这种方式，存储电容的电极层与第一薄膜晶体管的源漏极层异层设置，因此，能够将存储电容的电极层与VDD/Sense走线（即第一薄膜晶体管的源极或漏极）分开，能够避免二者间的短接，从而能够减少显示面板的异常亮点，提升显示效果。
 附图说明
图1是TFT基板一结构示意图；
图2是图1实施例TFT基板的像素结构示意图；
图3是图2实施例像素结构的等效电路图；
图4是本申请TFT基板第一实施例的结构示意图；
图5是图4实施例TFT基板的制作方法的一流程示意图；
图6是图4实施例TFT基板的制作方法的另一流程示意图；
图7是本申请TFT基板第二实施例的结构示意图；
图8是本申请TFT基板第三实施例的结构示意图；
图9是本申请显示面板一实施例的结构示意图；
图10是本申请显示装置一实施例的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
请参阅图1至图3，图1是TFT基板一结构示意图；图2是图1实施例TFT基板的像素结构示意图；图3是图2实施例像素结构的等效电路图。其中，VDD/Sense走线(常高电位)101与像素的阳极102都采用第二金属层M2走线，且至少VDD/Sense走线101与像素中的一个子像素紧邻排布。在像素制作工艺中，第二金属层M2易残留，因此，会导致VDD/Sense走线101与子像素的阳极102短接，从而使在显示面板出现异常亮点。
为解决上述问题，本申请进一步提出一种TFT基板，如图4所示，图4是本申请TFT基板第一实施例的结构示意图。本实施例TFT基板401至少包括设置在基板406上的第一薄膜晶体管402及存储电容403，其中，存储电容403包括：第一电极层414、第二电极层415及第三电极层416，第一电极层414、第二电极层415及第三电极层416均与第一薄膜晶体管402的源漏极层S1/D1异层设置；其中，第二电极层415设置在第一电极层414及第三电极层416之间。
本实施例所述第一电极层414、第二电极层415及第三电极层416均与第一薄膜晶体管402的源漏极层S1/D1异层设置是指，第一电极层414、第二电极层415及第三电极层416与第一薄膜晶体管402的源漏极层S1/D1设置在不同层。
区别于现有技术，本实施例的存储电容的电极层与第一薄膜晶体管的源漏极层异层设置，因此，能够将存储电容的电极层与VDD/Sense走线（即第一薄膜晶体管的源极或漏极）分开，能够避免二者间的短接，从而能够减少显示面板的异常亮点，提升显示效果。
可选地，本实施例的存储电容403进一步包括缓冲层404及第一绝缘层405；其中，第一电极层414设置在基板406上，缓冲层404至少覆盖第一电极层414，第二电极层415设置缓冲层404上，第一绝缘层405至少覆盖第二电极层415，第三电极层416设置在第一绝缘层405上，其中，第三电极层416与第一薄膜晶体管402的第一栅极G1同层设置。
本实施例的第一电极层414为公共电极线LS1，第二电极层415为活性层AOS1，第三电极层416为像素阳极层M1。其中，公共电极线LS1、活性层AOS1及像素阳极层M1对应设置，即活性层AOS1位于公共电极线LS1的正上方，像素阳极层M1位于活性层AOS1的正上方。
从图4中可以看出，本实施例的存储电容403的电极为三层结构，即公共电极线LS1、活性层AOS1及像素阳极层M1，且这三个电极层均未与第一薄膜晶体管402的源漏极层S1/D1同层设置，因此，能够将存储电容403的电极层与VDD/Sense走线（即第一薄膜晶体管402的源漏极层S1/D1）分开，能够避免存储电容403与VDD/Sense走线短接。
可选地，本实施例的第一薄膜晶体管402进一步包括：第一公共电极线LS2、第一活性层AOS2、第二绝缘层407及第一源极S1和第一漏极D1；其中，第一公共电极线LS2与第一电极层414（即公共电极线LS1）同层设置，且被缓冲层404覆盖；第一活性层AOS2与第二电极层415（即活性层AOS1）同层设置，且被第一绝缘层405覆盖；第一栅极G1设置在第一绝缘层405上；第二绝缘层407至少覆盖第一栅极G1及第三电极层416（即像素阳极层M1）；第一源极S1和第一漏极D1设置在第二绝缘层407上，第一源极S1和第一漏极D1通过第一通孔（图未标）与第一活性层AOS2连接。
其中，第一活性层AOS2是第一源极S1与第一漏极D1间的导电沟道。
其中，第一公共电极线LS2、第一活性层AOS2及第一栅极G1对应设置，即第一活性层AOS2位于第一公共电极线LS2的正上方，第一栅极G1位于第一活性层AOS2的正上方。
可选地，本实施例TFT基板401进一步包括：钝化层408、平坦层409及氧化铟锡（ITO，Indium Tin Oxides）层410；其中，钝化层408至少覆盖第一源极S1和第一漏极D1，平坦层409设置在钝化层408上，ITO层410设置在平坦层409上，且ITO层410通过第二通孔（图未标）与第一漏极D1连接。
当然，在其它实施例中，ITO层410还可以通过第二通孔与第一漏极连接。
可选地，本实施例TFT基板401进一步包括：像素定义层411、像素阴极层412；其中，像素定义层411至少覆盖ITO层410，像素阴极层412设置在像素定义层411上，且通过第三通孔（图未标）与ITO层410连接。
可选地，本实施例TFT基板401进一步包括：第二薄膜晶体管413，第二薄膜晶体管413包括：第二公共电极线LS3、第二活性层AOS3、第二栅极G2、第二源极S2和第二漏极D2；其中，第二公共电极线LS3与第一公共电极线LS2同层设置，且被缓冲层404覆盖，第二活性层AOS3与第一活性层AOS2同层设置，且被第一绝缘层覆盖405，第二栅极G2设置在第一绝缘层405与第二绝缘层407之间，第二源极S2和第二漏极D2设置在第二绝缘层407上，第二源极S2和第二漏极D2通过第四通孔（图未标）与第二活性层AOS3连接。
其中，第二活性层AOS3是第二源极S2与第二漏极D2间的导电沟道。
其中，本实施例的第二活性层AOS3与第二公共电极线LS3对应设置，即第二活性层AOS3位于第二公共电极线LS3的正上方；第二栅极G2与第二活性层AOS3对应设置，即第二栅极G2设置在第二活性层AOS3的正上方。
本实施例TFT基板401的像素结构等效电路与图3相同，其中，本实施例的第一薄膜晶体管402相当于T1，第二薄膜晶体管413相当于T2，存储电容403相当于电容Cst。T1为驱动薄膜晶体管，T1具体可以为氧化物薄膜晶体管；T2为开关薄膜晶体管，T2具体可以为低温多晶硅 (LTPS，Low Temperature Poly-silicon) 薄膜晶体管。
如图3所示，T2的控制端与扫描线Scan连接，T2的第一通信端与T1的控制端连接，T2的第二通信端与数据线Data连接；T1的第一通信端与VDD走线连接，T1的第二通信端与OLED的正极连接，OLED的负极接地；电容Cst的第一端与T1的控制端连接，电容Cst的第二端与T3的第二端连接，T3的控制端与RD走线连接，T3的第一端与Sense走线连接。
需要注意的是，本申请的图1、图2及图4中并未示出图3中的T3。
当然，在其它实施例中，不限定TFT基板上设置的薄膜晶体管的数量。
本申请进一步提出一种TFT基板的制作方法，如图5所示，图5是图4实施例TFT基板的制作方法的一流程示意图。具体地，本实施例的方法包括以下步骤：
步骤S501：准备基板。
其中，基板可以为玻璃基板或者树脂基板等，不做具体限定。
步骤S502：在基板上形成公共电极线。
步骤S503：形成至少覆盖公共电极线的缓冲层。
步骤S504：在缓冲层上形成活性层。
其中，活性层与公共电极线对应设置。
步骤S505：形成至少覆盖活性层的第一绝缘层。
步骤S506：在第一绝缘层上形成像素阳极层及第一栅极，其中，像素阳极层与第一栅极同层设置。
其中，像素阳极层与活性层对应设置。
通过本实施例的方法能够完成对TFT基板中存储电容的制作，其中，公共电极线、活性层及像素阳极层构成存储电容的三层电极结构。
本实施例的存储电容的三个电极层均未与第一薄膜晶体管的源漏极层S1/D1同层设置，因此，能够将存储电容的电极层与VDD/Sense走线（即第一薄膜晶体管的源漏极层S1/D1）分开，能够避免存储电容与VDD/Sense走线短接，能够减少显示面板的异常亮点，提升显示效果。
本申请进一步提出另一实施例的TFT基板的制作方法，如图6所示，本实施的方法用于制作如图4所示的TFT基板。本实施例的方法包括以下步骤：
步骤S601：准备基板406。
步骤S602：在基板406上形成公共电极线LS1、第一公共电极线LS2及第二公共电极线LS3。
步骤S603：形成至少覆盖公共电极线LS1、第一公共电极线LS2及第二公共电极线LS3的缓冲层404。
步骤S604：在缓冲层404上形成活性层AOS1、第一活性层AOS2及第二活性层AOS3。
其中，可以采用湿蚀刻方式在缓冲层404上预设置活性层AOS1、第一活性层AOS2及第二活性层AOS3的位置形成图案，以便于活性层AOS1、第一活性层AOS2及第二活性层AOS3的定位。
其中，活性层AOS1与公共电极线LS1对应设置，第一活性层AOS2与第一公共电极线LS2对应设置，第二活性层AOS3与第二公共电极线LS3对应设置。
步骤S605：形成至少覆盖活性层AOS1、第一活性层AOS2及第二活性层AOS3的第一绝缘层405。
步骤S606：在第一绝缘层405上形成像素阳极层M1、第一栅极G1及第二栅极G2，其中，像素阳极层M1与第一栅极G2同层设置。
其中，像素阳极层M1与活性层AOS1对应设置，第一栅极G1与第一活性层AOS2对应设置，第二栅极G2与第二活性层AOS3对应设置。
步骤S607：形成至少覆盖像素阳极层M1、第一栅极G1及第二栅极G2的第二绝缘层407。
步骤S608：在第二绝缘层407上形成第一源极S1、第一漏极D1、第二源极S2及第二漏极D2。
步骤S609：形成贯穿第一绝缘层405及第二绝缘层407的多个第一通孔，并将第一源极S1和第一漏极D1通过第一通孔与第一活性层AOS2连接，将第二源极S2和第二漏极D2通过第一通孔与第二活性层AOS3连接。
本实施的方法进一步包括：
步骤S610：形成至少覆盖第一源极S1、第一漏极D1、第二源极S2及第二漏极D2的钝化层408；在钝化层408上形成平坦层409；在平坦层409上形成ITO层410；形成贯穿钝化层408及平坦层409的第二通孔，将ITO层410通过第二通孔与第一漏极D1连接。
本实施的方法进一步包括：
步骤S611：形成至少覆盖ITO层410的像素定义层411；在像素定义层411上形成像素阴极层412；在像素定义层411形成第三通孔，将像素阴极层412通过第三通孔与ITO层410连接。
本申请进一步提出第二实施例的TFT基板，如图7所示，本实施例的TFT基板701与上述实施例TFT基板401的区别在于：本实施例的存储电容702的第一电极层703设置缓冲层704上；第一绝缘层705至少覆盖第一电极层703；第二电极层706设置在第一绝缘层705上，第二绝缘层707至少覆盖第二电极层706，且第二电极层706与第一薄膜晶体管708的第一栅极G1同层设置；第三电极层709设置在第二绝缘层707上。
因本实施例的第一薄膜晶体管708的源漏极层S1/D1设置在第二绝缘层707上，为使第三电极层709与源漏极层S1/D1不在同一层，可以将第三电极层709设置在钝化层710上。
本实施例的第一电极层703为活性层AOS1，第二电极层415为像素阳极层M1，第三电极层416为ITO层。其中，活性层AOS1、像素阳极层M1及ITO层对应设置，即像素阳极层M1位于活性层AOS1的正上方，ITO层位于像素阳极层M1的正上方。
从图7中可以看出，本实施例的存储电容702的三个电极层均未与第一薄膜晶体管708的源漏极层S1/D1同层设置，因此，能够将存储电容702的电极层与VDD/Sense走线（即第一薄膜晶体管708的源漏极层S1/D1）分开，能够避免存储电容702与VDD/Sense走线短接，能够减少显示面板的异常亮点，提升显示效果。
本实施例TFT基板701的制作方法与上述实施例类似，这里不赘述。
本申请进一步提出第三实施例的TFT基板，如图8所示，本实施例的TFT基板801与上述实施例TFT基板401的区别在于：本实施例的存储电容802的第一电极层803设置在基板804上；缓冲层805至少覆盖第一电极层803；第二电极层806设置缓冲层805上；第一绝缘层807至少覆盖第二电极层806；第三电极层808设置在第一绝缘层807上。
其中，本实施例的第一绝缘层807与上述实施例相当于上述实施例的第二绝缘层。
本实施例的第一电极层803为公共电极线LS1，第二电极层806为活性层AOS1，第三电极层808为ITO层。其中，公共电极线LS1、活性层AOS1及ITO层对应设置，即活性层AOS1位于公共电极线LS1的正上方，ITO层位于活性层AOS1的正上方。
从图8中可以看出，本实施例的存储电容802的三个电极层均未与第一薄膜晶体管809的源漏极层S1/D1同层设置，因此，能够将存储电容802的电极层与VDD/Sense走线（即第一薄膜晶体管809的源漏极层S1/D1）分开，能够避免存储电容802与VDD/Sense走线短接，能够减少显示面板的异常亮点，提升显示效果。
本实施例TFT基板801的制作方法与上述实施例类似，这里不赘述。
本申请进一步提出一种显示面板，如图9所示，图9是本申请显示面板一实施例的结构示意图。本实施例显示面板901包括彩色滤光基板902及TFT基板903，其中，TFT基板903为上述实施例TFT基板，这里不赘述。
区别于现有技术，本实施例存储电容的像素阳极层与第一薄膜晶体管的第一栅极，能够将像素阳极层与VDD走线（即第一薄膜晶体管的源极或漏极）分开，能够避免像素阳极层与VDD走线短接，从而能够减少显示面板的异常亮点，提升显示效果。
本申请还进一步提出一种显示装置，如图10所示，图10是本申请显示装置一实施例的结构示意图。本实施例显示装置1001至少包括显示面板1002。
区别于现有技术，本申请实施例TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，存储电容包括：第一电极层、第二电极层及第三电极层，第一电极层、第二电极层及第三电极层均与第一薄膜晶体管的源漏极层异层设置；其中，第二电极层设置在第一电极层及第三电极层之间。通过这种方式，存储电容的电极层与第一薄膜晶体管的源漏极层异层设置，因此，能够将存储电容的电极层与VDD/Sense走线（即第一薄膜晶体管的源极或漏极）分开，能够避免二者间的短接，从而能够减少显示面板的异常亮点，提升显示效果。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (20)

  1. 一种TFT基板，至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，所述存储电容包括：
    第一电极层、第二电极层及第三电极层，所述第一电极层、所述第二电极层及所述第三电极层均与所述第一薄膜晶体管的源漏极层异层设置；
    其中，所述第二电极层设置在所述第一电极层及第三电极层之间。
  2. 根据权利要求1所述的TFT基板，其中所述存储电容进一步包括缓冲层及第一绝缘层，所述第一电极层设置在所述基板上，所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上；
    其中，所述第三电极层与所述第一薄膜晶体管的第一栅极同层设置。
  3. 根据权利要求2所述的TFT基板，其中所述第一薄膜晶体管进一步包括：
    第一公共电极线，与所述第一电极层同层设置，且被所述缓冲层覆盖；
    第一活性层，与所述第二电极层同层设置，所述第一活性层被所述第一绝缘层覆盖；
    所述第一栅极设置在所述第一绝缘层上；
    第二绝缘层，至少覆盖所述第一栅极及所述第三电极层；以及
    所述源漏极层包括第一源极和第一漏极，设置在所述第二绝缘层上，所述第一源极和所述第一漏极通过第一通孔与所述第一活性层连接。
  4. 根据权利要求3所述的TFT基板，其中所述TFT基板进一步包括：
    钝化层，至少覆盖所述第一源极和所述第一漏极；
    平坦层，设置在所述钝化层上；
    ITO层，设置在所述平坦层上，所述ITO层通过第二通孔与所述第一源极或所述第一漏极连接。
  5. 根据权利要求4所述的TFT基板，其中所述TFT基板进一步包括：
    像素定义层，至少覆盖所述ITO层；
    像素阴极层，设置在所述像素定义层上，且通过第三通孔与所述ITO层连接。
  6. 根据权利要求3所述的TFT基板，其中所述TFT基板进一步包括第二薄膜晶体管，所述第二薄膜晶体管包括：
    第二公共电极线，与所述第一公共电极线同层设置，且被所述缓冲层覆盖；
    第二活性层，与所述第一活性层同层设置，且被所述第一绝缘层覆盖；
    第二栅极，设置在所述第一绝缘层与所述第二绝缘层之间；
    第二源极和第二漏极，设置在所述第二绝缘层上，且与所述第二活性层的对应设置，所述第二源极和所述第二漏极通过第四通孔与所述第二活性层连接。
  7. 根据权利要求1所述的TFT基板，其中所述存储电容进一步包括缓冲层、第一绝缘层及第二绝缘层，其中，所述第一电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第一电极层；所述第二电极层设置在所述第一绝缘层上，所述第二绝缘层至少覆盖所述第二电极层，且所述第二电极层与所述第一薄膜晶体管的第一栅极同层设置；所述第三电极层设置在所述第二绝缘层上。
  8. 根据权利要求1所述的TFT基板，其中所述存储电容进一步包括缓冲层及第一绝缘层，其中，所述第一电极层设置在所述基板上；所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上，所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上。
  9. 一种显示面板，包括TFT基板，所述TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，所述存储电容包括：
    第一电极层、第二电极层及第三电极层，所述第一电极层、所述第二电极层及所述第三电极层均与所述第一薄膜晶体管的源漏极层异层设置；
    其中，所述第二电极层设置在所述第一电极层及第三电极层之间。
  10. 根据权利要求9所述的显示面板，其中所述存储电容进一步包括缓冲层及第一绝缘层，所述第一电极层设置在所述基板上，所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上；
    其中，所述第三电极层与所述第一薄膜晶体管的第一栅极同层设置。
  11. 根据权利要求10所述的显示面板，其中所述第一薄膜晶体管进一步包括：
    第一公共电极线，与所述第一电极层同层设置，且被所述缓冲层覆盖；
    第一活性层，与所述第二电极层同层设置，所述第一活性层被所述第一绝缘层覆盖；
    所述第一栅极设置在所述第一绝缘层上；
    第二绝缘层，至少覆盖所述第一栅极及所述第三电极层；以及
    所述源漏极层包括第一源极和第一漏极，设置在所述第二绝缘层上，所述第一源极和所述第一漏极通过第一通孔与所述第一活性层连接。
  12. 根据权利要求11所述的显示面板，其中所述TFT基板进一步包括：
    钝化层，至少覆盖所述第一源极和所述第一漏极；
    平坦层，设置在所述钝化层上；
    ITO层，设置在所述平坦层上，所述ITO层通过第二通孔与所述第一源极或所述第一漏极连接。
  13. 根据权利要求12所述的显示面板，其中所述TFT基板进一步包括：
    像素定义层，至少覆盖所述ITO层；
    像素阴极层，设置在所述像素定义层上，且通过第三通孔与所述ITO层连接。
  14. 根据权利要求11所述的显示面板，其中所述TFT基板进一步包括第二薄膜晶体管，所述第二薄膜晶体管包括：
    第二公共电极线，与所述第一公共电极线同层设置，且被所述缓冲层覆盖；
    第二活性层，与所述第一活性层同层设置，且被所述第一绝缘层覆盖；
    第二栅极，设置在所述第一绝缘层与所述第二绝缘层之间；
    第二源极和第二漏极，设置在所述第二绝缘层上，且与所述第二活性层的对应设置，所述第二源极和所述第二漏极通过第四通孔与所述第二活性层连接。
  15. 根据权利要求9所述的显示面板，其中所述存储电容进一步包括缓冲层、第一绝缘层及第二绝缘层，其中，所述第一电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第一电极层；所述第二电极层设置在所述第一绝缘层上，所述第二绝缘层至少覆盖所述第二电极层，且所述第二电极层与所述第一薄膜晶体管的第一栅极同层设置；所述第三电极层设置在所述第二绝缘层上。
  16. 根据权利要求9所述的显示面板，其中所述存储电容进一步包括缓冲层及第一绝缘层，其中，所述第一电极层设置在所述基板上；所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上，所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上。
  17. 一种显示装置，包括显示面板，所述显示面板包括TFT基板，所述TFT基板至少包括设置在基板上的第一薄膜晶体管及存储电容，其中，所述存储电容包括：
    第一电极层、第二电极层及第三电极层，所述第一电极层、所述第二电极层及所述第三电极层均与所述第一薄膜晶体管的源漏极层异层设置；
    其中，所述第二电极层设置在所述第一电极层及第三电极层之间。
  18. 根据权利要求17所述的显示装置，其中所述存储电容进一步包括缓冲层及第一绝缘层，所述第一电极层设置在所述基板上，所述缓冲层至少覆盖所述第一电极层，所述第二电极层设置在所述缓冲层上；所述第一绝缘层至少覆盖所述第二电极层；所述第三电极层设置在所述第一绝缘层上；
    其中，所述第三电极层与所述第一薄膜晶体管的第一栅极同层设置。
  19. 根据权利要求18所述的显示装置，其中所述第一薄膜晶体管进一步包括：
    第一公共电极线，与所述第一电极层同层设置，且被所述缓冲层覆盖；
    第一活性层，与所述第二电极层同层设置，所述第一活性层被所述第一绝缘层覆盖；
    所述第一栅极设置在所述第一绝缘层上；
    第二绝缘层，至少覆盖所述第一栅极及所述第三电极层；以及
    所述源漏极层包括第一源极和第一漏极，设置在所述第二绝缘层上，所述第一源极和所述第一漏极通过第一通孔与所述第一活性层连接。
  20. 根据权利要求19所述的显示装置，其中所述TFT基板进一步包括：
    钝化层，至少覆盖所述第一源极和所述第一漏极；
    平坦层，设置在所述钝化层上；
    ITO层，设置在所述平坦层上，所述ITO层通过第二通孔与所述第一源极或所述第一漏极连接。
PCT/CN2019/093829 2018-10-12 2019-06-28 一种tft基板、显示面板及显示装置 Ceased WO2020073695A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811190358.XA CN109449164B (zh) 2018-10-12 2018-10-12 一种tft基板、显示面板及显示装置
CN201811190358.X 2018-10-12

Publications (1)

Publication Number Publication Date
WO2020073695A1 true WO2020073695A1 (zh) 2020-04-16

Family

ID=65546251

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/093829 Ceased WO2020073695A1 (zh) 2018-10-12 2019-06-28 一种tft基板、显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN109449164B (zh)
WO (1) WO2020073695A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109449164B (zh) * 2018-10-12 2020-12-04 深圳市华星光电半导体显示技术有限公司 一种tft基板、显示面板及显示装置
US11444132B2 (en) * 2019-11-29 2022-09-13 Hefei Boe Joint Technology Co., Ltd. Display substrate having gate extension portion protruding from gate electrode of first transistor, display device and manufacturing method the same thereof
US11482582B2 (en) * 2020-05-15 2022-10-25 Hefei Boe Joint Technology Co., Ltd. Display panel and electronic device
CN113628974B (zh) * 2021-07-27 2023-10-31 深圳市华星光电半导体显示技术有限公司 阵列基板的制备方法和阵列基板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075623A (zh) * 2007-06-11 2007-11-21 友达光电股份有限公司 画素结构及其形成方法
CN103268047A (zh) * 2012-12-31 2013-08-28 厦门天马微电子有限公司 一种ltps阵列基板及其制造方法
CN104733382A (zh) * 2013-12-24 2015-06-24 昆山工研院新型平板显示技术中心有限公司 一种阵列基板的制备方法及阵列基板
CN106129097A (zh) * 2016-05-25 2016-11-16 友达光电股份有限公司 像素结构及其显示面板
CN109449164A (zh) * 2018-10-12 2019-03-08 深圳市华星光电半导体显示技术有限公司 一种tft基板、显示面板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102253544A (zh) * 2011-07-29 2011-11-23 南京中电熊猫液晶显示科技有限公司 液晶显示装置
CN206098392U (zh) * 2016-10-10 2017-04-12 上海中航光电子有限公司 一种显示面板及显示装置
US11195863B2 (en) * 2018-09-21 2021-12-07 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel having a storage capacitor, manufacturing method the same thereof and display module having the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075623A (zh) * 2007-06-11 2007-11-21 友达光电股份有限公司 画素结构及其形成方法
CN103268047A (zh) * 2012-12-31 2013-08-28 厦门天马微电子有限公司 一种ltps阵列基板及其制造方法
CN104733382A (zh) * 2013-12-24 2015-06-24 昆山工研院新型平板显示技术中心有限公司 一种阵列基板的制备方法及阵列基板
CN106129097A (zh) * 2016-05-25 2016-11-16 友达光电股份有限公司 像素结构及其显示面板
CN109449164A (zh) * 2018-10-12 2019-03-08 深圳市华星光电半导体显示技术有限公司 一种tft基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN109449164B (zh) 2020-12-04
CN109449164A (zh) 2019-03-08

Similar Documents

Publication Publication Date Title
CN112071882B (zh) 显示基板及其制备方法、显示装置
KR102702938B1 (ko) 멀티 타입의 박막 트랜지스터를 포함하는 유기발광 표시장치
WO2022000339A1 (zh) 阵列基板、显示面板以及显示装置
CN215578564U (zh) 显示基板及显示装置
CN110690265A (zh) 一种显示基板及其制作方法、显示装置
US11705461B2 (en) Display substrate, manufacturing method thereof, display panel and display device
US12230215B2 (en) Display substrate, manufacturing method therefor, and display apparatus
WO2022226967A1 (zh) 显示面板和显示装置
WO2020073695A1 (zh) 一种tft基板、显示面板及显示装置
WO2020192208A1 (en) Array substrate, display panel and display apparatus
WO2020118900A1 (zh) 显示装置及其制造方法
KR102758332B1 (ko) 멀티 타입의 박막 트랜지스터를 포함하는 유기발광 표시장치 및 유기발광 표시장치 제조방법
US20230351957A1 (en) Display Substrate and Preparation Method Thereof, and Display Device
US20260123222A1 (en) Display panel and display apparatus
WO2022226882A1 (zh) 显示面板及显示装置
CN110571242A (zh) 阵列基板及显示面板
CN105070740A (zh) 一种阵列基板及其制备方法、显示面板和显示装置
WO2023023979A1 (zh) 显示基板和显示装置
WO2020118920A1 (zh) 有机发光二极管阵列基板及其制造方法
CN115424570A (zh) 像素电路及其驱动方法、显示基板和显示装置
WO2021258458A1 (zh) 阵列基板及其制造方法
WO2022000233A1 (zh) 显示基板及其制作方法和显示装置
WO2023044763A1 (zh) 阵列基板及显示装置
WO2022226994A1 (zh) 显示面板和显示装置
US12230201B2 (en) Pixel circuit and driving method thereof, display substrate and display apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19871884

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19871884

Country of ref document: EP

Kind code of ref document: A1