WO2020073695A1 - Substrat de tft, panneau d'affichage et appareil d'affichage - Google Patents

Substrat de tft, panneau d'affichage et appareil d'affichage Download PDF

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Publication number
WO2020073695A1
WO2020073695A1 PCT/CN2019/093829 CN2019093829W WO2020073695A1 WO 2020073695 A1 WO2020073695 A1 WO 2020073695A1 CN 2019093829 W CN2019093829 W CN 2019093829W WO 2020073695 A1 WO2020073695 A1 WO 2020073695A1
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layer
electrode
electrode layer
insulating layer
insulating
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PCT/CN2019/093829
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English (en)
Chinese (zh)
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肖辉
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020073695A1 publication Critical patent/WO2020073695A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters

Definitions

  • the present application relates to the technical field of display panels, in particular to a TFT substrate, a display panel and a display device.
  • the display device includes a display panel including a thin film transistor and a storage capacitor in each pixel area, where the storage capacitor is used to increase the charge storage amount of the pixel and maintain the pixel potential until the next scan period comes.
  • the inventor of the present application discovered in the long-term research and development that in the existing organic light-emitting display panel, due to the second layer metal used for VDD / Sense wiring, one of the electrode plates of the storage capacitor also uses the second layer metal. Due to the limited space of the layout and the short distance, the DD / Sense trace is easy to be short-circuited with the electrode plate of the storage capacitor, resulting in abnormal bright spots on the display panel.
  • the technical problem mainly solved by the present application is to provide a TFT substrate, a display panel and a display device to reduce the abnormal bright spots of the display panel and improve the display effect.
  • the TFT substrate includes at least a first thin film transistor and a storage capacitor provided on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode layer and a third electrode layer, the first electrode layer, the second electrode layer and the first
  • the three electrode layers are all provided in different layers from the source and drain layers of the first thin film transistor; wherein, the second electrode layer is provided between the first electrode layer and the third electrode layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, wherein the first electrode layer is disposed on the substrate; the buffer layer covers at least the first electrode layer; the second electrode layer is disposed on the buffer layer; the first The insulating layer covers at least the second electrode layer; the third electrode layer is disposed on the first insulating layer; wherein, the third electrode layer is disposed in the same layer as the first gate of the first thin film transistor.
  • the first thin film transistor further includes: a first common electrode line, which is disposed in the same layer as the first electrode layer and is covered by the buffer layer; a first active layer, which is disposed in the same layer as the second electrode layer, the first The active layer is covered by the first insulating layer; the first gate is disposed on the first insulating layer; the second insulating layer covers at least the first gate and the third electrode layer; the source and drain layers include the first source and the first The drain is disposed on the second insulating layer, and the first source and the first drain are connected to the first active layer through the first through hole.
  • the TFT substrate further includes: a passivation layer covering at least the first source electrode and the first drain electrode; a flat layer disposed on the passivation layer; an ITO layer disposed on the flat layer, the ITO layer passing through The two through holes are connected to the first source or the first drain.
  • the TFT substrate further includes: a pixel definition layer covering at least the ITO layer; a pixel cathode layer provided on the pixel definition layer and connected to the ITO layer through the third through hole.
  • the TFT substrate further includes a second thin film transistor.
  • the second thin film transistor includes: a second common electrode line, which is disposed in the same layer as the first common electrode line and is covered by the buffer layer; the second active layer, and the second An active layer is arranged in the same layer and is covered by the first insulating layer; the second gate is arranged between the first insulating layer and the second insulating layer; the second source and the second drain are arranged on the second insulating layer And corresponding to the second active layer, the second source electrode and the second drain electrode are connected to the second active layer through the fourth via hole.
  • the storage capacitor further includes a buffer layer, a first insulating layer, and a second insulating layer, wherein the first electrode layer is disposed on the buffer layer; the first insulating layer covers at least the first electrode layer; the second electrode layer is disposed On the first insulating layer, the second insulating layer covers at least the second electrode layer, and the second electrode layer is provided in the same layer as the first gate of the first thin film transistor; the third electrode layer is provided on the second insulating layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, wherein the first electrode layer is disposed on the substrate; the buffer layer covers at least the first electrode layer; the second electrode layer is disposed on the buffer layer; the first The insulating layer covers at least the second electrode layer; the third electrode layer is disposed on the first insulating layer.
  • the display panel includes a TFT substrate including at least a first thin film transistor and a storage capacitor provided on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode layer, and a A three-electrode layer, the first electrode layer, the second electrode layer, and the third electrode layer are all provided in different layers from the source-drain layer of the first thin film transistor; wherein, the second electrode layer is provided Between the first electrode layer and the third electrode layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, the first electrode layer is disposed on the substrate, the buffer layer covers at least the first electrode layer, and the second An electrode layer is provided on the buffer layer; the first insulating layer covers at least the second electrode layer; the third electrode layer is provided on the first insulating layer; wherein, the third electrode layer is The first gate of the first thin film transistor is arranged in the same layer.
  • the first thin film transistor further includes: a first common electrode line, which is disposed in the same layer as the first electrode layer and is covered by the buffer layer; a first active layer, and the second The electrode layers are arranged in the same layer, the first active layer is covered by the first insulating layer; the first gate is arranged on the first insulating layer; the second insulating layer covers at least the first gate And the third electrode layer; and the source-drain layer includes a first source electrode and a first drain electrode, which are disposed on the second insulating layer, and the first source electrode and the first drain electrode pass through The first through hole is connected to the first active layer.
  • the TFT substrate further includes: a passivation layer covering at least the first source electrode and the first drain electrode; a flat layer provided on the passivation layer; an ITO layer provided on the On the flat layer, the ITO layer is connected to the first source electrode or the first drain electrode through a second through hole.
  • the TFT substrate further includes: a pixel definition layer covering at least the ITO layer; a pixel cathode layer provided on the pixel definition layer and connected to the ITO layer through a third through hole.
  • the TFT substrate further includes a second thin film transistor
  • the second thin film transistor includes: a second common electrode line, which is disposed in the same layer as the first common electrode line and is covered by the buffer layer ;
  • the second active layer is provided in the same layer as the first active layer and is covered by the first insulating layer;
  • the second gate is provided between the first insulating layer and the second insulating layer;
  • the second source electrode and the second drain electrode are disposed on the second insulating layer and corresponding to the second active layer, and the second source electrode and the second drain electrode pass through the fourth through hole It is connected to the second active layer.
  • the storage capacitor further includes a buffer layer, a first insulating layer, and a second insulating layer, wherein the first electrode layer is disposed on the buffer layer; the first insulating layer covers at least The first electrode layer; the second electrode layer is disposed on the first insulating layer, the second insulating layer covers at least the second electrode layer, and the second electrode layer and the first film
  • the first gate of the transistor is arranged in the same layer; the third electrode layer is arranged on the second insulating layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, wherein the first electrode layer is disposed on the substrate; the buffer layer covers at least the first electrode layer, the A second electrode layer is provided on the buffer layer, the first insulating layer covers at least the second electrode layer; the third electrode layer is provided on the first insulating layer.
  • a display device includes a display panel including a TFT substrate, the TFT substrate includes at least a first thin film transistor and a storage capacitor disposed on the substrate, wherein the storage capacitor includes: a first An electrode layer, a second electrode layer and a third electrode layer, the first electrode layer, the second electrode layer and the third electrode layer are all provided in different layers from the source and drain layers of the first thin film transistor; Wherein, the second electrode layer is disposed between the first electrode layer and the third electrode layer.
  • the storage capacitor further includes a buffer layer and a first insulating layer, the first electrode layer is disposed on the substrate, the buffer layer covers at least the first electrode layer, and the second An electrode layer is provided on the buffer layer; the first insulating layer covers at least the second electrode layer; the third electrode layer is provided on the first insulating layer; wherein, the third electrode layer is The first gate of the first thin film transistor is arranged in the same layer.
  • the first thin film transistor further includes: a first common electrode line, which is disposed in the same layer as the first electrode layer and is covered by the buffer layer; a first active layer, and the second The electrode layers are arranged in the same layer, the first active layer is covered by the first insulating layer; the first gate is arranged on the first insulating layer; the second insulating layer covers at least the first gate And the third electrode layer; and the source-drain layer includes a first source electrode and a first drain electrode, which are disposed on the second insulating layer, and the first source electrode and the first drain electrode pass through The first through hole is connected to the first active layer.
  • the TFT substrate further includes: a passivation layer covering at least the first source electrode and the first drain electrode; a flat layer provided on the passivation layer; an ITO layer provided on the On the flat layer, the ITO layer is connected to the first source electrode or the first drain electrode through a second through hole.
  • the TFT substrate of the embodiments of the present application includes at least a first thin film transistor and a storage capacitor provided on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode Layer and third electrode layer, the first electrode layer, the second electrode layer and the third electrode layer are all provided in a different layer from the source and drain layers of the first thin film transistor; wherein, the second electrode layer is provided on the first electrode layer and the first Between three electrode layers.
  • the electrode layer of the storage capacitor and the source and drain layers of the first thin film transistor are provided in different layers. Therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (that is, the source or drain of the first thin film transistor Pole) separate, can avoid short circuit between the two, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • FIG. 1 is a schematic structural view of a TFT substrate
  • FIG. 2 is a schematic diagram of the pixel structure of the TFT substrate of the embodiment of FIG. 1;
  • FIG. 3 is an equivalent circuit diagram of the pixel structure of the embodiment of FIG. 2;
  • FIG. 4 is a schematic structural diagram of a first embodiment of a TFT substrate of the present application.
  • FIG. 5 is a schematic flow chart of the method for manufacturing a TFT substrate of the embodiment of FIG. 4;
  • FIG. 6 is another schematic flow chart of the method for manufacturing the TFT substrate of the embodiment of FIG. 4;
  • FIG. 7 is a schematic structural diagram of a second embodiment of a TFT substrate of the present application.
  • FIG. 8 is a schematic structural diagram of a third embodiment of a TFT substrate of the present application.
  • FIG. 9 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • FIG. 10 is a schematic structural diagram of an embodiment of a display device of the present application.
  • FIG. 1 is a schematic diagram of a TFT substrate
  • FIG. 2 is a schematic diagram of a pixel structure of the TFT substrate of the embodiment of FIG. 1
  • FIG. 3 is an equivalent circuit diagram of the pixel structure of the embodiment of FIG.
  • the VDD / Sense trace (normally high potential) 101 and the anode 102 of the pixel both use the second metal layer M2 trace, and at least the VDD / Sense trace 101 and one sub-pixel in the pixel are arranged next to each other.
  • the second metal layer M2 is likely to remain. Therefore, the VDD / Sense trace 101 and the anode 102 of the sub-pixel are short-circuited, thereby causing abnormal bright spots on the display panel.
  • FIG. 4 is a schematic structural diagram of a first embodiment of the TFT substrate of the present application.
  • the TFT substrate 401 includes at least a first thin film transistor 402 and a storage capacitor 403 disposed on the substrate 406, wherein the storage capacitor 403 includes: a first electrode layer 414, a second electrode layer 415, and a third electrode layer 416, An electrode layer 414, a second electrode layer 415, and a third electrode layer 416 are all disposed in different layers from the source / drain layer S1 / D1 of the first thin film transistor 402; wherein, the second electrode layer 415 is disposed on the first electrode layer 414 and Between the third electrode layers 416.
  • the first electrode layer 414, the second electrode layer 415, and the third electrode layer 416 are all arranged in different layers from the source / drain layer S1 / D1 of the first thin film transistor 402.
  • the second electrode layer 415 and the third electrode layer 416 are disposed on different layers from the source-drain layer S1 / D1 of the first thin film transistor 402.
  • the electrode layer of the storage capacitor and the source-drain layer of the first thin film transistor in this embodiment are provided in different layers, therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (ie, the first thin film transistor The source or the drain) are separated, which can avoid the short circuit between the two, thereby reducing the abnormal bright spots of the display panel and improving the display effect.
  • the storage capacitor 403 of this embodiment further includes a buffer layer 404 and a first insulating layer 405; wherein, the first electrode layer 414 is disposed on the substrate 406, the buffer layer 404 at least covers the first electrode layer 414, and the second electrode The layer 415 is disposed on the buffer layer 404, the first insulating layer 405 covers at least the second electrode layer 415, and the third electrode layer 416 is disposed on the first insulating layer 405, wherein the third electrode layer 416 and the first thin film transistor 402 A gate G1 is provided in the same layer.
  • the first electrode layer 414 is the common electrode line LS1
  • the second electrode layer 415 is the active layer AOS1
  • the third electrode layer 416 is the pixel anode layer M1.
  • the common electrode line LS1, the active layer AOS1 and the pixel anode layer M1 are correspondingly disposed, that is, the active layer AOS1 is located directly above the common electrode line LS1, and the pixel anode layer M1 is located directly above the active layer AOS1.
  • the electrode of the storage capacitor 403 in this embodiment has a three-layer structure, that is, the common electrode line LS1, the active layer AOS1, and the pixel anode layer M1, and none of these three electrode layers are connected to the first thin film transistor.
  • the source and drain layers S1 / D1 of 402 are provided in the same layer, therefore, the electrode layer of the storage capacitor 403 can be separated from the VDD / Sense trace (that is, the source / drain layer S1 / D1 of the first thin film transistor 402), which can avoid storage
  • the capacitor 403 is short-circuited with the VDD / Sense trace.
  • the first thin film transistor 402 of this embodiment further includes: a first common electrode line LS2, a first active layer AOS2, a second insulating layer 407, and a first source electrode S1 and a first drain electrode D1; wherein, the first A common electrode line LS2 is disposed in the same layer as the first electrode layer 414 (that is, the common electrode line LS1) and is covered by the buffer layer 404; the first active layer AOS2 and the second electrode layer 415 (that is, the active layer AOS1) are disposed in the same layer, And covered by the first insulating layer 405; the first gate G1 is disposed on the first insulating layer 405; the second insulating layer 407 at least covers the first gate G1 and the third electrode layer 416 (ie, the pixel anode layer M1); A source S1 and a first drain D1 are disposed on the second insulating layer 407, and the first source S1 and the first drain D1 are connected to the first active layer AOS2 through a
  • the first active layer AOS2 is a conductive channel between the first source S1 and the first drain D1.
  • the first common electrode line LS2, the first active layer AOS2 and the first gate G1 are correspondingly disposed, that is, the first active layer AOS2 is located directly above the first common electrode line LS2, and the first gate G1 is located in the first active layer Just above AOS2.
  • the TFT substrate 401 in this embodiment further includes: a passivation layer 408, a flat layer 409, and indium tin oxide (ITO, Indium Tin Oxides) layer 410; wherein, the passivation layer 408 covers at least the first source S1 and the first drain D1, the flat layer 409 is provided on the passivation layer 408, the ITO layer 410 is provided on the flat layer 409, and the ITO layer 410 It is connected to the first drain D1 through a second through hole (not marked in the figure).
  • ITO Indium Tin Oxides
  • the ITO layer 410 may also be connected to the first drain through the second through hole.
  • the TFT substrate 401 of this embodiment further includes: a pixel definition layer 411 and a pixel cathode layer 412; wherein, the pixel definition layer 411 at least covers the ITO layer 410, the pixel cathode layer 412 is disposed on the pixel definition layer 411, and passes the The three through holes (not marked in the figure) are connected to the ITO layer 410.
  • the TFT substrate 401 of this embodiment further includes: a second thin film transistor 413, and the second thin film transistor 413 includes: a second common electrode line LS3, a second active layer AOS3, a second gate G2, and a second source S2 And the second drain D2; wherein, the second common electrode line LS3 is arranged in the same layer as the first common electrode line LS2 and is covered by the buffer layer 404, and the second active layer AOS3 is arranged in the same layer as the first active layer AOS2 and is The first insulating layer covers 405, the second gate G2 is disposed between the first insulating layer 405 and the second insulating layer 407, the second source S2 and the second drain D2 are disposed on the second insulating layer 407, the second The source electrode S2 and the second drain electrode D2 are connected to the second active layer AOS3 through a fourth through hole (not shown).
  • the second active layer AOS3 is a conductive channel between the second source S2 and the second drain D2.
  • the second active layer AOS3 of this embodiment is disposed corresponding to the second common electrode line LS3, that is, the second active layer AOS3 is located directly above the second common electrode line LS3; the second gate G2 corresponds to the second active layer AOS3 It is provided that the second gate G2 is provided directly above the second active layer AOS3.
  • T1 is a driving thin film transistor, and T1 may specifically be an oxide thin film transistor; T2 is a switching thin film transistor, and T2 may specifically be a Low Temperature Poly-silicon (LTPS) thin film transistor.
  • LTPS Low Temperature Poly-silicon
  • the control terminal of T2 is connected to the scan line Scan, the first communication terminal of T2 is connected to the control terminal of T1, and the second communication terminal of T2 is connected to the data line Data;
  • the first communication terminal of T1 is connected to VDD Line connection, the second communication terminal of T1 is connected to the positive electrode of OLED, the negative electrode of OLED is grounded;
  • the first end of capacitor Cst is connected to the control terminal of T1, the second end of capacitor Cst is connected to the second terminal of T3, and the control of T3
  • the terminal is connected to the RD trace, and the first end of T3 is connected to the Sense trace.
  • T3 in FIG. 3 is not shown in FIGS. 1, 2 and 4 of this application.
  • the number of thin film transistors provided on the TFT substrate is not limited.
  • FIG. 5 is a schematic flowchart of a method for manufacturing a TFT substrate according to the embodiment of FIG. Specifically, the method of this embodiment includes the following steps:
  • Step S501 Prepare the substrate.
  • the substrate may be a glass substrate or a resin substrate, etc., which is not specifically limited.
  • Step S502 forming a common electrode line on the substrate.
  • Step S503 forming a buffer layer covering at least the common electrode line.
  • Step S504 forming an active layer on the buffer layer.
  • the active layer is provided corresponding to the common electrode line.
  • Step S505 forming a first insulating layer covering at least the active layer.
  • Step S506 forming a pixel anode layer and a first gate on the first insulating layer, wherein the pixel anode layer and the first gate are arranged in the same layer.
  • the pixel anode layer is provided corresponding to the active layer.
  • the method of this embodiment can complete the production of the storage capacitor in the TFT substrate.
  • the common electrode line, the active layer, and the pixel anode layer constitute a three-layer electrode structure of the storage capacitor.
  • the three electrode layers of the storage capacitor in this embodiment are not provided in the same layer as the source / drain layer S1 / D1 of the first thin film transistor, therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (ie the first thin film
  • the source / drain layers of the transistors (S1 / D1) are separated to avoid short-circuiting of storage capacitors and VDD / Sense traces, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • the present application further proposes a method for manufacturing a TFT substrate according to another embodiment. As shown in FIG. 6, the method of this embodiment is used to manufacture the TFT substrate shown in FIG.
  • the method of this embodiment includes the following steps:
  • Step S601 Prepare the substrate 406.
  • Step S602 forming a common electrode line LS1, a first common electrode line LS2, and a second common electrode line LS3 on the substrate 406.
  • Step S603 forming a buffer layer 404 covering at least the common electrode line LS1, the first common electrode line LS2, and the second common electrode line LS3.
  • Step S604 forming an active layer AOS1, a first active layer AOS2, and a second active layer AOS3 on the buffer layer 404.
  • the position of the active layer AOS1, the first active layer AOS2 and the second active layer AOS3 can be preset on the buffer layer 404 by wet etching to form a pattern to facilitate the active layer AOS1, the first active layer AOS2 and the second active layer AOS3 positioning.
  • the active layer AOS1 corresponds to the common electrode line LS1
  • the first active layer AOS2 corresponds to the first common electrode line LS2
  • the second active layer AOS3 corresponds to the second common electrode line LS3.
  • Step S605 forming a first insulating layer 405 covering at least the active layer AOS1, the first active layer AOS2, and the second active layer AOS3.
  • Step S606 forming a pixel anode layer M1, a first gate G1 and a second gate G2 on the first insulating layer 405, wherein the pixel anode layer M1 and the first gate G2 are disposed in the same layer.
  • the pixel anode layer M1 corresponds to the active layer AOS1
  • the first gate G1 corresponds to the first active layer AOS2
  • the second gate G2 corresponds to the second active layer AOS3.
  • Step S607 forming a second insulating layer 407 covering at least the pixel anode layer M1, the first gate G1, and the second gate G2.
  • Step S608 forming a first source S1, a first drain D1, a second source S2 and a second drain D2 on the second insulating layer 407.
  • Step S609 forming a plurality of first through holes penetrating the first insulating layer 405 and the second insulating layer 407, and connecting the first source S1 and the first drain D1 to the first active layer AOS2 through the first through holes, The second source electrode S2 and the second drain electrode D2 are connected to the second active layer AOS3 through the first via hole.
  • the method of this implementation further includes:
  • Step S610 forming a passivation layer 408 covering at least the first source S1, the first drain D1, the second source S2 and the second drain D2; forming a flat layer 409 on the passivation layer 408; An ITO layer 410 is formed thereon; a second through hole penetrating the passivation layer 408 and the flat layer 409 is formed, and the ITO layer 410 is connected to the first drain D1 through the second through hole.
  • the method of this implementation further includes:
  • Step S611 forming a pixel definition layer 411 covering at least the ITO layer 410; forming a pixel cathode layer 412 on the pixel definition layer 411; forming a third through hole in the pixel definition layer 411, passing the pixel cathode layer 412 through the third through hole Layer 410 is connected.
  • This application further proposes the TFT substrate of the second embodiment.
  • the difference between the TFT substrate 701 of this embodiment and the TFT substrate 401 of the above embodiment is that the first electrode layer 703 of the storage capacitor 702 of this embodiment is provided On the buffer layer 704; the first insulating layer 705 covers at least the first electrode layer 703; the second electrode layer 706 is disposed on the first insulating layer 705, the second insulating layer 707 covers at least the second electrode layer 706, and the second electrode layer 706 is provided in the same layer as the first gate G1 of the first thin film transistor 708; the third electrode layer 709 is provided on the second insulating layer 707.
  • the source / drain layer S1 / D1 of the first thin film transistor 708 of this embodiment is provided on the second insulating layer 707, in order to make the third electrode layer 709 and the source / drain layer S1 / D1 not in the same layer, the third The electrode layer 709 is provided on the passivation layer 710.
  • the first electrode layer 703 is an active layer AOS1
  • the second electrode layer 415 is a pixel anode layer M1
  • the third electrode layer 416 is an ITO layer.
  • the active layer AOS1, the pixel anode layer M1 and the ITO layer are provided correspondingly, that is, the pixel anode layer M1 is located directly above the active layer AOS1, and the ITO layer is located directly above the pixel anode layer M1.
  • none of the three electrode layers of the storage capacitor 702 of this embodiment are provided in the same layer as the source and drain layers S1 / D1 of the first thin film transistor 708, therefore, the electrode layer of the storage capacitor 702 can be Separated from the VDD / Sense trace (that is, the source / drain layer S1 / D1 of the first thin film transistor 708), the storage capacitor 702 can be prevented from being short-circuited with the VDD / Sense trace, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • the manufacturing method of the TFT substrate 701 in this embodiment is similar to the above embodiment, and will not be repeated here.
  • the present application further proposes a TFT substrate of a third embodiment.
  • the difference between the TFT substrate 801 of this embodiment and the TFT substrate 401 of the above embodiment is that the first electrode layer 803 of the storage capacitor 802 of this embodiment is provided On the substrate 804; the buffer layer 805 covers at least the first electrode layer 803; the second electrode layer 806 is provided on the buffer layer 805; the first insulating layer 807 covers at least the second electrode layer 806; the third electrode layer 808 is provided on the first insulation On layer 807.
  • the first insulating layer 807 of the present embodiment is equivalent to the second insulating layer of the above-mentioned embodiment.
  • the first electrode layer 803 is a common electrode line LS1
  • the second electrode layer 806 is an active layer AOS1
  • the third electrode layer 808 is an ITO layer.
  • the common electrode line LS1, the active layer AOS1 and the ITO layer are arranged correspondingly, that is, the active layer AOS1 is located directly above the common electrode line LS1, and the ITO layer is located directly above the active layer AOS1.
  • none of the three electrode layers of the storage capacitor 802 of this embodiment are provided in the same layer as the source / drain layer S1 / D1 of the first thin film transistor 809, therefore, the electrode layer of the storage capacitor 802 can be Separated from the VDD / Sense trace (that is, the source / drain layer S1 / D1 of the first thin film transistor 809), the storage capacitor 802 can be prevented from short-circuiting with the VDD / Sense trace, which can reduce the abnormal bright spots of the display panel and improve the display effect.
  • the manufacturing method of the TFT substrate 801 in this embodiment is similar to the above embodiment, and will not be repeated here.
  • FIG. 9 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • the display panel 901 of this embodiment includes a color filter substrate 902 and a TFT substrate 903, wherein the TFT substrate 903 is the TFT substrate of the foregoing embodiment, which is not described here.
  • the pixel anode layer of the storage capacitor and the first gate of the first thin film transistor in this embodiment can separate the pixel anode layer from the VDD trace (that is, the source or drain of the first thin film transistor), The short circuit of the pixel anode layer and the VDD trace can be avoided, thereby reducing the abnormal bright spots of the display panel and improving the display effect.
  • FIG. 10 is a schematic structural diagram of an embodiment of the display device of the present application.
  • the display device 1001 of this embodiment includes at least a display panel 1002.
  • the TFT substrate in the embodiment of the present application includes at least a first thin film transistor and a storage capacitor disposed on the substrate, wherein the storage capacitor includes: a first electrode layer, a second electrode layer, and a third electrode layer, the first The electrode layer, the second electrode layer, and the third electrode layer are all disposed in a different layer from the source and drain layers of the first thin film transistor; wherein, the second electrode layer is disposed between the first electrode layer and the third electrode layer.
  • the electrode layer of the storage capacitor and the source and drain layers of the first thin film transistor are provided in different layers. Therefore, the electrode layer of the storage capacitor and the VDD / Sense trace (that is, the source or drain of the first thin film transistor Pole) separate, can avoid short circuit between the two, which can reduce the abnormal bright spots of the display panel and improve the display effect.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

La présente invention concerne un substrat de TFT, un panneau d'affichage et un appareil d'affichage. Le substrat de TFT comprend au moins un premier transistor à couches minces et un condensateur de stockage agencés sur le substrat. Le condensateur de stockage comprend : une première couche d'électrode, une deuxieme couche d'électrode et une troisième couche d'électrode, la première couche d'électrode, la deuxième couche d'électrode et la troisième couche d'électrode sont toutes disposées sur une couche différente d'une couche d'électrode de source et de drain du premier transistor à couches minces, et la deuxième couche d'électrode est disposée entre la première couche d'électrode et la troisième couche d'électrode. De cette manière, des points brillants anormaux d'un panneau d'affichage peuvent être réduits, ce qui améliore l'effet d'affichage.
PCT/CN2019/093829 2018-10-12 2019-06-28 Substrat de tft, panneau d'affichage et appareil d'affichage WO2020073695A1 (fr)

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WO2021102997A1 (fr) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 Substrat d'écran et son procédé de fabrication, et dispositif d'écran
EP4012774A4 (fr) * 2020-05-15 2022-10-12 BOE Technology Group Co., Ltd. Panneau d'affichage et appareil électronique
CN113628974B (zh) * 2021-07-27 2023-10-31 深圳市华星光电半导体显示技术有限公司 阵列基板的制备方法和阵列基板

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