WO2020073426A1 - 芯片异常检测电路及芯片异常检测装置 - Google Patents

芯片异常检测电路及芯片异常检测装置 Download PDF

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Publication number
WO2020073426A1
WO2020073426A1 PCT/CN2018/115877 CN2018115877W WO2020073426A1 WO 2020073426 A1 WO2020073426 A1 WO 2020073426A1 CN 2018115877 W CN2018115877 W CN 2018115877W WO 2020073426 A1 WO2020073426 A1 WO 2020073426A1
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Prior art keywords
chip
switch
signal
detection
circuit
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Ceased
Application number
PCT/CN2018/115877
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English (en)
French (fr)
Inventor
黄笑宇
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/487,432 priority Critical patent/US11099233B2/en
Publication of WO2020073426A1 publication Critical patent/WO2020073426A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2632—Circuits therefor for testing diodes
    • G01R31/2633—Circuits therefor for testing diodes for measuring switching properties thereof

Definitions

  • the present application relates to the technical field of test devices, in particular to a chip abnormality detection circuit and a chip abnormality detection device.
  • electrostatic protection diodes are generally installed in chips such as timing controllers or power management chips.
  • chips such as timing controllers or power management chips.
  • a commonly used method is to detect whether the screen display is abnormal, and analyze whether the electrostatic protection diode is abnormal according to the abnormal characteristics. This method is not intuitive to detect the structure; while another method is to detect it by a manual handheld multimeter and other measurement tools. , And this requires a lot of manpower, and the detection efficiency is low.
  • the main purpose of the present application is to propose a chip abnormality detection circuit and a chip abnormality detection device, aiming to solve the automatic detection of the diode characteristic value corresponding to the test electrostatic protection diode.
  • the chip abnormality detection circuit includes:
  • Test power supply set to provide test current to the chip to be tested
  • the connector includes a signal output terminal and a ground terminal, the signal output terminal is set to connect the function pin of the chip to be tested and the cathode of the electrostatic protection diode, and the ground terminal is set to connect the ground pin and the electrostatic protection diode of the chip to be tested Anode
  • a power switch circuit is provided in series between the test power supply and the signal output terminal of the connector.
  • the power switch circuit is configured to output the test current provided by the test power supply to the connector when it is turned on Signal output terminal;
  • the abnormal signal detection circuit is arranged to detect the reverse cut-off characteristic of the electrostatic protection diode of the chip to be tested, and outputs a corresponding detection signal.
  • the chip abnormality detection circuit further includes a picture detection switch circuit, an input terminal of the picture detection switch circuit is set to access a picture detection signal, and an output terminal of the picture detection switch circuit and a signal of the connector The output terminal is connected, and the picture detection switch circuit is configured to output the connected picture detection signal to the signal output terminal of the connector when turned on.
  • the chip abnormality detection circuit further includes a switch control circuit, and the output end of the switch control circuit is respectively connected to the controlled end of the power switch circuit and the controlled end of the picture detection switch circuit;
  • the switch control circuit is configured to output a first level signal and a second level signal with opposite polarities to control the power switch circuit to turn on when receiving the first level signal, and to control the The picture detection switch circuit is turned on when receiving the second level signal.
  • the switch control circuit includes a dip switch configured to output the first level signal or the second level signal when triggered.
  • the picture detection switch circuit includes a first switch tube, an input end of the first switch tube is an input end of the picture detection switch circuit, and an output end of the first switch tube is the picture detection The output end of the switch circuit, the controlled end of the first switch tube is the controlled end of the picture detection switch circuit.
  • the power switch circuit includes a second switch tube, the input terminal of the second switch tube is the input terminal of the power switch circuit, and the output terminal of the second switch tube is the power switch circuit At the output end, the controlled end of the second switch tube is the controlled end of the power switch circuit.
  • the abnormal signal detection circuit includes a light emitting diode, an anode of the light emitting diode is connected to a positive output terminal of the power supply, and a cathode of the light emitting diode is a detection terminal of the abnormal signal detection circuit.
  • the number of the signal output terminals is multiple;
  • the power switch circuit includes multiple power switch branches, and the output ends of the multiple power switch branches are in one-to-one correspondence with the multiple power switch branches;
  • the abnormal signal detection circuit includes a plurality of abnormal signal detection branches, and a detection end of each abnormal signal detection branch is connected to an input end of a power switch branch.
  • the present application also proposes a chip abnormality detection circuit, which is applied to the abnormality detection of a chip provided with an electrostatic protection diode.
  • the chip abnormality detection circuit includes:
  • Test power supply set to provide test current to the chip to be tested
  • the connector includes a ground terminal and a plurality of signal output terminals.
  • the plurality of signal output terminals are configured to connect a plurality of functional pins of the chip to be tested and the anodes of a plurality of electrostatic protection diodes.
  • the ground terminal is configured to connect to the test The ground pin of the chip and the anode of the electrostatic protection diode;
  • the power switch circuit includes a plurality of second switch tubes, and the output ends of the plurality of second switch tubes are correspondingly connected to the plurality of signal output terminals in one-to-one correspondence; each of the second switch tubes is configured to turn on Output the test current provided by the test power supply to the signal output terminal corresponding to the connector;
  • the abnormal signal detection circuit includes a plurality of light-emitting diodes, the anode of each light-emitting diode is connected to the positive output terminal of the power supply, the cathode of the plurality of light-emitting diodes and the input terminals of the plurality of second switch tubes One-to-one connection.
  • the present application also proposes a chip abnormality detection device, including the chip abnormality detection circuit described above;
  • the chip abnormality detection circuit includes: a test power supply configured to provide a test current to the chip to be tested; a connector including a signal output terminal and Ground terminal, the signal output terminal is set to connect the function pin of the chip to be tested and the cathode of the electrostatic protection diode, the ground terminal is set to connect the ground pin of the chip to be tested and the anode of the electrostatic protection diode; power switch circuit, in series It is provided between the test power supply and the signal output terminal of the connector, and the power switch circuit is configured to output the test current provided by the test power supply to the signal output terminal of the connector when it is turned on;
  • the abnormal signal detection circuit the detection end of which is connected to the input end of the power switch circuit, is arranged to detect the reverse cut-off characteristic of the electrostatic protection diode of the chip to be tested, and outputs a corresponding detection signal.
  • a connector is provided, and through the connector, the test power supply, the abnormal signal detection circuit and the power switch circuit are sequentially connected to the cathode of the electrostatic protection diode, and the cathode of the electrostatic protection diode and the anode of the electrostatic protection diode are turned on at the power switch circuit At this time, whether the test current provided by the test power supply forms a current loop through the electrostatic protection diode, the test power supply, the abnormal signal detection circuit and the power switch circuit, detects the reverse cut-off characteristic of the electrostatic protection diode of the chip to be tested, and outputs a corresponding detection signal.
  • the application can realize the automatic detection of the characteristic value of the diode corresponding to the electrostatic protection diode without holding a measuring tool.
  • the test staff can intuitively know the detection result, and the detection efficiency is improved.
  • FIG. 1 is a schematic diagram of functional modules of an embodiment of a chip abnormality detection circuit of the present application
  • FIG. 2 is a circuit schematic diagram of an embodiment of a chip abnormality detection circuit of the present application.
  • FIG. 3 is a schematic structural diagram of another embodiment of a chip abnormality detection circuit of the present application.
  • first”, “second”, etc. are for descriptive purposes only, and cannot be interpreted as indications or hints Its relative importance or implicitly indicates the number of technical features indicated.
  • the features defined with “first” and “second” may include at least one of the features either explicitly or implicitly.
  • the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary people in the art to achieve, when the combination of technical solutions conflicts with each other or cannot be realized, it should be considered that the combination of such technical solutions does not exist , Nor within the scope of protection required by this application.
  • the present application proposes a chip abnormality detection circuit, which is applied to the abnormality detection of a chip provided with an electrostatic protection diode.
  • the chip provided with an electrostatic protection diode may be a timing controller (TCON) suitable for use in a display device to drive the display panel to work IC) or Power Management Integrated Circuit (PMIC) ),
  • TCON timing controller
  • PMIC Power Management Integrated Circuit
  • the integrated chip of the timing controller and power management is generally set on the timing control board, that is, the TCON board.
  • an electrostatic protection (ESD) protection diode is generally provided.
  • the electrostatic protection diode is integrated in the timing controller, the power management integrated chip and other chips provided on the TCON board Internally, it is connected to the chip pins, or a plurality of electrostatic protection diodes can be provided on the TCON board to protect the chip from static electricity.
  • the circuit When the circuit is working normally, it is in the cut-off state (high impedance state), which does not affect the normal operation of the circuit.
  • the electrostatic protection diode quickly changes from a high-impedance state to a low-impedance state, providing a low-impedance conduction path for the instantaneous current, and clamping the abnormal high voltage at a safe level In order to protect the protected chip; when the abnormal overvoltage disappears, it returns to the high resistance state and the circuit works normally.
  • the chip abnormal signal detection circuit includes:
  • Test power supply 10 set to provide test current to the chip to be tested
  • the connector 20 includes a signal output terminal and a ground terminal, the signal output terminal is set to connect the functional pin of the chip to be tested and the cathode of the electrostatic protection diode D2, and the ground terminal is set to connect the ground pin and static electricity of the chip to be tested Anode of protection diode D2;
  • a power switch circuit 30 is provided in series between the test power supply 10 and the signal output terminal of the connector 20.
  • the power switch circuit 30 is configured to output the test current provided by the test power supply 10 when turned on A signal output terminal to the connector 20;
  • the abnormal signal detection circuit 40 has a detection terminal connected to the input terminal of the power switch circuit 30, is configured to detect the reverse cut-off characteristic of the electrostatic protection diode D2 of the chip to be tested, and outputs a corresponding detection signal.
  • the test power supply 10 may be a DC power supply for chip operation, such as a 5V or 12V output power supply that drives the timing controller.
  • the test power supply 10 may also use a storage battery, such as a lithium battery, a secondary rechargeable dry battery, or a button battery Wait to achieve.
  • the voltage output by the test power supply 10 is less than the breakdown voltage of the electrostatic protection diode D2, that is, the breakdown voltage.
  • the connector 20 has multiple terminals, and the multiple terminals are respectively connected to the pins of the chip to be tested, such as a timing controller or a power chip, and the number of terminals of the connector 20 is adapted to the pins of the chip.
  • the number of pins is set, here is not limited.
  • the power switch circuit 30 is controlled based on an externally input control signal, such as a switch signal triggered by a user based on a key circuit.
  • an externally input control signal such as a switch signal triggered by a user based on a key circuit.
  • the test power supply 10 is output to the signal output terminal of the connector 20 to realize the electrostatic protection diode D2 Anomaly detection.
  • the abnormal signal detection circuit 40 can be realized by using light emitting diodes D1, buzzers and other signal output components.
  • the light emitting diode D1 can be selected.
  • the light emitting diode D1 is arranged in series between the test power supply 10 and the power switch circuit 30, The anode of the light emitting diode D1 is connected to the positive output end of the test power supply 10, and the cathode is connected to the power switch circuit 30.
  • the output current of the test power supply 10 constitutes a current loop, the light-emitting diode D1 lights up, otherwise it goes out.
  • the positive output terminal of the test power supply 10 is connected to the input terminal of the power switch circuit 30, and the output terminal of the power switch circuit 30 is connected to the cathode of the electrostatic protection diode D2 via the signal output terminal of the connector 20;
  • the negative output terminal of 10 is connected to the anode of the electrostatic protection diode D2 through the ground terminal of the connector 20, that is, when the power switch circuit 30 is turned on, the current output by the positive output terminal of the test power supply 10 passes through the power switch circuit 30 and the connector
  • the signal output terminal of 20 is output to the cathode of the electrostatic protection diode D2.
  • the ESD protection diode D2 works normally, that is, there is no abnormality, because the test current is less than its breakdown voltage, and is in the cut-off state, at this time, the current output by the test power supply 10 is reversely cut off by the ESD protection diode D2, and the negative pole of the test power supply 10
  • the input terminal is connected to the anode of the electrostatic protection diode D2 through the ground terminal of the connector 20.
  • a current loop cannot be formed between the test power supply 10 and the electrostatic protection diode D2.
  • the light-emitting diode D1 in the abnormal signal detection circuit 40 does not work.
  • the electrostatic protection diode D2 is normal.
  • the current output by the test power supply 10 returns to the negative input terminal of the test power supply 10 through the electrostatic protection diode D2 and the ground terminal of the connector 20.
  • a current loop is formed between the test power supply 10 and the electrostatic protection diode D2.
  • the light-emitting diode D1 in the abnormal signal detection circuit 40 is lit, which indicates that the electrostatic protection diode D2 is abnormal at this time.
  • the connector 20 is provided, and through the connector 20, the test power supply 10, the abnormal signal detection circuit 40 and the power switch circuit 30 are sequentially connected to the cathode of the electrostatic protection diode D2.
  • This application can realize automatic detection of the diode characteristic value corresponding to the electrostatic protection diode D2 without the need of a handheld measurement tool.
  • the test staff can intuitively know the detection result, and the detection efficiency is improved.
  • the chip abnormal signal detection circuit further includes a picture detection switch circuit 50.
  • the input terminal CV-in of the picture detection switch circuit 50 is set to access the picture detection signal.
  • the output end of the picture detection switch circuit 50 is connected to the signal output terminal of the connector 20, and the picture detection switch circuit 50 is configured to output the connected picture detection signal to the connector 20 when turned on Signal output terminal.
  • the input terminal CV-in of the picture detection switch circuit 50 is connected to the drive signal for picture detection of the display device, for example, the input terminal CV-in of the picture detection switch circuit 50 can be connected to the main control board of the display device , To access the power or data signals, control signals, etc. that drive the display panel, which can be set according to the type of test chip.
  • the main control board When the connector 20 is connected to a power management integrated chip, the main control board outputs It is a power supply.
  • the main control board outputs data signals, control signals or timing control signals.
  • the screen detection switch circuit 50 is controlled based on externally input control signals.
  • the switch signal triggered by the circuit, and when it is turned on, outputs a data signal or a control signal to the signal output terminal of the connector 20, so as to realize the abnormal detection of the screen of the display panel.
  • the chip abnormal signal detection circuit further includes a switch control circuit 60, the output terminal of the switch control circuit 60 and the controlled end of the power switch circuit 30 respectively Connected to the controlled end of the picture detection switch circuit 50; the switch control circuit 60 is configured to output a first level signal and a second level signal of opposite polarities to control the power switch circuit 30 Turns on when the first level signal is received, and controls the picture detection switch circuit 50 to turn on when the second level signal is received.
  • the switch control circuit 60 may generate the corresponding first level signal and second level signal according to the user's triggered key instruction.
  • the key instruction may be one or two, when set to one , You can generate a pulse signal according to the key command, the period and duty cycle of the pulse signal can be set according to the test needs. When it is set to two, it can be correspondingly output according to the user's trigger instruction. For example, when the screen abnormality is detected, the first level signal is output, and when the electrostatic protection diode D2 is abnormal, the second level signal is output. Such setting can realize abnormal detection of the screen of the display panel and abnormal detection of the electrostatic protection diode D2 of the chip.
  • the above switch control circuit 60 can be implemented by a switch circuit such as a dial switch (not shown), a single pole double throw switch, a touch screen, etc.
  • a dial switch can be selected, and the dial switch is set to be triggered Output the first level signal or the second level signal according to the received switch trigger instruction.
  • the picture detection switch circuit 50 includes a first switch Q1, the input terminal of the first switch Q1 is the input terminal of the picture detection switch circuit 50 CV-in, the output end of the first switch tube Q1 is the output end of the picture detection switch circuit 50, and the controlled end of the first switch tube Q1 is the controlled end of the picture detection switch circuit 50.
  • the first switch Q1 may be implemented by switches such as transistors, field effect transistors, double gate insulated transistors, etc.
  • an N-type field effect transistor may be used for implementation. The N-type field effect transistor turns on when it receives a high-level first-level signal, turns off when it receives a low-level second-level signal, and outputs a driver for the display panel test when it is on The signal is output to the signal output terminal of the connector 20.
  • the power switch circuit 30 includes a second switch tube Q2.
  • the input terminal of the second switch tube Q2 is the input terminal of the power switch circuit 30.
  • the output terminal of the second switch tube Q2 is the output terminal of the power switch circuit 30, and the controlled terminal of the second switch tube Q2 is the controlled terminal of the power switch circuit 30.
  • the second switching transistor Q2 may be implemented by switches such as transistors, field effect transistors, and double gate insulated transistors.
  • a P-type field effect transistor may be used for implementation. The P-type field effect transistor turns on when it receives a low-level second-level signal, turns off when it receives a high-level first-level signal, and when it is on, it tests the current signal output by the power supply 10 The signal output terminal output to the connector 20.
  • the number of the signal output terminal is multiple;
  • the power switch circuit 30 includes a plurality of power switch branches (labeled 301, 302 ... 30N, respectively), and the output ends of the plurality of power switch branches are in one-to-one correspondence with the plurality of power switch branches;
  • the abnormal signal detection circuit 40 includes a plurality of abnormal signal detection branches (labeled 401 ... 40N, respectively), the detection end of each of the abnormal signal detection branches (not shown) and a power switch branch Input connection.
  • the power switch circuit 30, the abnormal signal detection circuit 40, and the above screen abnormality can all be provided with multiple branches
  • the connector 20 has multiple terminals, and the multiple terminals are respectively connected to the chip to be tested, such as a timing controller or a power supply
  • the pins of the chip are connected in a one-to-one correspondence.
  • the number of terminals of the connector 20 is adapted to the pins of the chip. The specific number can be set according to the number of pins of the chip. It is not limited here.
  • the abnormal signal detection circuit 40 and the power switch circuit 30 is sequentially arranged in series between the positive output terminal of the test power supply 10 and a signal output terminal of the connector 20 to test the diode characteristics of the chip ESD protection diode D2, so as to realize the abnormal test of the ESD protection diode D2.
  • the picture detection switch circuit 50 is provided with a plurality of picture detection switch branches, the corresponding drive signal, control signal or drive power can be input to the input terminal, and when the picture detection switch branches are turned on, the above signals or drives The power is output to each signal output terminal of the connector 20, and thus to the chip to be tested, so as to detect the abnormality of the screen of the display panel.
  • the present application also proposes a chip abnormal signal detection circuit, which is applied to the abnormal detection of a chip provided with an electrostatic protection diode D2.
  • the chip abnormal signal detection circuit includes:
  • Test power supply 10 set to provide test current to the chip to be tested
  • the connector 20 includes a ground terminal and a plurality of signal output terminals.
  • the plurality of signal output terminals are configured to connect a plurality of functional pins of the chip to be tested and the anodes of a plurality of electrostatic protection diodes D2.
  • the ground terminal is configured to connect The ground pin of the chip to be tested and the anode of the electrostatic protection diode D2;
  • the power switch circuit 30 includes a plurality of second switch tubes Q2, and the output ends of the plurality of second switch tubes Q2 are connected in a one-to-one correspondence with the plurality of signal output terminals; each of the second switch tubes Q2 is provided as When turned on, the test current provided by the test power supply 10 is output to the signal output terminal corresponding to the connector 20;
  • the abnormal signal detection circuit 40 includes a plurality of light emitting diodes D1, the anode of each light emitting diode D1 is connected to the positive output end of the power supply, the cathode of the plurality of light emitting diodes D1 and the plurality of second switch tubes The input terminals of Q2 are connected one-to-one.
  • the connector 20 is provided, and through the connector 20, the test power supply 10, the abnormal signal detection circuit 40, and the second switch tube Q2 are connected to the cathode of the electrostatic protection diode D2 in turn, the cathode of the electrostatic protection diode D2, and the electrostatic protection diode D2 Anode, and when the second switch Q2 is turned on, the test current provided by the test power supply 10 through the electrostatic protection diode D2 and the test power supply 10, the light-emitting diode D1 and the second switch Q2 constitute a current loop to detect the chip under test
  • the electrostatic protection diode D2 has a reverse cut-off characteristic and outputs a corresponding detection signal.
  • This application can realize automatic detection of the diode characteristic value corresponding to the electrostatic protection diode D2 without the need of a handheld measurement tool.
  • the tester by placing the light-emitting diode D1 in series in the detection circuit, the tester can intuitively obtain the detection result through the on / off state of the light-emitting diode D1, and the detection efficiency is improved.
  • the present application can realize batch testing of the electrostatic protection diode D2 of the chip to be tested through multiple detection loops.
  • the present application also provides a chip abnormality detection device, including the chip abnormality detection circuit as described above.
  • a chip abnormality detection circuit including the chip abnormality detection circuit as described above.
  • the chip abnormality detection circuit please refer to the above embodiments, which will not be repeated here; it can be understood that, because the above chip abnormality detection circuit is used in the chip abnormality detection device of the present application, the chip abnormality detection device of the present application.
  • the embodiment includes all the technical solutions of all the above embodiments of the chip abnormality detection circuit, and the technical effects achieved are also the same, which will not be repeated here.

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  • Engineering & Computer Science (AREA)
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Abstract

一种芯片异常检测电路及芯片异常检测装置，该电路包括异常信号检测电路（40），设置为检测待测芯片的静电防护二极管（D2）的反向截止特性，并输出相应的检测信号。

Description

芯片异常检测电路及芯片异常检测装置
技术领域
本申请涉及测试装置技术领域，特别涉及一种芯片异常检测电路及芯片异常检测装置。
背景技术
在显示驱动架构中，一般会在时序控制器或者电源管理芯片等芯片中设置静电防护二极管，当有外部环境异常使得静电防护二极管出现异常时，将导致芯片静电防护失效，因此通常需要对静电防护二极管进行检测。
目前，常用的一种方法是通过检测画面显示是否异常，并根据异常特性来分析静电防护二极管是否异常，这种方式检测结构不直观；而另外一种方法则是通过人工手持万用表等测量工具检测，而这又需要消耗大量的人力，且检测效率低。
申请内容
本申请的主要目的是提出一种芯片异常检测电路及芯片异常检测装置，旨在解决实现测试静电防护二极管对应的二极体特性值的自动检测。
为实现上述目的，本申请提出一种芯片异常检测电路，应用于设置有静电防护二极管的芯片的异常检测，所述芯片异常检测电路包括：
测试电源，设置为给待测芯片提供测试电流；
连接器，包括信号输出端子及接地端子，所述信号输出端子设置为连接待测芯片的功能引脚及静电防护二极管的阴极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管的阳极；
电源开关电路，串联设置于所述测试电源与所述连接器的信号输出端子之间，所述电源开关电路，设置为在开启时，将所述测试电源提供的测试电流输出至所述连接器的信号输出端子；
异常信号检测电路，其检测端与所述电源开关电路的输入端连接，设置为检测待测芯片的静电防护二极管的反向截止特性，并输出相应的检测信号。
可选地，所述芯片异常检测电路还包括画面检测开关电路，所述画面检测开关电路的输入端设置为接入画面检测信号，所述画面检测开关电路的输出端与所述连接器的信号输出端子连接，所述画面检测开关电路，设置为在开启时，将接入的所述画面检测信号输出所述连接器的信号输出端子。
可选地，所述芯片异常检测电路还包括有开关控制电路，所述开关控制电路的输出端分别与所述电源开关电路的受控端及所述画面检测开关电路的受控端连接；所述开关控制电路，设置为输出极性互为相反的第一电平信号和第二电平信号，以控制所述电源开关电路在接收到所述第一电平信号时开启，以及控制所述画面检测开关电路在接收到所述第二电平信号时开启。
可选地，所述开关控制电路包括拨码开关，所述拨码开关设置为在被触发时输出所述第一电平信号或所述第二电平信号。
可选地，所述画面检测开关电路包括第一开关管，所述第一开关管的输入端为所述画面检测开关电路的输入端，所述第一开关管的输出端为所述画面检测开关电路的输出端，所述第一开关管的受控端为画面检测开关电路的受控端。
可选地，所述电源开关电路包括第二开关管，所述第二开关管的输入端为所述电源开关电路的输入端，所述第二开关管的输出端为所述电源开关电路的输出端，所述第二开关管的受控端为所述电源开关电路的受控端。
可选地，所述异常信号检测电路包括发光二极管，所述发光二极管的阳极与所述供电电源的正极输出端连接，所述发光二极管的阴极为所述异常信号检测电路的检测端。
可选地，所述信号输出端子的数量为多个；
所述电源开关电路包括多个电源开关支路，多个所述电源开关支路的输出端与多个所述电源开关支路一一对应连接；
所述异常信号检测电路包括多个异常信号检测支路，每一所述异常信号检测支路的检测端与一所述电源开关支路的输入端连接。
本申请还提出一种芯片异常检测电路，应用于设置有静电防护二极管的芯片的异常检测，所述芯片异常检测电路包括：
测试电源，设置为给待测芯片提供测试电流；
连接器，包括接地端子及多个信号输出端子，多个所述信号输出端子设置为连接待测芯片的多个功能引脚及多个静电防护二极管的阳极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管的阳极；
电源开关电路，包括多个第二开关管，多个所述第二开关管的输出端与多个所述信号输出端子一一对应连接；各所述第二开关管，设置为在开启时，将所述测试电源提供的测试电流输出至所述连接器对应的信号输出端子；
异常信号检测电路，包括多个发光二极管，各所述发光二极管的阳极与所述供电电源的正极输出端连接，多个所述发光二极管的阴极与多个所述第二开关管的输入端一一对应连接。
本申请还提出一种芯片异常检测装置，包括如上所述的芯片异常检测电路；所述芯片异常检测电路包括：测试电源，设置为给待测芯片提供测试电流；连接器，包括信号输出端子及接地端子，所述信号输出端子设置为连接待测芯片的功能引脚及静电防护二极管的阴极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管的阳极；电源开关电路，串联设置于所述测试电源与所述连接器的信号输出端子之间，所述电源开关电路，设置为在开启时，将所述测试电源提供的测试电流输出至所述连接器的信号输出端子；异常信号检测电路，其检测端与所述电源开关电路的输入端连接，设置为检测待测芯片的静电防护二极管的反向截止特性，并输出相应的检测信号。
本申请通过设置连接器，并通过连接器，使得测试电源、异常信号检测电路及电源开关电路依次静电防护二极管的阴极连接，静电防护二极管的阴极、静电防护二极管的阳极，并在电源开关电路开启时，测试电源提供的测试电流经静电防护二极管与测试电源、异常信号检测电路及电源开关电路是否构成电流回路，检测待测芯片的静电防护二极管反向截止特性，并输出相应的检测信号。本申请无需手持测量工具，即可实现测试静电防护二极管对应的二极体特性值的自动检测。此外，本申请通过将异常信号检测电路串联设置于检测回路中，可以使测试工作人员直观的获知检测结果，提高了检测效率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请芯片异常检测电路一实施例的功能模块示意图；
图2为本申请芯片异常检测电路一实施例的电路示意图；
图3为本申请芯片异常检测电路另一实施例的结构示意图。
附图标号说明：
标号 名称 标号 名称
10 测试电源 60 开关控制电路
20 连接器 Q1 第一开关管
30 电源开关电路 Q2 第二开关管
40 异常信号检测电路 D1 发光二极管
50 画面检测开关电路 D2 静电防护二极管
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种芯片异常检测电路，应用于设置有静电防护二极管的芯片的异常检测。该设置有静电防护二极管的芯片可以是适用于显示装置中，驱动显示面板工作的时序控制器（TCON IC）或者电源管理集成芯片（Power Management Integrated Circuit，PMIC ），时序控制器与电源管理集成芯片一般设置在时序控制板，也即TCON板上。
在生产的过程中，大多需要对显示面板进行画面异常检测，在检测的过程中，可以输出数据信号、控制信号及其他驱动显示面板工作的驱动信号至时序控制器，以供时序控制器根据接收到的上述信号产生对应的时序控制信号，进而驱动显示面板工作；或者输出交流电源/直流电源至电源管理集成芯片，以使电源管理集成芯片转换成对应的驱动电压，从而驱动显示面板工作。
为了防止被外部接入的静电击伤时序控制器或者电源管理集成芯片，一般设置静电（ESD）防护二极管，该静电防护二极管集成于时序控制器、电源管理集成芯片等设置于TCON板上的芯片内部，并与芯片引脚连接，或者还可以在TCON板上，设置多个静电防护二极管，以对芯片静电防护。当电路正常工作时，它处于截止状态（高阻态），不影响线路正常工作。例如，当电路出现异常过压并达到其击穿电压时，静电防护二极管迅速由高阻态变为低阻态，给瞬间电流提供低阻抗导通路径，同时把异常高压箝制在一个安全水平之内，从而保护被保护芯片；当异常过压消失，其恢复至高阻态，电路正常工作。
　当有外部环境异常使得静电防护二极管出现异常时，将导致芯片静电防护失效，因此通常需要对静电防护二极管进行检测。目前，常用的一种方法是通过检测画面显示是否异常，并根据异常特性来分析静电防护二极管是否异常，这种方式检测结构不直观，需要工作人员根据经验或者大量的数据分析才能获知；而另外一种方法则是通过万用表量来测试静电防护二极管对应的二极体特性值，而这又需要消耗大量的人力，且检测效率低。
为了解决上述问题，参照图1至图3，在本申请一实施例中，该芯片异常信号检测电路包括：
测试电源10，设置为给待测芯片提供测试电流；
连接器20，包括信号输出端子及接地端子，所述信号输出端子设置为连接待测芯片的功能引脚及静电防护二极管D2的阴极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管D2的阳极；
电源开关电路30，串联设置于所述测试电源10与所述连接器20的信号输出端子之间，所述电源开关电路30，设置为在开启时，将所述测试电源10提供的测试电流输出至所述连接器20的信号输出端子；
异常信号检测电路40，其检测端与所述电源开关电路30的输入端连接，设置为检测待测芯片的静电防护二极管D2的反向截止特性，并输出相应的检测信号。
本实施例中，测试电源10可以是供芯片工作的直流电源，例如驱动时序控制器工作的5V或者12V的输出电源，测试电源10还可以采用蓄电池，例如锂电池、二次充电干电池、纽扣电池等来实现。测试电源10输出的电压小于静电防护二极管D2的被击穿时的电压，也即小于其击穿电压。
连接器20具有多个端子，多个端子分别与待测芯片，例如时序控制器或者电源芯片的各引脚一一对应连接，连接器20的端子数量与芯片引脚适配，具体可以根据芯片的引脚数量进行设定，此处不做限定。
电源开关电路30基于外部输入的控制信号控制，例如用户基于按键电路触发的开关信号，电源开关电路30在开启时，将测试电源10输出至连接器20的信号输出端子，以实现静电防护二极管D2的异常检测。
异常信号检测电路40可以采用发光二极管D1、蜂鸣器等信号输出元件来实现，本实施例可选为发光二极管D1，发光二极管D1串联设置于测试电源10与电源开关电路30之间，也即发光二极管D1的阳极与测试电源10的正极输出端连接，阴极与电源开关电路30连接。在测试电源10输出电流构成电流回路时，发光二极管D1点亮，反之则熄灭。
在具体的实施例中，测试电源10的正极输出端与电源开关电路30的输入端连接，电源开关电路30的输出端经连接器20的信号输出端子与静电防护二极管D2的阴极连接；测试电源10的负极输出端则经连接器20的接地端子与静电防护二极管D2的阳极连接，也即在电源开关电路30开启时，测试电源10的正极输出端输出的电流经电源开关电路30、连接器20的信号输出端输出至静电防护二极管D2的阴极。若静电防护二极管D2正常工作，也即未出现异常，由于测试电流小于其击穿电压，而处于截止状态，此时测试电源10输出的电流被静电防护二极管D2反向截止，测试电源10的负极输入端经连接器20的接地端子与静电防护二极管D2的阳极连接，测试电源10与静电防护二极管D2之间无法构成电流回路，此时异常信号检测电路40中的发光二极管D1不工作，则表征此时静电防护二极管D2正常。若静电防护二极管D2被击穿而程低阻特性，也即出现异常时，此时测试电源10输出的电流经静电防护二极管D2、连接器20的接地端子回到测试电源10的负极输入端，测试电源10与静电防护二极管D2之间构成电流回路，此时异常信号检测电路40中的发光二极管D1被点亮，则表征此时静电防护二极管D2出现异常。
本申请通过设置连接器20，并通过连接器20，使得测试电源10、异常信号检测电路40及电源开关电路30依次静电防护二极管D2的阴极连接，静电防护二极管D2的阴极、静电防护二极管D2的阳极，并在电源开关电路30开启时，测试电源10提供的测试电流经静电防护二极管D2与测试电源10、异常信号检测电路40及电源开关电路30是否构成电流回路，检测待测芯片的静电防护二极管D2反向截止特性，并输出相应的检测信号。本申请无需手持测量工具，即可实现测试静电防护二极管D2对应的二极体特性值的自动检测。此外，本申请通过将异常信号检测电路40串联设置于检测回路中，可以使测试工作人员直观的获知检测结果，提高了检测效率。
参照图1至图3，在一可选实施例中，芯片异常信号检测电路还包括画面检测开关电路50，所述画面检测开关电路50的输入端CV-in设置为接入画面检测信号，所述画面检测开关电路50的输出端与所述连接器20的信号输出端子连接，所述画面检测开关电路50，设置为在开启时，将接入的所述画面检测信号输出所述连接器20的信号输出端子。
本实施例中，画面检测开关电路50的输入端CV-in接入供显示装置的画面检测用的驱动信号，例如画面检测开关电路50的输入端CV-in可以与显示装置的主控板连接，以接入驱动显示面板工作的电源或者数据信号、控制信号等，其具体可以根据测试芯片的类型设定，例如在连接器20接入的为电源管理集成芯片时，主控板输出的则为电源，在连接器20接入的为时序控制器时，主控板输出的则为数据信号、控制信号或者时序控制信号，画面检测开关电路50基于外部输入的控制信号控制，例如用户基于按键电路触发的开关信号，并在开启时，将数据信号或者控制信号输出至连接器20的信号输出端子，以实现显示面板的画面异常检测。
参照图1至图3，在一可选实施例中，所述芯片异常信号检测电路还包括开关控制电路60，所述开关控制电路60的输出端分别与所述电源开关电路30的受控端及所述画面检测开关电路50的受控端连接；所述开关控制电路60，设置为输出极性互为相反的第一电平信号和第二电平信号，以控制所述电源开关电路30在接收到所述第一电平信号时开启，以及控制所述画面检测开关电路50在接收到所述第二电平信号时开启。
本实施例中，开关控制电路60可以根据用户的触发的按键指令生成对应的第一电平信号和第二电平信号，该按键指令可以是一个，也可以是两个，当设置为一个时，则可以根据该按键指令生成一个脉冲信号，脉冲信号的周期及占空比可以根据测试需要进行设定。当设置为两个时，则可以根据用户触发指令对应输出，例如在进行画面异常检测时，则输出第一电平信号，在进行静电防护二极管D2异常时，则输出第二电平信号。如此设置可以实现对显示面板的画面异常检测，同时对芯片的静电防护二极管D2异常检测。
上述开关控制电路60可以采用拨码开关（图未示出）、单刀双掷开关、触摸屏等开关电路来实现，本实施例可选为拨码开关，所述拨码开关设置为在被触发时根据接收到的开关触发指令输出所述第一电平信号或所述第二电平信号。
参照图1至图3，在一可选实施例中，所述画面检测开关电路50包括第一开关管Q1，所述第一开关管Q1的输入端为所述画面检测开关电路50的输入端CV-in，所述第一开关管Q1的输出端为所述画面检测开关电路50的输出端，所述第一开关管Q1的受控端为画面检测开关电路50的受控端。
本实施例中，第一开关管Q1可以是三极管、场效应管、双栅绝缘晶体管等开关来实现，本实施例可选为N型场效应管来实现。N型场效应管在接收到高电平的第一电平信号时导通，在接收到低电平的第二电平信号时截止，并在导通时，输出供显示面板测试用的驱动信号至连接器20的信号输出端子。
参照图1至图3，在一可选实施例中，所述电源开关电路30包括第二开关管Q2，所述第二开关管Q2的输入端为所述电源开关电路30的输入端，所述第二开关管Q2的输出端为所述电源开关电路30的输出端，所述第二开关管Q2的受控端为所述电源开关电路30的受控端。
本实施例中，第二开关管Q2可以是三极管、场效应管、双栅绝缘晶体管等开关来实现，本实施例可选为P型场效应管来实现。P型场效应管在接收到低电平的第二电平信号时导通，在接收到高电平的第一电平信号时截止，并在导通时，将测试电源10输出的电流信号输出至连接器20的信号输出端子。
参照图1至图3，在一可选实施例中，所述信号输出端子的数量为多个；
所述电源开关电路30包括多个电源开关支路（分别标记为301、302…30N），多个所述电源开关支路的输出端与多个所述电源开关支路一一对应连接；
所述异常信号检测电路40包括多个异常信号检测支路（分别标记为401…40N），每一所述异常信号检测支路（图未示出）的检测端与一所述电源开关支路的输入端连接。
本实施例中，电源开关电路30、异常信号检测电路40以及上述画面异常均可以设置多个支路，连接器20具有多个端子，多个端子分别与待测芯片，例如时序控制器或者电源芯片的各引脚一一对应连接，连接器20的端子数量与芯片引脚适配，具体可以根据芯片的引脚数量进行设定，此处不做限定，异常信号检测电路40及电源开关电路30依次串联设置于测试电源10的正极输出端以及连接器20的一信号输出端子之间，以测试芯片静电防护二极管D2的二极体特性，从而实现静电防护二极管D2的异常测试。画面检测开关电路50在设置多条画面检测开关支路时，其输入端则可以输入对应的驱动信号、控制信号或者驱动电源，并在各画面检测开关支路导通时，将上述信号或者驱动电源输出至连接器20的各信号输出端子，从而输出至待测芯片，实现对显示面板的画面异常检测。
本申请还提出一种芯片异常信号检测电路，应用于设置有静电防护二极管D2的芯片的异常检测。
参照图1至图3，所述芯片异常信号检测电路包括：
测试电源10，设置为给待测芯片提供测试电流；
连接器20，包括接地端子及多个信号输出端子，多个所述信号输出端子设置为连接待测芯片的多个功能引脚及多个静电防护二极管D2的阳极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管D2的阳极；
电源开关电路30，包括多个第二开关管Q2，多个所述第二开关管Q2的输出端与多个所述信号输出端子一一对应连接；各所述第二开关管Q2，设置为在开启时，将所述测试电源10提供的测试电流输出至所述连接器20对应的信号输出端子；
异常信号检测电路40，包括多个发光二极管D1，各所述发光二极管D1的阳极与所述供电电源的正极输出端连接，多个所述发光二极管D1的阴极与多个所述第二开关管Q2的输入端一一对应连接。
本申请通过设置连接器20，并通过连接器20，使得测试电源10、异常信号检测电路40及第二开关管Q2依次静电防护二极管D2的阴极连接，静电防护二极管D2的阴极、静电防护二极管D2的阳极，并在第二开关管Q2导通时，测试电源10提供的测试电流经静电防护二极管D2与测试电源10、发光二极管D1及第二开关管Q2是否构成电流回路，检测待测芯片的静电防护二极管D2反向截止特性，并输出相应的检测信号。本申请无需手持测量工具，即可实现测试静电防护二极管D2对应的二极体特性值的自动检测。此外，本申请通过将发光二极管D1串联设置于检测回路中，通过发光二极管D1的亮/灭状态即可以使测试工作人员直观的获知检测结果，提高了检测效率。本申请通过多个检测回路，可以实现对待测芯片的静电防护二极管D2进行批量测试。
本申请还一种芯片异常检测装置，包括如上所述的芯片异常检测电路。该芯片异常检测电路的详细结构可参照上述实施例，此处不再赘述；可以理解的是，由于在本申请芯片异常检测装置中使用了上述芯片异常检测电路，因此，本申请芯片异常检测装置的实施例包括上述芯片异常检测电路全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (14)

  1. 一种芯片异常检测电路，应用于设置有静电防护二极管的芯片的异常检测，其中，所述芯片异常检测电路包括：
    测试电源，设置为给待测芯片提供测试电流；
    连接器，包括信号输出端子及接地端子，所述信号输出端子设置为连接待测芯片的功能引脚及静电防护二极管的阴极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管的阳极；
    电源开关电路，串联设置于所述测试电源与所述连接器的信号输出端子之间，所述电源开关电路，设置为在开启时，将所述测试电源提供的测试电流输出至所述连接器的信号输出端子；
    异常信号检测电路，其检测端与所述电源开关电路的输入端连接，设置为检测待测芯片的静电防护二极管的反向截止特性，并输出相应的检测信号。
  2. 如权利要求1所述的芯片异常检测电路，其中，所述芯片异常检测电路还包括画面检测开关电路，所述画面检测开关电路的输入端设置为接入画面检测信号，所述画面检测开关电路的输出端与所述连接器的信号输出端子连接，所述画面检测开关电路，设置为在开启时，将接入的所述画面检测信号输出所述连接器的信号输出端子。
  3. 如权利要求2所述的芯片异常检测电路，其中，所述芯片异常检测电路还包括开关控制电路，所述开关控制电路的输出端分别与所述电源开关电路的受控端及所述画面检测开关电路的受控端连接；所述开关控制电路，设置为输出极性互为相反的第一电平信号和第二电平信号，以控制所述电源开关电路在接收到所述第一电平信号时开启，以及控制所述画面检测开关电路在接收到所述第二电平信号时开启。
  4. 如权利要求3所述的芯片异常检测电路，其中，所述开关控制电路包括拨码开关，所述拨码开关设置为在被触发时输出所述第一电平信号或所述第二电平信号。
  5. 如权利要求3所述的芯片异常检测电路，其中，所述画面检测开关电路包括第一开关管，所述第一开关管的输入端为所述画面检测开关电路的输入端，所述第一开关管的输出端为所述画面检测开关电路的输出端，所述第一开关管的受控端为画面检测开关电路的受控端。
  6. 如权利要求5所述的芯片异常检测电路，其中，所述第一开关管为N型场效应管。
  7. 如权利要求3所述的芯片异常检测电路，其中，所述电源开关电路包括第二开关管，所述第二开关管的输入端为所述电源开关电路的输入端，所述第二开关管的输出端为所述电源开关电路的输出端，所述第二开关管的受控端为所述电源开关电路的受控端。
  8. 如权利要求7所述的芯片异常检测电路，其中，所述第二开关管为P型场效应管。
  9. 如权利要求1所述的芯片异常检测电路，其中，所述异常信号检测电路包括发光二极管，所述发光二极管的阳极与所述供电电源的正极输出端连接，所述发光二极管的阴极为所述异常信号检测电路的检测端。
  10. 如权利要求2所述的芯片异常检测电路，其中，
    所述信号输出端子的数量为多个；
    所述电源开关电路包括多个电源开关支路，多个所述电源开关支路的输出端与多个所述电源开关支路一一对应连接；
    所述异常信号检测电路包括多个异常信号检测支路，每一所述异常信号检测支路的检测端与一所述电源开关支路的输入端连接。
  11. 如权利要求10所述的芯片异常检测电路，其中，所述画面检测开关电路包括多个画面检测开关支路时，多个所述画面检测开关支路的输入端设置为输入对应的驱动信号、控制信号或者驱动电源，各所述画面检测开关支路在导通时，将上述信号或者驱动电源输出至连接器的各信号输出端子。
  12. 一种芯片异常检测电路，应用于设置有静电防护二极管的芯片的异常检测，其中，所述芯片异常检测电路包括：
    测试电源，设置为给待测芯片提供测试电流；
    连接器，包括接地端子及多个信号输出端子，多个所述信号输出端子设置为连接待测芯片的多个功能引脚及多个静电防护二极管的阳极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管的阳极；
    电源开关电路，包括多个第二开关管，多个所述第二开关管的输出端与多个所述信号输出端子一一对应连接；各所述第二开关管，设置为在开启时，将所述测试电源提供的测试电流输出至所述连接器对应的信号输出端子；
    异常信号检测电路，包括多个发光二极管，各所述发光二极管的阳极与所述供电电源的正极输出端连接，多个所述发光二极管的阴极与多个所述第二开关管的输入端一一对应连接。
  13. 一种芯片异常检测装置，其中，包括如权利要求1所述的芯片异常检测电路；所述芯片异常检测电路包括：
    测试电源，设置为给待测芯片提供测试电流；
    连接器，包括信号输出端子及接地端子，所述信号输出端子设置为连接待测芯片的功能引脚及静电防护二极管的阴极，所述接地端子设置为连接待测芯片的接地脚及静电防护二极管的阳极；
    电源开关电路，串联设置于所述测试电源与所述连接器的信号输出端子之间，所述电源开关电路，设置为在开启时，将所述测试电源提供的测试电流输出至所述连接器的信号输出端子；
    异常信号检测电路，其检测端与所述电源开关电路的输入端连接，设置为检测待测芯片的静电防护二极管的反向截止特性，并输出相应的检测信号。
  14. 如权利要求13所述的芯片异常检测装置，其中，
    所述电源开关电路，包括多个第二开关管，多个所述第二开关管的输出端与多个所述信号输出端子一一对应连接；各所述第二开关管，设置为在开启时，将所述测试电源提供的测试电流输出至所述连接器对应的信号输出端子；
    所述异常信号检测电路包括多个发光二极管，各所述发光二极管的阳极与所述供电电源的正极输出端连接，多个所述发光二极管的阴极与多个所述第二开关管的输入端一一对应连接。
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