WO2020073395A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2020073395A1
WO2020073395A1 PCT/CN2018/113981 CN2018113981W WO2020073395A1 WO 2020073395 A1 WO2020073395 A1 WO 2020073395A1 CN 2018113981 W CN2018113981 W CN 2018113981W WO 2020073395 A1 WO2020073395 A1 WO 2020073395A1
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Prior art keywords
array substrate
holes
connection end
substrate according
fan
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PCT/CN2018/113981
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English (en)
French (fr)
Inventor
马伟欣
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/326,934 priority Critical patent/US11139319B2/en
Publication of WO2020073395A1 publication Critical patent/WO2020073395A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the invention relates to the field of display, in particular to an array substrate and a display device.
  • AMOLED Active-Matrix Organ circuit
  • the drive circuit transmits the signal to the display area through the fan-out line on the array substrate, but as the display effect of the display device becomes better and better, the more signals the drive circuit outputs, the more fan-out lines are required More and more.
  • the resistance of all fan-out lines from the driving circuit to the display area must be the same.
  • a winding method is used to keep the resistance of all fan-out wires the same. By changing the length of the fan-out wire bending winding to change the size of the resistor, to achieve the basically the same purpose of the resistance of each fan-out wire.
  • This method not only wastes material and space, but also because of the steep corners of the inside of the trace, it is easy to break the interlayer dielectric layer overlying it, resulting in a short circuit between the fan-out line and the source and drain on the interlayer dielectric layer. Phenomenon, greatly reducing the service life of the product.
  • the purpose of the present invention is to provide an array substrate and a display device to solve the problems of waste materials, high cost, and short product service life in the prior art.
  • the present invention provides an array substrate provided with a display area and a non-display area, and the array substrate further includes a number of thin film transistors, a number of thin film transistors, a driving circuit, a number of polysilicon resistors, and a number of fanout lines.
  • the thin film transistors are arranged in an array in the display area, and the thin film transistors have input terminals.
  • the driving circuit corresponds to the non-display area, and the driving circuit has an output terminal.
  • the polysilicon resistance and the fan-out line correspond to the non-display area. Wherein, the two ends of each polysilicon resistor are respectively connected to the input end of the thin film transistor and the output end of the driving circuit through corresponding fan-out lines.
  • the fan-out line includes a number of first scan lines and a number of second scan lines.
  • the array substrate further includes a buffer layer, a first insulating layer, a second insulating layer, and an interlayer dielectric layer.
  • the polysilicon resistor is provided on the buffer layer.
  • the first insulating layer covers the polysilicon resistor, and the first scan line is provided thereon.
  • the second insulating layer covers the first scan line, and the second scan line is provided thereon.
  • the interlayer dielectric layer covers the second scanning line.
  • the material of the interlayer dielectric layer is an insulating dielectric material.
  • the array substrate further includes source traces and drain traces, which are disposed above the interlayer dielectric layer.
  • one end of the polysilicon resistor is provided with a first series hole, and the other end is provided with a second series hole.
  • Each first scanning line is provided with a first connection end and a second connection end.
  • Each of the second scanning lines is provided with a third connection end and a fourth connection end.
  • the first insulating layer is provided with a plurality of first through holes. Each of the first through holes corresponds to the first series hole or the second series hole.
  • the second insulating layer is provided with a plurality of second through holes.
  • Each of the second through holes corresponds to the first series hole or the second series hole.
  • third through holes are provided on the interlayer dielectric layer.
  • Each of the third through holes corresponds to the second through hole or the third connection end or the fourth connection end.
  • the total number of the first through holes and the total number of the third through holes are both twice that of the second through holes.
  • the invention also provides a display device including the array substrate.
  • an array substrate and a display device are provided.
  • the resistance of each fan-out line is kept consistent by connecting a polysilicon resistor in series.
  • the size of the resistance can be adjusted by changing the length and size of the polysilicon. Using this method to keep the resistance basically the same will not cause the interlayer dielectric layer to break, so it will not cause a short circuit between the fan-out line and the source and drain on the interlayer dielectric layer, thereby improving the short service life of the product.
  • the winding method is eliminated, making the structure simpler, saving raw materials, and reducing costs.
  • 1 is a schematic plan view of an array substrate in an embodiment of the invention.
  • FIG. 2 is a schematic cross-sectional view of a structure of a first scan line wiring in an embodiment of the present invention
  • FIG. 3 is a schematic plan view of a first scanning line series structure in an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a structure of a second scanning line in an embodiment of the present invention.
  • FIG. 5 is a schematic plan view of a second scanning line series structure in an embodiment of the present invention.
  • Polysilicon resistor 1 first series hole 11; second series hole 12;
  • Source trace 3 Drain trace 4; Buffer layer 5;
  • Second insulating layer 7 Second insulating layer 7; second through holes 71, 72;
  • Interlayer dielectric layer 8 third through holes 81, 82, 83, 84.
  • the component When certain components are described as “on” another component, the component may be placed directly on the other component; there may also be an intermediate component, which is placed on the intermediate component, And the intermediate component is placed on another component.
  • the two When a component is described as “mounted to” or “connected to” another component, the two can be understood to be “installed” or “connected” directly, or a component indirectly “mounted to” or “connected” through an intermediate component To "another part.
  • this embodiment provides an array substrate 1000 including a display area 200 and a non-display area 100.
  • a plurality of thin film transistors 201 are arranged on the display area 200, which are arranged in an array on the display area 200, and the thin film transistors 201 are provided with input terminals.
  • a driving circuit 101 is provided on the non-display area 100, and the driving circuit 101 is provided with an output terminal.
  • the non-display area 100 is further provided with a polysilicon resistor 1 and a plurality of fan-out lines 2. Both ends of each polysilicon resistor 1 are connected to the input end of the thin film transistor 201 and the output end of the driving circuit 101 through corresponding fan-out lines 2 respectively.
  • the driving circuit 101 is used to transmit a display signal
  • the thin film transistor 201 is used to receive a limit number
  • the fan-out line 2 is used to transmit a signal
  • the polysilicon resistance is used to keep the resistance of each fan-out line 2 consistent.
  • the fan-out line 2 in this embodiment includes a number of first scan lines 21 and a number of second scan lines 22 for transmitting signals sent by the driving circuit 101.
  • the first scan line 21 is still
  • the gate of the thin film transistor and the second scan line 22 are also used at one end of the electrode of the pixel circuit capacitor.
  • the array substrate 1000 provided in this embodiment further includes a buffer layer 5, a first insulating layer 6, a second insulating layer 7, and an interlayer dielectric layer 8.
  • a polysilicon resistor 1 is provided on the buffer layer 5.
  • the buffer layer 5 may be made of silicon oxide, used to protect the overall structure of the array substrate 1000, and reduce damage to the array substrate 1000 during the manufacturing process.
  • the first insulating layer 6 covers the polysilicon resistor 1, the first scan line 21 is provided above the first insulating layer 6, the second insulating layer 7 covers the first scan line 21, and the second scan line 22 is provided on the second insulation Above layer 7.
  • Both the first insulating layer 6 and the second insulating layer 7 are made of insulating materials, such as tetrafluoroethylene plastic, to separate the wiring of each layer and prevent the circuits of each layer from affecting each other.
  • the interlayer dielectric layer 8 covers the second scan line 22.
  • the interlayer dielectric layer 8 uses dielectric isolation technology and is made of an insulating dielectric material, such as silicon dioxide, to isolate important circuits.
  • a source trace 3 and a drain trace 4 are also provided above the interlayer dielectric layer.
  • the source trace 3 is used to connect the source of the thin film transistor
  • the drain trace is used to connect the drain of the thin film transistor.
  • the first insulating layer 6 is provided with a number of first through holes.
  • the second insulating layer 7 is provided with a number of second through holes.
  • the interlayer dielectric layer 8 is provided with a number of third through holes. The total number of the first through holes and the total number of the third through holes are twice that of the second through holes.
  • each polysilicon resistor 1 is provided with a first series hole 11 and a second series hole 12 located at both ends of the polysilicon resistor 1.
  • Each first scan line 21 is provided with a first connection end 211 and a second connection end 212.
  • Each second scan line 22 is provided with a third connection terminal 221 and a fourth connection terminal 222.
  • the first connection end 211 of the first scan line 21 is connected to the first series hole 11 of the polysilicon resistor 1 through the corresponding first through hole 61, and the second connection end 212 is connected to the polysilicon resistance 1 through the corresponding first through hole 62
  • the second series holes 12 are connected, so that each first scan line 21 is connected in series with the corresponding polysilicon resistor 1.
  • One end of the source trace 3 is connected to the third connection end 221 of the corresponding second scan line 22 through the third through hole 83, and the other end passes through the third through hole 81, the second through hole 71, and the first through hole in this order 63 is connected to the first series hole 11 corresponding to the polysilicon resistor 1.
  • One end of the drain trace 4 is connected to the fourth connection end 222 of the corresponding second scan line 22 through the third through hole 84, and the other end passes through the third through hole 82, the second through hole 72, and the first through hole in this order 64 is connected to the second series hole 12 corresponding to the polysilicon resistor 1.
  • the second scan line 22 realizes the series connection with the corresponding polysilicon resistor 1 while also controlling the current between the source and the drain.
  • each fan-out line 2 is a straight line.
  • This embodiment also provides a display device (not shown), including the above-mentioned array substrate.
  • each fan-out line is connected with a corresponding polysilicon resistor in series.
  • This method greatly simplifies the trace structure and eliminates the The structure of a large number of curved windings in the prior art also avoids the breakage of the interlayer dielectric layer and the short circuit between the second scan line and the source and drain caused by the breakage, which not only saves the wiring material, but also reduces the cost , Also increased product life.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板（1000）和显示装置，阵列基板（1000）设有一显示区（200）和一非显示区（100），以及阵列基板（1000）还包括若干薄膜晶体管（201）、一驱动电路（101）、若干多晶硅电阻（1）以及若干扇出线（2）。薄膜晶体管（201）阵列式排布于显示区（200），薄膜晶体管（201）设有输入端。驱动电路（101）对应于非显示区（100），驱动电路（101）设有输出端。多晶硅电阻（1）和扇出线（2）对应于非显示区（100）。其中，每一多晶硅电阻（1）的两端通过对应扇出线（2）分别连接至薄膜晶体管（201）的输入端和驱动电路（101）的输出端。简化了扇出线（2）的走线结构，减少了现有技术中大量弯曲绕线的结构，从而节省了走线原材料，降低了成本，同时提高了产品的使用寿命。

Description

阵列基板及显示装置 技术领域
本发明涉及显示领域，特别是一种阵列基板及显示装置。
 背景技术
随着科技的迅猛发展，人们对于信息交流和传递等方面的依赖程度日益增加。而显示装置作为信息交换和传递的主要载体和物质基础，先以成为众多从事信息光电研究科学家争相抢占的热点和高地。AMOLED（Active-Matrix Organ电路 Light Emitting Diode，有源矩阵有机发光二极体面板）的出现是显示技术领域的一大突破，由于其自发光体原理，无需背光源、彩色滤光片等部件，比LCD（Liquid Crystal Display，液晶显示器）更加轻薄，能耗也更低，并且由于其拥有一定的柔韧性，相比玻璃基板的LCD不易损坏。
在AMOLED中，驱动电路通过阵列基板上的扇出线将信号传输到显示区域，但是随着显示装置的显示效果越来越佳，驱动电路输出的信号越来越多，所需的扇出线也越来越多。为了保证显示效果的均一性，所有从驱动电路到显示区域的扇出线的电阻必须相同。在现有技术中，采用绕线的方式来保持所有扇出线的电阻一致。通过改变扇出线弯曲绕线的长度来改变电阻的大小，以达到每个扇出线电阻的基本一致的目的。这种方式不仅浪费材料、空间，而且由于走线弯曲内侧的边角陡峭，容易使覆于其上方的层间介质层断裂，从而导致扇出线与层间介质层上源极和漏极出现短路现象，大大降低了产品的使用寿命。
 技术问题
本发明的目的是提供一种阵列基板及显示装置，以解决现有技术中所存在的浪费材料、高成本、产品使用寿命短等问题。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，设有一显示区和一非显示区，以及该阵列基板还包括若干薄膜晶体管若干薄膜晶体管、一驱动电路、若干多晶硅电阻以及若干扇出线。所述薄膜晶体管阵列式排布于所述显示区，该薄膜晶体管具有输入端。所述驱动电路，对应于所述非显示区，该驱动电路具有输出端。所述多晶硅电阻和所述扇出线对应于所述非显示区。其中，每一所述多晶硅电阻的两端通过对应所述扇出线分别连接至所述薄膜晶体管的输入端和所述驱动电路的输出端。
进一步地，所述扇出线包括若干第一扫描线以及若干第二扫描线。所述阵列基板还包括一缓冲层、一第一绝缘层、一第二绝缘层以及一层间介质层。所述缓冲层上设有所述多晶硅电阻。所述第一绝缘层覆于所述多晶硅电阻上，其上设有所述第一扫描线。所述第二绝缘层覆于所述第一扫描线上，其上设有所述第二扫描线。所述层间介质层覆于所述第二扫描线上。
进一步地，所述层间介质层的材料为绝缘电介质材料。
进一步地，所述阵列基板还包括源极走线以及漏极走线，设于所述层间介质层上方。
进一步地，所述多晶硅电阻的一端设有一第一串联孔，另一端设有一第二串联孔。每一所述第一扫描线上均设有一第一连接端以及一第二连接端。每一所述第二扫描线上均设有一第三连接端以及一第四连接端。其中，当所述多晶硅电阻与对应所述第一扫描线连接时，所述第一串联孔与所述第一连接端连接，所述第二串联孔与所述第二连接端连接。当所述多晶硅电阻与对应所述第一扫描线连接时，所述第一串联孔通过所述源极走线与所述第三连接端连接，所述第二串联孔通过所述漏极走线与所述第四连接端连接。
进一步地，所述第一绝缘层上设有若干第一贯穿孔。其中，每一所述第一贯穿孔与所述第一串联孔或所述第二串联孔上下对应。
进一步地，所述第二绝缘层上设有若干第二贯穿孔。其中，每一所述第二贯穿孔与第一串联孔或所述第二串联孔上下对应。
进一步地，所述层间介质层上设有若干第三贯穿孔。其中，每一所述第三贯穿孔与所述第二贯穿孔或所述第三连接端或所述第四连接端上下对应。
进一步地，所述第一贯穿孔的总数量和所述第三贯穿孔的总数量均为所述第二贯穿孔的2倍。
本发明还提供一种显示装置，包括了所述的阵列基板。
 有益效果
本发明中提供阵列基板及显示装置，通过串联多晶硅电阻的方式来保持每个扇出线的电阻一致，电阻的大小可以通过改变多晶硅的长度和大小来调整。采用这种方式保持电阻基本一致，不会造成层间介质层的断裂，故而也不会导致扇出线与层间介质层上源极和漏极的短路，从而提高了产品使用寿命短。取消了绕线的方式，使结构更加简单，节省了原材料，降低了成本。
 附图说明
图1为本发明实施例中的阵列基板平面示意图；
图2为本发明实施例中的第一扫描线走线结构截面示意图；
图3为本发明实施例中的第一扫描线串联结构平面示意图；
图4为本发明实施例中的第二扫描线走线结构截面示意图；
图5为本发明实施例中的第二扫描线串联结构平面示意图。
图中部件表示如下：
阵列基板1000；
非显示区100；驱动电路101；显示区200；薄膜晶体管201；
多晶硅电阻1；第一串联孔11；第二串联孔12；
扇出线2；
第一扫描线21；第一连接端211；第二连接端212；
第二扫描线22；第三连接端221；第四连接端222；
源极走线3；漏极走线4；缓冲层5；
第一绝缘层6；第一贯穿孔61、62 、63、64；
第二绝缘层7；第二贯穿孔71、72；
层间介质层8；第三贯穿孔81、82、83、84。
 本发明的实施方式
以下参考说明书附图介绍本发明的优选实施例，证明本发明可以实施，所述实施例可以向本领域中的技术人员完整介绍本发明，使其技术内容更加清楚和便于理解。本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。附图所示的每一部件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。为了使图示更清晰，附图中有些地方适当夸大了部件的厚度。
本发明所提到的方向用语，例如「上」、「下」、「左」、「右」等，仅是附图中的方向，只是用来解释和说明本发明，而不是用来限定本发明的保护范围。
当某些部件被描述为“在”另一部件“上”时，所述部件可以直接置于所述另一部件上；也可以存在一中间部件，所述部件置于所述中间部件上，且所述中间部件置于另一部件上。当一个部件被描述为“安装至”或“连接至”另一部件时，二者可以理解为直接“安装”或“连接”，或者一个部件通过一中间部件间接“安装至”、或“连接至”另一个部件。
如图1所示，本实施例提供一种阵列基板1000，包括了显示区200和非显示区100。在显示区200上设有若干薄膜晶体管201，其阵列式排布于显示区200上，该薄膜晶体管201设有输入端。在非显示区100上设有驱动电路101，该驱动电路101设有输出端。在非显示区100上还设有若多晶硅电阻1以及若干扇出线2，每一多晶硅电阻1的两端通过对应的扇出线2分别连接至薄膜晶体管201的输入端和驱动电路101的输出端。驱动电路101用于发射显示信号，薄膜晶体管201用于接收限号，扇出线2用于传输信号，多晶硅电阻用于保持每一扇出线2的电阻一致。
如图2、图4所示，本实施例中的扇出线2包括若干第一扫描线21和若干第二扫描线22，用于传输驱动电路101发出的信号，同时，第一扫描线21还是薄膜晶体管的栅极，第二扫描线22还用于像素电路电容的电极一端。本实施例提供的阵列基板1000还包括一缓冲层5、一第一绝缘层6、一第二绝缘层7以及一层间介质层8。缓冲层5上设有多晶硅电阻1。缓冲层5可由氧化硅制成，用于保护阵列基板1000的整体结构，减少阵列基板1000在制备过程中产生的损伤。第一绝缘层6覆于多晶硅电阻1上方，第一扫描线21设于第一绝缘层6上方，第二绝缘层7覆于第一扫描线21上方，第二扫描线22设于第二绝缘层7上方。第一绝缘层6和第二绝缘层7均由绝缘材料制成，例如四氟乙烯塑料，用于将每一层走线分隔开，防止各层电路互相影响。层间介质层8覆于第二扫描线22上方。层间介质层8采用介质隔离技术，由绝缘电介质材料制成，例如二氧化硅，用于隔离重要电路。
在层间介质层上方还设有源极走线3和漏极走线4，源极走线3用于连接薄膜晶体管的源极，漏极走线用于连接薄膜晶体管的漏极。
第一绝缘层6上设有若干第一贯穿孔。第二绝缘层7上设有若干第二贯穿孔。层间介质层8上设有若干第三贯穿孔。第一贯穿孔的总数量和第三贯穿孔的总数量均为第二贯穿孔的2倍。
如图3、图5所示，每一多晶硅电阻1上均设有一第一串联孔11以及一第二串联孔12，位于多晶硅电阻1的两端。每一第一扫描线21上均设有一第一连接端211以及一第二连接端212。每一第二扫描线22上均设有一第三连接端221以及一第四连接端222。
第一扫描线21的第一连接端211穿过对应的第一贯穿孔61与多晶硅电阻1的第一串联孔11连接，第二连接端212穿过对应的第一贯穿孔62与多晶硅电阻1的第二串联孔12连接，以此实现每一第一扫描线21与对应多晶硅电阻1的串联。
源极走线3的一端通过第三贯穿孔83与对应的第二扫描线22的第三连接端221连接，另一端依次穿过第三贯穿孔81、第二贯穿孔71、第一贯穿孔63与对应多晶硅电阻1的第一串联孔11连接。漏极走线4的一端通过第三贯穿孔84与对应的第二扫描线22的第四连接端222连接，另一端依次穿过第三贯穿孔82、第二贯穿孔72、第一贯穿孔64与对应多晶硅电阻1的第二串联孔12连接。第二扫描线22以此方式实现与对应多晶硅电阻1的串联，同时还能控制源极和漏极间的电流。
本实施例中的每一扇出线2均为直线走线。
本实施例还提供一种显示装置（图未示），包括了以上所述的阵列基板。
在本实施例中的每一扇出线均串联了对应的多晶硅电阻，可以通过改变多晶硅电阻的大小和长度来保持每条走线的电阻基本一致，这种方式大大简化了走线结构，去除了现有技术中大量弯曲绕线的结构，从而也避免了层间介质层出现断裂，以及断裂所导致的第二扫描线与源、漏极短路的现象，不仅节省了走线原材料，降低了成本，也提高了产品使用寿命。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，设有一显示区和一非显示区，其中，该阵列基板包括：
    若干薄膜晶体管，阵列式排布于所述显示区，每一薄膜晶体管具有输入端；
    一驱动电路，对应于所述非显示区，该驱动电路具有输出端；
    若干多晶硅电阻以及若干扇出线，对应于所述非显示区；
    其中，每一所述多晶硅电阻的两端通过对应所述扇出线分别连接至所述薄膜晶体管的输入端和所述驱动电路的输出端。
  2. 如权利要求1所述的阵列基板，其中，所述扇出线包括若干第一扫描线以及若干第二扫描线；
    所述阵列基板还包括：
    一缓冲层，所述多晶硅电阻设于所述缓冲层上；
    一第一绝缘层，覆于所述多晶硅电阻上，所述第一扫描线设于所述第一绝缘层的上方；
    一第二绝缘层，覆于所述第一扫描线上，所述第二扫描线设于所述第二绝缘层的上方；
    一层间介质层，覆于所述第二扫描线上。
  3. 如权利要求2所述的阵列基板，其中，所述层间介质层的材料为绝缘电介质材料。
  4. 如权利要求2所述的阵列基板，其中，还包括源极走线以及漏极走线，设于所述层间介质层上方。
  5. 如权利要求1所述的阵列基板，其中，所述多晶硅电阻的一端设有一第一串联孔，另一端设有一第二串联孔；
    每一所述第一扫描线上均设有一第一连接端以及一第二连接端；每一所述第二扫描线上均设有一第三连接端以及一第四连接端；
    其中，当所述多晶硅电阻与对应所述第一扫描线连接时，所述第一串联孔与所述第一连接端连接，所述第二串联孔与所述第二连接端连接；
    当所述多晶硅电阻与对应所述第一扫描线连接时，所述第一串联孔通过所述源极走线与所述第三连接端连接，所述第二串联孔通过所述漏极走线与所述第四连接端连接。
  6. 如权利要求2所述的阵列基板，其中，还包括：
    若干第一贯穿孔，贯穿式设于所述第一绝缘层上；
    其中，每一所述第一贯穿孔与所述第一串联孔或所述第二串联孔上下对应。
  7. 如权利要求6所述的阵列基板，其中，还包括：
    若干第二贯穿孔，贯穿式设于所述第二绝缘层上；
    其中，每一所述第二贯穿孔与所述第一串联孔或所述第二串联孔上下对应。
  8. 如权利要求6所述的阵列基板，其中，还包括：
    若干第三贯穿孔，贯穿式设于所述层间介质层上；
    其中，每一所述第三贯穿孔与所述第二贯穿孔或所述第三连接端或所述第四连接端上下对应。
  9. 如权利要求6所述的阵列基板，其中，所述第一贯穿孔的总数量和所述第三贯穿孔的总数量均为所述第二贯穿孔的2倍。
  10. 一种显示装置，其中，包括如权利要求1所述的阵列基板。
PCT/CN2018/113981 2018-10-08 2018-11-05 阵列基板及显示装置 Ceased WO2020073395A1 (zh)

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