WO2020063356A1 - 阵列基板及其检测方法、显示面板 - Google Patents

阵列基板及其检测方法、显示面板 Download PDF

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Publication number
WO2020063356A1
WO2020063356A1 PCT/CN2019/105510 CN2019105510W WO2020063356A1 WO 2020063356 A1 WO2020063356 A1 WO 2020063356A1 CN 2019105510 W CN2019105510 W CN 2019105510W WO 2020063356 A1 WO2020063356 A1 WO 2020063356A1
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Prior art keywords
sub
pixel
pixels
detection line
array substrate
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PCT/CN2019/105510
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English (en)
French (fr)
Inventor
袁粲
李永谦
袁志东
李蒙
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/645,088 priority Critical patent/US11322550B2/en
Priority to EP19858706.5A priority patent/EP3859784A4/en
Publication of WO2020063356A1 publication Critical patent/WO2020063356A1/zh
Priority to US17/731,874 priority patent/US20220320195A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a detection method thereof, and a display panel.
  • OLED display panels In the display field, organic light-emitting diode (OLED) display panels have the characteristics of self-luminous, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide temperature range, simple manufacturing, etc. Prospects. External compensation circuits are widely used in OLED display panels so that the display panel has a uniform display effect.
  • At least one embodiment of the present disclosure provides an array substrate including a plurality of sub-pixels and a plurality of detection line structures.
  • the plurality of sub-pixels are arranged in an array of multiple rows and columns along a first direction and a second direction.
  • the first direction intersects the second direction;
  • each detection line structure includes at least one first detection line extending along the first direction;
  • at least one sub-pixel in each row of sub-pixels includes a light emitting element and drives the light emission
  • a first transistor that emits light, and adjacent nth and n + 1th rows of sub-pixels in the array form a sub-pixel row group, and the nth and n + 1th rows in each sub-pixel row group
  • One of the detection line structures is disposed between the sub-pixels, and the detection line structure is configured to be connected to the n-th and n + 1-th sub-pixels and used to detect the n-th and n + 1-th rows
  • n is an odd
  • any one of the plurality of detection line structures is not located between two adjacent sub-pixel row groups.
  • the array substrate further includes a plurality of first power lines extending along the first direction, and the first power lines are disposed between two adjacent sub-pixel row groups, and each of the first A power line is configured to connect to two adjacent rows of sub-pixels and provide a first power signal.
  • the plurality of first power supply lines and the plurality of detection line structures are alternately distributed in the second direction.
  • the adjacent two sub-pixel row groups are symmetrically disposed with respect to the first power line located between the adjacent two sub-pixel row groups.
  • the array substrate further includes a plurality of second power supply lines, the plurality of second power supply lines extending along the second direction and being electrically connected to the plurality of first power supply lines respectively.
  • each detection line structure includes a plurality of first detection lines, the plurality of first detection lines are sequentially arranged along the first direction and are insulated from each other, and the plurality of first detection lines in the plurality of detection line structures are A detection line constitutes an array of detection lines arranged in multiple rows and columns along the first direction and the second direction; each of the first detection lines corresponds to at least two of the sub-pixels located in the same row.
  • the array substrate further includes a plurality of second detection lines, and the plurality of second detection lines extend along the second direction and are respectively connected to a plurality of columns of the first detection lines in the detection line array.
  • One-to-one correspondence and cross-electrical connection Multiple first detection lines located in the same column are electrically connected to each other through a corresponding second detection line.
  • each of the first detection lines is correspondingly connected to two of the pixel units, and the second detection line connected to each of the first detection lines is provided at a corresponding connection of the first detection line. Between 2 pixel units.
  • the sub-pixel further includes a second transistor, a third transistor, and a first capacitor; a gate and a first electrode of the second transistor are respectively configured to receive a first scanning signal and a data signal, and the first The second pole of the two transistors is connected to the gate of the first transistor; the first pole of the first transistor is configured to receive a first power signal, and the second pole of the first transistor and the third pole of the third transistor are respectively The first electrode is connected to the first electrode of the light-emitting element; the gate of the third transistor is configured to receive a second scan signal, and the second electrode of the third transistor is connected to the detection line structure of the sub-pixel. Electrically connected; the second electrode of the light-emitting element is configured to receive a second power signal; one end of the first capacitor is connected to the gate of the first transistor, and the other end is connected to the second electrode of the first transistor.
  • the array substrate further includes a plurality of first scan lines extending along the first direction, and the plurality of first scan lines are respectively one-to-one corresponding to a plurality of rows of sub-pixels, and are respectively corresponding to the corresponding ones.
  • the gates of the second transistors in the connected multiple rows of sub-pixels are connected to provide the first scan signal.
  • each sub-pixel row group two first scan lines connected to the n-th and n + 1-th rows of sub-pixels are respectively provided in the n-th and n + 1-th rows of sub-pixels. Between pixels.
  • a detection line structure connected to the n-th and n + 1-th rows of sub-pixels is disposed separately from the n-th and n + 1-th rows of sub-pixels, respectively. Between two first scan lines connected.
  • each sub-pixel row group two first scan lines respectively connected to the n-th and n + 1-th sub-pixels are located relative to the n-th and n + 1-th rows.
  • the detection line structure between the rows of sub-pixels is arranged symmetrically.
  • the first scan line is further connected to a gate of a third transistor in a correspondingly connected sub-pixel to provide the second scan signal.
  • the array substrate further includes a plurality of second scan lines extending along the first direction, and the plurality of second scan lines are respectively one-to-one corresponding to a plurality of rows of sub-pixels, and are respectively corresponding to the corresponding ones.
  • the gates of the third transistors in the connected sub-pixels are connected to provide the second scanning signal.
  • the second transistor and the third transistor are arranged side by side along the first direction, and a channel length direction of the second transistor and a channel length direction of the third transistor are both The second direction is parallel.
  • the n-th and n + 1-th rows of sub-pixels are arranged symmetrically with respect to a detection line structure connected to them.
  • the light emitting element is a top emission organic light emitting diode.
  • At least one embodiment of the present disclosure also provides a display panel including the above array substrate.
  • At least one embodiment of the present disclosure further provides a detection method for the above array substrate, the detection method includes: selecting a target sub-pixel among the plurality of sub-pixels; and for the target sub-pixel in the sub-pixel array A pixel applies a detection signal; and an electrical characteristic of a first transistor or a light emitting element in the target sub-pixel is obtained through a detection line structure connected to the target sub-pixel.
  • FIG. 1A is a block diagram of an array substrate
  • FIG. 1B is a schematic circuit diagram of an array substrate
  • FIG. 1C is a schematic diagram of a 3T1C pixel circuit
  • FIG. 2 is a schematic diagram of a layout structure of an array substrate
  • 3A is one of schematic diagrams of an array substrate provided by an embodiment of the present disclosure.
  • 3B is a second schematic view of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 4A is a third schematic view of an array substrate provided by an embodiment of the present disclosure.
  • 4B is a fourth schematic view of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a simulation comparison diagram of the array substrate shown in FIG. 4A and the array substrate shown in FIG. 2;
  • FIG. 7 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 1A is a block diagram of an array substrate 10, and FIG. 1B is a schematic circuit diagram of an array substrate.
  • the array substrate 10 includes a plurality of sub-pixels 100 arranged in an array structure of multiple rows and columns along the first direction D1 and the second direction D2.
  • Each sub-pixel 100 includes a light-emitting element and drives the light-emitting element.
  • Glowing pixel circuit for example, the array substrate is an organic light emitting diode (OLED) array substrate, and the light emitting element is an OLED.
  • the display panel further includes a plurality of scanning lines and a plurality of data lines for providing scanning signals and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels.
  • the display panel may further include a power line, a sensing line, and the like.
  • each m sub-pixel 100 constitutes a pixel unit, and the m sub-pixels include, for example, OLEDs emitting light of different colors (basic colors), thereby implementing color display.
  • m 2, 3, or 4.
  • one pixel unit includes three sub-pixels 100, and the three sub-pixels emit red light (R), green light (G), and blue light (B), respectively.
  • one pixel unit includes four RGBW sub-pixels 100, and the three sub-pixels emit red light (R), green light (G), blue light (B), and white light (W), respectively.
  • the pixel unit may emit colored light, there may be multiple implementations, including but not limited to, using an OLED that emits three primary colors, or using an OLED that emits white light with a color filter, or using an OLED that emits blue light with a light conversion material (Such as a fluorescent layer or a quantum dot layer).
  • FIG. 1C shows a schematic diagram of a 3T1C pixel circuit for an OLED array substrate (display panel).
  • the pixel circuit may further include a compensation circuit, a reset circuit, and the like. Please refer to FIG. 1B and FIG. 1C together.
  • the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, and a first detection line 111.
  • the first pole of the first transistor T1 is connected to the first power line 113, the second pole is connected to the anode of the OLED and the first pole of the third transistor T3, and the gate is connected to the second pole of the second transistor T2.
  • the first transistor T1 is A driving transistor that drives the OLED to emit light.
  • the gate of the second transistor T2 is connected to the first scan line 141 to receive the first scan signal SCN1, and the first electrode is connected to the data line to receive the data signal DT.
  • the first capacitor C1 is connected between the gate and the second electrode of the first transistor T1.
  • the cathode of the OLED is connected to the second power supply voltage VSS, for example, to ground.
  • the gate of the third transistor T3 is connected to the second scan line 142 to receive the second scan signal SCN2, and the second electrode is connected to the first detection line 111 to the detection circuit 11 to receive the detection signal SE.
  • the first detection line 111 is configured to detect an electrical characteristic of the first transistor T1.
  • the electrical characteristic includes, for example, a threshold voltage and / or a carrier mobility of the first transistor T1.
  • the first detection line 111 may also be configured to detect an electrical property of the OLED. Characteristics, including threshold voltage and drive current of OLED.
  • the first detection line 111 is connected to the detection circuit 11 so as to output an electric signal of the pixel circuit to the detection circuit 11 for analysis and detection.
  • the detection circuit is, for example, a conventional circuit including a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and the like, which are not described in detail in the embodiments of the present disclosure.
  • the first scan line 141 and the second scan line 142 may be different scan lines, that is, the first scan signal SCN1 and the second scan signal SCN2 may be signals provided by different scan lines.
  • the first scan signal SCN1 and the second scan signal SCN2 may also be the same signal provided by the same scan line, that is, the first scan line 141 and the second scan line 142 may be the same scan line.
  • the first scan signal SCN1 and the second scan signal SCN2 may be the same or different as required.
  • a detection process of the 3T1C pixel circuit includes applying a detection control signal to the 3T1C pixel circuit, and then acquiring the electrical characteristics of the driving transistor through a detection line connected thereto, as described below.
  • the first scan signal SCN1 and the second scan signal SCN2 are both on signals
  • the second transistor T2 and the third transistor T3 are both turned on
  • the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2.
  • the detection signal SE is transmitted to the second electrode of the first transistor T1 and the second electrode of the first capacitor C1 via the third transistor T3, and the voltage of the detection signal SE does not reach the point of the OLED Bright voltage, so the OLED does not emit light.
  • the first detection line 111 is floated, and the second and third transistors T2 and T3 are both turned on.
  • a driving current is generated in the first transistor T1 and the first
  • the two electrodes are charged to a voltage Vdata-Vth, where Vdata is the voltage of the data signal DT and Vth is the threshold voltage of the first transistor T1.
  • Vdata is the voltage of the data signal DT
  • Vth is the threshold voltage of the first transistor T1.
  • the first transistor T1 changes from an on state to an off state.
  • the first scan signal SCN1 and the second scan signal SCN2 are both on signals, and the second transistor T2 and the third transistor T3 are both turned on.
  • the detection circuit 11 passes the first detection line 111 to the first transistor T1.
  • the saturation voltage Vdata-Vth on the two poles (that is, the second electrode of the first capacitor C1) is sampled to obtain the electrical characteristic of the threshold voltage of the first transistor T1.
  • the detection control signal includes a scan signal, a data signal, a detection signal, and the like applied to the second transistor T2 and the third transistor T3.
  • another detection process of the 3T1C pixel circuit includes: applying a detection control signal to the 3T1C pixel circuit, and then acquiring the electrical characteristics of the light-emitting element through a detection line connected to the detection control signal, as described below.
  • the first scan signal SCN1 is an off signal
  • the second scan signal SCN2 is an on signal
  • the second transistor T2 is turned off
  • the third transistor T3 is turned on.
  • the first detection line 111 passes through the third transistor T3 to the OLED.
  • the anode writes a reset signal; in the second stage, the first scan signal SCN1 is an on signal, the second scan signal SCN2 is an off signal, the second transistor T2 is turned on, the third transistor T3 is turned off, and the data signal DT is passed through the second transistor T2 is transmitted to the gate of the first transistor T1.
  • the first transistor T1 is turned on and generates a driving current to charge the anode of the OLED to the working voltage.
  • the first scan signal SCN1 is a shutdown signal and the second scan signal SCN2 is Turn on the signal, the second transistor T2 is turned off, and the third transistor T3 is turned on.
  • the first detection line 111 writes a reset signal to the anode of the OLED through the third transistor T3 again.
  • the first detection line 111 is floated, and the first transistor T1 charges the first detection line 111 until saturation, and then uses the detection circuit 11 to the first detection line 11
  • the saturation voltage on 1 is sampled to obtain the electrical characteristics of the OLED.
  • the first scan line and the second scan line may be separately provided to provide the first scan signal SCN1 and the second scan signal SCN2, respectively.
  • the detection control signal includes a scanning signal, a data signal, a detection signal, and the like applied to the second transistor T2, the third transistor T3.
  • the array substrate 10 may further include a data driving circuit 13 and a scan driving circuit 14.
  • the data driving circuit 13 is configured to issue a data signal, such as the above-mentioned data signal DT, as needed (for example, an image signal input to a display device); the pixel circuit of each sub-pixel is further configured to receive the data signal and apply the data signal to the first The gate of a transistor.
  • the scan driving circuit 14 is configured to output various scan signals, including, for example, the first scan signal SCN1 and the second scan signal SCN2 described above, such as an integrated circuit chip or a gate drive circuit (GOA) prepared directly on a display substrate.
  • GOA gate drive circuit
  • the array substrate 10 further includes a control circuit 12.
  • the control circuit 12 is configured to control the data driving circuit 13 to apply a data signal, and to control the gate driving circuit to apply a scan signal.
  • An example of the control circuit 12 is a timing control circuit (T-con).
  • the control circuit 12 may be in various forms, including, for example, a processor 121 and a memory 122.
  • the memory 121 includes executable code, and the processor 121 runs the executable code to perform the foregoing detection method.
  • the processor 121 may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), and the like.
  • CPU central processing unit
  • PLC programmable logic controller
  • the storage device 122 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory.
  • the volatile memory may include, for example, a random access memory (RAM) and / or a cache memory.
  • the non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, and the like.
  • One or more computer program instructions may be stored on a computer-readable storage medium, and the processor 121 may execute functions desired by the program instructions.
  • Various computer programs and various data can also be stored in the computer-readable storage medium, such as the electrical characteristic parameters obtained in the above detection method.
  • FIG. 2 is a schematic diagram of a layout structure of an array substrate.
  • FIG. 2 only shows a part of a pixel array in the array substrate.
  • a plurality of first detection lines 111 extend along a first direction (for example, a row direction of an array) D1 and are respectively connected to a plurality of rows of sub-pixels; the plurality of first scanning lines G1 and G2 are along the first direction.
  • D1 extends, and is respectively connected to a plurality of rows of sub-pixels; a plurality of first power lines 113 extend along the first direction D1, and are respectively connected to a plurality of rows of sub-pixels; that is, each row of sub-pixels is configured with a first detection line, A first scan line and a first power line.
  • the plurality of data lines 140 extend along the second direction (for example, the column direction of the array) D2 and are correspondingly connected to the multiple sub-pixels, for example, the first red sub-pixel column, the first green sub-pixel column, and the first blue sub-pixel.
  • the pixel column, the second red sub-pixel column, the second green sub-pixel column, and the second blue sub-pixel column are correspondingly connected.
  • the array substrate further includes a second detection line 112 extending along the second direction D2 and a plurality of second power supply lines 114.
  • the second detection line 112 is electrically connected to the plurality of first detection lines 111 respectively to connect different rows of The plurality of first detection lines 111 are electrically connected to each other, and the second power supply lines 114 are electrically connected to the plurality of first power supply lines 113 crosswise.
  • the first direction D1 and the second direction D2 intersect, for example, orthogonally to each other.
  • the first power supply line 113 and the first detection line 111 overlap with the data line extending in the second direction D2 in a direction perpendicular to the array substrate to generate a parasitic capacitance. Show.
  • the parasitic capacitance generated by the overlapping portion not only affects the signal transmission efficiency of the data line and the first detection line, but also easily causes yield problems such as short circuits due to static electricity and other factors.
  • An embodiment of the present disclosure provides an array substrate.
  • adjacent n-th and n + 1-th rows of sub-pixels constitute a sub-pixel row group, and two sub-rows of each sub-pixel row group.
  • a detection line structure is provided between the pixels, the detection line structure includes at least one first detection line, and the detection line structure is configured to be connected to the nth and n + 1th rows of subpixels and used to detect the first of the subpixels.
  • the array substrate reduces the number of detection line structures (first detection lines) by alternately sharing detection line structures between adjacent rows of sub-pixels, thereby reducing the overlap of the first detection lines and the data lines in the detection line structure. This can not only improve the product yield, but also reduce the parasitic capacitance between lines. For example, the parasitic capacitance of the first detection line is reduced by about 20%, which provides technical support for high-frequency driving of high-resolution (PPI) display panels.
  • PPI high-resolution
  • the “detection line structure” in the embodiment of the present disclosure may include only one first detection line extending along the first direction, that is, a row of sub-pixels share the same first detection line (as shown in FIG. 3A).
  • the detection line structure may also include a plurality of first detection lines (shown in FIG. 3B) insulated from each other and sequentially arranged along the first direction.
  • a row of sub-pixels is divided into multiple regions and multiple The first detection lines are connected to receive detection signals respectively, and by providing multiple detection lines in a row to provide detection signals, the charging speed of each first detection line can be increased, thereby increasing the detection speed.
  • FIG. 3A is one of the schematic diagrams of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate includes multiple sub-pixels, and the multiple sub-pixels are distributed in an array of multiple rows and columns along the first direction D1 and the second direction D2.
  • At least one of the pixels includes a light emitting element and a pixel circuit that drives the light emitting element to emit light.
  • the array substrate is an array substrate of an organic light-emitting diode (OLED) display panel
  • the light-emitting element of the sub-pixel is an OLED.
  • the pixel circuit is, for example, the 3T1C pixel circuit described above or other functions with compensation and reset based on the 3T1C pixel circuit
  • the pixel circuit is not limited in the embodiments of the present disclosure.
  • the array substrate includes a display area and a peripheral area outside the display area, and the pixel array may be located only in the display area.
  • each sub-pixel in the pixel array includes the light emitting element and the pixel circuit;
  • the pixel array may further include a portion located in the peripheral area, such as a dummy sub-pixel located in the peripheral area.
  • the dummy sub-pixel does not emit light, for example, does not include a light-emitting element or a pixel circuit. .
  • each detection line structure 110 includes one first detection line 111 is shown in FIG. 3A.
  • a row of the sub-pixels 120 is briefly shown in FIG. 3A, and only the first detection line 111 and the first power line 113 are shown.
  • signal lines such as the second detection line, the second power supply line, and the data line are omitted.
  • the connection relationship with a row of sub-pixels 120 in the figure represents that each sub-pixel 100 in the row of sub-pixels 120 is connected.
  • the adjacent n-th and n + 1-th sub-pixels 120 form a sub-pixel row group 200 (shown by a dashed box in FIG. 3A), and n is an odd or even number greater than 0.
  • a first detection line 111 is disposed between two rows of sub-pixels 100 of each sub-pixel row group 200, and the first detection line is configured to correspond to two rows (nth row and n + th row) in the sub-pixel row group 200.
  • (1 row) sub-pixels are connected and used to detect the electrical characteristics of the first transistor or light-emitting element in the two rows of sub-pixels.
  • any one of the plurality of detection line structures is not located between two adjacent sub-pixel row groups 200, that is, in the embodiment shown in FIG. 3A, no first sub-pixel row group 200 exists. ⁇ ⁇ ⁇ 111 ⁇ A detection line 111.
  • each m sub-pixel 100 constitutes a pixel unit
  • the m sub-pixels each include, for example, light emitting elements emitting different colors of light, thereby achieving color display.
  • m 2, 3, or 4.
  • m sub-pixels in a pixel unit are arranged in one or two rows.
  • the first detection line 111 is disposed between two rows of sub-pixels in the same pixel unit so that the sub-pixels in the same pixel unit are shared The same first detection line 111.
  • every two rows of sub-pixels share a first detection line, which reduces the number of first detection lines by half. Therefore, the overlap between the first detection line and the data line is reduced, which can not only improve the product yield, but also reduce the parasitic capacitance between the lines.
  • a first power line 113 is disposed between two adjacent sub-pixel row groups 200, and each first power line 113 is configured to connect to two adjacent sub-pixels 120 and provide a first power signal, such as A power supply voltage VDD.
  • a first power signal such as A power supply voltage VDD.
  • the plurality of first power supply lines 113 and the plurality of first detection lines 111 are alternately distributed along the second direction D2.
  • the array substrate provided by the embodiment of the present disclosure further shares the first power line 113, reducing the number of the first power lines 113, thereby reducing the overlap of the first power line and the data line, which further improves Product yield and reduce parasitic capacitance between lines.
  • each detection line structure 110 may include a plurality of first detection lines 111 sequentially arranged along the first direction D1 and insulated from each other, and a plurality of first detection lines 111 in the plurality of detection line structures 110. Forms a detection line array arranged in multiple rows and columns along the first direction D1 and the second direction D2. Each first detection line 111 corresponds to at least two sub-pixels 100 located in the same row, that is, a row of sub-pixels is divided into The plurality of regions are respectively connected to a plurality of first detection lines 111 in one detection line structure 110.
  • the array substrate 10 includes a plurality of pixel units 130 arranged in an array, and each pixel unit 130 includes m sub-pixels 100.
  • the m sub-pixels 100 are located in the same row, that is, each pixel unit 130 is distributed in The same line.
  • the positional relationship between the first detection line 111 and the pixel unit 130 is mainly shown in FIG. 3B, and the connection relationship between the first detection line 111 and the sub-pixels in the pixel unit 130 is not shown, and FIG. 3B only The connection relationship between the first detection line 111 and the pixel unit 130 in one detection line structure 110 is schematically shown.
  • the array substrate includes a plurality of second detection lines 112, each of which extends along a second direction D2, and corresponds to the first detection lines 111 in the detection line array one by one and is electrically connected to each other.
  • a plurality of first detection lines 111 located in each column of the detection line array are electrically connected to each other through a corresponding second detection line 112.
  • the plurality of first detection lines 111 located in the same detection line structure 110 (that is, located in the same row) are respectively electrically connected to different second detection lines 112. It can be understood that each first detection line 111 corresponds to two adjacent rows of sub-pixels.
  • a row of sub-pixels is divided into multiple areas and connected to multiple first detection lines to receive detection signals respectively.
  • the charging speed of each first detection line can be increased, thereby Increase detection speed.
  • each first detection line 111 is correspondingly connected to one or two pixel units in the same row, thereby preventing each first detection line 111 from being connected due to connection. Too many sub-pixels affect its signal transmission rate, such as the charging rate of the first detection line.
  • one first detection line 111 corresponds to four sub-pixels connected to one pixel unit in the same row.
  • the second detection line corresponding to the first detection line 111 is disposed in the middle of the four sub-pixels.
  • the four sub-pixels are symmetrically disposed with respect to the second detection line.
  • one pixel unit includes three sub-pixels 100 (for example, three kinds of RGB sub-pixels), and one first detection line 111 corresponds to six sub-pixels connected to two pixel units in the same row.
  • the second detection line corresponding to the first detection line 111 is disposed in the middle of the six sub-pixels.
  • the six sub-pixels are symmetrically disposed with respect to the second detection line.
  • the array substrate includes a plurality of sub-pixels arranged in an array structure of multiple rows and columns along the first direction D1 and the second direction D2. At least one of the sub-pixels in each row includes a light-emitting element and drives the light-emitting element to emit light.
  • Pixel circuit For example, the array substrate is an array substrate of an organic light-emitting diode (OLED) display panel, and the light-emitting element of the sub-pixel is an OLED.
  • the pixel circuit is, for example, the 3T1C pixel circuit described above or other functions with compensation and reset based on the 3T1C pixel circuit Pixel circuit.
  • each detection line structure 110 includes a plurality of first detection lines 111 that are sequentially arranged in a first direction D1 and are insulated from each other.
  • Each first detection line 111 corresponds to two pixel units 130 in the same row.
  • different first detection lines 111 are respectively connected to different second detection lines 112.
  • a second detection line 112 connected to the first detection line 111 is disposed between two pixel units 130 corresponding to the first detection line 111.
  • the adjacent pixel units 130 in the x-th column and the (x + 1) -th column constitute a pixel unit column group 210 (shown by a vertical dashed box in FIG. 3B), and x is an odd or even number greater than 0.
  • a second power line 114 is disposed between the adjacent pixel unit column groups 210, and the second power line extends along the second direction D2 and cross-connects the first power line 113.
  • the plurality of second power lines 114 and the plurality of second detection lines 112 are alternately arranged in the first direction D1.
  • FIGS. 1B-1C The following still takes the 3T1C pixel circuit shown in FIGS. 1B-1C as an example and further describes the array substrate provided by the embodiment of the present disclosure with reference to FIGS. 4A-4B.
  • the embodiment of the present disclosure does not limit the specific structure of the pixel circuit.
  • FIG. 4A is a schematic diagram of an array substrate provided by an embodiment of the present disclosure. For clarity, only a part of the sub-pixel array (3 rows and 6 columns of sub-pixels 100) in the array substrate is shown in the figure. For each row of sub-pixels 100, only a portion corresponding to one first detection line 111 is shown. For example, the sub-pixel array includes a plurality of sub-pixel array portions shown in FIG. 4A.
  • the array substrate is an array substrate of an organic light emitting diode (OLED) display panel
  • the light emitting element of the sub-pixel is an OLED.
  • three adjacent sub-pixels 100 in each row of sub-pixels constitute one pixel unit 130, that is, two pixel units 130 are shown in each row of sub-pixels in FIG. 4A.
  • one first detection line 111 corresponds to 6 sub-pixels located in the same row.
  • One first detection line 111 corresponds to two pixel units 130 located in the same row.
  • a plurality of first scan lines 141 extend along the first direction D1, and are respectively connected to the gates of the second transistors T2 in the plurality of rows of sub-pixels to provide the first Scan signal SCN1.
  • the first scan line 141 is also connected to the gate of the third transistor T3 in the correspondingly connected sub-pixel to provide a second scan signal. That is, in the embodiment shown in FIG. 4A, the first scan signals SCN1 and SCN1 The second scan signals SCN2 are all scan signals provided by the first scan lines 114.
  • the second transistor T2 and the third transistor T3 are arranged side by side in the first direction D1, and the channel length direction of the second transistor T2 and the channel length direction of the third transistor T3 are both along the second The direction D2 is parallel to the second direction D2.
  • each sub-pixel row group 200 (shown as a large dashed box in FIG. 4A)
  • two first scanning lines 141 connected to the n-th row and the (n + 1) -th row of sub-pixels are respectively disposed in the n-th row.
  • the n + 1th row of subpixels are respectively disposed in the n-th row.
  • a first detection line 111 (detection line structure 110) connected to the n-th and n + 1-th rows of sub-pixels 120 (shown as small dashed boxes in FIG. 4A) is provided in the Between the two first scanning lines 141 to which the nth and n + 1th rows of sub-pixels are connected respectively, and the two first scanning lines 111 are symmetrical with respect to the first detection line 111 (detection line structure 110) Settings.
  • each sub-pixel row group 200 the n-th and n + 1-th sub-pixels are symmetrically disposed with respect to the detection line structure 110 connected thereto.
  • the n-th and n + 1-th rows of sub-pixels, and the two first scanning lines 141 respectively connected to the n-th and n + 1-th rows of sub-pixels are respectively detected with respect to the same detection.
  • the line structure 110 (that is, the detection line structure 110 connected to the n-th row and the (n + 1) -th sub-pixel) is disposed symmetrically.
  • each first detection line 111 shown in FIG. 4A corresponds to two pixel units 130 in the same row
  • a second detection line 112 connected to the first detection line 111 is provided on the first detection line 111 between the correspondingly connected two pixel units 130, and the two pixel units 130 correspondingly connected to the first detection line 111 are symmetrically disposed with respect to the second detection line 112.
  • the y-th and y + 1-th sub-pixels 100 are arranged symmetrically with respect to the second direction D2, where y is an odd number.
  • the adjacent two sub-pixel row groups 200 are symmetrically disposed with respect to the first power line 113 located between the adjacent two sub-pixel row groups 200.
  • FIG. 4B is a schematic diagram of an array substrate provided by another embodiment of the present disclosure.
  • the array substrate is an array substrate of an organic light emitting diode (OLED) display panel
  • the light emitting element of the sub-pixel is an OLED.
  • FIG. 4B shows only a part of the sub-pixel array (3 rows and 3 columns of sub-pixels) in the array substrate. For each row of sub-pixels 100, only a portion corresponding to one first detection line 111 is shown.
  • the sub-pixel array includes a plurality of sub-pixel array portions shown in FIG. 4B.
  • the three sub-pixels in each row emit red light, green light, and blue light respectively to form a pixel unit.
  • the embodiment of the present disclosure does not limit this.
  • the array substrate 10 further includes a plurality of second scan lines 142 extending along the first direction D1, and the plurality of second scan lines 142 are respectively connected to the rows of sub-pixels in a one-to-one manner and are respectively connected to the corresponding ones.
  • the gate of the third transistor T3 in the sub-pixel is connected to provide the second scan signal SCN2, that is, the gates of the second transistor T2 and the third transistor T3 are connected to the first scan line 141 and the second scan line, respectively. 142.
  • the first scan signal SCN1 and the second scan signal SCN2 are provided by different signal lines, respectively.
  • the detection line structure 110 connected to the n-th and n + 1-th rows of sub-pixels is disposed at two respectively connected to the n-th and n + 1-th rows of sub-pixels.
  • the detection line structure 110 is disposed symmetrically with respect to the detection line structure 110.
  • FIG. 5 shows a cross-sectional view of the array substrate shown in FIG. 4A along a section line A-A '.
  • the array substrate is an array substrate of an organic light emitting diode (OLED) display panel
  • the light emitting element of the sub-pixel is an OLED.
  • the light emitting element 170 includes a first electrode 131, a light emitting layer 132, and a second electrode 133.
  • One of the first electrode 131 and the second electrode 133 is an anode, and the other is a cathode.
  • the light emitting element 170 is an organic light emitting diode.
  • the light emitting element may include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and the like in addition to the light emitting layer 132.
  • the first transistor T1 includes a gate 151, an active layer 152, a source 153, and a drain 154.
  • the embodiment of the present disclosure does not limit the type, material, and structure of the first transistor T1.
  • it may be a top-gate type, a bottom-gate type, and the like.
  • the active layer of the first transistor T1 may be amorphous silicon or polysilicon (for example, low temperature). Polysilicon or high-temperature polysilicon), an oxide semiconductor (such as IGZO), and the first transistor T1 may be an N-type or a P-type.
  • the light emitting element 170 is a top emission structure
  • the first electrode 131 is reflective and the second electrode 133 is transmissive or semi-transmissive.
  • the first electrode 131 is a material with a high work function to serve as an anode, such as an ITO / Ag / ITO laminated structure
  • the second electrode 133 is a material with a low work function to serve as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag / Mg alloy material.
  • the light-transmitting regions that is, regions other than transistors, blank areas in the figure
  • the detection line structure 110 is not provided in a one-to-one correspondence with multiple rows of sub-pixels. Therefore, the light-emitting elements of the top emission structure can make the light-emitting elements evenly distributed and not limited to the light-transmitting area of the pixels, which helps the display panel to achieve uniformity. Display effect.
  • FIG. 6 shows a simulation comparison between the array substrate shown in FIG. 4A and the array substrate shown in FIG. 2.
  • Curve A shows the charging process of the first detection line in the array substrate shown in FIG. 2
  • curve B shows the charging process of the first detection line in the array substrate shown in FIG. 4A.
  • the two array substrates have the same features (eg, dimensions, materials, etc.) except for the differences in the layout design shown.
  • the time required to charge the voltage of the first detection line from 0 to 2V is about 120 ⁇ s; and the array substrate provided in the embodiment of the present disclosure shown in FIG. 4A is the first
  • the time required to charge the voltage of a detection line from 0 to 2V is about 96 ⁇ s.
  • the charging speed is increased by 25%.
  • an embodiment of the present disclosure further provides a display panel 300 including the above-mentioned array substrate 10.
  • the display panel is an OLED display panel, and accordingly, the array substrate included therein is an OLED array substrate, and the light-emitting element of the sub-pixel is an OLED.
  • the display panel further includes an encapsulation layer 301 and a cover plate 302 disposed on the array substrate 10, and the encapsulation layer 301 is configured to seal the light emitting element 170 to prevent external moisture and oxygen from reaching the light emitting element and the pixel circuit. Infiltration can cause damage to the device.
  • the encapsulation layer 301 includes an organic thin film or a structure including an organic thin film and an inorganic thin film alternately stacked.
  • a water-absorbing layer (not shown) may be further disposed between the packaging layer 301 and the array substrate 10, and configured to absorb the moisture or sol remaining in the light-emitting element 170 during the previous manufacturing process.
  • the cover plate 302 is, for example, a glass cover plate.
  • the cover plate 302 and the packaging layer 301 may be an integrated structure.
  • An embodiment of the present disclosure further provides a detection method for detecting the above-mentioned array substrate.
  • the detection method includes: selecting a target sub-pixel among the plurality of sub-pixels, and applying a detection signal to the target sub-pixel in the sub-pixel array. ; Acquiring the electrical characteristics of the first transistor or light-emitting element in the sub-pixel through a detection line structure (first detection line) connected to the target sub-pixel.
  • a target sub-pixel is selected by applying a corresponding gate signal to the sub-pixel.
  • the third transistor T3 can be turned on by applying a gate signal to it, thereby allowing the detection circuit 11 to apply a detection signal to the first transistor T1 via the third transistor T3 to perform detection.
  • the specific process please refer to the description of FIG. 1C above, which will not be repeated here.
  • each sub-pixel row group 200 A detection line structure 110 is disposed between the two rows of sub-pixels 100, and the detection line structure 110 is configured to be connected to two sub-pixels (nth and n + 1th) of the sub-pixel row group 200 and used For detecting the electrical characteristics of the first transistors or light-emitting elements in the two rows of sub-pixels.
  • each sub-pixel row group 200 a time-division multiplexing method is required, so that the first detection line 110 in the shared detection line structure 110 can be time-divisionally connected to each sub-pixel in the sub-pixel row group 200. Pixels, each sub-pixel in the sub-pixel row group 200 is detected. For example, for the above 3T1C pixel circuit, whether to select a certain target sub-pixel can be determined by whether the third transistor T3 is turned on. For the above 3T1C pixel circuit, when a detection control signal is applied, the detection method refers to the foregoing description, for example, and is not repeated here.

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Abstract

一种阵列基板(10)及其检测方法、显示面板(300)，阵列基板(10)包括多个子像素(100)以及多个检测线结构(110)，多个子像素(100)沿第一方向(D1)和第二方向(D2)排布为多行多列的阵列，第一方向(D1)和第二方向(D2)相交。每个检测线结构(110)包括至少一条沿第一方向(D1)延伸的第一检测线(111)；每行子像素中的至少一个子像素(100)包括发光元件(OLED)以及驱动发光元件发光的第一晶体管(T1)，阵列中相邻的第n行和第n+1行子像素(100)构成一个子像素行组(200)，每个子像素行组(200)中的两行子像素(100)之间设置有一个检测线结构(110)，且检测线结构(110)配置为与第n行和第n+1行子像素(100)连接并用于检测子像素(100)中的第一晶体管(T1)或发光元件(OLED)的电特性，n为大于0的奇数或偶数。阵列基板(10)通过相邻行子像素交替共用检测线结构(110)而减小了检测线结构(110)的数量，从而减小了检测线与数据线（140）的交叠，这不仅能够降低寄生电容，还能提高产品良率。

Description

阵列基板及其检测方法、显示面板
本申请要求于2018年9月27日递交的中国专利申请第201811134277.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种阵列基板及其检测方法、显示面板。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。外部补偿电路被广泛应用于OLED显示面板中以使得显示面板具有均匀的显示效果。
发明内容
本公开至少一个实施例提供一种一种阵列基板，包括多个子像素以及多个检测线结构，所述多个子像素沿第一方向和第二方向排布为多行多列的阵列，所述第一方向与所述第二方向相交；每个检测线结构包括至少一条沿所述第一方向延伸的第一检测线；每行子像素中的至少一个子像素包括发光元件以及驱动所述发光元件发光的第一晶体管，所述阵列中相邻的第n行和第n+1行子像素构成一个子像素行组，每个子像素行组中的所述第n行和第n+1行子像素之间设置有一个所述检测线结构，且所述检测线结构配置为与所述第n行和第n+1行子像素连接并用于检测所述第n行和第n+1行子像素中的第一晶体管或发光元件的电特性，n为大于0的奇数或偶数。
在一些示例中，所述多个检测线结构中的任一个不位于相邻的两个子像素行组之间。
在一些示例中，所述阵列基板还包括沿所述第一方向延伸的多条第一电源线，所述第一电源线设置于相邻的两个子像素行组之间，每条所述第一电源线配置为和与之相邻的两行子像素连接并提供第一电源信号。
在一些示例中，所述多条第一电源线与所述多个检测线结构在所述第二方向上交替分布。
在一些示例中，所述相邻的两个子像素行组相对于位于所述相邻的两个子像素行组之间的所述第一电源线对称设置。
在一些示例中，所述阵列基板还包括多条第二电源线，所述多条第二电源线沿所述第二方向延伸，且分别与所述多条第一电源线交叉电连接。
在一些示例中，每个检测线结构包括多条第一检测线，所述多条第一检测线沿所述第一方向依次布置且彼此绝缘，所述多个检测线结构中的多条第一检测线构成沿所述第一方向和所述第二方向排布为多行多列的检测线阵列；每条所述第一检测线对应连接位于同一行的至少两个所述子像素。
在一些示例中，所述阵列基板还包括多条第二检测线，所述多条第二检测线沿所述第二方向延伸，且分别与所述检测线阵列中的多列第一检测线一一对应且交叉电连接，位于同一列的多条第一检测线通过所对应的一条第二检测线彼此电连接。
在一些示例中，位于同一行的每m个子像素构成一个像素单元，每条第一检测线对应连接所述同一行中的1个或2个所述像素单元，m＝2、3或4。
在一些示例中，每条所述第一检测线对应连接2个所述像素单元，与每条所述第一检测线连接的所述第二检测线设置于所述第一检测线所对应连接的2个像素单元之间。
在一些示例中，所述子像素还包括第二晶体管、第三晶体管和第一电容；所述第二晶体管的栅极和第一极分别配置为接收第一扫描信号和数据信号，所述第二晶体管的第二极连接所述第一晶体管的栅极；所述第一晶体管的第一极配置为接收第一电源信号，所述第一晶体管的第二极分别与所述第三晶体管的第一极以及所述发光元件的第一电极连接；所述第三晶体管的栅极配置为接收第二扫描信号，所述第三晶体管的第二极与所述子像素所连接的检测线结构电连接；所述发光元件的第二电极配置为接收第二电源信号；所述第一电容的一端连接所述第一晶体管的栅极，另一端连 接所述第一晶体管的第二极。
在一些示例中，所述阵列基板还包括沿所述第一方向延伸的多条第一扫描线，所述多条第一扫描线分别与多行子像素一一对应连接，并分别与所对应连接的多行子像素中的第二晶体管的栅极连接以提供所述第一扫描信号。
在一些示例中，在每个子像素行组中，分别与所述第n行和第n+1行子像素连接的两条第一扫描线设置于所述第n行和第n+1行子像素之间。
在一些示例中，在每个子像素行组中，与所述第n行和第n+1行子像素连接的检测线结构设置于与所述第n行和第n+1行子像素所分别连接的两条第一扫描线之间。
在一些示例中，在每个子像素行组中，与所述第n行和第n+1行子像素所分别连接的两条第一扫描线相对于位于所述第n行和第n+1行子像素之间的检测线结构对称设置。
在一些示例中，所述第一扫描线还与所对应连接的子像素中的第三晶体管的栅极连接以提供所述第二扫描信号。
在一些示例中，所述阵列基板还包括沿所述第一方向延伸的多条第二扫描线，所述多条第二扫描线分别与多行子像素一一对应连接，并分别与所对应连接的子像素中的第三晶体管的栅极连接以提供所述第二扫描信号。
在一些示例中，所述第二晶体管和所述第三晶体管沿所述第一方向并列设置，且所述第二晶体管的沟道长度方向和所述第三晶体管的沟道长度方向均与所述第二方向平行。
在一些示例中，在每个子像素行组中，所述第n行和第n+1行子像素相对于与其相连的检测线结构对称设置。
在一些示例中，所述发光元件为顶发射有机发光二极管。
本公开至少一实施例还提供一种显示面板，包括上述阵列基板。
本公开至少一实施例还提供一种检测方法，用于上述阵列基板，所述检测方法包括：在所述多个子像素之中选择目标子像素；对于所述子像素 阵列中的所述目标子像素施加检测信号；通过与所述目标子像素连接的检测线结构获取所述目标子像素中的第一晶体管或发光元件的电特性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是一种阵列基板的框图；
图1B是一种阵列基板的电路示意图；
图1C是一种3T1C像素电路的示意图；
图2为一种阵列基板的版图结构示意图；
图3A为本公开实施例提供的阵列基板的示意图之一；
图3B为本公开实施例提供的阵列基板的示意图之二；
图4A为本公开实施例提供的阵列基板的示意图之三；
图4B是本公开实施例提供的阵列基板的示意图之四；
图5示出了本公开实施例提供的阵列基板的剖视图；
图6示出了图4A所示的阵列基板与图2所示的阵列基板的仿真对比图；
图7为本公开实施例提供的显示面板的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第 一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1A是一种阵列基板10的框图，图1B是一种阵列基板的电路示意图。如图1A和图1B所示，阵列基板10包括沿第一方向D1和第二方向D2分布为多行多列的阵列结构的多个子像素100，每个子像素100包括发光元件以及驱动该发光元件发光的像素电路。例如，该阵列基板是有机发光二极管(OLED)阵列基板，该发光元件为OLED。该显示面板还包括多条扫描线、多条数据线以用于为该多个子像素提供扫描信号和数据信号，从而驱动该多个子像素。根据需要，该显示面板还可以进一步包括电源线、感测线等。
例如，每m个子像素100构成一个像素单元，该m个子像素例如分别包括发出不同颜色(基础色)光的OLED，从而实现彩色显示。例如，m＝2、3或4。例如，一个像素单元包括三个子像素100，三个子像素分别发出红光(R)、绿光(G)和蓝光(B)。又如，一个像素单元包括RGBW四个子像素100，三个子像素分别发出红光(R)、绿光(G)、蓝光(B)和白光(W)。为了使得像素单元发出彩色光，可以有多种实现方式，其包括但不限于，使用发出三原色光的OLED，或者使用发出白光的OLED配合彩色滤光片，或者使用发出蓝光的OLED配合光转换材料(例如荧光层或量子点层)等。
图1C示出了一种用于OLED阵列基板(显示面板)的3T1C像素电路的示意图。根据需要，该像素电路还可以进一步包括补偿电路、复位电路等。请一并参照图1B和图1C，该像素电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第一电容C1以及第一检测线111。第一晶体管T1 的第一极连接第一电源线113，第二极分别连接OLED的阳极和第三晶体管T3的第一极，栅极连接第二晶体管T2的第二极，第一晶体管T1是驱动OLED发光的驱动晶体管。第二晶体管T2的栅极连接第一扫描线141以接收第一扫描信号SCN1，第一极连接数据线以接收数据信号DT。第一电容C1连接于第一晶体管T1的栅极和第二极之间。OLED的阴极连接到第二电源电源电压VSS，例如接地。第三晶体管T3的栅极连接第二扫描线142以接收第二扫描信号SCN2，第二极连接第一检测线111连接检测电路11以接收检测信号SE。第一检测线111配置为检测第一晶体管T1的电特性，该电特性例如包括第一晶体管T1的阈值电压和/或载流子迁移率，第一检测线111还可以配置为检测OLED的电特性，包括OLED的阈值电压、驱动电流等。例如，第一检测线111与检测电路11连接，从而将像素电路的电信号输出到检测电路11以进行分析和检测。该检测电路例如为包括数模转换器(DAC)和模数转换器(ADC)等的常规电路，本公开的实施例对此不作赘述。
例如，第一扫描线141和第二扫描线142可以是不同的扫描线，也即第一扫描信号SCN1和第二扫描信号SCN2可以为不同扫描线提供的信号。第一扫描信号SCN1和第二扫描信号SCN2也可以为同一扫描线提供的同一信号，也即第一扫描线141和第二扫描线142可以是相同的扫描线。第一扫描信号SCN1和第二扫描信号SCN2可以根据需要相同或不同。
例如，该3T1C像素电路的一种检测过程包括对其施加检测控制信号，然后通过与之连接的检测线获取驱动晶体管的电特性，具体如下所述。在写入阶段，第一扫描信号SCN1和第二扫描信号SCN2均为开启信号，第二晶体管T2和第三晶体管T3均导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极以及第一电容C1的第一电极，检测信号SE经第三晶体管T3传输至第一晶体管T1的第二极以及第一电容C1的第二电极，该检测信号SE的电压未达到OLED的点亮电压，因此OLED不发光。之后，将第一检测线111浮置，第二晶体管T2和第三晶体管T3均导通，在第一电源电压VDD的作用下，第一晶体管T1中产生驱动电流并将第一电容C1的第二电极充电至电压Vdata-Vth，其中，Vdata为数据信号DT的电压，Vth为第一晶体管T1的阈值电压。此时，第一晶体管T1由开启状态转为截止状 态。在检测阶段，第一扫描信号SCN1和第二扫描信号SCN2均为开启信号，第二晶体管T2和第三晶体管T3均导通，利用检测电路11通过第一检测线111对于第一晶体管T1的第二极(也即第一电容C1的第二电极)上的饱和电压Vdata-Vth进行采样，从而得到第一晶体管T1的阈值电压这一电特性。在该检测过程中，检测控制信号包括施加至第二晶体管T2、第三晶体管T3的扫描信号、数据信号、检测信号等。
例如，该3T1C像素电路的另一种检测过程包括：对其施加检测控制信号，然后通过与之连接的检测线获取发光元件的电特性，具体如下所述。在第一阶段，第一扫描信号SCN1为关闭信号，第二扫描信号SCN2为开启信号，第二晶体管T2关断，第三晶体管T3导通，第一检测线111通过第三晶体管T3向OLED的阳极写入复位信号；在第二阶段，第一扫描信号SCN1为开启信号，第二扫描信号SCN2为关闭信号，第二晶体管T2导通，第三晶体管T3关断，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极，第一晶体管T1导通并产生驱动电流将OLED的阳极充电至工作电压；在第三阶段，第一扫描信号SCN1为关闭信号，第二扫描信号SCN2为开启信号，第二晶体管T2关断，第三晶体管T3导通，第一检测线111再次通过第三晶体管T3向OLED的阳极写入复位信号，此时由于第一电容C1的自举效应，第一电容C1两端的电压保持不变，将第一检测线111进行浮置，第一晶体管T1对第一检测线111进行充电直至饱和，再利用检测电路11对第一检测线111上的饱和电压取样从而得到OLED的电特性。在这个示例中，可以分别设置第一扫描线和第二扫描线以分别提供第一扫描信号SCN1和第二扫描信号SCN2。同样，在该检测过程中，检测控制信号包括施加至第二晶体管T2、第三晶体管T3的扫描信号、数据信号、检测信号等。
例如，如图1A所示，阵列基板10还可以包括数据驱动电路13和扫描驱动电路14。数据驱动电路13配置为根据需要(例如输入显示装置的图像信号)可发出数据信号，例如上述数据信号DT；每个子像素的像素电路还配置为接收该数据信号并将该数据信号施加至该第一晶体管的栅极。扫描驱动电路14配置为输出各种扫描信号，例如包括上述第一扫描信号SCN1和第二扫描信号SCN2，其例如为集成电路芯片或者为直接制备在显示基板 上的栅驱动电路(GOA)。
例如，阵列基板10还包括控制电路12。例如，控制电路12配置为控制数据驱动电路13施加数据信号，以及控制栅极驱动电路施加扫描信号。该控制电路12的一个示例为时序控制电路(T-con)。控制电路12可以为各种形式，例如包括处理器121和存储器122，存储器121包括可执行代码，处理器121运行该可执行代码以执行上述检测方法。
例如，处理器121可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置122可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器121可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据，例如在上述检测方法中获取的电特性参数等。
图2为一种阵列基板的版图结构示意图，图2中仅示出了该阵列基板中像素阵列的一部分。如图2所示，多条第一检测线111沿第一方向(例如为阵列的行方向)D1延伸，分别与多行子像素对应连接；多条第一扫描线G1、G2沿第一方向D1延伸，分别与多行子像素对应连接；多条第一电源线113沿第一方向D1延伸，分别与多行子像素连接；也即，每一行子像素分别配置有一条第一检测线、第一扫描线以及第一电源线。多条数据线140沿第二方向(例如为阵列的列方向)D2延伸，分别与多列子像素对应连接，例如分别与第一红色子像素列、第一绿色子像素列、第一蓝色子像素列、第二红色子像素列、第二绿色子像素列、第二蓝色子像素列等对应连接。该阵列基板包括还包括沿第二方向D2延伸的第二检测线112以及多条第二电源线114，该第二检测线112分别与多条第一检测线111交叉电连接从而将不同行的多条第一检测线111彼此电连接，这些第二电源线114与多条第一电源线113交叉电连接。第一方向D1和第二方向D2相交，例如彼此正 交。
第一电源线113和第一检测线111在垂直于阵列基板的方向上均与沿第二方向D2延伸的数据线发生交叠从而产生寄生电容，该交叠部分例如如图2中虚线框所示。该交叠部分产生的寄生电容，不仅影响了数据线以及第一检测线上的信号传输效率，还容易因静电等因素引起短路等良率问题。
本公开实施例提供一种阵列基板，在该阵列基板的子像素阵列中，相邻的第n行和第n+1行子像素构成一个子像素行组，每个子像素行组的两行子像素之间设置有一个检测线结构，该检测线结构包括至少一条第一检测线，且该检测线结构配置为与第n行和第n+1行子像素连接并用于检测子像素中的第一晶体管或发光元件的电特性，其中n为大于0的奇数或偶数。例如，n＝1、3、5……；或者n＝2、4、6……。
该阵列基板通过相邻行子像素交替共用检测线结构而减小了检测线结构(第一检测线)的数量，进而减小了检测线结构中的第一检测线与数据线的交叠，这不仅能够提高产品良率，还降低了线间寄生电容，例如将第一检测线的寄生电容降低了20％左右，为高分辨率(PPI)的显示面板实现高频驱动提供了技术支持。
需要说明的是，本公开实施例中的“检测线结构”可以仅包括一条沿第一方向延伸的第一检测线，也即一行子像素共用同一条第一检测线(如图3A所示)；该检测线结构也可以包括沿第一方向依次排布的彼此绝缘的多条第一检测线(如图3B所示)，在这种情形，将一行子像素分为多个区分别与多条第一检测线连接以分别接收检测信号，通过在一行设置多条第一检测线分区提供检测信号，可以提高每条第一检测线的充电速度，从而提高检测速度。
还需要说明的是，本公开中“行”和“列”不一定是沿直线分布，可能是沿曲线分布，如呈蛇形状等。相应地，第一检测线(或检测线结构)总体趋势是沿第一方向延伸，但并不一定沿直线延伸。
图3A为本公开实施例提供的阵列基板的示意图之一，该阵列基板包括多个子像素，多个子像素沿第一方向D1和第二方向D2分布为多行多列的的阵列，每行子像素中的至少一个包括发光元件以及驱动该发光元件发光 的像素电路。例如，该阵列基板为有机发光二极管(OLED)显示面板的阵列基板，子像素的发光元件为OLED，该像素电路例如为上述3T1C像素电路或其他基于上述3T1C像素电路的具有补偿、复位等功能的像素电路，本公开的实施例对此不作限制。例如，该阵列基板包括显示区和显示区外的周边区，该像素阵列可以仅位于显示区内，在这种情形，该像素阵列中的每个子像素都包括该发光元件和该像素电路；在另一些示例中，该像素阵列还可以包括位于该周边区的部分，例如包括位于周边区的虚设子像素(dummy pixel)，该虚设子像素并不进行发光，例如并不包括发光元件或者像素电路。
图3A中示出了每个检测线结构110包括一条第一检测线111的示例。为了清楚表示本公开实施例中子像素共用第一检测线111的特征，图3A中简略地表示出一行子像素120，并仅示出了第一检测线111和第一电源线113，为清楚起见省略了第二检测线、第二电源线和数据线等信号线。图中与一行子像素120的连接关系代表与该行子像素120中的每个子像素100均连接。
如图3A所示，相邻的第n行和第n+1行子像素120构成一个子像素行组200(图3A中虚线框所示)，n为大于0的奇数或偶数。每个子像素行组200的两行子像素100之间设置有一条第一检测线111，且该第一检测线配置为与该子像素行组200中的两行(第n行和第n+1行)子像素连接并用于检测该两行子像素中的第一晶体管或发光元件的电特性。例如，多个检测线结构中的任一个不位于相邻的两个子像素行组200之间，也即在图3A所示实施例中，相邻的两个子像素行组200之间不存在第一检测线111。
例如，每m个子像素100构成一个像素单元，该m个子像素例如分别包括发出不同颜色光的发光元件，从而实现彩色显示。例如，m＝2、3或4。例如，一个像素单元中的m个子像素排列为一行或者两行。例如，在一个像素单元中的m个子像素排列为两行的情形，该第一检测线111设置于同一个像素单元中的两行子像素之间，以使得同一个像素单元中的子像素共用同一条第一检测线111。
比起每一行子像素分别配置一条第一检测线的技术方案，在本公开实施例提供的阵列基板，每两行子像素共用一条第一检测线，将第一检测线 的数量减少了一半，从而减小了第一检测线与数据线的交叠，不仅能够提高产品良率，还降低了线间寄生电容。
例如，相邻的两个子像素行组200之间设置一条第一电源线113每条第一电源线113配置为和与之相邻的两行子像素120连接并提供第一电源信号，例如第一电源电压VDD。例如，在该子像素阵列中，多条第一电源线113与多条第一检测线111沿第二方向D2交替分布。
这样一来，本公开实施例提供的阵列基板进一步共用了第一电源线113，减少了第一电源线113的数量，从而减小了第一电源线与数据线的交叠，这进一步提高了产品良率，并降低了线间寄生电容。
图3B为本公开实施例提供的阵列基板的示意图之二。例如，如图3B所示，每个检测线结构110可以包括沿第一方向D1依次布置且彼此绝缘的多条第一检测线111，多个检测线结构110中的多条第一检测线111构成沿第一方向D1和第二方向D2排布为多行多列的检测线阵列，每条第一检测线111对应连接位于同一行中的至少两个子像素100，也即将一行子像素分为多个区，分别与一个检测线结构110中的多条第一检测线111连接。
如图3B所示，阵列基板10包括阵列排布的多个像素单元130，每个像素单元130包括m个子像素100，例如该m个子像素100位于同一行，也即每个像素单元130分布在同一行。为了清楚起见，图3B中主要示出了第一检测线111与像素单元130的位置关系，并未示出第一检测线111与像素单元130中的子像素的连接关系，并且图3B中仅仅示意性地示出了一个检测线结构110中的第一检测线111与像素单元130的连接关系。
例如，该阵列基板包括多条第二检测线112，每条第二检测线112沿第二方向D2延伸，且分别与检测线阵列中的多列第一检测线111一一对应且交叉电连接，位于该检测线阵列中的每一列的多条第一检测线111通过所对应的一条第二检测线112彼此电连接。位于同一个检测线结构110中的(也即位于同一行的)多条第一检测线111分别与不同的第二检测线112电连接。可以理解，每条第一检测线111对应连接与之相邻的两行子像素，这里仅描述其中一行子像素与该第一检测线111之间的连接情形，另一行子像素的连接情形与此类似，不再赘述。将一行子像素分为多个区分别与多条第 一检测线连接以分别接收检测信号，通过设置多条第一检测线分区提供检测信号，可以提高每条第一检测线的充电速度，从而提高检测速度。
例如，在像素单元中的多个子像素分布在同一行中的情形，每条第一检测线111对应连接同一行中的1个或2个像素单元，从而避免每条第一检测线111因连接过多子像素而影响其信号传输速率，例如该第一检测线的充电速率。
例如，在m＝4的情形，也即一个像素单元包括4个子像素100(例如为RGBW四种子像素)，一条第一检测线111对应连接同一行中1个像素单元的4个子像素，此时，该第一检测线111对应连接的第二检测线设置于该4个子像素的中间，例如该4个子像素相对于该第二检测线对称设置。
例如，在m＝3的情形，也即一个像素单元包括3个子像素100(例如为RGB三种子像素)，一条第一检测线111对应连接同一行中2个像素单元的6个子像素，此时，该第一检测线111对应连接的第二检测线设置于该6个子像素的中间，例如该6个子像素相对于该第二检测线对称设置。
继续参考图3B，该阵列基板包括沿第一方向D1和第二方向D2分布为多行多列的阵列结构的多个子像素，每行个子像素中的至少一个包括发光元件以及驱动该发光元件发光的像素电路。例如，该阵列基板为有机发光二极管(OLED)显示面板的阵列基板，子像素的发光元件为OLED，该像素电路例如为上述3T1C像素电路或其他基于上述3T1C像素电路的具有补偿、复位等功能的像素电路。
如图3B所示，每个检测线结构110包括沿第一方向D1依次布置且彼此绝缘的多条第一检测线111，每条第一检测线111对应连接同一行中2个像素单元130，且不同的第一检测线111分别连接到不同的第二检测线112。例如，与第一检测线111连接的第二检测线112设置于该第一检测线111所对应连接的两个像素单元130之间。
例如，相邻的第x列和第x+1列像素单元130构成一个像素单元列组210(图3B中纵向虚线框所示)，x为大于0的奇数或偶数。相邻的像素单元列组210之间设置有一条第二电源线114，该第二电源线沿第二方向D2延伸并与第一电源线113交叉连接。例如，多条第二电源线114与多条第二 检测线112在第一方向D1上交替排布。
以下仍然以图1B-1C所示的3T1C像素电路为例、并结合图4A-4B对本公开实施例提供的阵列基板进行进一步说明，然而，本公开实施例对于像素电路的具体结构不作限制。
图4A为本公开一实施例提供的阵列基板的示意图，为了清楚起见，图中仅示出了阵列基板中的子像素阵列的一部分(3行6列子像素100)。对于每一行子像素100，仅示出了一条第一检测线111所对应连接的部分。例如，该子像素阵列包括多个图4A所示的子像素阵列部分。
例如，该阵列基板为有机发光二极管(OLED)显示面板的阵列基板，子像素的发光元件为OLED。例如，每一行子像素中相邻的三个子像素100构成一个像素单元130，也即图4A在每行子像素中分别示出了两个像素单元130。例如，如图4A所示，一条第一检测线111对应连接位于同一行的6子像素。一条第一检测线111对应连接位于同一行的两个像素单元130。
请一并参照图1C、图3A-3B和图4A，多条第一扫描线141沿第一方向D1延伸，分别与多行子像素中的第二晶体管T2的栅极对应连接以提供第一扫描信号SCN1。
例如，第一扫描线141还与所对应连接的子像素中的第三晶体管T3的栅极连接以提供第二扫描信号，也即在图4A所示的实施例中，第一扫描信号SCN1和第二扫描信号SCN2均为由第一扫描线114提供的扫描信号。
例如，在一个子像素100中，第二晶体管T2和第三晶体管T3沿第一方向D1并列设置，且第二晶体管T2的沟道长度方向和第三晶体管T3的沟道长度方向均沿第二方向D2，也即与第二方向D2平行。
例如，在每个子像素行组200(如图4A中大虚线框所示)中，分别与第n行和第n+1行子像素连接的两条第一扫描线141设置于该第n行和第n+1行子像素之间。
例如，在每个子像素行组200中，与第n行和第n+1行子像素120(如图4A中小虚线框所示)连接的第一检测线111(检测线结构110)设置于与该第n行和第n+1行子像素所分别连接的两条第一扫描线141之间，且该两条第一扫描线111相对于该第一检测线111(检测线结构110)对称设置。
例如，在每个子像素行组200中，第n行和第n+1行子像素相对于与其相连的检测线结构110对称设置。在每个子像素组200中，第n行和第n+1行子像素、与该第n行和第n+1行子像素所分别连接的两条第一扫描线141分别相对于同一个检测线结构110(也即与第n行和第n+1行子像素连接的检测线结构110)对称设置。
例如，在图4A中示出的每条第一检测线111对应连接同一行中2个像素单元130的情形，与第一检测线111连接的第二检测线112设置于该第一检测线111所对应连接的两个像素单元130之间，且该第一检测线111所对应连接的2个像素单元130相对于该第二检测线112对称设置。
例如，对于每行子像素，第y与y+1个子像素100相对于第二方向D2轴对称设置，其中y为奇数。
例如，相邻的两个子像素行组200相对于位于该相邻的两个子像素行组200之间的第一电源线113对称设置。
图4B是本公开另一实施例提供的阵列基板的示意图。例如，该阵列基板为有机发光二极管(OLED)显示面板的阵列基板，子像素的发光元件为OLED。图4B中仅示出了该阵列基板中中的子像素阵列的一部分(3行3列子像素)，对于每一行子像素100，仅示出了一条第一检测线111所对应连接的部分。例如，该子像素阵列包括多个图4B所示的子像素阵列部分。例如，每行中的三个子像素分别发出红光、绿光和蓝光从而构成一个像素单元。然而，本公开实施例对此不作限制。
如图4B所示，阵列基板10还包括沿第一方向D1延伸的多条第二扫描线142，多条第二扫描线142分别与多行子像素一一对应连接，并分别与所对应连接的子像素中的第三晶体管T3的栅极连接以提供所述第二扫描信号SCN2，也即，第二晶体管T2和第三晶体管T3的栅极分别连接第一扫描线141和第二扫描线142，第一扫描信号SCN1和第二扫描信号SCN2分别由不同的信号线提供。
例如，在每个子像素行组200中，与第n行和第n+1行子像素连接的检测线结构110设置于与该第n行和第n+1行子像素所分别连接的两条第一扫描线141和两条第二扫描线142之间，且该两条第一扫描线141和两条第二 扫描线142分别相对于该检测线结构110对称设置。
图5示出了图4A所示阵列基板沿剖面线A-A’的剖视图。为了清楚起见，图中仅示出了第一晶体管T1和发光元件170。例如，该阵列基板为有机发光二极管(OLED)显示面板的阵列基板，子像素的发光元件为OLED。如图所示，发光元件170包括第一电极131、发光层132和第二电极133，第一电极131和第二电极133之一为阳极，另一个为阴极。例如，发光元件170为有机发光二极管。例如，发光元件除了发光层132之外还可以包括空穴注入层、空穴传输层、电子注入层、电子传输层等。
第一晶体管T1包括栅极151、有源层152、源极153和漏极154。本公开的实施例对于第一晶体管T1的类型、材料、结构不作限制，例如其可以为顶栅型、底栅型等，第一晶体管T1的有源层可以为非晶硅、多晶硅(例如低温多晶硅或高温多晶硅)、氧化物半导体(例如IGZO)等，且第一晶体管T1可以为N型或P型。
例如，发光元件170为顶发射结构，第一电极131具有反射性而第二电极133具有透射性或半透射性。例如，第一电极131为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极133为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
在本公开实施例提供的阵列基板中，例如请参照图4A和图4B，由于像素中的透光区域(也即晶体管以外的区域，图中的空白区)集中在检测线结构110的两侧，而检测线结构110并不与多行子像素一一对应设置，因此，顶发射结构的发光元件可以使得发光元件可以均匀分布而不局限于像素的透光区域，有助于显示面板实现均匀的显示效果。
图6示出了图4A所示的阵列基板与图2所示的阵列基板的仿真对比图。曲线A示出了图2所示的阵列基板中第一检测线的充电过程，曲线B示出了图4A所示的阵列基板中第一检测线的充电过程。用于比较的两个阵列基板，除了所示出的版图设计的区别之外，其他特征(例如尺寸、材料等)相同。如图所示，在图2所示的阵列基板中，第一检测线的电压从0充电到2V所需要的时间约为120μs；而图4A所示的本公开实施例提供的阵 列基板中第一检测线的电压从0充电到2V所需要的时间约为96μs，与图2所示的阵列基板相比，充电速度提高了25％。
如图7所示，本公开实施例还提供一种显示面板300，包括上述阵列基板10。例如，该显示面板为OLED显示面板，相应地其包括的阵列基板为OLED阵列基板，子像素的发光元件为OLED。例如，该显示面板还包括设置于阵列基板10上的封装层301和盖板302，该封装层301配置为对发光元件170进行密封以防止外界的湿气和氧向该发光元件及像素电路的渗透而造成对器件的损坏。例如，封装层301包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层301与阵列基板10之间还可以设置吸水层(未示出)，配置为吸收发光元件170在前期制作工艺中残余的水汽或者溶胶。盖板302例如为玻璃盖板。例如，盖板302和封装层301可以为一体的结构。
本公开实施例还提供一种检测方法，用于检测上述阵列基板，该检测方法包括：在所述多个子像素之中选择目标子像素，对于所述子像素阵列中的目标子像素施加检测信号；通过与该目标子像素连接的检测线结构(第一检测线)获取该子像素中的第一晶体管或发光元件的电特性。
例如，通过对子像素施加相应的栅信号来选择目标子像素。以图1C所示像素电路为例，可以通过对第三晶体管T3施加栅信号使第三晶体管导通，从而允许检测电路11经第三晶体管T3向第一晶体管T1施加检测信号以对进行检测。具体过程详见上文关于图1C的描述，此处不再赘述。
在本公开的实施例中，由于相邻的第n行和第n+1行子像素120构成一个子像素行组200(例如，图4A中大虚线框所示)，每个子像素行组200的两行子像素100之间设置有一个检测线结构110，且该检测线结构110配置为与该子像素行组200中的两行(第n行和第n+1行)子像素连接并用于检测该两行子像素中的第一晶体管或发光元件的电特性。为此，对于每个子像素行组200，需要采用分时复用的方法，使得被共享的检测线结构110中的第一检测线110可以分时连接到该子像素行组200中的各个子像素，对该子像素行组200中的各个子像素实现检测。例如对于上述3T1C像素电路，可以通过是否开启第三晶体管T3来确定是否选择某一目标子像素。对于上述3T1C像素电路，在施加了检测控制信号的情况下，该检测方法例如 参照前文的描述，此处不再赘述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (22)

  1. 一种阵列基板，包括多个子像素以及多个检测线结构，所述多个子像素沿第一方向和第二方向排布为多行多列的阵列，所述第一方向与所述第二方向相交；
    每个检测线结构包括至少一条沿所述第一方向延伸的第一检测线；
    每行子像素中的至少一个子像素包括发光元件以及驱动所述发光元件发光的第一晶体管，
    其中，所述阵列中相邻的第n行和第n+1行子像素构成一个子像素行组，每个子像素行组中的所述第n行和第n+1行子像素之间设置有一个所述检测线结构，且所述检测线结构配置为与所述第n行和第n+1行子像素连接并用于检测所述第n行和第n+1行子像素中的第一晶体管或发光元件的电特性，n为大于0的奇数或偶数。
  2. 如权利要求1所述的阵列基板，其中，所述多个检测线结构中的任一个不位于相邻的两个子像素行组之间。
  3. 如权利要求1或2所述的阵列基板，还包括沿所述第一方向延伸的多条第一电源线，
    其中，所述第一电源线设置于相邻的两个子像素行组之间，每条所述第一电源线配置为和与之相邻的两行子像素连接并提供第一电源信号。
  4. 如权利要求3所述的阵列基板，其中，所述多条第一电源线与所述多个检测线结构在所述第二方向上交替分布。
  5. 如权利要求3或4所述的阵列基板，其中，所述相邻的两个子像素行组相对于位于所述相邻的两个子像素行组之间的所述第一电源线对称设置。
  6. 如权利要求3-5任一所述的阵列基板，还包括多条第二电源线，其中，所述多条第二电源线沿所述第二方向延伸，且分别与所述多条第一电源线交叉电连接。
  7. 如权利要求1-6任一所述的阵列基板，其中，每个检测线结构包括多条第一检测线，所述多条第一检测线沿所述第一方向依次布置且彼此绝缘，所述多个检测线结构中的多条第一检测线构成沿所述第一方向和所述第二方向排布为多行多列的检测线阵列；每条所述第一检测线对应连接位于同 一行的至少两个所述子像素。
  8. 如权利要求7所述的阵列基板，还包括多条第二检测线，其中，所述多条第二检测线沿所述第二方向延伸，且分别与所述检测线阵列中的多列第一检测线一一对应且交叉电连接，位于同一列的多条第一检测线通过所对应的一条第二检测线彼此电连接。
  9. 如权利要求8所述的阵列基板，其中，位于同一行的每m个子像素构成一个像素单元，每条第一检测线对应连接所述同一行中的1个或2个所述像素单元，
    m＝2、3或4。
  10. 如权利要求9所述的阵列基板，其中，每条所述第一检测线对应连接2个所述像素单元，与每条所述第一检测线连接的所述第二检测线设置于所述第一检测线所对应连接的2个像素单元之间。
  11. 如权利要求1-10任一所述的阵列基板，其中，所述子像素还包括第二晶体管、第三晶体管和第一电容；
    所述第二晶体管的栅极和第一极分别配置为接收第一扫描信号和数据信号，所述第二晶体管的第二极连接所述第一晶体管的栅极；
    所述第一晶体管的第一极配置为接收第一电源信号，所述第一晶体管的第二极分别与所述第三晶体管的第一极以及所述发光元件的第一电极连接；
    所述第三晶体管的栅极配置为接收第二扫描信号，所述第三晶体管的第二极与所述子像素所连接的检测线结构电连接；
    所述发光元件的第二电极配置为接收第二电源信号；
    所述第一电容的一端连接所述第一晶体管的栅极，另一端连接所述第一晶体管的第二极。
  12. 如权利要求11所述的阵列基板，还包括沿所述第一方向延伸的多条第一扫描线，
    其中，所述多条第一扫描线分别与多行子像素一一对应连接，并分别与所对应连接的多行子像素中的第二晶体管的栅极连接以提供所述第一扫描信号。
  13. 如权利要求12所述的阵列基板，其中，在每个子像素行组中，分别与所述第n行和第n+1行子像素连接的两条第一扫描线设置于所述第n行 和第n+1行子像素之间。
  14. 如权利要求12或13所述的阵列基板，其中，在每个子像素行组中，与所述第n行和第n+1行子像素连接的检测线结构设置于与所述第n行和第n+1行子像素所分别连接的两条第一扫描线之间。
  15. 如权利要求14所述的阵列基板，其中，在每个子像素行组中，与所述第n行和第n+1行子像素所分别连接的两条第一扫描线相对于位于所述第n行和第n+1行子像素之间的检测线结构对称设置。
  16. 如权利要求12-15任一所述的阵列基板，其中，所述第一扫描线还与所对应连接的子像素中的第三晶体管的栅极连接以提供所述第二扫描信号。
  17. 如权利要求12-16任一所述的阵列基板，还包括沿所述第一方向延伸的多条第二扫描线，
    其中，所述多条第二扫描线分别与多行子像素一一对应连接，并分别与所对应连接的子像素中的第三晶体管的栅极连接以提供所述第二扫描信号。
  18. 如权利要求12-17任一所述的阵列基板，其中，所述第二晶体管和所述第三晶体管沿所述第一方向并列设置，且所述第二晶体管的沟道长度方向和所述第三晶体管的沟道长度方向均与所述第二方向平行。
  19. 如权利要求1-18任一所述的阵列基板，其中，在每个子像素行组中，所述第n行和第n+1行子像素相对于与其相连的检测线结构对称设置。
  20. 如权利要求1-19任一所述的阵列基板，其中，所述发光元件为顶发射有机发光二极管。
  21. 一种显示面板，包括如权利要求1-20任一所述的阵列基板。
  22. 一种检测方法，用于如权利要求1-20任一所述的阵列基板，包括：
    在所述多个子像素之中选择目标子像素；
    对于所述子像素阵列中的所述目标子像素施加检测信号；
    通过与所述目标子像素连接的检测线结构获取所述目标子像素中的第一晶体管或发光元件的电特性。
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