WO2020062704A1 - 激光器与硅光芯片集成结构 - Google Patents

激光器与硅光芯片集成结构 Download PDF

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Publication number
WO2020062704A1
WO2020062704A1 PCT/CN2019/070516 CN2019070516W WO2020062704A1 WO 2020062704 A1 WO2020062704 A1 WO 2020062704A1 CN 2019070516 W CN2019070516 W CN 2019070516W WO 2020062704 A1 WO2020062704 A1 WO 2020062704A1
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Prior art keywords
waveguide
silicon
silicon nitride
laser
layer
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PCT/CN2019/070516
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English (en)
French (fr)
Inventor
蔡艳
余明斌
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中国科学院上海微系统与信息技术研究所
上海新微科技服务有限公司
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Publication of WO2020062704A1 publication Critical patent/WO2020062704A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region

Definitions

  • the invention belongs to the technical field of hybrid integration, and particularly relates to an integrated structure of a laser and a silicon optical chip.
  • the laser is the light source of the silicon optical chip. Since the silicon material itself cannot emit light, how to integrate the laser (for example, a family of three or five lasers) with the silicon optical chip is the key to the development of the optical transceiver module.
  • the current integration technology of laser and silicon optical chip is mainly composed of three types: one is monolithic integration, that is, the laser is directly generated on the silicon-based substrate through epitaxy; the second is heterogeneous integration, that is, the silicon optical chip is bonded to the silicon optical chip through the laser chip.
  • the third is hybrid integration, that is, first preparing the laser, and then integrating the laser with the silicon optical chip by flip-chip welding or external laser .
  • the existing laser and silicon optical chip integration technologies have problems such as high alignment accuracy requirements and low coupling efficiency.
  • an object of the present invention is to provide an integrated structure of a laser and a silicon optical chip and a preparation method thereof, which are used to solve the alignment accuracy existing in the integrated technology of a laser and a silicon optical chip in the prior art High requirements and low coupling efficiency.
  • the present invention provides an integrated structure of a laser and a silicon optical chip.
  • the integrated structure of the laser and the silicon optical chip includes:
  • a laser chip including a first waveguide
  • a silicon optical chip which includes a second waveguide, and the second waveguide and the first waveguide couple light emitted by the laser chip into the silicon optical chip.
  • the second waveguide and the first waveguide couple light emitted by the laser chip into the silicon optical chip in an evanescent wave coupling manner.
  • the first waveguide includes a first inverted tapered waveguide portion, a rectangular waveguide portion, and a second inverted tapered waveguide portion which are integrally connected in order;
  • the second waveguide includes a first silicon nitride waveguide, a second silicon nitride waveguide, and a silicon waveguide; wherein the first silicon nitride waveguide, the second silicon nitride waveguide, and the silicon waveguide all include a sequence A first inverted tapered waveguide portion, a rectangular waveguide portion, and a second inverted tapered waveguide portion that are integrally connected; wherein the first silicon nitride waveguide is located below the first waveguide, and the first silicon nitride The orthographic projection of the first inverted tapered waveguide portion of the waveguide coincides with the orthographic projection of the second inverted tapered waveguide portion of the first waveguide; the second silicon nitride waveguide is located on the first silicon nitride waveguide.
  • the orthographic projection of the first inverted tapered waveguide portion of the second silicon nitride waveguide coincides with the orthographic projection of the second inverted tapered waveguide portion of the first silicon nitride waveguide;
  • an orthographic projection of a first inverted tapered waveguide portion of the silicon waveguide coincides with an orthographic projection of a second inverted tapered waveguide portion of the second silicon nitride waveguide.
  • a width of an end of each of the first inverted tapered waveguide portions remote from the rectangular waveguide portion is 10 nm to 1000 nm, and each of the first inverted tapered waveguide portions is integrated with the rectangular waveguide portion.
  • the width of one end of the connection is 100 nm to 10 ⁇ m, and the length of each of the first inverted tapered waveguide portions is 10 ⁇ m to 1000 ⁇ m; the width of one end of each of the second inverted tapered waveguide portions away from the rectangular waveguide portion is 10 nm to 1000 nm, A width of one end of each of the second inverted tapered waveguide portions and the rectangular waveguide portion integrally connected is 100 nm to 10 ⁇ m, and a length of each of the second inverted tapered waveguide portions is 10 ⁇ m to 1000 ⁇ m.
  • the silicon optical chip further includes:
  • a second dielectric layer located on a surface of the first dielectric layer away from the buried oxygen layer and covering the second silicon nitride waveguide; the first silicon nitride waveguide located on the second dielectric layer away from the The surface of the first dielectric layer;
  • a third dielectric layer is located on a surface of the second dielectric layer away from the first dielectric layer and covers the first silicon nitride waveguide.
  • the laser chip further includes:
  • a first doping type III-V material layer which is located on the surface of the second substrate;
  • a first optical confinement layer is located on a surface of the first doping type group III-V material layer away from the second substrate; the first waveguide is located on the first optical confinement layer away from the first doping type Surfaces of three or five group material layers;
  • a second optical confinement layer is located on a surface of the first waveguide away from the first optical confinement layer; the second optical confinement layer includes a bonding portion and a boss portion, and the thickness of the boss portion is greater than that of the key Thickness of joint
  • a second doping type III-V material layer is located on the surface of the boss portion of the second optical confinement layer
  • the laser chip is flip-chip soldered to the surface of the silicon optical chip, and the bonding portion of the second optical confinement layer is in contact with the surface of the third dielectric layer.
  • the first waveguide includes a group III or material waveguide, a multiple quantum well material waveguide, or a quantum dot material waveguide
  • the first substrate includes a silicon substrate
  • the second substrate includes Substrate of three or five materials.
  • the integrated structure of the laser and the silicon optical chip further includes:
  • a solder ball is located between the first pad and the second pad to solder the laser chip and the silicon optical chip together.
  • the present invention also provides a method for preparing an integrated structure of a laser and a silicon optical chip.
  • the method for preparing an integrated structure of a laser and a silicon optical chip includes the following steps:
  • Preparing a laser chip the laser chip including a first waveguide
  • Preparing a silicon optical chip the silicon optical chip including a second waveguide
  • preparing the silicon optical chip includes the following steps:
  • the SOI substrate includes a first substrate, a buried oxygen layer, and an epitaxial silicon layer which are sequentially stacked from bottom to top.
  • the first substrate includes a silicon substrate.
  • first dielectric layer Forming a first dielectric layer on a surface of the buried oxygen layer away from the first substrate, the first dielectric layer covering the silicon waveguide;
  • the first silicon nitride waveguide, the second silicon nitride waveguide, and the silicon waveguide each include a first inverted tapered waveguide portion, a rectangular waveguide portion, and a second inverted tapered waveguide portion that are integrally connected in order;
  • the orthographic projection of the first inverted tapered waveguide portion of the first silicon nitride waveguide coincides with the orthographic projection of the second inverted tapered waveguide portion of the first waveguide; the first inverted cone of the second silicon nitride waveguide
  • the orthographic projection of the shaped waveguide portion coincides with the orthographic projection of the second inverted tapered waveguide portion of the first silicon nitride waveguide; the orthographic projection of the first inverted tapered waveguide portion of the silicon waveguide and the second nitrogen
  • the orthographic projections of the second inverted tapered waveguide portion of the silicon waveguide are coincident.
  • preparing the laser chip includes the following steps:
  • a first waveguide is formed on a surface of the first optical confinement layer far from the first doped type III-V material layer.
  • the first waveguide includes a first inverted tapered waveguide portion, a rectangular waveguide portion, and A second inverted tapered waveguide portion; the first silicon nitride waveguide, the second silicon nitride waveguide, and the silicon waveguide together constitute a second waveguide;
  • a width of an end of each of the first inverted tapered waveguide portions remote from the rectangular waveguide portion is 10 nm to 1000 nm, and each of the first inverted tapered waveguide portions is integrated with the rectangular waveguide portion.
  • the width of one end of the connection is 100 nm to 10 ⁇ m, and the length of each of the first inverted tapered waveguide portions is 10 ⁇ m to 1000 ⁇ m; the width of one end of each of the second inverted tapered waveguide portions away from the rectangular waveguide portion is 10 nm to 1000 nm; A width of one end of each of the second inverted tapered waveguide portions and the rectangular waveguide portion integrally connected is 100 nm to 10 ⁇ m, and a length of each of the second inverted tapered waveguide portions is 10 ⁇ m to 1000 ⁇ m.
  • the integrated structure of the laser and silicon optical chip of the present invention and the preparation method thereof have the following beneficial effects:
  • the first waveguide in the laser and the second waveguide in the silicon optical chip in the integrated structure of the laser prepared by the present invention and the second waveguide in the silicon optical chip couple the light emitted by the laser into the silicon optical chip by way of evanescent wave coupling.
  • the end-face coupling ie, the first waveguide in the laser is directly butt-coupling with a silicon waveguide or a silicon nitride waveguide
  • the coupling method of the present invention requires lower alignment accuracy during flip-chip welding. Even under the actual process conditions with misalignment, it still has high coupling efficiency;
  • the laser prepared by the present invention and the silicon-optic chip integrated structure laser are bonded to the SOI silicon substrate through solder balls. Since the silicon substrate has better heat dissipation performance, the laser can obtain more effective heat dissipation.
  • FIG. 1 is a flowchart of a method for manufacturing an integrated structure of a laser and a silicon optical chip provided in Embodiment 1 of the present invention.
  • FIG. 2 to FIG. 9 are schematic cross-sectional structure diagrams of structures obtained in step 1) in the method for manufacturing an integrated structure of a laser and a silicon optical chip provided in Embodiment 1 of the present invention.
  • FIG. 10 shows the top structure of the first silicon nitride waveguide, the second silicon nitride waveguide, and the silicon waveguide in the silicon optical chip obtained in step 1) of the method for preparing the integrated structure of the laser and the silicon optical chip provided in the first embodiment of the present invention.
  • FIG. 11 to 18 are schematic cross-sectional structural diagrams of the structure obtained in step 2) of the method for manufacturing an integrated structure of a laser and a silicon optical chip provided in Embodiment 1 of the present invention; wherein, FIG. 15 is a schematic plan view of a first waveguide.
  • FIG. 19 is a schematic cross-sectional structure diagram of the structure obtained in step 3) in the method for manufacturing an integrated structure of a laser and a silicon optical chip provided in Embodiment 1 of the present invention.
  • FIG. 20 shows the first waveguide, the first silicon nitride waveguide, the second silicon nitride waveguide, and the silicon waveguide in the structure obtained in step 3) of the method for preparing the integrated structure of the laser and the silicon optical chip provided in the first embodiment of the present invention.
  • FIGS. 1 to 20 Please refer to FIGS. 1 to 20.
  • the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the contents disclosed in the description for those familiar with this technology to understand and read, and are not intended to limit the implementation of the present invention. Limited conditions, so it does not have technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size shall still fall within the present invention without affecting the efficacy and the purpose that can be achieved by the present invention.
  • the disclosed technical content must be within the scope.
  • the terms such as “up”, “down”, “left”, “right”, “middle”, and “one” cited in this specification are only for the convenience of description, and are not intended to limit the text.
  • the scope of the invention that can be implemented, and the changes or adjustments in its relative relationship, should be regarded as the scope in which the invention can be implemented without substantial changes in the technical content.
  • the present invention provides a method for preparing an integrated structure of a laser and a silicon optical chip.
  • the method for preparing an integrated structure of a laser and a silicon optical chip includes the following steps:
  • the second waveguide and the first waveguide 13 couple the light emitted by the laser chip 1 into the silicon optical chip 2 in an evanescent wave coupling manner.
  • the laser chip 1 may be prepared first, and then the silicon optical chip 2 may be prepared, or the silicon optical chip 2 may be prepared first, and then the laser chip 1 may be prepared. That is, the order of preparing the laser chip 1 and the silicon optical chip 2 can be interchanged.
  • preparing the silicon optical chip includes the following steps:
  • the SOI substrate 20 includes a first substrate 201, a buried oxygen layer 202, and an epitaxial silicon layer 203, which are sequentially stacked from bottom to top, as shown in FIG. 2;
  • the substrate 201 includes a silicon substrate, that is, the first substrate 201 is the bottom silicon in the SOI substrate 20, and the epitaxial silicon layer 203 is the top silicon in the SOI substrate 20;
  • first dielectric layer 22 forming a first dielectric layer 22 on the surface of the buried oxygen layer 202, and the first dielectric layer 22 covers the silicon waveguide 21, as shown in FIG. 4;
  • a second silicon nitride waveguide 23 is formed on a surface of the first dielectric layer 22 away from the buried oxygen layer 202, as shown in FIG. 5;
  • a second dielectric layer 24 is formed on a surface of the first dielectric layer 22 away from the buried oxygen layer 202, and the second dielectric layer 24 covers the second silicon nitride waveguide 23, as shown in FIG. ⁇ ; Showing;
  • a third dielectric layer 26 is formed on a surface of the second dielectric layer 24 away from the first dielectric layer 22, and the third dielectric layer 26 covers the first silicon nitride waveguide 25, as shown in FIG. 8 Shown
  • the first silicon nitride waveguide 25, the second silicon nitride waveguide 23, and the silicon waveguide 21 each include a first inverted tapered waveguide portion 131, which is integrally connected in sequence, and a rectangular shape.
  • the orthographic projection of the first inverted tapered waveguide portion 131 of the second silicon nitride waveguide 23 coincides with the orthographic projection of the second inverted tapered waveguide portion 133 of the first silicon nitride waveguide 25 Coincide; the orthographic projection of the first inverted tapered waveguide portion 131 of the silicon waveguide 21 and the orthographic projection of the second inverted tapered waveguide portion 133 of the second silicon nitride waveguide 23 coincide.
  • steps 1-2) may specifically include the following steps: first, epitaxially growing an SOI epitaxial silicon layer on the first substrate 201 by using an epitaxial process;
  • the silicon waveguide 21 can be obtained by layer etching.
  • the thickness of the silicon waveguide 21 may be set according to actual needs.
  • the thickness of the silicon waveguide 21 may be 150 nm to 250 nm.
  • the thickness of the silicon waveguide 21 is preferably 220 nm.
  • the first dielectric layer 22 may be formed by using a chemical vapor deposition process or a physical vapor deposition process.
  • the first dielectric layer 22 covers the silicon waveguide 21 and covers the buried oxygen.
  • the layer 202 is formed with a part of the surface of the silicon waveguide 21.
  • the first dielectric layer 22 may include, but is not limited to, a silicon oxide layer, and a thickness of the first dielectric layer 22 on an upper surface portion of the silicon waveguide 21 may be, but is not limited to, 100 nm to 300 nm, that is, the second nitride
  • the distance between the silicon waveguide 23 and the silicon waveguide 21 may be 100 nm to 300 nm.
  • steps 1-4) may specifically include the following steps: first, a silicon nitride layer is formed on a surface of the first dielectric layer 22 away from the buried oxygen layer 202; The silicon nitride layer is etched to obtain the second silicon nitride waveguide 23.
  • the thickness of the second silicon nitride waveguide 23 may be set according to actual needs. Preferably, the thickness of the second silicon nitride waveguide 23 may be, but not limited to, 100 nm to 300 nm.
  • the second dielectric layer 24 may be formed by using a chemical vapor deposition process or a physical vapor deposition process, and the second dielectric layer 24 covers the second silicon nitride waveguide 23.
  • the second dielectric layer 24 may include, but is not limited to, a silicon oxide layer.
  • the thickness of the second dielectric layer 24 on the upper surface portion of the second silicon nitride waveguide 23 may be, but is not limited to, 50 nm to 600 nm, that is, the first silicon nitride waveguide 25 and the first silicon nitride waveguide.
  • the spacing between 23 may be 50nm to 600nm.
  • steps 1-6) may specifically include the following steps: first, a silicon nitride layer is formed on a surface of the second dielectric layer 24 away from the first dielectric layer 22;
  • the first silicon nitride waveguide 25 can be obtained by etching the silicon nitride layer.
  • the thickness of the first silicon nitride waveguide 25 can be set according to actual needs.
  • the thickness of the first silicon nitride waveguide 25 can be, but not limited to, 10 nm to 100 nm.
  • the thickness of the first silicon nitride waveguide 25 may be 50 nm.
  • the third dielectric layer 26 may be formed by using a chemical vapor deposition process or a physical vapor deposition process, and the third dielectric layer 26 covers the first silicon nitride waveguide 25.
  • the third dielectric layer 26 may include, but is not limited to, a silicon oxide layer.
  • step 1-8 a portion of the third dielectric layer 26, the second dielectric layer 24, the first dielectric layer 22, and the third dielectric layer 26 can be etched and removed in sequence using a dry etching process. Buried oxygen layer 202.
  • the first inverted tapered waveguide portion 131 in the silicon waveguide 21, the first inverted tapered waveguide 131 in the first silicon nitride waveguide 25, and the second silicon nitride waveguide The specific structure and size of the first inverted tapered waveguide portion 131 in 23 are the same, and the second inverted tapered waveguide portion 133 in the silicon waveguide 21 and the first inverted silicon waveguide 25 in the silicon waveguide 21 are the same.
  • the specific structure and size of the second inverted tapered waveguide portion 133 in the second inverted tapered waveguide portion 133 and the second silicon nitride waveguide 23 are the same. Specifically, as shown in FIG.
  • a width d1 of each end of the first inverted tapered waveguide portion 131 away from the rectangular waveguide portion 132 may be 10 nm.
  • a width d2 of one end of each of the first inverted tapered waveguide portions 131 and the rectangular waveguide portion 132 may be 100 nm to 10 ⁇ m, and a length L1 of each of the first inverted tapered waveguide portions 131 may be 10 ⁇ m ⁇ 1000 ⁇ m; a width d3 of an end of each of the second inverted tapered waveguide portions 133 away from the rectangular waveguide portion 132 may be 10 nm to 1000 nm.
  • Each of the second reverse tapered waveguide section 133 is connected to an end of the width d4 of the rectangular waveguide portion 132 may be integrally 100nm ⁇ 10 ⁇ m, each of said second reverse tapered portion length L2 of the waveguide 133 may be 10 ⁇ m ⁇ 1000 ⁇ m.
  • preparing the laser chip 1 includes the following steps:
  • a first waveguide 13 is formed on a surface of the first optical confinement layer 12 away from the first doped type III-V material layer 11, and the first waveguide 13 includes a first inverted cone that is integrally connected in sequence.
  • the second substrate 10 provided in step 2-1) may include, but is not limited to, a group III-V (III-V) material substrate.
  • the first doped type III-V material layer 11 may be an n-type doped III-V material layer or a p-type doped III-V material layer.
  • the first doping type III-V material layer 11 is used for metal contact.
  • the first optical confinement layer 12 formed in step 2-3) is used to confine the light field, and any material layer that can implement light confinement can be used as the first optical confinement layer 12.
  • steps 2-4) may specifically include the following steps: first, a waveguide material layer is formed on a surface of the first optical confinement layer 12 away from the first doped type III-V material layer 11;
  • the first waveguide 13 can be obtained by etching the waveguide material layer by a photolithography etching process.
  • the first waveguide 13 may include a group III or material waveguide, a multiple quantum well material waveguide, or a quantum dot material waveguide.
  • the second optical confinement layer 14 formed in step 2-5) is used to confine the light field, and any material layer capable of realizing the confined light field can be used as the second optical confinement layer 14.
  • the second doped type III-V material layer 15 may be an n-type doped III-V material layer or a p-type doped III-V material layer.
  • the doping type of the second doping type III-V material layer 15 is different from the doping type of the first doping type III-V material layer 11, that is, if the first doping type When the heterotype III-V material layer 11 is an n-type doped III-V material layer, the second doped type III-V material layer 15 is a p-type doped III-V material layer, and when the first When the doped type III-V material layer 11 is a p-type doped III-V material layer, the second doped type III-V material layer 15 is an n-type doped III-V material layer.
  • the second doping type group 3-5 material layer 15 is used for metal contact.
  • the second doping type III-V material layer 15 and the second optical confinement layer 14 may be etched by a photolithography etching process.
  • the second doping type III-V material layer 15 and the second optical confinement layer 14 may be etched by a photolithography etching process.
  • a width d1 of an end of the first inverted tapered waveguide portion 131 away from the rectangular waveguide portion 132 may be 10 nm to 1000 nm.
  • the width d2 of one end of the tapered waveguide portion 131 integrally connected with the rectangular waveguide portion 132 may be 100 nm to 10 ⁇ m, and the length L1 of the first inverted tapered waveguide portion 131 may be 10 ⁇ m to 1000 ⁇ m; the second inverted tapered portion;
  • the width d3 of one end of the waveguide portion 133 away from the rectangular waveguide portion 132 may be 10 nm to 1000 nm, and the width d4 of one end where the second inverted tapered waveguide portion 133 is integrally connected with the rectangular waveguide portion 132 may be 100 nm to 10 ⁇ m.
  • the length L2 of the second inverted tapered waveguide portion 133 may be 10 ⁇ m to 1000 ⁇ m.
  • the first inverted tapered waveguide portion 131 and the first waveguide 13, the first silicon nitride waveguide 25, the second silicon nitride waveguide 23, and the silicon waveguide 21 are defined.
  • the width and length of the two ends of the second inverted tapered waveguide portion 132 can achieve high coupling efficiency of the light emitted by the laser chip 1 from the laser chip 1 to the silicon optical chip 2.
  • a first pad 16 is formed on a surface of the laser chip 1 of the second doped type III-V material layer 15 away from the second optical confinement layer 14.
  • a substrate 201 is formed with a second pad 27 on a surface of the silicon waveguide 21. After the laser chip 1 is inverted, the first pad 16 and the second pad 27 are soldered by using a solder ball 3. Together to achieve flip-chip bonding of the laser chip 1 and the silicon optical chip 2.
  • the laser chip 1 needs to be aligned with the silicon optical chip 2 so that the first waveguide 13 and the first silicon nitride waveguide 25 can be effectively coupled, that is, the laser After the chip 1 is flip-chip soldered to the silicon optical chip 2, the orthographic projection of the first inverted tapered waveguide portion 131 of the first silicon nitride waveguide 25 and the second inverted tapered waveguide of the first waveguide 13 The orthographic projections of the portion 133 are coincident.
  • the present invention also provides an integrated structure of a laser and a silicon optical chip.
  • the integrated structure of the laser and the silicon optical chip includes:
  • a laser chip 1 which includes a first waveguide 13;
  • Silicon optical chip 2 which includes a second waveguide, and the second waveguide and the first waveguide 13 couple the light emitted by the laser chip 1 to the silicon light in an evanescent wave coupling manner. Inside the chip 2.
  • the first waveguide 13 includes a first inverted tapered waveguide portion 131, a rectangular waveguide portion 132, and a second inverted tapered waveguide portion 133 that are integrally connected in this order.
  • the second waveguide includes a first silicon nitride waveguide 25.
  • the orthographic projection of the first inverted tapered waveguide portion 131 of the first coincides with the orthographic projection of the second inverted tapered waveguide portion 133 of the first waveguide 13; the second silicon nitride waveguide 23 is located in the first nitride Below the silicon waveguide 25, the orthographic projection of the first inverted tapered waveguide portion 131 of the second silicon nitride waveguide 23 and the orthographic projection of the second inverted tapered waveguide portion 133 of the first silicon n
  • the first inverted tapered waveguide portion 131 in the first waveguide 13, the first inverted tapered waveguide portion 131 in the silicon waveguide 21, and the first silicon nitride waveguide 25 The first inverted tapered waveguide 131 and the second silicon nitride waveguide 23 have the same specific structure and size as the first inverted tapered waveguide 131, and the first inverted Two inverted tapered waveguide portions 133, the second inverted tapered waveguide portion 133 in the silicon waveguide 21, the second inverted tapered waveguide portion 133 in the first silicon nitride waveguide 25, and the The specific structure and size of the second inverted tapered waveguide portion 133 in the second silicon nitride waveguide 23 are the same. Specifically, as shown in FIG.
  • a width d1 of an end of each of the first inverted tapered waveguide portions 131 away from the rectangular waveguide portion 132 may be 10 nm to 1000 nm.
  • a width d2 of one end of each of the first inverted tapered waveguide portions 131 and the rectangular waveguide portion 132 integrally connected may be 100 nm to 10 ⁇ m.
  • a width d4 at one end where 133 is integrally connected to the rectangular waveguide portion 132 may be 100 nm to 10 ⁇ m, and a length L2 of each of the second inverted tapered waveguide portions 133 may be 10 ⁇ m to 1000 ⁇ m.
  • the thickness of the silicon waveguide 21 may be 150 nm to 250 nm.
  • the thickness of the silicon waveguide 21 is preferably 220 nm; the thickness of the second silicon nitride waveguide 23 may be, but not only The thickness is limited to 100 nm to 300 nm; the thickness of the first silicon nitride waveguide 25 may be, but is not limited to, 10 nm to 100 nm.
  • the thickness of the first silicon nitride waveguide 25 may be 50 nm.
  • the first waveguide 13 includes a group three or five material waveguide, a multiple quantum well material waveguide, or a quantum dot material waveguide.
  • the silicon optical chip 2 further includes:
  • Buried oxygen layer 202 the buried oxygen layer 202 is located on the surface of the first substrate 201; the silicon waveguide 21 is located on the surface of the buried oxygen layer 202 away from the first substrate 201;
  • the surface of the buried oxygen layer 202; the first dielectric layer 22 may include, but is not limited to, a silicon oxide layer; the thickness of the first dielectric layer 22 on the upper surface portion of the silicon waveguide 21 may be, but is not limited to, 100 nm to 300 nm That is, the distance between the second silicon nitride waveguide 23 and the silicon waveguide 21 may be 100 nm to 300 nm;
  • the thickness of the upper surface portion of the siliconized waveguide 23 may be, but is not limited to, 50 nm to 600 nm, that is, the distance between the first silicon nitride waveguide 25 and the first silicon nitride waveguide 23 may be 50 nm to 600 nm;
  • the laser chip 1 further includes:
  • a second substrate 10; the second substrate 10 may include, but is not limited to, a III-V material substrate;
  • the first doping type III-V material layer 11 is located on the surface of the second substrate 10; the first doping type III-V material layer 11 may be It is an n-type doped group of three or five material layer, or a p-type doped group of three or five material layer; the first doped type group of three or five material layer 11 is used for metal contact;
  • the first optical confinement layer 12 is located on a surface of the first doped type III-V material layer 11 away from the second substrate 10; the first waveguide 13 is located on the first An optical confinement layer 12 is far from the surface of the first doped type III-V material layer 11; the first optical confinement layer 12 is used to confine the light field, and any material layer capable of realizing light confinement can be used as The first optical confinement layer 12;
  • a second optical confinement layer 14 which is located on a surface of the first waveguide 13 away from the first optical confinement layer 12; the second optical confinement layer 14 includes a bonding portion 141 and a boss The thickness of the boss portion 142 is greater than the thickness of the bonding portion 141.
  • the second optical confinement layer 14 is used to confine the light field. Any material layer that can implement light confinement can be used as Said second optical confinement layer 14;
  • the second doping type III-V material layer 15 is located on the surface of the boss portion 142 of the second optical confinement layer 14; the second doping type III-V material layer 15
  • the group material layer 15 may be an n-type doped group 3-5 material layer, or may be a p-type doped group 3-5 material layer.
  • the doping type of the second doping type III-V material layer 15 is different from the doping type of the first doping type III-V material layer 11, that is, if the first doping type When the heterotype III-V material layer 11 is an n-type doped III-V material layer, the second doped type III-V material layer 15 is a p-type doped III-V material layer, and when the first When the doping type III-V material layer 11 is a p-type doped III-V material layer, the second doping type III-V material layer 15 is an n-type doped III-V material layer; the second The doping type group 3 or 5 material layer 15 is used for metal contact;
  • the laser chip 1 is flip-chip soldered to the surface of the silicon optical chip 2, and the bonding portion 141 of the second optical confinement layer 14 is in contact with the surface of the third dielectric layer 26.
  • the integrated structure of the laser and the silicon optical chip further includes:
  • the solder ball 3 is located between the first pad 16 and the second pad 27 to solder the laser chip 1 and the silicon optical chip 2 together.
  • the present invention provides an integrated structure of a laser and a silicon optical chip and a preparation method thereof.
  • the integrated structure of the laser and the silicon optical chip includes: a laser chip, the laser chip includes a first waveguide;
  • the silicon optical chip includes a second waveguide, and the second waveguide and the first waveguide couple light emitted by the laser chip into the silicon optical chip in an evanescent wave coupling manner.
  • the first waveguide in the laser and the second waveguide in the silicon optical chip in the integrated structure of the laser prepared by the present invention and the second waveguide in the silicon optical chip couple the light emitted by the laser into the silicon optical chip by way of evanescent wave coupling.
  • the coupling method of the present invention requires lower alignment accuracy during flip-chip welding. Even under the actual process conditions of the alignment error, it still has high coupling efficiency; the laser and silicon optical chip integrated structure laser prepared by the present invention are bonded to the SOI silicon substrate through solder balls, due to the heat dissipation performance of the silicon substrate Better, so the laser can get more efficient heat dissipation.

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Abstract

一种激光器与硅光芯片集成结构，结构包括：激光器芯片（1），激光器芯片（1）包括第一波导（13）；硅光芯片（2），硅光芯片（2）包括第二波导，第二波导及第一波导（13）将激光器芯片（1）发出的光耦合至硅光芯片（2）内；第一波导（13）包括依次一体连接的第一倒锥形波导部（131）、矩形波导部（132）及第二倒锥形波导部（133）；第二波导包括第一氮化硅波导（25）、第二氮化硅波导（23）及硅波导（21）；其中，第一氮化硅波导（25）、第二氮化硅波导（23）及硅波导（21）均包括依次一体连接的第一倒锥形波导部（131）、矩形波导部（132）及第二倒锥形波导部（133）。相比于现有技术中的端面耦合，激光器与硅光芯片集成结构的耦合方式对倒装焊过程中的对准精度要求更低，即使在对准有误差的实际工艺条件下，仍然具有较高的耦合效率。

Description

激光器与硅光芯片集成结构 技术领域
本发明属于混合集成技术领域，特别是涉及一种激光器与硅光芯片集成结构。
背景技术
激光器是硅光芯片的光源，由于硅材料本身不能发光，因此如何将激光器(譬如，三五族激光器)与硅光芯片集成是研发光收发模块的关键。目前的激光器与硅光芯片的集成技术主要由三种：一是单片集成，即直接将激光器通过外延的方式生在在硅基；二是异质集成，即通过激光器芯片对硅光芯片键合的方式将三五族材料与硅光芯片进行异质集成，然后制备激光器；三是混合集成，即首先制备好激光器，然后通过倒装焊接或外接激光器的方式将激光器与硅光芯片进行集成。然而，现有的激光器与硅光芯片集成技术存在对准精度要求高及耦合效率低等问题
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种激光器与硅光芯片集成结构及其制备方法，用于解决现有技术中的激光器与硅光芯片集成技术存在的对准精度要求高及耦合效率低的问题。
为实现上述目的及其他相关目的，本发明提供一种激光器与硅光芯片集成结构，所述激光器与硅光芯片集成结构包括：
激光器芯片，所述激光器芯片包括第一波导；
硅光芯片，所述硅光芯片包括第二波导，所述第二波导及所述第一波导将所述激光器芯片发出的光耦合至所述硅光芯片内。
在另外一个实施例中，所述第二波导及所述第一波导将所述激光器芯片发出的光以倏逝波耦合的方式耦合至所述硅光芯片内。
作为本发明的一种优选方案，所述第一波导包括依次一体连接的第一倒锥形波导部、矩形波导部及第二倒锥形波导部；
所述第二波导包括第一氮化硅波导、第二氮化硅波导及硅波导；其中，所述第一氮化硅波导、所述第二氮化硅波导及所述硅波导均包括依次一体连接的第一倒锥形波导部、矩形波导部及第二倒锥形波导部；其中，所述第一氮化硅波导位于所述第一波导的下方，且所述第一氮化硅波导的第一倒锥形波导部的正投影与所述第一波导的第二倒锥形波导部的正投影部 分重合；所述第二氮化硅波导位于所述第一氮化硅波导的下方，且所述第二氮化硅波导的第一倒锥形波导部的正投影与所述第一氮化硅波导的第二倒锥形波导部的正投影部分重合；所述硅波导位于所述第二氮化硅波导的下方，且所述硅波导的第一倒锥形波导部的正投影与所述第二氮化硅波导的第二倒锥形波导部的正投影部分重合。
作为本发明的一种优选方案，各所述第一倒锥形波导部远离所述矩形波导部一端的宽度为10nm～1000nm，各所述第一倒锥形波导部与所述矩形波导部一体连接一端的宽度为100nm～10μm，各所述第一倒锥形波导部的长度为10μm～1000μm；各所述第二倒锥形波导部远离所述矩形波导部一端的宽度为10nm～1000nm，各所述第二倒锥形波导部与所述矩形波导部一体连接一端的宽度为100nm～10μm，各所述第二倒锥形波导部的长度为10μm～1000μm。
作为本发明的一种优选方案，所述硅光芯片还包括：
第一衬底；
埋氧层，位于所述第一衬底的表面；所述硅波导位于所述埋氧层远离所述第一衬底的表面；
第一介质层，位于所述埋氧层的表面，并覆盖所述硅波导；所述第二氮化硅波导位于所述第一介质层远离所述埋氧层的表面；
第二介质层，位于所述第一介质层远离所述埋氧层的表面，并覆盖所述第二氮化硅波导；所述第一氮化硅波导位于所述第二介质层远离所述第一介质层的表面；
第三介质层，位于所述第二介质层远离所述第一介质层的表面，且覆盖所述第一氮化硅波导。
作为本发明的一种优选方案，所述激光芯片还包括：
第二衬底；
第一掺杂类型三五族材料层，位于所述第二衬底的表面；
第一光学限制层，位于所述第一掺杂类型三五族材料层远离所述第二衬底的表面；所述第一波导位于所述第一光学限制层远离所述第一掺杂类型三五族材料层的表面；
第二光学限制层，位于所述第一波导远离所述第一光学限制层的表面；所述第二光学限制层包括键合部及凸台部，所述凸台部的厚度大于所述键合部的厚度；
第二掺杂类型三五族材料层，位于所述第二光学限制层的凸台部表面；
所述激光芯片倒装焊接于所述硅光芯片的表面，且所述第二光学限制层的键合部与所述第三介质层的表面相接触。
作为本发明的一种优选方案，所述第一波导包括三五族材料波导、多重量子阱材料波导 或量子点材料波导，所述第一衬底包括硅衬底，所述第二衬底包括三五族材料衬底。
作为本发明的一种优选方案，所述激光器与所述硅光芯片集成结构还包括：
第一焊盘，位于所述第二掺杂类型三五族材料层远离所述第二光学限制层的表面；
第二焊盘，位于所述第一衬底形成有所述硅波导的表面；
焊球，位于所述第一焊盘与所述第二焊盘之间，以将所述激光器芯片与所述硅光芯片焊接在一起。
本发明还提供一种激光器与硅光芯片集成结构的制备方法，所述激光器与硅光芯片集成结构的制备方法包括如下步骤：
制备激光芯片，所述激光芯片包括第一波导；
制备硅光芯片，所述硅光芯片包括第二波导；
将所述激光芯片倒装焊接于所述硅光芯片上，以使得所述激光器芯片发出的光经由所述第二波导及所述第一波导以倏逝波耦合的方式耦合至所述硅光芯片内。
作为本发明的一种优选方案，制备所述硅光芯片包括如下步骤：
提供SOI衬底，所述SOI衬底包括由下至上依次叠置的第一衬底、埋氧层及外延硅层；所述第一衬底包括硅衬底；
刻蚀所述外延硅层以于所述埋氧层远离所述第一衬底的表面形成硅波导；
于所述埋氧层远离所述第一衬底的表面形成第一介质层，所述第一介质层覆盖所述硅波导；
于所述第一介质层远离所述埋氧层的表面形成第二氮化硅波导；
于所述第一介质层远离所述埋氧层的表面形成第二介质层，所述第二介质层覆盖所述第二氮化硅波导；
于所述第二介质层远离所述第一介质层的表面形成第一氮化硅波导；
于所述第二介质层远离所述第一介质层的表面形成第三介质层，所述第三介质层覆盖所述第一氮化硅波导；
依次刻蚀去除部分所述第三介质层、所述第二介质层、所述第一介质层及所述埋氧层，以露出部分所述第一衬底；其中，
所述第一氮化硅波导、所述第二氮化硅波导及所述硅波导均包括依次一体连接的第一倒锥形波导部、矩形波导部及第二倒锥形波导部；所述第一氮化硅波导的第一倒锥形波导部的正投影与所述第一波导的第二倒锥形波导部的正投影部分重合；所述第二氮化硅波导的第一倒锥形波导部的正投影与所述第一氮化硅波导的第二倒锥形波导部的正投影部分重合；所述 硅波导的第一倒锥形波导部的正投影与所述第二氮化硅波导的第二倒锥形波导部的正投影部分重合。
作为本发明的一种优选方案，制备所述激光芯片包括如下步骤：
提供第二衬底；
于所述第二衬底上形成第一掺杂类型三五族材料层；
于所述第一掺杂类型三五族材料层远离所述第二衬底的表面形成第一光学限制层；
于所述第一光学限制层远离所述第一掺杂类型三五族材料层的表面形成第一波导，所述第一波导包括依次一体连接的第一倒锥形波导部、矩形波导部及第二倒锥形波导部；所述第一氮化硅波导、所述第二氮化硅波导及所述硅波导共同构成第二波导；
于所述第一波导远离所述第一光学限制层的表面形成第二光学限制层；
于所述第二光学限制层远离所述第一波导的表面形成第二掺杂类型三五族材料层；
刻蚀所述第二掺杂类型三五族材料层及所述第二光学限制层，使得所述第二光学限制层包括键合部及凸台部，所述凸台部的厚度大于所述键合部的厚度，保留的所述第二掺杂类型三五族材料层位于所述凸台部表面。
作为本发明的一种优选方案，各所述第一倒锥形波导部远离所述矩形波导部一端的宽度为10nm～1000nm，各所述第一倒锥形波导部与所述矩形波导部一体连接一端的宽度为100nm～10μm，各所述第一倒锥形波导部的长度为10μm～1000μm；各所述第二倒锥形波导部远离所述矩形波导部一端的宽度为10nm～1000nm，各所述第二倒锥形波导部与所述矩形波导部一体连接一端的宽度为100nm～10μm，各所述第二倒锥形波导部的长度为10μm～1000μm。
如上所述，本发明的激光器与硅光芯片集成结构及其制备方法，具有以下有益效果：
本发明制备的激光器与硅光芯片集成结构中激光器中的第一波导与硅光芯片中的第二波导通过倏逝波耦合的方式将激光器发出的光耦合至所述硅光芯片内，相比于现有技术中的端面耦合(即激光器中的第一波导直接与硅波导或氮化硅波导的butt-coupling)，本发明的耦合方式对倒装焊过程中的对准精度要求更低，即使在对准有误差的实际工艺条件下，仍然具有较高的耦合效率；
本发明制备的激光器与硅光芯片集成结构激光器通过焊球与SOI硅衬底键合，由于硅衬底的散热性能比较好，因此激光器可以得到更为有效的散热。
附图说明
图1显示为本发明实施例一中提供的激光器与硅光芯片集成结构的制备方法的流程图。
图2至图9显示为本发明实施例一中提供的激光器与硅光芯片集成结构的制备方法中步骤1)所得结构的截面结构示意图。
图10显示为本发明实施例一中提供的激光器与硅光芯片集成结构的制备方法中步骤1)所得硅光芯片中第一氮化硅波导、第二氮化硅波导及硅波导的俯视结构示意图。
图11至图18显示为本发明实施例一中提供的激光器与硅光芯片集成结构的制备方法中步骤2)所得结构的截面结构示意图；其中，图15为第一波导的俯视结构示意图。
图19显示为本发明实施例一中提供的激光器与硅光芯片集成结构的制备方法中步骤3)所得结构的截面结构示意图。
图20显示为本发明实施例一中提供的激光器与硅光芯片集成结构的制备方法中步骤3)所得结构中第一波导、第一氮化硅波导、第二氮化硅波导及硅波导的俯视结构示意图。
元件标号说明
1        激光器芯片
10       第二衬底
11       第一掺杂类型三五族材料层
12       第一光学限制层
13       第一波导
131      第一倒锥形波导部
132      矩形波导部
133      第二倒锥形波导部
14       第二光学限制层
141      键合部
142      凸台部
15       第二掺杂类型三五族材料层
16       第一焊盘
2        硅光芯片
20       SOI衬底
201      第一衬底
202      埋氧层
203      外延硅层
21       硅波导
22       第一介质层
23       第二氮化硅波导
24       第二介质层
25       第一氮化硅波导
26       第三介质层
27       第二焊盘
3        焊球
d1       第一倒锥形波导部远离矩形波导部一端的宽度
d2       第一倒锥形波导部与矩形波导部一体连接一端的宽度
L1       第一倒锥形波导部的长度
d3       第二倒锥形波导部远离矩形波导部一端的宽度
d4       第二倒锥形波导部与矩形波导部一体连接一端的宽度
L2       第二倒锥形波导部的长度
具体实施方式
以下由特定的具体实施例说明本发明的实施方式，熟悉此技术的人士可由本说明书所揭露的内容轻易地了解本发明的其他优点及功效。
请参阅图1至图20。须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“左”、“右”、“中间”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
实施例一
请参阅图1，本发明提供一种激光器与硅光芯片集成结构的制备方法，所述激光器与硅光芯片集成结构的制备方法包括如下步骤：
制备激光芯片1，所述激光芯片1包括第一波导13；
制备硅光芯片2，所述硅光芯片2包括第二波导；
将所述激光芯片1倒装焊接于所述硅光芯片2上，以使得所述激光器芯片1发出的光经由所述第二波导及所述第一波导13耦合至所述硅光芯片2内。
在另外一个例子中，所述第二波导及所述第一波导13将所述激光器芯片1发出的光以倏逝波耦合的方式耦合至所述硅光芯片2内
作为示例，可以先制备所述激光芯片1，然后再制备所述硅光芯片2，也可以先制备所述硅光芯片2，然后再制备所述激光芯片1。即制备所述激光芯片1及制备所述硅光芯片2的顺序可以互换。
作为示例，请参阅图2至图10，制备所述硅光芯片包括如下步骤：
1-1)提供SOI衬底20，所述SOI衬底20包括由下至上依次叠置的第一衬底201、埋氧层202及外延硅层203，如图2所示；所述第一衬底201包括硅衬底，即所述第一衬底201即为所述SOI衬底20中的底层硅，所述外延硅层203即为所述SOI衬底20中的顶层硅；
1-2)刻蚀所述外延硅层203以于所述埋氧层202的表面形成硅波导21，如图3所示；
1-3)于所述埋氧层202表面形成第一介质层22，所述第一介质层22覆盖所述硅波导21，如图4所示；
1-4)于所述第一介质层22远离所述埋氧层202的表面形成第二氮化硅波导23，如图5所示；
1-5)于所述第一介质层22远离所述埋氧层202的表面形成第二介质层24，所述第二介质层24覆盖所述第二氮化硅波导23，如图6所示；
1-6)于所述第二介质层24远离所述第一介质层22的表面形成第一氮化硅波导25，如图7所示；
1-7)于所述第二介质层24远离所述第一介质层22的表面形成第三介质层26，所述第三介质层26覆盖所述第一氮化硅波导25，如图8所示；
1-8)依次刻蚀去除部分所述第三介质层26、所述第二介质层24、所述第一介质层22及所述埋氧层202，以露出部分所述第一衬底201，如图9所示；其中，
如图10及图20所示，所述第一氮化硅波导25、所述第二氮化硅波导23及所述硅波导21均包括依次一体连接的第一倒锥形波导部131、矩形波导部132及第二倒锥形波导部133；所述第一氮化硅波导25的第一倒锥形波导部131的正投影与所述第一波导13的第二倒锥形波导部133的正投影部分重合；所述第二氮化硅波导23的第一倒锥形波导部131的正投影与所述第一氮化硅波导25的第二倒锥形波导部133的正投影部分重合；所述硅波导21的第一倒锥形波导部131的正投影与所述第二氮化硅波导23的第二倒锥形波导部133的正投影部分 重合。
作为示例，步骤1-2)具体可以包括如下步骤：首先，采用外延工艺于所述第一衬底201上外延生长SOI外延硅层；然后，对采用光刻刻蚀工艺对所述SOI外延硅层刻蚀即可得到所述硅波导21。所述硅波导21的厚度可以根据实际需要进行设定，优选地，所述硅波导21的厚度可以为150nm～250nm，优选地，本实施例中，所述硅波导21的厚度优选为220nm。
作为示例，步骤1-3)中可以采用化学气相沉积工艺或物理气相沉积工艺等形成所述第一介质层22，所述第一介质层22覆盖所述硅波导21，并覆盖所述埋氧层202形成有所述硅波导21的部分表面。所述第一介质层22可以包括但不仅限于氧化硅层，所述第一介质层22位于所述硅波导21上表面部分的厚度可以为但不仅限于100nm～300nm，即所述第二氮化硅波导23与所述硅波导21之间的间距可以为100nm～300nm。
作为示例，步骤1-4)具体可以包括如下步骤：首先，于所述第一介质层22远离所述埋氧层202的表面形成氮化硅层；然后，采用光刻刻蚀工艺对所述氮化硅层进行刻蚀即可得到所述第二氮化硅波导23。所述第二氮化硅波导23的厚度可以根据实际需要进行设定，优选地，所述第二氮化硅波导23的厚度可以为但不仅限于100nm～300nm。
作为示例，步骤1-5)中可以采用化学气相沉积工艺或物理气相沉积工艺等形成所述第二介质层24，所述第二介质层24覆盖所述第二氮化硅波导23。所述第二介质层24可以包括但不仅限于氧化硅层。所述第二介质层24位于所述第二氮化硅波导23上表面部分的厚度可以为但不仅限于50nm～600nm，即所述第一氮化硅波导25与所述第一氮化硅波导23之间的间距可以为50nm～600nm。
作为示例，步骤1-6)具体可以包括如下步骤：首先，于所述第二介质层24远离所述第一介质层22的表面形成氮化硅层；然后，采用光刻刻蚀工艺对所述氮化硅层进行刻蚀即可得到所述第一氮化硅波导25。所述第一氮化硅波导25的厚度可以根据实际需要进行设定，优选地，所述第一氮化硅波导25的厚度可以为但不仅限于10nm～100nm，优选地，本实施例中，所述第一氮化硅波导25的厚度可以为50nm。
作为示例，步骤1-7)中可以采用化学气相沉积工艺或物理气相沉积工艺等形成所述第三介质层26，所述第三介质层26覆盖所述第一氮化硅波导25。所述第三介质层26可以包括但不仅限于氧化硅层。
作为示例，步骤1-8)中可以采用但不仅限于干法刻蚀工艺依次刻蚀去除部分所述第三介质层26、所述第二介质层24、所述第一介质层22及所述埋氧层202。
作为示例，所述硅波导21中的所述第一倒锥形波导部131、所述第一氮化硅波导25中 的所述第一倒锥形波导131及所述第二氮化硅波导23中的所述第一倒锥形波导部131的具体结构及尺寸相同，所述硅波导21中的所述第二倒锥形波导部133、所述第一氮化硅波导25中的所述第二倒锥形波导部133及所述第二氮化硅波导23中的所述第二倒锥形波导部133的具体结构及尺寸相同，具体的，如图10所示，在所述硅波导21、所述第一氮化硅波导25及所述第二氮化硅波导23中，各所述第一倒锥形波导部131远离所述矩形波导部132一端的宽度d1可以为10nm～1000nm，各所述第一倒锥形波导部131与所述矩形波导部132一体连接一端的宽度d2可以为100nm～10μm，各所述第一倒锥形波导部131的长度L1可以为10μm～1000μm；各所述第二倒锥形波导部133远离所述矩形波导部132一端的宽度d3可以为10nm～1000nm，各所述第二倒锥形波导部133与所述矩形波导部132一体连接一端的宽度d4可以为100nm～10μm，各所述第二倒锥形波导部133的长度L2可以为10μm～1000μm。
作为示例，请参阅图11至图18，制备所述激光器芯片1包括如下步骤：
2-1)提供第二衬底10，如图11所示；
2-2)于所述第二衬底10上形成第一掺杂类型三五族(III-V)材料层11，如图12所示；
2-3)于所述第一掺杂类型三五族材料层11远离所述第二衬底10的表面形成第一光学限制层12，如图13所示；
2-4)于所述第一光学限制层12远离所述第一掺杂类型三五族材料层11的表面形成第一波导13，所述第一波导13包括依次一体连接的第一倒锥形波导部131、矩形波导部132及第二倒锥形波导部133，如图14及图15所示；所述第一氮化硅波导25、所述第二氮化硅波导23及所述硅波导21共同构成第二波导；
2-5)于所述第一波导13远离所述第一光学限制层12的表面形成第二光学限制层14，如图16所示；
2-6)于所述第二光学限制层14远离所述第一波导13的表面形成第二掺杂类型三五族材料层15，如图17所示；
2-7)刻蚀所述第二掺杂类型三五族材料层15及所述第二光学限制层14，使得所述第二光学限制层14包括键合部141及凸台部142，所述凸台部142的厚度大于所述键合部141的厚度，即刻蚀去除所述键合部141所在区域的部分所述第二光学限制层14，保留的所述第二掺杂类型三五族材料层15位于所述凸台部142表面。
作为示例，步骤2-1)中提供的所述第二衬底10可以包括但不仅限于三五族(III-V)材料衬底。
作为示例，步骤2-2)中，所述第一掺杂类型三五族材料层11可以为n型掺杂三五族材 料层，也可以为p型掺杂三五族材料层。所述第一掺杂类型三五族材料层11用于金属接触。
作为示例，步骤2-3)中形成的所述第一光学限制层12用于限制光场，任意一种可以实现限制光场的材料层均可作为所述第一光学限制层12。
作为示例，步骤2-4)中具体可以包括如下步骤：首先，于所述第一光学限制层12远离所述第一掺杂类型三五族材料层11的表面形成波导材料层；然后，采用光刻刻蚀工艺刻蚀所述波导材料层即可得到所述第一波导13。所述第一波导13可以包括三五族材料波导、多重量子阱材料波导或量子点材料波导。
作为示例，步骤2-5)中形成的所述第二光学限制层14用于限制光场，任意一种可以实现限制光场的材料层均可作为所述第二光学限制层14。
作为示例，步骤2-6)中，所述第二掺杂类型三五族材料层15可以为n型掺杂三五族材料层，也可以为p型掺杂三五族材料层。但需要说明的是，所述第二掺杂类型三五族材料层15的掺杂类型与所述第一掺杂类型三五族材料层11的掺杂类型不同，即若所述第一掺杂类型三五族材料层11为n型掺杂三五族材料层时，所述第二掺杂类型三五族材料层15为p型掺杂三五族材料层，而当所述第一掺杂类型三五族材料层11为p型掺杂三五族材料层时，则所述第二掺杂类型三五族材料层15为n型掺杂三五族材料层。所述第二掺杂类型三五族材料层15用于金属接触。
作为是，在步骤2-7)中，可以采用光刻刻蚀工艺刻蚀所述第二掺杂类型三五族材料层15及所述第二光学限制层14。通过刻蚀所述第二掺杂类型三五族材料层15及所述第二光学限制层14，在所述激光器芯片1与所述硅光芯片2倒装焊接在一起后，可以缩短所述第一波导13与所述第一氮化硅波导25之间的举例，更利于所述第一波导13与所述第一氮化硅波导25的高效耦合。
作为示例，如图15所示，在所述第一波导13中，所述第一倒锥形波导部131远离所述矩形波导部132一端的宽度d1可以为10nm～1000nm，所述第一倒锥形波导部131与所述矩形波导部132一体连接一端的宽度d2可以为100nm～10μm，所述第一倒锥形波导部131的长度L1可以为10μm～1000μm；所述第二倒锥形波导部133远离所述矩形波导部132一端的宽度d3可以为10nm～1000nm，所述第二倒锥形波导部133与所述矩形波导部132一体连接一端的宽度d4可以为100nm～10μm，所述第二倒锥形波导部133的长度L2可以为10μm～1000μm。本发明通过限定所述第一波导13、所述第一氮化硅波导25、所述第二氮化硅波导23及所述硅波导21中的所述第一倒锥形波导部131及所述第二倒锥形波导部132两端的宽度及长度，可以实现所述激光器芯片1发出的光从所述激光器芯片1到所述硅光芯片2较高 的耦合效率。
作为示例，如图19所示，所述激光器芯片1的所述第二掺杂类型三五族材料层15远离所述第二光学限制层14的表面形成有第一焊盘16，所述第一衬底201形成有所述硅波导21的表面形成有第二焊盘27，将所述激光器芯片1倒置后使用焊球3将所述第一焊盘16与所述第二焊盘27焊接在一起，以实现所述激光器芯片1与所述硅光芯片2的倒装焊接。倒装焊接过程中，所述激光器芯片1需与所述硅光芯片2对准，以使得所述第一波导13与所述第一氮化硅波导25可以实现有效的耦合，即所述激光器芯片1倒装焊接于所述硅光芯片2上之后，所述第一氮化硅波导25的第一倒锥形波导部131的正投影与所述第一波导13的第二倒锥形波导部133的正投影部分重合。
实施例二
请结合图2至图18继续参阅图19至图20，本发明还提供一种激光器与硅光芯片集成结构，所述激光器与硅光芯片集成结构包括：
激光器芯片1，所述激光器芯片1包括第一波导13；
硅光芯片2，所述硅光芯片2包括第二波导，所述第二波导及所述第一波导13将所述激光器芯片1发出的光以倏逝波耦合的方式耦合至所述硅光芯片2内。
作为示例，所述第一波导13包括依次一体连接的第一倒锥形波导部131、矩形波导部132及第二倒锥形波导部133；所述第二波导包括第一氮化硅波导25、第二氮化硅波导23及硅波导21；其中，所述第一氮化硅波导25、所述第二氮化硅波导23及所述硅波导21均包括依次一体连接的第一倒锥形波导部131、矩形波导部132及第二倒锥形波导部133；其中，所述第一氮化硅波导25位于所述第一波导13的下方，且所述第一氮化硅波导25的第一倒锥形波导部131的正投影与所述第一波导13的第二倒锥形波导部133的正投影部分重合；所述第二氮化硅波导23位于所述第一氮化硅波导25的下方，且所述第二氮化硅波导23的第一倒锥形波导部131的正投影与所述第一氮化硅波导25的第二倒锥形波导部133的正投影部分重合；所述硅波导21位于所述第二氮化硅波导23的下方，且所述硅波导21的第一倒锥形波导部131的正投影与所述第二氮化硅波导23的第二倒锥形波导部133的正投影部分重合。
作为示例，所述第一波导13中的所述第一倒锥形波导部131、所述硅波导21中的所述第一倒锥形波导部131、所述第一氮化硅波导25中的所述第一倒锥形波导131及所述第二氮化硅波导23中的所述第一倒锥形波导部131的具体结构及尺寸相同，所述第一波导13中的所述第二倒锥形波导部133、所述硅波导21中的所述第二倒锥形波导部133、所述第一氮化硅波导25中的所述第二倒锥形波导部133及所述第二氮化硅波导23中的所述第二倒锥形波 导部133的具体结构及尺寸相同，具体的，如图10及图15所示，在所述第一波导13、所述硅波导21、所述第一氮化硅波导25及所述第二氮化硅波导23中，各所述第一倒锥形波导部131远离所述矩形波导部132一端的宽度d1可以为10nm～1000nm，各所述第一倒锥形波导部131与所述矩形波导部132一体连接一端的宽度d2可以为100nm～10μm，各所述第一倒锥形波导部131的长度L1可以为10μm～1000μm；各所述第二倒锥形波导部133远离所述矩形波导部132一端的宽度d3可以为10nm～1000nm，各所述第二倒锥形波导部133与所述矩形波导部132一体连接一端的宽度d4可以为100nm～10μm，各所述第二倒锥形波导部133的长度L2可以为10μm～1000μm。
作为示例，所述硅波导21的厚度可以为150nm～250nm，优选地，本实施例中，所述硅波导21的厚度优选为220nm；所述第二氮化硅波导23的厚度可以为但不仅限于100nm～300nm；所述第一氮化硅波导25的厚度可以为但不仅限于10nm～100nm，优选地，本实施例中，所述第一氮化硅波导25的厚度可以为50nm。
作为示例，所述第一波导13包括三五族材料波导、多重量子阱材料波导或量子点材料波导。
作为示例，所述硅光芯片2还包括：
第一衬底201；所述第一衬底201包括硅衬底；
埋氧层202，所述埋氧层202位于所述第一衬底201的表面；所述硅波导21位于所述埋氧层202远离所述第一衬底201的表面；
第一介质层22，所述第一介质层22位于所述埋氧层202的表面，并覆盖所述硅波导21；所述第二氮化硅波导23位于所述第一介质层22远离所述埋氧层202的表面；所述第一介质层22可以包括但不仅限于氧化硅层；所述第一介质层22位于所述硅波导21上表面部分的厚度可以为但不仅限于100nm～300nm，即所述第二氮化硅波导23与所述硅波导21之间的间距可以为100nm～300nm；
第二介质层24，所述第二介质层24位于所述第一介质层22远离所述埋氧层202的表面，并覆盖所述第二氮化硅波导23；所述第一氮化硅波导25位于所述第二介质层24远离所述第一介质层22的表面；所述第二介质层24可以包括但不仅限于氧化硅层；所述第二介质层24位于所述第二氮化硅波导23上表面部分的厚度可以为但不仅限于50nm～600nm，即所述第一氮化硅波导25与所述第一氮化硅波导23之间的间距可以为50nm～600nm；
第三介质层26，所述第三介质层26位于所述第二介质层24远离所述第一介质层22的表面，且覆盖所述第一氮化硅波导25；所述第三介质层26可以包括但不仅限于氧化硅层。
作为示例，所述激光芯片1还包括：
第二衬底10；所述第二衬底10可以包括但不仅限于三五族(III-V)材料衬底；
第一掺杂类型三五族材料层11，所述第一掺杂类型三五族材料层11位于所述第二衬底10的表面；所述第一掺杂类型三五族材料层11可以为n型掺杂三五族材料层，也可以为p型掺杂三五族材料层；所述第一掺杂类型三五族材料层11用于金属接触；
第一光学限制层12，所述第一光学限制层12位于所述第一掺杂类型三五族材料层11远离所述第二衬底10的表面；所述第一波导13位于所述第一光学限制层12远离所述第一掺杂类型三五族材料层11的表面；所述第一光学限制层12用于限制光场，任意一种可以实现限制光场的材料层均可作为所述第一光学限制层12；
第二光学限制层14，所述第二光学限制层14位于所述第一波导13远离所述第一光学限制层12的表面；所述第二光学限制层14包括键合部141及凸台部142，所述凸台部142的厚度大于所述键合部141的厚度；所述第二光学限制层14用于限制光场，任意一种可以实现限制光场的材料层均可作为所述第二光学限制层14；
第二掺杂类型三五族材料层15，所述第二掺杂类型三五族材料层15位于所述第二光学限制层14的凸台部142表面；所述第二掺杂类型三五族材料层15可以为n型掺杂三五族材料层，也可以为p型掺杂三五族材料层。但需要说明的是，所述第二掺杂类型三五族材料层15的掺杂类型与所述第一掺杂类型三五族材料层11的掺杂类型不同，即若所述第一掺杂类型三五族材料层11为n型掺杂三五族材料层时，所述第二掺杂类型三五族材料层15为p型掺杂三五族材料层，而当所述第一掺杂类型三五族材料层11为p型掺杂三五族材料层时，则所述第二掺杂类型三五族材料层15为n型掺杂三五族材料层；所述第二掺杂类型三五族材料层15用于金属接触；
所述激光芯片1倒装焊接于所述硅光芯片2的表面，且所述第二光学限制层14的键合部141与所述第三介质层26的表面相接触。
作为示例，所述激光器与所述硅光芯片集成结构还包括：
第一焊盘16，所述第一焊盘16位于所述第二掺杂类型三五族材料层15远离所述第二光学限制层14的表面；
第二焊盘27，所述第二焊盘27位于所述第一衬底201形成有所述埋氧层202的表面；
焊球3，所述焊球3位于所述第一焊盘16与所述第二焊盘27之间，以将所述激光器芯片1与所述硅光芯片2焊接在一起。
综上所述，本发明提供一种激光器与硅光芯片集成结构及其制备方法，所述激光器与硅 光芯片集成结构包括：激光器芯片，所述激光器芯片包括第一波导；硅光芯片，所述硅光芯片包括第二波导，所述第二波导及所述第一波导将所述激光器芯片发出的光以倏逝波耦合的方式耦合至所述硅光芯片内。本发明制备的激光器与硅光芯片集成结构中激光器中的第一波导与硅光芯片中的第二波导通过倏逝波耦合的方式将激光器发出的光耦合至所述硅光芯片内，相比于现有技术中的端面耦合(即激光器中的第一波导直接与硅波导或氮化硅波导的butt-coupling)，本发明的耦合方式对倒装焊过程中的对准精度要求更低，即使在对准有误差的实际工艺条件下，仍然具有较高的耦合效率；本发明制备的激光器与硅光芯片集成结构激光器通过焊球与SOI硅衬底键合，由于硅衬底的散热性能比较好，因此激光器可以得到更为有效的散热。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

  1. 一种激光器与硅光芯片集成结构，其特征在于，包括：
    激光器芯片，所述激光器芯片包括第一波导；
    硅光芯片，所述硅光芯片包括第二波导，所述第二波导及所述第一波导将所述激光器芯片发出的光耦合至所述硅光芯片内；
    所述第一波导包括依次一体连接的第一倒锥形波导部、矩形波导部及第二倒锥形波导部；
    所述第二波导包括第一氮化硅波导、第二氮化硅波导及硅波导；其中，所述第一氮化硅波导、所述第二氮化硅波导及所述硅波导均包括依次一体连接的第一倒锥形波导部、矩形波导部及第二倒锥形波导部。
  2. 根据权利要求1所述的激光器与硅光芯片集成结构，其特征在于所述第一氮化硅波导位于所述第一波导的下方，且所述第一氮化硅波导的第一倒锥形波导部的正投影与所述第一波导的第二倒锥形波导部的正投影部分重合；所述第二氮化硅波导位于所述第一氮化硅波导的下方，且所述第二氮化硅波导的第一倒锥形波导部的正投影与所述第一氮化硅波导的第二倒锥形波导部的正投影部分重合；所述硅波导位于所述第二氮化硅波导的下方，且所述硅波导的第一倒锥形波导部的正投影与所述第二氮化硅波导的第二倒锥形波导部的正投影部分重合。
  3. 根据权利要求1所述的激光器与硅光芯片集成结构，其特征在于，各所述第一倒锥形波导部远离所述矩形波导部一端的宽度为10nm～1000nm，各所述第一倒锥形波导部与所述矩形波导部一体连接一端的宽度为100nm～10μm，各所述第一倒锥形波导部的长度为10μm～1000μm；各所述第二倒锥形波导部远离所述矩形波导部一端的宽度为10nm～1000nm，各所述第二倒锥形波导部与所述矩形波导部一体连接一端的宽度为100nm～10μm，各所述第二倒锥形波导部的长度为10μm～1000μm。
  4. 根据权利要求1所述的激光器与硅光芯片集成结构，其特征在于，所述硅光芯片还包括：
    第一衬底；
    埋氧层，位于所述第一衬底的表面；所述硅波导位于所述埋氧层远离所述第一衬底的表面；
    第一介质层，位于所述埋氧层的表面，并覆盖所述硅波导；所述第二氮化硅波导位于 所述第一介质层远离所述埋氧层的表面；
    第二介质层，位于所述第一介质层远离所述埋氧层的表面，并覆盖所述第二氮化硅波导；所述第一氮化硅波导位于所述第二介质层远离所述第一介质层的表面；
    第三介质层，位于所述第二介质层远离所述第一介质层的表面，且覆盖所述第一氮化硅波导。
  5. 根据权利要求4所述的激光器与硅光芯片集成结构，其特征在于，所述激光芯片还包括：
    第二衬底；
    第一掺杂类型三五族材料层，位于所述第二衬底的表面；
    第一光学限制层，位于所述第一掺杂类型三五族材料层远离所述第二衬底的表面；所述第一波导位于所述第一光学限制层远离所述第一掺杂类型三五族材料层的表面；
    第二光学限制层，位于所述第一波导远离所述第一光学限制层的表面；所述第二光学限制层包括键合部及凸台部，所述凸台部的厚度大于所述键合部的厚度；
    第二掺杂类型三五族材料层，位于所述第二光学限制层的凸台部表面；
    所述激光芯片倒装焊接于所述硅光芯片的表面，且所述第二光学限制层的键合部与所述第三介质层的表面相接触。
  6. 根据权利要求5所述的激光器与硅光芯片集成结构，其特征在于，所述第一波导包括三五族材料波导、多重量子阱材料波导或量子点材料波导，所述第一衬底包括硅衬底，所述第二衬底包括三五族材料衬底。
  7. 根据权利要求5所述的激光器与硅光芯片集成结构，其特征在于，所述激光器与所述硅光芯片集成结构还包括：
    第一焊盘，位于所述第二掺杂类型三五族材料层远离所述第二光学限制层的表面；
    第二焊盘，位于所述第一衬底形成有所述硅波导的表面；
    焊球，位于所述第一焊盘与所述第二焊盘之间，以将所述激光器芯片与所述硅光芯片焊接在一起。
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