WO2020062535A1 - 抗静电放电的显示面板 - Google Patents

抗静电放电的显示面板 Download PDF

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Publication number
WO2020062535A1
WO2020062535A1 PCT/CN2018/117896 CN2018117896W WO2020062535A1 WO 2020062535 A1 WO2020062535 A1 WO 2020062535A1 CN 2018117896 W CN2018117896 W CN 2018117896W WO 2020062535 A1 WO2020062535 A1 WO 2020062535A1
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Prior art keywords
substrate
metal layer
ground
group
pad
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English (en)
French (fr)
Inventor
唐维
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures

Definitions

  • the invention relates to the field of liquid crystal display, in particular to an antistatic discharge display panel.
  • static electricity is inevitable in industrial production and can cause serious harm.
  • static electricity is mainly caused by electrostatic discharge (electro-static The form of discharge (ESD) causes malfunctions or erroneous actions of electronic equipment, causes electromagnetic interference and unstable operation of electronic products, breaks down integrated circuits and precision electronic components, or promotes the aging of electronic components and reduces the production yield.
  • ESD electrostatic discharge
  • FIG. 1 is a schematic top view of a conventional electrostatic protection design of an LCD panel
  • FIG. 2 is an enlarged schematic view of part A in FIG. 1.
  • the liquid crystal display panel includes a thin film transistor substrate (TFT) 10 and a color filter substrate (CF) 20 disposed above the thin film transistor substrate 10.
  • TFT thin film transistor substrate
  • CF color filter substrate
  • the thin film transistor substrate 10 is designed with a second ground line 11 on the periphery of the panel, which is completed in the SD process, and is connected to a ground pad (FPC GND Pad) 12, which is connected to the flexible circuit board.
  • the ground pad connection is used to block or guide the static electricity on the side of the thin film transistor substrate 10; because there is no metal line on the color film substrate 20 side, it cannot be used as a ground wiring. It is used to guide subsequent processes or product ESD testing.
  • the static electricity on the color film substrate side will be a silver glue conductive point 21 on the thin film transistor substrate 10 side, and the color film substrate 20 side is connected to the first thin film transistor substrate 10 side through the silver glue conductive point 21.
  • a ground line 13 is connected to the ground pad 12 to conduct static electricity away from the color filter substrate 20 side.
  • a fanout line 14 of a first metal layer of the thin film transistor substrate 10 (because the fanout line group 14 of the first metal layer is The passivation layer is shielded, and it is shown with a dashed line in the drawing.)
  • a fan-out area C is collectively formed and connected to a first metal layer pad 15 which is connected to the signal line of the flexible circuit board. Pad connection.
  • the first ground line 13 belongs to the second metal layer and needs to be connected to the ground pad 12 across the fan-out area C.
  • the bottom of the first ground line 13 has a large-area fan-out line 14 of a first metal layer, and the fan-out line 14 of the first metal layer and the first ground line 13 are separated only by a passivation layer (ILD) (attached (Not shown in the figure), when the product undergoes a reliability test to generate static electricity, ESD is prone to occur, causing the first ground line 13 and the fan-out line 14 of the first metal layer to be short-circuited. Since the fan-out lines 14 of the first metal layer are respectively connected to TP / CT / DMUX / CK / GAS / VGL and other signal lines of the flexible circuit board, ESD will cause these signal lines to short-circuit, thereby causing the display panel to display abnormally. .
  • ILD passivation layer
  • the technical problem to be solved by the present invention is to provide an anti-static discharge display panel capable of reducing the electrostatic discharge.
  • the present invention provides an anti-static discharge display panel, which includes a first substrate and a second substrate.
  • the first substrate is opposite to the second substrate, and the first substrate includes At least one first metal layer fan-out line group, at least one first metal layer pad group, at least one conductive bump, at least one first ground line, and at least one first ground pad, the first metal layer fan-out line group Connected to the first metal layer pad group, the conductive bump is connected to a metal trace of the second substrate, one end of the first ground line is connected to the conductive bump, and the first The other end of the ground wire bypasses the side of the first metal layer pad group that is not connected to the first metal layer fan-out line group and is connected to the first ground pad, the first metal layer pad group
  • the first substrate further includes a substrate ground line, at least one second ground line, and at least one second ground line disposed on the periphery of the first substrate. A ground pad, the ground wire of the substrate passes through the second connection Line is connected to said second ground pad.
  • the first substrate includes two sets of the first metal layer fan-out lines, two sets of the first metal layer pads, two of the conductive bumps, and two The first ground line and the two first ground pads.
  • an edge of the first substrate protrudes from an edge of the second substrate to form a frame area.
  • the first metal layer fan-out line group, the first metal layer pad group, The conductive bump, the first ground line, and the first ground pad are disposed in the frame region.
  • the first substrate includes two of the second ground lines and two of the second ground pads disposed symmetrically, and the substrate ground line is disposed around the first substrate, and the substrate Both ends of the ground line are connected to one of the second ground lines, respectively.
  • one end of the second ground line is connected to the substrate ground line, and the other end of the second ground line bypasses the first metal layer pad group and does not connect with the first metal layer.
  • One side of the fanout line group is connected to the second ground pad.
  • one end of the second ground line is connected to the substrate ground line, and the other end of the second ground line passes through the first metal layer fan-out line group and is welded to the first metal layer.
  • the connection point of the pad group is connected to the second ground pad, and an insulating isolation layer is provided between the second ground line and the first metal layer fan-out line group.
  • the first substrate further includes at least one second metal layer fan-out line group, and an insulating isolation layer is provided between the second metal layer fan-out line group and the first metal layer fan-out line group.
  • the first substrate is a thin film transistor substrate
  • the second substrate is a color filter substrate
  • the present invention provides a display panel for reducing electrostatic discharge, which includes a first substrate and a second substrate.
  • the first substrate is opposite to the second substrate, and the first substrate includes at least A first metal layer fan-out line group, at least one first metal layer pad group, at least one conductive bump, at least one first ground line, and at least one first ground pad, the first metal layer fan-out line group and The first metal layer bonding pad group is connected, the conductive bump is connected to a metal trace of the second substrate, one end of the first ground line is connected to the conductive bump, and the first ground line The other end of the bypass wire is connected to the first ground pad by bypassing the side of the first metal layer pad group that is not connected to the first metal layer fan-out line group.
  • the first metal layer pad group is disposed between the conductive bump and the first ground pad.
  • the first substrate includes two sets of the first metal layer fan-out lines, two sets of the first metal layer pads, two of the conductive bumps, and two The first ground line and the two first ground pads.
  • an edge of the first substrate protrudes from an edge of the second substrate to form a frame area.
  • the first metal layer fan-out line group, the first metal layer pad group, The conductive bump, the first ground line, and the first ground pad are disposed in the frame region.
  • the first substrate further includes a substrate ground line, at least one second ground line, and at least one second ground pad disposed on the periphery of the first substrate.
  • the substrate ground line passes through the substrate.
  • a second ground line is connected to the second ground pad.
  • the first substrate includes two of the second ground lines and two of the second ground pads disposed symmetrically, and the substrate ground line is disposed around the first substrate, and the substrate Both ends of the ground line are connected to one of the second ground lines, respectively.
  • one end of the second ground line is connected to the substrate ground line, and the other end of the second ground line bypasses the first metal layer pad group and does not connect with the first metal layer.
  • One side of the fanout line group is connected to the second ground pad.
  • one end of the second ground line is connected to the substrate ground line, and the other end of the second ground line passes through the first metal layer fan-out line group and is welded to the first metal layer.
  • the connection point of the pad group is connected to the second ground pad, and an insulating isolation layer is provided between the second ground line and the first metal layer fan-out line group.
  • the first substrate further includes at least one second metal layer fan-out line group, and an insulating isolation layer is provided between the second metal layer fan-out line group and the first metal layer fan-out line group.
  • the first substrate is a thin film transistor substrate
  • the second substrate is a color filter substrate
  • An advantage of the present invention is that the first ground line avoids a fan-out area of a large area of the first metal layer, avoiding the occurrence of electrostatic discharge when the product undergoes a reliability test and generates a large static electricity, thereby avoiding the first A ground line is short-circuited with the first metal layer fan-out line group, which can improve the anti-static discharge capability of the display panel.
  • FIG. 1 is a schematic top view of a conventional electrostatic protection design of an LCD panel
  • FIG. 2 is an enlarged schematic view of part A in FIG. 1; FIG.
  • FIG. 3 is a schematic plan view of a display panel capable of reducing electrostatic discharge according to the present invention.
  • FIG. 4 is an enlarged schematic view of a portion B in FIG. 3.
  • FIG. 3 is a schematic plan view of an antistatic discharge display panel of the present invention
  • FIG. 4 is an enlarged schematic view of a portion B in FIG. 3.
  • the display panel for reducing electrostatic discharge according to the present invention includes a first substrate 30 and a second substrate 40.
  • the first substrate 30 is a thin film transistor substrate, that is, a TFT substrate
  • the second substrate 40 is a color filter substrate, that is, a CF substrate.
  • the first substrate 30 is disposed opposite to the second substrate 40, and the first substrate 30 is disposed below the second substrate 40 in FIG. 3.
  • the substrate ground line 36 of the second substrate 30 is indicated by the first
  • the part obscured by the two substrates 40 is shown by dashed lines, and the size of each component is appropriately exaggerated.
  • the first substrate 30 is a thin film transistor substrate (TFT substrate)
  • the second substrate 40 is a color filter substrate (CF substrate).
  • the first substrate 30 includes at least one first metal layer fan-out line group 31, at least one first metal layer pad group 32, at least one conductive bump 33, at least one first ground line 34, and at least one first ground bond.
  • the pad 35 since the first metal layer fan-out line group 31 is blocked by an insulating isolation layer, it is shown by a dotted line in the drawing).
  • An edge of the first substrate 30 protrudes from the second substrate 40 to form a frame region S.
  • the point 33, the first ground line 34, and the first ground pad 35 are disposed in the frame area S.
  • the lower edge of the first substrate 30 protrudes from the lower edge of the second substrate 40 to form a frame region S, that is, a lower frame region.
  • the first metal layer fan-out line group 31 The first metal layer pad group 32, the conductive bumps 33, the first ground line 34 and the first ground pad 35 are disposed in the lower frame area.
  • the side edge of the first substrate 30 protrudes from the side edge of the second substrate 40 to form a frame area S, that is, a side frame area.
  • the first metal layer fan-out line group 31 The first metal layer pad group 32, the conductive bumps 33, the first ground line 34, and the first ground pad 35 are disposed in the side frame region.
  • the first metal layer fan-out line group 31 is used to fan out metal lines belonging to the first metal layer, such as scan lines (not shown in the drawings) of the first substrate 30, and the first metal layer fan-out lines One end of the group 31 is connected to the metal line of the first metal layer, and the other end of the first metal layer fan-out line group 31 is connected to the first metal layer pad group 32.
  • the first metal layer fan-out line group 31 is manufactured simultaneously with the metal wires of the first metal layer, and belongs to the first metal layer.
  • the first metal layer fan-out line group 31 includes a plurality of first metal layer fan-out lines 311. In FIG. 4, only five first metal layer fan-out lines 311 are schematically shown.
  • the number of the first metal layer fan-out lines 311 included in the first metal layer fan-out line group 31 is not limited to five, and it needs to be determined according to the actual needs of the first substrate 30.
  • the area where the first metal layer fan-out line group 31 is defined is a fan-out area C.
  • the first metal layer pad group 32 is located on one side of the fan-out area C. Specifically, the first metal layer pad group 32 is located on a side of the fan-out region C facing away from the center of the first substrate 30.
  • the frame area S is a lower frame area
  • the first metal layer pad group 32 is located below the fan-out area C.
  • the first metal layer pad group 32 includes a plurality of first metal layer pads 321, and only five first metal layer pads 321 are schematically illustrated in FIG. 4.
  • the first metal layer pad 321 of the first metal layer pad group 32 includes, but is not limited to, providing signals such as TP / CT / DMUX / CK / GAS / VGL.
  • a flexible circuit board having an IC chip may be soldered with the first metal layer pad group 32 to connect the first metal layer to the IC chip.
  • the conductive bump 33 is connected to a metal trace of the second substrate 40. Specifically, the conductive bump 33 extends to the second substrate 40, and the second substrate 40 needs a metal trace connected to the ground to be connected to the conductive bump 33.
  • the conductive bumps 33 include, but are not limited to, silver conductive bumps.
  • One end of the first ground line 34 is connected to the conductive bump 33, and the other end of the first ground line 34 bypasses the first metal layer pad group 321 and does not fan out with the first metal layer.
  • One side of the group 31 is connected to the first ground pad 35.
  • one end of the first ground line 34 is connected to the bottom of the conductive bump 33, and the other end of the first ground line 34 extends around the first A side of a metal layer pad group 321 that is not connected to the first metal layer fan-out line group 31 is connected to the first ground pad 35.
  • one end of the first ground line 34 is connected to the bottom of the conductive bump 33, and the other end of the first ground line 34 extends to bypass the first metal layer pad group.
  • the lower end of 321 is connected to the first ground pad 35.
  • the static electricity of the second substrate 40 can be conducted to the first ground pad 35 through the conductive bump 33 and the first ground line 34.
  • the first ground pad 35 is welded to the ground terminal of the flexible circuit board, and further The static electricity of the second substrate 40 is discharged.
  • the other end of the first ground wire 34 extends around the side of the first metal layer pad group 321 that is not connected to the first metal layer fan-out line group 31 and is connected to the first ground pad 35.
  • the advantage is that the first ground line 34 avoids the fan-out area C of the large area of the first metal layer, which prevents the occurrence of electrostatic discharge when the product undergoes a reliability test and generates a large static electricity, thereby avoiding the first A ground line 34 is short-circuited with the first metal layer fan-out line group 31, which can improve the anti-static discharge capability of the display panel.
  • the first metal layer pad group 32 is disposed between the conductive bump 33 and the first ground pad 35.
  • the conductive bumps 33 are disposed on the edge of the frame region S
  • the first ground pad 35 may be disposed in the middle of the frame region S
  • the first metal layer pad group 32 is disposed In between. If the first ground line 34 is connected to the first ground pad 35, it needs to bypass the first metal layer pad group 32.
  • the first substrate 30 includes two of the first metal layer fan-out wire groups 31, two of the first metal layer pad groups 32, two of the conductive bumps 33, and two The first ground line 34 and the two first ground pads 35 are described.
  • the lines 34 and the two first ground pads 35 are symmetrically distributed around the center line of the first substrate 30.
  • the first substrate 30 further includes a substrate ground line 36, at least one second ground line 37 and at least one second ground pad 38 disposed on the periphery of the first substrate 30.
  • the substrate ground line 36 is connected to the second ground pad 38 through the second ground line 37.
  • the substrate ground line 36 is used to conduct the static electricity of the first substrate 30 to the second ground pad 38 through the second ground line 37, and the second ground pad 38 is welded to the ground end of the flexible circuit board. , And further, the static electricity of the first substrate 30 is discharged.
  • one end of the second ground line 37 is connected to the substrate ground line 36, and the other end of the second ground line 37 bypasses the first metal layer pad group 32 and is not connected to the first
  • the metal layer fan-out line group 31 is connected to one side of the second ground pad 38.
  • one end of the second ground line 37 is connected to the substrate ground line 36, and the other end of the second ground line 37 bypasses the lower end of the first metal layer pad group 32 and connects to the second The ground pad 38 is connected.
  • the second ground line 37 avoids the fan-out area C of the large-area first metal layer, which prevents the occurrence of electrostatic discharge when the product undergoes a reliability test and generates large static electricity, thereby avoiding the first
  • the two ground wires 37 are short-circuited with the first metal layer fan-out wire group 31, which can improve the anti-ESD capability of the display panel.
  • the first substrate 30 includes two of the second ground lines 37 and two of the second ground pads 38 disposed symmetrically.
  • the substrate ground line 36 is disposed around the first substrate 30, and two ends of the substrate ground line 36 are respectively connected to one of the second ground lines 37.
  • One end of the second ground line 37 is connected to the substrate ground line 36, and the other end of the second ground line 37 passes through the first metal layer pad group 32 and the first metal layer fan-out line group.
  • 31 is connected to the second ground pad 38 after the connection (ie, the fan-out area C).
  • the substrate ground line 36 is disposed around the first substrate 30, the ESD resistance of the first substrate 30 is stronger than the ESD resistance of the second substrate 40, so even if the second substrate 40 The other end of the ground wire 37 passes through the fan-out area C, which may not cause electrostatic discharge.
  • An insulating isolation layer (not shown in the drawings) is provided between the second ground line 37 and the first metal layer fan-out line group 31, and the insulating isolation layer can prevent the second ground line 37 and the The first metal layer fan-out line group 31 is turned on.
  • the first substrate 30 further includes at least one second metal layer fan-out line group 39.
  • One end of the second metal layer fan-out line group 39 is connected to a metal line (not shown in the drawing) of a second metal layer such as a data line of the first substrate 30, and the other end is connected to the second metal of the frame area S.
  • the layer pad group 50 is connected.
  • a flexible circuit board having an IC chip may be soldered with the second metal layer pad group 50 to connect the second metal layer to the IC chip.
  • the second metal layer fan-out line group 39 includes a plurality of second metal layer fan-out lines 391, and only two second metal layer fan-out lines 391 are schematically illustrated in FIG. 4.
  • the first substrate 30 may include two symmetrically disposed second metal layer fan-out wire groups 39. Accordingly, the first substrate 30 includes two symmetrically disposed second metal layer fan pad groups 50. .
  • the layer fan-out line group 39 is electrically connected to the first metal layer fan-out line group 31.

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Abstract

一种抗静电放电的显示面板，第一接地线（34）避开大面积的第一金属层的扇出区域（C），避免了在产品进行可靠性测试产生静电较大时，静电放电的发生，进而避免第一接地线（34）与第一金属层扇出线组（31）短路，可提高显示面板抗静电放电的能力。

Description

抗静电放电的显示面板 技术领域
本发明涉及液晶显示领域，尤其涉及一种抗静电放电的显示面板。
 背景技术
静电的产生在工业生产中是不可避免的，并会造成严重危害。以电子工业为例，静电主要以静电放电(electro-static discharge，ESD)的形式引起电子设备的故障或错误动作，造成电磁干扰和电子产品运行不稳定，击穿集成电路和精密的电子元件，或者促使电子元件老化，降低生产成品率。
液晶显示面板（LCD）的产品设计中，静电释放的防护设计经常使用的方法是，显示面板最外围通过柔性线路板的接地端接入驱动芯片(IC)的接地端 (GND)，其作用是屏蔽外界电荷，保护显示面板内部结构。具体地说，图1是现有的LCD面板静电防护设计的俯视示意图，图2是图1中A部位的放大示意图。请参阅图1及图2，所述液晶显示面板包括一薄膜晶体管基板（TFT）10及设置在所述薄膜晶体管基板10上方的彩膜基板（CF）20。其中，薄膜晶体管基板10被所述彩膜基板20遮挡的结构采用虚线示意性地绘示。在液晶显示面板中，薄膜晶体管基板10在面板外围设计一圈一第二接地线11，在SD制程完成，连接至一接地焊盘（FPC GND Pad）12，所述接地焊盘与柔性线路板的接地焊盘连接，用于阻挡或导走所述薄膜晶体管基板10侧的静电；所述彩膜基板20侧因无金属线路，无法做接地走线，为导走后续制程或产品ESD测试时彩膜基板侧的静电，会在薄膜晶体管基板10侧做一银胶导电点21，通过所述银胶导电点21将所述彩膜基板20侧连接至所述薄膜晶体管基板10侧的一第一接地线13，所述第一接地线13再连接至所述接地焊盘12，从而将所述彩膜基板20侧的静电导走。
 技术问题
上述方法的缺点在于，请参阅图2，在所述薄膜晶体管基板10上，所述薄膜晶体管基板10的一第一金属层的扇出线14（由于所述第一金属层的扇出线组14被钝化层遮挡，则在附图中采用虚线绘示）集中形成一扇出区域C并与一第一金属层焊盘15连接，所述第一金属层焊盘15与柔性线路板的信号线焊盘连接。第一接地线13属于第二金属层，其需跨过扇出区域C与所述接地焊盘12连接。所述第一接地线13底部具有大面积的第一金属层的扇出线14，而第一金属层的扇出线14与所述第一接地线13之间仅由钝化层（ILD）（附图中未绘示）阻隔，则在产品进行可靠性测试产生静电较大时，易发生ESD，导致所述第一接地线13与所述第一金属层的扇出线14短路。由于所述第一金属层的扇出线14分别连接柔性线路板的TP/CT/DMUX/CK/GAS/VGL等信号线，则ESD会导致该些信号线短路，从而使所述显示面板显示异常。
 技术解决方案
本发明所要解决的技术问题是，提供一种抗静电放电的显示面板，其能够降低静电放电。
为了解决上述问题，本发明提供了一种抗静电放电的显示面板，其包括一第一基板及一第二基板，所述第一基板与所述第二基板相对设置，所述第一基板包括至少一第一金属层扇出线组、至少一第一金属层焊垫组、至少一导电凸点、至少一第一接地线及至少一第一接地焊垫，所述第一金属层扇出线组与所述第一金属层焊垫组连接，所述导电凸点与所述第二基板的一金属走线连接，所述第一接地线的一端与所述导电凸点连接，所述第一接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第一接地焊垫连接，所述第一金属层焊垫组设置在所述导电凸点与所述第一接地焊垫之间，所述第一基板还包括一设置在所述第一基板外围的基板接地线、至少一第二接地线及至少一第二接地焊垫，所述基板接地线通过所述第二接地线连接至所述第二接地焊垫。
在一实施例中，所述第一基板包括对称设置的两个所述第一金属层扇出线组、两个所述第一金属层焊垫组、两个所述导电凸点、两个所述第一接地线及两个所述第一接地焊垫。
在一实施例中，所述第一基板的一边缘突出于所述第二基板的一边缘，形成一边框区域，所述第一金属层扇出线组、所述第一金属层焊垫组、所述导电凸点、所述第一接地线及所述第一接地焊垫设置在所述边框区域。
在一实施例中，所述第一基板包括对称设置的两个所述第二接地线及两个所述第二接地焊垫，所述基板接地线环绕所述第一基板设置，所述基板接地线的两端分别与一个所述第二接地线连接。
在一实施例中，所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第二接地焊垫连接。
在一实施例中，所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端穿过所述第一金属层扇出线组与所述第一金属层焊垫组的连接处与所述第二接地焊垫连接，在所述第二接地线与所述第一金属层扇出线组之间具有一绝缘隔离层。
在一实施例中，所述第一基板还包括至少一第二金属层扇出线组，所述第二金属层扇出线组与所述第一金属层扇出线组之间具有一绝缘隔离层。
在一实施例中，所述第一基板为一薄膜晶体管基板，所述第二基板为一彩膜基板。
为了解决上述问题，本发明提供了一种降低静电放电的显示面板，包括一第一基板及一第二基板，所述第一基板与所述第二基板相对设置，所述第一基板包括至少一第一金属层扇出线组、至少一第一金属层焊垫组、至少一导电凸点、至少一第一接地线及至少一第一接地焊垫，所述第一金属层扇出线组与所述第一金属层焊垫组连接，所述导电凸点与所述第二基板的金属走线连接，所述第一接地线的一端与所述导电凸点连接，所述第一接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第一接地焊垫连接。
在一实施例中，所述第一金属层焊垫组设置在所述导电凸点与所述第一接地焊垫之间。
在一实施例中，所述第一基板包括对称设置的两个所述第一金属层扇出线组、两个所述第一金属层焊垫组、两个所述导电凸点、两个所述第一接地线及两个所述第一接地焊垫。
在一实施例中，所述第一基板的一边缘突出于所述第二基板的一边缘，形成一边框区域，所述第一金属层扇出线组、所述第一金属层焊垫组、所述导电凸点、所述第一接地线及所述第一接地焊垫设置在所述边框区域。
在一实施例中，所述第一基板还包括一设置在所述第一基板外围的基板接地线、至少一第二接地线及至少一第二接地焊垫，所述基板接地线通过所述第二接地线连接至所述第二接地焊垫。
在一实施例中，所述第一基板包括对称设置的两个所述第二接地线及两个所述第二接地焊垫，所述基板接地线环绕所述第一基板设置，所述基板接地线的两端分别与一个所述第二接地线连接。
在一实施例中，所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第二接地焊垫连接。
在一实施例中，所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端穿过所述第一金属层扇出线组与所述第一金属层焊垫组的连接处与所述第二接地焊垫连接，在所述第二接地线与所述第一金属层扇出线组之间具有一绝缘隔离层。
在一实施例中，所述第一基板还包括至少一第二金属层扇出线组，所述第二金属层扇出线组与所述第一金属层扇出线组之间具有一绝缘隔离层。
在一实施例中，所述第一基板为薄膜晶体管基板，所述第二基板为彩膜基板。
 有益效果
本发明的优点在于，所述第一接地线避开大面积的第一金属层的扇出区域，避免了在产品进行可靠性测试产生静电较大时，静电放电的发生，进而避免所述第一接地线与所述第一金属层扇出线组短路，可提高显示面板抗静电放电的能力。
 附图说明
图1是现有的LCD面板静电防护设计的俯视示意图；
图2是图1中A部位的放大示意图；
图3是本发明降低静电放电的显示面板的俯视结构示意图；
图4是图3中B部位的放大示意图。
 本发明的实施方式
下面结合附图对本发明提供的降低静电放电的显示面板的具体实施方式做详细说明。
图3是本发明抗静电放电的显示面板的俯视结构示意图，图4是图3中B部位的放大示意图。请参阅图3及图4，本发明降低静电放电的显示面板包括一第一基板30及一第二基板40。在本实施例中，所述第一基板30为薄膜晶体管基板，即TFT基板，所述第二基板40为彩膜基板，即CF基板。所述第一基板30与所述第二基板40相对设置，在图3中所述第一基板30设置在所述第二基板40的下方。为了清楚说明本发明技术方案，在附图中，本发明涉及的结构被所述第二基板40遮挡的部分采用虚线绘示，例如，所述第二基板30的基板接地线36被所述第二基板40遮挡的部分采用虚线绘示，且适当夸大各个部件的尺寸。在本实施例中，所述第一基板30为薄膜晶体管基板（TFT基板），所述第二基板40为彩膜基板（CF基板）。
所述第一基板30包括至少一第一金属层扇出线组31、至少一第一金属层焊垫组32、至少一导电凸点33、至少一第一接地线34及至少一第一接地焊垫35，由于所述第一金属层扇出线组31被绝缘隔离层遮挡，则在附图中采用虚线绘示）。所述第一基板30的一边缘突出于所述第二基板40，形成一边框区域S，所述第一金属层扇出线组31、所述第一金属层焊垫组32、所述导电凸点33、所述第一接地线34及所述第一接地焊垫35设置在所述边框区域S内。例如，在本实施例中，所述第一基板30的下边缘突出于所述第二基板40的下边缘，形成一边框区域S，即下边框区域，所述第一金属层扇出线组31、所述第一金属层焊垫组32、所述导电凸点33、所述第一接地线34及所述第一接地焊垫35设置在所述下边框区域内。在其他实施例中，所述第一基板30的侧边缘突出于所述第二基板40的侧边缘，形成一边框区域S，即侧边框区域，所述第一金属层扇出线组31、所述第一金属层焊垫组32、所述导电凸点33、所述第一接地线34及所述第一接地焊垫35设置在所述侧边框区域内。
所述第一金属层扇出线组31用于将所述第一基板30的扫描线（附图中未绘示）等属于第一金属层的金属线扇出，所述第一金属层扇出线组31的一端与所述第一金属层的金属线连接，所述第一金属层扇出线组31的另一端与所述第一金属层焊垫组32连接。在显示面板的制作工艺中，所述第一金属层扇出线组31与第一金属层的金属线同时制作，其属于第一金属层。所述第一金属层扇出线组31包括多根第一金属层扇出线311，在图4中仅示意性地绘示五根第一金属层扇出线311，在显示面板的实际结构中，所述第一金属层扇出线组31包括的第一金属层扇出线311的数量不限于五根，其需要根据所述第一基板30的实际需求而定。其中，定义所述第一金属层扇出线组31所在的的区域为扇出区域C。
所述第一金属层焊垫组32位于所述扇出区域C的一侧。具体地说，所述第一金属层焊垫组32位于所述扇出区域C背离所述第一基板30中心的一侧。例如，在本实施例中，所述边框区域S为下边框区域，则所述第一金属层焊垫组32位于所述扇出区域C的下方。所述第一金属层焊垫组32包括多个第一金属层焊垫321，在图4中仅示意性地绘示五个第一金属层焊垫321。其中，所述第一金属层焊垫组32的第一金属层焊垫321包括但不限于提供TP/CT/DMUX/CK/GAS/VGL等信号。在显示面板中，具有IC芯片的柔性线路板可与所述第一金属层焊垫组32焊接，以将所述第一金属层连接至IC芯片。
所述导电凸点33与所述第二基板40的金属走线连接。具体地说，所述导电凸点33延伸至所述第二基板40，第二基板40需要接地的金属走线与所述导电凸点33连接。所述导电凸点33包括但不限于银胶导电凸点。
所述第一接地线34的一端与所述导电凸点33连接，所述第一接地线34的另一端绕过所述第一金属层焊垫组321未与所述第一金属层扇出线组31连接的一侧与所述第一接地焊垫35连接。具体的说，在所述第一基板30的表面，所述第一接地线34一端与所述导电凸点33的底部连接，所述第一接地线34的另一端则延伸绕过所述第一金属层焊垫组321未与所述第一金属层扇出线组31连接的一侧后与所述第一接地焊垫35连接。例如，在本实施例中，所述第一接地线34一端与所述导电凸点33的底部连接，所述第一接地线34的另一端则延伸绕过所述第一金属层焊垫组321的下端后与所述第一接地焊垫35连接。
第二基板40的静电可经由所述导电凸点33及所述第一接地线34传导至第一接地焊垫35，所述第一接地焊垫35与柔性线路板的接地端焊接，进而将所述第二基板40的静电导出。所述第一接地线34的另一端延伸绕过所述第一金属层焊垫组321未与所述第一金属层扇出线组31连接的一侧后与所述第一接地焊垫35连接的优点在于，所述第一接地线34避开大面积的第一金属层的扇出区域C，避免了在产品进行可靠性测试产生静电较大时，静电放电的发生，进而避免所述第一接地线34与所述第一金属层扇出线组31短路，可提高显示面板抗静电放电的能力。
在本实施例中，所述第一金属层焊垫组32设置在所述导电凸点33与所述第一接地焊垫35之间。具体地说，所述导电凸点33设置在所述边框区域S的边缘，所述第一接地焊垫35可设置在所述边框区域S的中部，所述第一金属层焊垫组32设置在两者之间。所述第一接地线34若与所述第一接地焊垫35连接，则需要绕过所述第一金属层焊垫组32。进一步，所述第一基板30包括对称设置的两个所述第一金属层扇出线组31、两个所述第一金属层焊垫组32、两个所述导电凸点33、两个所述第一接地线34及两个所述第一接地焊垫35。例如，在本实施例中，两个所述第一金属层扇出线组31、两个所述第一金属层焊垫组32、两个所述导电凸点33、两个所述第一接地线34及两个所述第一接地焊垫35以所述第一基板30的中心线对称分布。
所述第一基板30还包括一设置在所述第一基板30外围的基板接地线36、至少一第二接地线37及至少一第二接地焊垫38。所述基板接地线36通过所述第二接地线37连接至所述第二接地焊垫38。所述基板接地线36用于将所述第一基板30的静电经所述第二接地线37传导至第二接地焊垫38，所述第二接地焊垫38与柔性线路板的接地端焊接，进而将所述所述第一基板30的静电导出。
可选地，所述第二接地线37的一端与所述基板接地线36连接，所述第二接地线37的另一端绕过所述第一金属层焊垫组32未与所述第一金属层扇出线组31连接的一侧后与所述第二接地焊垫38连接。例如，所述第二接地线37的一端与所述基板接地线36连接，所述第二接地线37的另一端绕过所述第一金属层焊垫组32的下端后与所述第二接地焊垫38连接。其优点在于，所述第二接地线37避开大面积的第一金属层的扇出区域C，避免了在产品进行可靠性测试产生静电较大时，静电放电的发生，进而避免所述第二接地线37与所述第一金属层扇出线组31短路，可提高显示面板抗ESD的能力。
可选地，在本实施例中，所述第一基板30包括对称设置的两个所述第二接地线37及两个所述第二接地焊垫38。所述基板接地线36环绕所述第一基板30设置，所述基板接地线36的两端分别与一个所述第二接地线37连接。所述第二接地线37的一端与所述基板接地线36连接，所述第二接地线37的另一端穿过所述第一金属层焊垫组32与所述第一金属层扇出线组31的连接处（即扇出区域C）后与所述第二接地焊垫38连接。在本实施例中，由于所述基板接地线36环绕所述第一基板30设置，使得所述第一基板30抗ESD能力相对第二基板40抗ESD的能力更强，所以即使所述第二接地线37的另一端穿过扇出区域C，其也可能不会引起静电放电。在所述第二接地线37与所述第一金属层扇出线组31之间具有一绝缘隔离层（附图中未绘示），所述绝缘隔离层能够避免所述第二接地线37与所述第一金属层扇出线组31导通。
进一步，所述第一基板30还包括至少一第二金属层扇出线组39。所述第二金属层扇出线组39的一端与所述第一基板30的数据线等第二金属层的金属线（附图中未绘示）连接，另一端与边框区域S的第二金属层焊垫组50连接。在显示面板中，具有IC芯片的柔性线路板可与所述第二金属层焊垫组50焊接，以将所述第二金属层连接至IC芯片。所述第二金属层扇出线组39包括多个第二金属层扇出线391，在图4中仅示意性地绘示两个第二金属层扇出线391。所述第一基板30可包括两个对称设置的所述第二金属层扇出线组39，则对应地，所述第一基板30包括两个对称设置的所述第二金属层焊垫组50。
所述第二金属层扇出线组39与所述第一金属层扇出线组31之间也具有一绝缘隔离层（附图中未绘示），所述绝缘隔离层能够避免所述第二金属层扇出线组39与所述第一金属层扇出线组31导通。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (18)

  1. 一种抗静电放电的显示面板，其包括一第一基板及一第二基板，所述第一基板与所述第二基板相对设置，所述第一基板包括至少一第一金属层扇出线组、至少一第一金属层焊垫组、至少一导电凸点、至少一第一接地线及至少一第一接地焊垫，所述第一金属层扇出线组与所述第一金属层焊垫组连接，所述导电凸点与所述第二基板的一金属走线连接，所述第一接地线的一端与所述导电凸点连接，所述第一接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第一接地焊垫连接，所述第一金属层焊垫组设置在所述导电凸点与所述第一接地焊垫之间，所述第一基板还包括一设置在所述第一基板外围的基板接地线、至少一第二接地线及至少一第二接地焊垫，所述基板接地线通过所述第二接地线连接至所述第二接地焊垫。
  2. 根据权利要求1所述的抗静电放电的显示面板，其中所述第一基板包括对称设置的两个所述第一金属层扇出线组、两个所述第一金属层焊垫组、两个所述导电凸点、两个所述第一接地线及两个所述第一接地焊垫。
  3. 根据权利要求1所述的抗静电放电的显示面板，其中所述第一基板的一边缘突出于所述第二基板的一边缘，形成一边框区域，所述第一金属层扇出线组、所述第一金属层焊垫组、所述导电凸点、所述第一接地线及所述第一接地焊垫设置在所述边框区域。
  4. 根据权利要求1所述的抗静电放电的显示面板，其中所述第一基板包括对称设置的两个所述第二接地线及两个所述第二接地焊垫，所述基板接地线环绕所述第一基板设置，所述基板接地线的两端分别与一个所述第二接地线连接。
  5. 根据权利要求1所述的抗静电放电的显示面板，其中所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第二接地焊垫连接。
  6. 根据权利要求1所述的抗静电放电的显示面板，其中所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端穿过所述第一金属层扇出线组与所述第一金属层焊垫组的连接处与所述第二接地焊垫连接，在所述第二接地线与所述第一金属层扇出线组之间具有一绝缘隔离层。
  7. 根据权利要求1所述的抗静电放电的显示面板，其中所述第一基板还包括至少一第二金属层扇出线组，所述第二金属层扇出线组与所述第一金属层扇出线组之间具有一绝缘隔离层。
  8. 根据权利要求1所述的抗静电放电的显示面板，其中所述第一基板为一薄膜晶体管基板，所述第二基板为一彩膜基板。
  9. 一种抗静电放电的显示面板，其包括一第一基板及一第二基板，所述第一基板与所述第二基板相对设置，所述第一基板包括至少一第一金属层扇出线组、至少一第一金属层焊垫组、至少一导电凸点、至少一第一接地线及至少一第一接地焊垫，所述第一金属层扇出线组与所述第一金属层焊垫组连接，所述导电凸点与所述第二基板的一金属走线连接，所述第一接地线的一端与所述导电凸点连接，所述第一接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第一接地焊垫连接。
  10. 根据权利要求9所述的抗静电放电的显示面板，其中所述第一金属层焊垫组设置在所述导电凸点与所述第一接地焊垫之间。
  11. 根据权利要求9所述的抗静电放电的显示面板，其中所述第一基板包括对称设置的两个所述第一金属层扇出线组、两个所述第一金属层焊垫组、两个所述导电凸点、两个所述第一接地线及两个所述第一接地焊垫。
  12. 根据权利要求9所述的抗静电放电的显示面板，其中所述第一基板的一边缘突出于所述第二基板的一边缘，形成一边框区域，所述第一金属层扇出线组、所述第一金属层焊垫组、所述导电凸点、所述第一接地线及所述第一接地焊垫设置在所述边框区域。
  13. 根据权利要求9所述的抗静电放电的显示面板，其中所述第一基板还包括一设置在所述第一基板外围的基板接地线、至少一第二接地线及至少一第二接地焊垫，所述基板接地线通过所述第二接地线连接至所述第二接地焊垫。
  14. 根据权利要求13所述的抗静电放电的显示面板，其中所述第一基板包括对称设置的两个所述第二接地线及两个所述第二接地焊垫，所述基板接地线环绕所述第一基板设置，所述基板接地线的两端分别与一个所述第二接地线连接。
  15. 根据权利要求13所述的抗静电放电的显示面板，其中所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端绕过所述第一金属层焊垫组未与所述第一金属层扇出线组连接的一侧与所述第二接地焊垫连接。
  16. 根据权利要求13所述的抗静电放电的显示面板，其中所述第二接地线的一端与所述基板接地线连接，所述第二接地线的另一端穿过所述第一金属层扇出线组与所述第一金属层焊垫组的连接处与所述第二接地焊垫连接，在所述第二接地线与所述第一金属层扇出线组之间具有一绝缘隔离层。
  17. 根据权利要求9所述的抗静电放电的显示面板，其中所述第一基板还包括至少一第二金属层扇出线组，所述第二金属层扇出线组与所述第一金属层扇出线组之间具有一绝缘隔离层。
  18. 根据权利要求9所述的抗静电放电的显示面板，其中所述第一基板为一薄膜晶体管基板，所述第二基板为一彩膜基板。
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