WO2020062363A1

WO2020062363A1 - Method for fabricating semiconductor optoelectronic device

Info

Publication number: WO2020062363A1
Application number: PCT/CN2018/111050
Authority: WO
Inventors: 张晓东; 林文魁; 张宝顺
Original assignee: 中国科学院苏州纳米技术与纳米仿生研究所
Priority date: 2018-09-26
Filing date: 2018-10-19
Publication date: 2020-04-02
Also published as: CN110957399B; CN110957399A

Abstract

A method for fabricating a semiconductor optoelectronic device, the fabricating method comprising a step of growing and forming an optoelectronic device structure on a substrate, the optoelectronic device structure comprising an N-type layer, an active zone light-emitting layer, and a P-type layer; and further comprising: providing a mask on the optoelectronic device structure, and using the mask to perform ion implantation on any one or more among the N-type layer, the active zone light-emitting layer, and the P-type layer, thereby regulating the area and/or shape of a light-exiting region of the optoelectronic device structure. The present fabricating method may take increasing the effective usage area of a chip, lowering the damage effect to a sidewall of a material, eliminating the problem of optical crosstalk of a device, and improving the light-emitting efficiency of the device into consideration; moreover, the space between high impedance isolation regions (1, 3) may be precisely regulated in practical production by means of changing the size of a mask, thereby flexibly defining the characteristic size of a chip so as to prepare devices having a size of several microns to several hundred microns.

Description

Manufacturing method of semiconductor optoelectronic device

Technical field

The present application particularly relates to a method for manufacturing a semiconductor optoelectronic device, and belongs to the technical field of semiconductor device manufacturing.

Background technique

The light-emitting diode miniaturization and matrix technology (Micro-LED) in the field of semiconductor optoelectronic devices refers to high-density and small-size LED array display technologies integrated on the same chip with a dot pitch as low as micrometers. The lighted address LEDs are driven as independently controlled red, green and blue sub-pixels to form a display system with high speed, high contrast and wide viewing angle characteristics. Compared with LCD and OLED display technology, Micro-LED has the advantages of stable material properties, high resolution and color saturation, short response time, no image burn-in, simple optical system, low power consumption, and strong durability. Therefore, Micro-LED -LED is bound to develop into a new generation of display technology.

At present, the mainstream technology route of Micro-LED is to use micro-fabrication process technology to micro-fabricate traditional millimeter-level LED chips into miniature LED chips of tens of micrometers or smaller, and then combine Massively parallel transfer technology or monolithic arrays. Integrated technology (Arrays, monolithic integration) realizes RGB full color image display. Generally, sidewall etching damage caused by dry etching (RIE, ECR, ICP) in the microfabrication process will severely restrict the chip performance of Micro-LEDs, and high-energy etching particles will bombard the material lattice and form defects on the material surface. The dangling bond, and at the same time, the etching particles will be injected into the material. The side wall damage effect will extend a few μm into the chip, which greatly reduces the usable area of the Micro-LED device, such as the side wall damage effect. As a result, the usable area of 5μm × 5μm Micro-LED is only about 4% of the total chip size. At the same time, chip sidewall damage defects will form deep energy levels that act as non-radiative recombination centers inside the material, greatly increasing the non-radiative recombination rate of the device, making the peak luminous efficiency of Micro-LEDs generally lower than 10%, which results in tens of microns Micro-LEDs do not yet have the advantage of low power consumption. In addition, with the reduction of the size and adjacent pitch of Micro-LED devices, the lateral beam expansion will cause serious optical crosstalk between adjacent devices, which will greatly affect the color uniformity and resolution of Micro-LED devices. Causes color distortion.

The existing Micro-LED chip structure and its manufacturing technology still cannot make Micro-LED meet the requirements of commercialization. Therefore, in order to address the problem of sidewall damage and device light crosstalk during the preparation of Micro-LEDs, this application proposes a new method for manufacturing Micro-LEDs by ion implantation.

Summary of the Invention

Aiming at the practical problems of the damage effect of the side wall of the Micro-LED material and the optical crosstalk of the device, the main purpose of this application is to provide a method for manufacturing a semiconductor optoelectronic device to overcome the shortcomings of the prior art.

In order to achieve the foregoing invention objectives, the technical solutions used in this application include:

An embodiment of the present application provides a method for manufacturing a semiconductor optoelectronic device, including a step of growing an optoelectronic device structure on a substrate, the optoelectronic device structure including an N-type layer, an active region light-emitting layer, and a P-type layer; and The method includes: setting a mask on the optoelectronic device structure, and using the mask to perform ion implantation on any one or more of the N-type layer, the active region light-emitting layer, and the P-type layer, so as to regulate the The area and / or shape of the light emitting area of the optoelectronic device structure.

Compared with the prior art, the method for manufacturing a semiconductor optoelectronic device provided by this application has a simple and reliable process and is compatible with the existing process technology. It can take into account the improvement of the effective use area of the chip, the reduction of the side wall damage effect of the material, and the elimination of optical crosstalk of the device. In order to improve the luminous efficiency of the device, the pitch of the high-resistance isolation region can be precisely adjusted by changing the mask size in actual production, so as to flexibly define the characteristic size of the chip and realize device preparation with a size of several micrometers to hundreds of micrometers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a distribution of ion implantation regions in a method for manufacturing a semiconductor optoelectronic device in Embodiment 1 of the present application; FIG.

FIG. 2 is a schematic diagram of a device structure formed in step 2 of a method for manufacturing a semiconductor optoelectronic device in Embodiment 1 of the present application

3 is a schematic diagram of a device structure formed in step 4 of a method for manufacturing a semiconductor optoelectronic device in Embodiment 1 of the present application

4 is a schematic diagram of a device structure formed in step 5 of a method for manufacturing a semiconductor optoelectronic device in Embodiment 1 of the present application

5 is a schematic structural diagram of a semiconductor optoelectronic device manufactured and formed in Embodiment 1 of the present application;

6 is a schematic diagram showing a distribution of ion implantation regions in a method for manufacturing a semiconductor optoelectronic device in Embodiment 2 of the present application;

7 is a schematic structural diagram of a semiconductor optoelectronic device fabricated and formed in Embodiment 2 of the present application;

8 is a schematic diagram of a distribution of ion implantation regions in a method for manufacturing a semiconductor optoelectronic device in Embodiment 3 of the present application;

FIG. 9 is a schematic structural diagram of a semiconductor optoelectronic device manufactured and formed in Embodiment 3 of the present application; FIG.

10 is a schematic diagram showing a distribution of ion implantation regions in a method for manufacturing a semiconductor optoelectronic device in Embodiment 4 of the present application;

11 is a schematic diagram showing a distribution of ion implantation regions in a method for manufacturing a semiconductor optoelectronic device in Embodiment 4 of the present application;

FIG. 12 is a schematic structural diagram of a semiconductor optoelectronic device manufactured and formed in Embodiment 4 of the present application.

detailed description

In view of the shortcomings in the prior art, the inventor of the present case was able to propose the technical solution of the present application through long-term research and a lot of practice. The technical scheme, its implementation process and principle will be further explained as follows.

Further, the manufacturing method includes: during the ion implantation, at least independently adjusting the energy and / or dose of the implanted ions to control the depth and width of the ion implantation region.

Further, the manufacturing method includes: during the ion implantation, forming a part or all of the region of the optoelectronic device structure that is in contact with the implanted ions to form a high-resistance implantation isolation region, and the implantation isolation region surrounds and forms The light emitting area.

In some more specific embodiments, the implantation isolation region includes a first isolation implantation region and a second implantation isolation region, and the first implantation isolation region continuously penetrates the P-type layer and the active region light-emitting layer and reaches N The second implant isolation region continuously runs through the P-type layer, the active region light-emitting layer, and the N-type layer.

Further, the manufacturing method includes: during the ion implantation, forming part or all of the region of the optoelectronic device structure in contact with the implanted ion to form an implanted doped region, and the implanted doped region continuously runs through the The P-type layer and the active region light-emitting layer reach the N-type layer, thereby forming an N-type conductive mesa.

Further, the implanted ions forming the implanted doped region include silicon ions, but are not limited thereto.

In some more specific implementations, the implantation isolation region includes a third isolation implantation region, and the third implantation isolation region continuously runs through the P-type layer, the active region light-emitting layer, the N-type layer, and the substrate.

Further, the manufacturing method further includes: performing secondary ion implantation in the implantation isolation region or performing ion implantation between two implantation isolation regions of adjacent semiconductor optoelectronic devices to form an ion implantation barrier layer.

Further, the implanted ions forming the implantation isolation region and the ion implantation barrier include any one of hydrogen ions, helium ions, nitrogen ions, and fluoride ions, but are not limited thereto.

Further, the area of the light emitting region is controlled to be on the order of micrometers.

Further, the material of the mask includes any one of photoresist, silicon dioxide, silicon nitride, and metal, but is not limited thereto.

Further, the manufacturing method further includes a step of manufacturing an electrode matched with the P-type layer and the N-type layer of the optoelectronic device structure.

Further, the optoelectronic device structure includes a buffer layer, a high-resistance layer, an N-type layer, an active area light-emitting layer, and a P-type layer.

Further, the material of the substrate includes any one of sapphire, gallium nitride, silicon carbide, and silicon, but is not limited thereto.

Further, the semiconductor optoelectronic device includes any one of Micro-LED, VCSEL, SLD, and LED device, but is not limited thereto.

Further, the structure of the semiconductor optoelectronic device includes any one of a front-mounted structure, a flip-chip structure, and a vertical structure, but is not limited thereto.

The technical solution, its implementation process and principle will be further explained with reference to the drawings and specific embodiments as follows.

The method for manufacturing a semiconductor optoelectronic device provided in the embodiment of the present application epitaxially grows an LED structure on different substrate materials through a metal organic chemical vapor deposition method, and uses an ion implantation method to replace the traditional dry etching process, and simultaneously independently adjusts different The energy and dose of the implanted ions precisely control the depth of the ion implantation region, and realize the ion implantation isolation and implantation doping of semiconductor optoelectronic devices.

The manufacturing method of the semiconductor optoelectronic device provided by the embodiment of the present application uses an ion implantation isolation and doping process to replace the etching processes such as mesa isolation and N conductive mesa in the traditional process. The ion implantation has large area doping uniformity and high directivity. The characteristics such as low lateral effect can avoid etch damage to the chip, thereby significantly increasing the effective use area of the chip and improving the peak luminous efficiency of the chip. At the same time, an ion implantation barrier layer is used to avoid light crosstalk between adjacent devices.

In the embodiment of the present application, a high-resistance isolation region is formed by hydrogen (or helium, nitrogen, fluorine) ion implantation, and the depth of the high-resistance isolation region is adjusted according to the actual thickness of the LED epitaxial structure, which can be used for mutual interaction between devices. Isolation can also be used for isolation between P-type layer, active area light-emitting layer and N-type conductive mesa.

The ion implantation process in the method for manufacturing a semiconductor optoelectronic device provided in the embodiment of the present application may also select a suitable ion source for N-type or P-type doping. In this application, a high-conductivity region (that is, an implanted doped region) is formed by silicon ion implantation. ), And the depth of the high-conductivity region is adjusted according to the actual thickness of the LED epitaxial structure to form an N-type conductive mesa.

Due to the low temperature of the ion implantation process, a photoresist, a dielectric (silicon dioxide, silicon nitride, etc.) or a metal (such as aluminum) can be selected as a mask for ion implantation, which is a self-aligned mask in the preparation of semiconductor optoelectronic devices. The technology provides great flexibility, so the pitch of high-resistance isolation regions can be precisely adjusted by changing the mask size in actual production, so as to flexibly define the feature size of the chip and achieve device fabrication of sizes from several microns to hundreds of microns.

In the embodiment of the present application, an ion implantation barrier layer is used to avoid optical crosstalk between adjacent semiconductor optoelectronic devices. The ion implantation barrier layer can be implemented by performing common ion implantation on the implantation isolation layer, and can also be implanted in the area between the isolation layers of adjacent devices. By ion implantation, the ion implantation barrier layer can effectively avoid lateral beam expansion, thereby eliminating the problem of optical crosstalk between adjacent devices and greatly improving the color uniformity and resolution of semiconductor optoelectronic devices.

Further, the embodiments of the present application are suitable for the preparation of high-performance chips based on the front structure, the flip structure, and the vertical structure of different substrates by adjusting the type of implanted ions and the order of implantation, which is very beneficial to the industrialization of semiconductor optoelectronic devices. preparation.

Based on a method for manufacturing a semiconductor optoelectronic device, the following three examples are given.

Production equipment and materials:

1. Planetary disc type 2 inch 11 pieces, metal organic chemical vapor deposition (MOCVD) preparation system, used to prepare semiconductor optoelectronic devices such as Micro-LED, light emitting diode, super-radiation light emitting diode, vertical cavity surface laser;

2. Plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), and magnetron sputtering are used to prepare mask materials for the ion implantation process;

3. The ion implanter is used for ion implantation of hydrogen, helium, nitrogen, fluorine, silicon and other elements.

Example 1: Micro-LED front mounting structure

Please refer to FIGS. 1-5. The specific manufacturing process steps of a micro-LED chip front-loaded structure based on ion implantation are as follows:

Step 1: using MOCVD (metal organic chemical vapor deposition) on the sapphire substrate material to sequentially epitaxially grow a buffer nucleation layer, an N-type layer, an active region light-emitting layer, and a P-type layer to form an LED structure;

Step 2: Use a photoresist (or silicon dioxide, silicon nitride, metal aluminum, etc.) mask to define the ion implantation area, and form a high-resistance implantation isolation area 1 by hydrogen (or helium, nitrogen, fluorine) ion implantation. Adjusting the energy and dose of implanted ions to precisely control the depth of ion implantation, so that the implanted isolation region 1 penetrates the P-type layer and the active region light-emitting layer to reach the N-type layer;

Step 3: Further performing a second ion implantation on the ion implantation isolation region 1 to form an ion implantation barrier layer of the device;

Step 4: Use the photoresist (or silicon dioxide, silicon nitride, metal aluminum, etc.) mask to define the ion implantation area, and form the implanted doped area 2 by Si ion implantation. Adjust the energy and dose of the implanted ions to precisely control the ions. Implantation depth, so that the implanted doped region 2 penetrates the P-type layer and the active region light-emitting layer to reach the N-type layer to form an N-type conductive mesa;

Step 5: Use a photoresist (or silicon dioxide, silicon nitride, metal aluminum, etc.) mask to define the ion implantation area, and form a high-resistance implantation isolation area 3 by hydrogen (or helium, nitrogen, fluorine) ion implantation. Adjust the energy and dose of the implanted ions to precisely control the depth of the ion implantation, so that the depth of the implanted isolation region 3 reaches the sapphire substrate to form the isolation of the LED device;

Step 6: Further performing a second ion implantation on the ion implantation isolation region 3 to form an ion implantation barrier layer of the device;

Step 7: N- and P-electrode metals are respectively formed by an electron beam evaporation process, and rapid thermal annealing is performed to form ohmic contacts to complete the preparation of the Micro-LED device.

Example 2: Micro-LED front mounting structure

Please refer to FIGS. 6-7. The specific manufacturing process steps of a micro-LED chip front-mounted structure based on ion implantation are as follows:

Step 1: Using MOCVD (metal organic chemical vapor deposition) on the sapphire substrate to sequentially epitaxially grow a buffer nucleation layer, a high-resistance layer, an N-type layer, an active area light-emitting layer, and a P-type layer to form an LED structure;

Step 2: Use a photoresist (or silicon dioxide, silicon nitride, metal aluminum, etc.) mask to define the ion implantation region, and form a high-resistance implantation isolation region 4 by hydrogen (or helium, nitrogen, fluorine) ion implantation. Adjusting the energy and dose of implanted ions to precisely control the depth of ion implantation, so that the implanted isolation region 4 penetrates the P-type layer and the active region light-emitting layer to reach the N-type layer;

Step three: performing a second ion implantation on the ion implantation isolation region 4 to form an ion implantation barrier layer for the LED device;

Step 4: Use the photoresist (or silicon dioxide, silicon nitride, metal aluminum, etc.) mask to define the ion implantation area, and form the implanted doped area 5 by Si ion implantation. Adjust the energy and dose of the implanted ions to precisely control the ions. Implantation depth, so that the implanted doped region 5 penetrates the P-type layer and the active region light-emitting layer to reach the N-type layer to form an N-type conductive mesa;

Step 5: Use a photoresist (or silicon dioxide, silicon nitride, metal aluminum, etc.) mask to define the ion implantation area, and form a high-resistance ion implantation isolation area by hydrogen (or helium, nitrogen, fluorine) ion implantation. 7 , Adjust the energy and dose of the implanted ions to precisely control the depth of ion implantation, so that the depth of the implanted isolation region 6 reaches the high-resistance layer to form the isolation of the LED device;

Step 6: Further performing a second ion implantation on the ion implantation isolation region 6 to form an ion implantation barrier layer of the device;

Example 3: Micro-LED vertical structure

Please refer to FIGS. 8-9. The specific manufacturing process steps of the vertical structure of the micro-LED chip based on ion implantation are as follows:

Step 1: Using MOCVD (metal organic chemical vapor deposition) on the GaN or SiC substrate to sequentially epitaxially grow an N-type layer, an active region light-emitting layer, and a P-type layer to form an LED structure;

Step 2: Use the photoresist mask to define the ion implantation area, and form a high-resistance ion implantation isolation area 7 by hydrogen (or helium, nitrogen, fluorine) ion implantation, adjust the energy and dose of the implanted ions to precisely control the depth of ion implantation , So that the depth of the injection isolation region 7 completely penetrates the GaN or SiC substrate to form the isolation of the LED device;

Step 3: performing a second ion implantation on the ion implantation isolation region 7 to form an ion implantation barrier layer of the device;

Step 4: N- and P-electrode metals are respectively formed by an electron beam evaporation process, and rapid thermal annealing is performed to form ohmic contacts to complete the preparation of the Micro-LED device.

Example 4: Micro-LED flip-chip structure

Please refer to FIG. 10-12, the specific manufacturing process steps of a flip-chip structure of a micro-LED chip based on ion implantation are as follows:

Step 1: Using MOCVD (metal organic chemical vapor deposition) on the sapphire substrate to sequentially epitaxially grow an N-type layer, an active region light-emitting layer, and a P-type layer to form an LED structure, and then remove the sapphire substrate and thin it by a lift-off technique. N-type layer

Step 2: Use the photoresist mask to define the ion implantation area, and form a high-resistance ion implantation isolation area 8 by hydrogen (or helium, nitrogen, fluorine) ion implantation. Adjust the energy and dose of the implanted ions to precisely control the ion implantation depth , So that the depth of the injection isolation region 8 completely penetrates the N-type layer to form the isolation of the LED device;

Step 3: performing a second ion implantation on the ion implantation isolation region 8 to form an ion implantation barrier layer of the device;

It can be seen from Examples 1-4 that the ion implantation method can completely avoid the traditional etching of the mesa and the etching process during the formation of the N mesa to cause side wall etching damage to the chip, thereby significantly increasing the effective area of the chip and improving The chip's peak luminous efficiency, and at the same time, the barrier layer formed by the ion implantation method can effectively absorb lateral light propagation, effectively eliminating the optical crosstalk problem of semiconductor optoelectronic devices.

The ion implantation isolation, doping and blocking processes used in the embodiments of the present application are not limited to Micro-LEDs, but can also be applied to other III-nitride light-emitting devices, such as light-emitting diodes, super-radiation light-emitting diodes, and vertical cavity surfaces. Lasers, etc. Further, by adjusting the type of implanted ions and the order of implantation, the present application is suitable for the production of high-performance chips based on the front structure, the flip structure, and the vertical structure of different substrates, and is beneficial to the industrial production of semiconductor optoelectronic devices.

The process of this application is simple and reliable, compatible with the existing process technology, and can have the advantages of increasing the effective use area of the chip, reducing the damage effect of the material sidewall, eliminating the problem of optical crosstalk of the device, and improving the light emitting efficiency of the device.

It should be understood that the above-mentioned embodiments are only for describing the technical concept and features of the present application, and the purpose thereof is to enable persons familiar with the technology to understand and implement the content of the present application, and shall not limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit of this application shall be covered by the protection scope of this application.

Claims

A method for manufacturing a semiconductor optoelectronic device includes the steps of growing an optoelectronic device structure on a substrate. The optoelectronic device structure includes an N-type layer, an active region light-emitting layer, and a P-type layer. A mask is provided on the optoelectronic device structure, and any one or more of the N-type layer, the active region light-emitting layer, and the P-type layer are ion-implanted by using the mask, thereby regulating the optoelectronic device structure The area and / or shape of the light emitting area.
The manufacturing method according to claim 1, further comprising: during the ion implantation, at least independently adjusting the energy and / or dose of the implanted ions to control the depth and width of the ion implantation region.
The manufacturing method according to claim 1, comprising: during the ion implantation, forming a part or all of the region of the optoelectronic device structure in contact with the implanted ions into a high-resistance implantation isolation region, and the implantation The isolation area is enclosed to form the light emitting area.
The manufacturing method according to claim 3, wherein the implant isolation region includes a first isolation implant region and a second implant isolation region, and the first implant isolation region continuously penetrates the P-type layer and the active region. The light-emitting layer reaches the N-type layer, and the second injection isolation region continuously runs through the P-type layer, the active region light-emitting layer, and the N-type layer.
The manufacturing method according to claim 4, comprising: during the ion implantation, forming part or all of the region of the optoelectronic device structure in contact with the implanted ions into an implanted doped region, the implanted doped region The impurity region continuously penetrates the P-type layer and the active region light-emitting layer and reaches the N-type layer, thereby forming an N-type conductive mesa.
The method according to claim 5, wherein the implanted ions forming the implanted doped region include silicon ions.
The manufacturing method according to claim 3, wherein the implantation isolation region includes a third isolation implantation region, and the third implantation isolation region continuously penetrates the P-type layer, the active region light-emitting layer, and the N-type layer. As well as the substrate.
The manufacturing method according to claim 3, further comprising: performing secondary ion implantation in the implantation isolation region or performing ion implantation between two implantation isolation regions of adjacent semiconductor optoelectronic devices to form an ion implantation barrier. Floor.
The manufacturing method according to claim 8, wherein the implanted ions forming the implantation isolation region and the ion implantation barrier layer include any one of hydrogen ions, helium ions, nitrogen ions, and fluoride ions.
The manufacturing method according to claim 1, wherein an area of the light emitting region is controlled to be on the order of micrometers.
The manufacturing method according to claim 1, wherein the material of the mask comprises any one of photoresist, silicon dioxide, silicon nitride, and metal.
The manufacturing method according to claim 1, further comprising a step of manufacturing an electrode matched with a P-type layer and an N-type layer of the optoelectronic device structure.
The manufacturing method according to claim 1, wherein the optoelectronic device structure comprises a buffer layer, a high-resistance layer, an N-type layer, an active area light-emitting layer, and a P-type layer.
The manufacturing method according to claim 1, wherein the material of the substrate comprises any one of sapphire, gallium nitride, silicon carbide, and silicon.
The manufacturing method according to claim 1, wherein the semiconductor optoelectronic device comprises any one of Micro-LED, VCSEL, SLD, and LED device.
The manufacturing method according to claim 1, wherein the structure of the semiconductor optoelectronic device includes any one of a front-mounted structure, a flip-chip structure, and a vertical structure.