Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/56—Modifications of input or output impedances, not otherwise provided for
  • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
  • H03F3/2176—Class E amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
  • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H19/00—Networks using time-varying elements, e.g. N-path filters
  • H03H19/004—Switched capacitor networks
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
  • H03H7/38—Impedance-matching networks
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K7/00—Modulating pulses with a continuously-variable modulating signal
  • H03K7/08—Duration or width modulation ; Duty cycle modulation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
  • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
  • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/351—Pulse width modulation being used in an amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

• impedance matching networks are commonly used for maximizing power transfer within many radio frequency (RF) and microwave systems.
• impedance matching networks might be used to provide an impedance match from an output
• impedance of an RF power amplifier (PA) to an impedance of an RF load e.g., an antenna.
• PA RF power amplifier
• RF load e.g., an antenna
• Such impedance matching increases the transmitted power, reduces power loss and reduces or eliminates the need for additional circuit elements (e.g., isolators, etc.).
• Tunable impedance matching networks sometimes called automatic antenna tuning units.
• Conventional TMNs might be implemented as single-element or lumped-element reactive networks where at least one of the reactive elements are variable (e.g., tunable) components such that the impedance of the variable components at a particular frequency, or over a range of frequencies, can be modified.
• the reactive elements within a TMN might be arranged in circuit topologies such as a ladder-network, an L-network, a T-network, or a Pi-network.
• TMNs can be classified as either analog (continuously adjustable) or digital (adjustable among a set of discrete values).
• Analog TMNs utilize variable reactance elements having reactance values (at some frequency or over a range of frequencies) that can be tuned in a continuous manner by adjusting bias conditions.
• Digital TMNs implement the variable reactive elements as digitally switched arrays of static reactance elements. This approach allows adjustment of the impedance of the reactance values in finite and discrete steps.
• Analog TMNs are often implemented using varactor diodes (or varactor diode circuits) or micro-electromechanical systems (MEMS) varactors. Although analog TMNs allow fast and accurate impedance matching over a wide range of impedances, relatively high bias voltages are required to operate at high power levels.
• varactor diodes or varactor diode circuits
• MEMS micro-electromechanical systems
• Digital TMNs are often implemented using CMOS switches, MEMS switches, PIN diodes or discrete power transistors. Although MEMS switches have low on-state resistance and can operate up to tens of GHz with low power consumption, MEMS switches require large control voltages. PIN diode and CMOS switch-based digital TMNs exhibit low-to-moderate on-state resistance and, thus, can handle high power levels at the expense of some resistive power loss. PIN diode and CMOS switch-based digital TMNs are favorable for on-die integration, for example for Software Defined Radio (SDR) integrated circuits (ICs) and other on-chip TMNs.
• SDR Software Defined Radio
• Digital TMNs exhibit limited tuning resolution, and hence, limited accuracy with which impedance matching can be achieved.
• the use of digital TMNs can be impractical due to the large number of digital switches needed to achieve the required fine-tuning resolution.
• the concepts, systems and techniques described herein are directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms (signals) with the ability to dynamically control pulse width and phase with respect to a reference signal.
• PWM pulse width modulated
• the pulse width and phase of each PWM waveform (with respect to the reference signal) can be independently adjusted over a 0° to 360° range with arbitrarily fine resolution that is not affected by the operating frequency.
• the generated PWM signals are capable of maintaining phase and frequency lock to the reference signal for a wide modulation range of the reference signal frequency.
• the concepts, systems, devices and techniques described herein are suitable for generating accurate and dynamically adjustable PWM waveforms for HF and VHF applications.
• PSIM phase-switched impedance modulation
• TNNs tunable matching networks
• a pulse width modulation (PWM) generator includes a phase-shifting circuit that has at least one input and a plurality of outputs.
• the phase-shifting circuit is configured to receive a reference signal and, in response, provide a phase-shifted signal on each of said two or more outputs.
• Each phase-shifted signal can have a phase shift relative to the reference signal.
• the PWM generator can further include a waveform combiner.
• the waveform combiner can have a plurality of inputs with each input coupled to a respective output of the phase- shifting circuit.
• the waveform combiner can be configured to receive the phase- shifted signals from the phase-shifting circuit and, in response, generate a PWM signal having a pulse width and phase-shift relative to the reference signal.
• a PWM generator for generating a PWM signal with a pulse width and phase shift relative to a reference signal.
• the pulse width and phase shift relative to the reference signal of the PWM signal can be dynamically controlled. Because the waveform combiner is configured to generate the PWM in response to the phase-shifting signals, altering the phase-shifting signals may adjust the pulse width and phase shift relative to the reference signal of the PWM signal.
• the phase-shifting circuit can include a plurality of phase-shifting elements coupled in a parallel architecture or in a cascaded architecture.
• the phase-shifting circuit can include an In- phase/quadrature-phase (IQ) modulator having at least three inputs and at least one output.
• One input of the IQ modulator can be configured to receive the reference signal and two other inputs of the IQ modulator can be configured to receive baseband signals derived from the reference signal.
• the IQ modulator can include an adder coupled between its output and at least two of its inputs.
• the waveform combiner can include at least one of an edge detector, logic gate, flip-flop, or amplifier.
• the waveform combiner can also include a plurality of amplifiers that each have an input and an output. Each input of the amplifiers can be configured to receive a phase-shifted signal.
• the waveform combiner can further include a logic gate that has a plurality of inputs and at least one output. Each input of the waveform combiner can be configured to be coupled to the output of at least one amplifier.
• phase-shifting circuit can be configured to generate two or more phase shifted signals based upon at least one predetermined phase- shift parameter.
• the phase-shifting circuit can also be configured to receive the at least one predetermined phase-shift parameter from a controller.
• the controller can be configured to generate at least one predetermined phase-shift parameter based upon the pulse width and phase-shift relative to the reference signal of the generated PWM signal.
• the PWM generator can be realized in an integrated circuit.
• phase-shifting elements that take an input waveform and generate an output waveform locked to the input in both phase and frequency (or in both delay and frequency),
• the phase shift (or delay) between the input and the output can be dynamically controlled (via digital or analog methods), and the resolution with which the phase shift can be set ultimately determines the resolution with which one can adjust the phase and pulse width of a PWM signal.
• phase-shifting elements can be cascaded or connected in parallel to form cascaded or paralleled system architectures respectively.
• an apparatus for generating dynamically controlled pulse width modulation (PWM) signals can include two or more phase-shifting elements. Each phase-shifting element can have an input and output with the input of each phase-shifting element that can be configured to receive a reference signal.
• the apparatus can further include a waveform combiner that can be electronically coupled to the outputs of the phase-shifting elements. Each phase- shifting element can be configured to generate a respective phase-shifted signal at its output based upon the reference signal and a respective predetermined phase-shift parameter.
• the waveform combiner can be configured to generate a PWM signal having a pulse width and pulse shift based upon the phase-shifted signals generated at the outputs of the phase-shifting elements.
• the PWM signal can have a dynamically adjustable pulse width and phase shift relative to the reference signal.
• the pulse width and phase shift of the PWM signal can be dynamically controlled.
• each predetermined phase-shift parameter can include at least one of a predetermined phase shift or a predetermined pulse width.
• At least one of the phase-shifting elements can include an In-phase/Quadrature modulator or a phase-lock loop.
• each phase-shifting element can be coupled to a respective control signal.
• Each respective control signal can include the respective predetermined phase shift parameter.
• the apparatus can further include a phase detector coupled to the reference signal and the generated PWM signal.
• the phase detector can be configured to generate a phase correction signal based upon a comparison of the reference signal to the generated PWM signal. The phase correction signal can be provided to each phase-shifting element.
• the waveform combiner can include at least one edge detector, each edge detector being coupled to at least one flip-flop.
• the flip- flop can be configured to generate the PWM signal based upon a rising edge of at least one generated phase-shifted signal and a rising edge of at least one other generated phase-shifted signal.
• an apparatus for generating dynamically controlled pulse width modulation (PWM) signals can include a first phase- shifting element having input and outputs. The input of the first phase-shifting element can be coupled to a reference signal.
• the apparatus can also include a second phase-shifting element that can have an input and output. The input of the second phase shifting element can be coupled to the output of the first phase- shifting element.
• the apparatus can also include a waveform combiner that can be electronically coupled to the outputs of the first and second phase-shifting elements.
• the first phase-shifting element can be configured to generate a first phase-shifted signal at its output based upon the reference signal and a respective predetermined phase shift.
• the second phase-shifting element can be configured to generate a second phase-shifted signal at its output based upon the first phase-shifted signal and a respective predetermined phase shift.
• the waveform combiner can be configured to generate a PWM signal having a pulse width and pulse shift based upon the first and second phase-shifted signals.
• each phase- shifting element may receive a distinct, unrelated phase-shift parameter. Due to this, fewer phase-shift parameters may need to be adjusted to achieve a desired pulse width and phase-shift relative to the reference signal for the generated PWM signal.
• each predetermined phase-shift parameter can include at least a predetermined phase shift or a predetermined pulse width.
• At least one of the phase-shifting elements can include an In-phase/Quadrature modulator.
• the apparatus can also include a control circuitry coupled to the at least one In-phase/Quadrature modulator, said control circuitry configured to provide a control signal to the at least one In- phase/Quadrature modulator.
• the control signal can include a respective predetermined phase shift parameter for the In-phase/Quadrature modulator.
• At least one of the phase-shifting elements comprises a phase-lock loop.
• the apparatus can further include a phase detector that can be coupled to the reference signal and the generated PWM signal.
• the phase detector can be configured to generate a phase correction signal based upon a comparison of the reference signal to the generated PWM signal.
• each phase-shifting element can further be configured to generate a phase-shifted signal based upon the phase correction signal.
• the waveform combiner can include at least one logic gate.
• the logic gate can be configured to compare the first and second phase-shifted signals.
• an apparatus for generating dynamically controlled pulse width modulation (PWM) signals can include a first set of phase-shifting elements electronically coupled in parallel and each having an input and output. The inputs of the first set of phase-shifting elements can each electronically coupled to a reference signal.
• the apparatus can also include a second set of phase-shifting elements electronically coupled in parallel and each having an input and output. The inputs of the second set of phase-shifting elements can each electronically coupled to the output of at least one phase- shifting element of the first set.
• the apparatus can also include a waveform combiner electronically coupled to the outputs of the phase-shifting elements of the first and second sets.
• Each phase-shifting element of the first set can be configured to generate a respective phase-shifted signal at its output based upon the reference signal and a respective predetermined phase shift.
• Each phase- shifting element of the second set can be configured to generate a respective phase-shifted signal at its output based upon at least one phase- shifted signal generated by a phase-shifting element of the first set and a respective
• the waveform combiner can be configured to generate a dual-pulse PWM signal having a first pulse with a pulse width and pulse shift based upon the phase-shifted signals generated by the phase-shifting elements of the first set.
• the PWM signal can also have a second pulse with a pulse width and pulse shift based upon the phase-shifted signals generated by the phase-shifting elements of the second set.
• the dual pulse PWM signal can have two pulse widths and phase shifts relative to a reference signal that can be
• phase-switched reactance elements By having two pulse widths and phase shifts, multiple phase-switched reactance elements can be driven at once.
• phase-shifting elements of the first set can be electronically coupled in a parallel architecture.
• the inputs of each phase-shifting element of the first set can be coupled to the reference signal.
• the phase-shifting elements of the first set can be coupled in a cascading architecture
• a method for generating dynamically controlled pulse width modulation (PWM) waveforms can include receiving a reference signal at one or more phase-shifting elements. Each phase-shifting element can have a respective predetermined phase-shift parameter.
• the method can also include generating respective phase-shifted signals at outputs of the one or more phase-shifting elements based upon the reference signal and the respective predetermined phase shift parameters.
• the method can further include combining the generated phase-shifted signals to obtain a PWM waveform having a pulse width and phase shift based upon the predetermined phase shift parameters of the phase-shifting elements.
• a method for generating a PWM signal with dynamically controlled pulse widths and phase shifts relative to a reference signal is provided.
• the pulse width and phase shifts of the PWM signal can be dynamically controlled.
• each respective predetermined phase shift parameter can include at least one of a respective predetermined phase shift or respective predetermined pulse width.
• the method can further include providing a respective control signal to each phase-shifting element.
• the control signal can include the respective predetermined phase shift parameter.
• the method can also include generating a phase correction signal based upon a comparison of the reference signal to the PWM waveform.
• the method can further include adjusting the generated phase-shifted signals based upon the phase correction signal.
• a power generation and delivery system having an input port and an output port.
• the power generation and delivery system can include a pulse width modulation (PWM) signal generator that can include one or more phase-shifting elements.
• the PWM signal generator can be to generate a PWM signal based upon a phase-shift parameter associated with the one or more phase-shifting elements.
• the power generation and delivery system can also include a phase-switched tunable impedance network coupled to the output port.
• the phase-switched tunable impedance network can be configured to receive a generated PWM signal from the PWM signal generator, and, in response, can vary an impedance thereof to modulate an impedance presented to the output port.
• a phase-switched tunable impedance (PSIM) network driven by a PWM signal is provided. Because the PWM signal generated by the PWM generator can have its pulse width or phase shift relative to a reference signal dynamically adjusted, these parameters may be adjusted in order to change the impedances presented by the PSIM.
• PSIM phase-switched tunable impedance
• the one or more phase-shift elements are electronically coupled in a parallel architecture or cascading architecture.
• FIG. 1 is a block diagram of an illustrative tunable impedance matching network (TMN) in accordance with described embodiments;
• FIG. 2 is a schematic diagram of an illustrative phase-switched variable capacitance element of the TMN of FIG. 1 ;
• FIG. 3 is a plot of current and voltage versus phase with respect to a control signal of the phase-switched variable capacitance element of FIG. 2;
• FIG. 4 is a schematic diagram of an illustrative phase-switched variable inductance element of the TMN of FIG. 1 ;
• FIG. 5 is a plot of current and voltage versus phase with respect to a control signal of the phase-switched variable inductance element of FIG. 4;
• FIG. 6 is a plot of normalized effective capacitance (or inductance) of the phase-switched elements of FIGs. 2 and 4 versus a control angle of the phase-switched element;
• FIG. 7 is a plot of total harmonic distortion of the phase-switched elements of FIGs. 2 and 4 versus the control angle of the phase-switched element;
• FIG. 8 is a plot of current and voltage versus phase with respect to a control signal of a full-wave switched variable capacitance element
• FIG. 9 is a plot of current and voltage versus phase with respect to a control signal of a full-wave switched variable inductance element
• FIGs. 10A-D are schematic diagrams of illustrative switched reactance elements in accordance with described embodiments.
• FIG. 11 is a schematic diagram of an illustrative phase-switched tunable matching network (TMN) employing a digitally-switched capacitance matrix;
• TNN phase-switched tunable matching network
• FIG. 12 is a schematic diagram of an illustrative phase-switched TMN employing a digitally-switched inductance matrix
• FIG. 13 is a schematic diagram of an illustrative phase-switched TMN in accordance with described embodiments
• FIG. 14 is a Smith chart of a range of load impedances that can be matched by the tuning network of FIG. 13 for an illustrative operating range
• FIG. 15 is a schematic diagram of additional detail of the tuning network of FIG. 13;
• FIG. 16 is a block diagram of an illustrative topology of a phase- switched impedance modulation amplifier in accordance with described embodiments
• FIG. 17 is a block diagram of another illustrative topology of a phase-switched impedance modulation amplifier in accordance with described embodiments.
• FIGs. 18A-E are schematic diagrams of illustrative three-switch phase-switched impedance modulation amplifiers in accordance with described embodiments.
• FIGs. 19 and 20 are schematic diagrams of illustrative two-switch phase-switched impedance modulation amplifiers in accordance with described embodiments;
• FIG. 21 is a schematic diagram of an illustrative phase-switched impedance modulation amplifier over an illustrative operating range
• FIGs. 22 and 23 are Smith charts showing a range of load impedances that can be matched by the phase-switched impedance modulation amplifier of FIG. 21 for an illustrative operating range
• FIG. 24 is a flow diagram of an illustrative process of operating a TMN
• Fig. 25A is a block diagram of a system for generating pulse width modulated (PWM) signals having predetermined phase shifts and pulse widths;
• PWM pulse width modulated
• Fig. 25B is a plot of a pulse width modulated (PWM) waveform having pulse width w and a phase shift f relative to a reference signal with the PWM signal being in phase and frequency lock with the reference signal;
• PWM pulse width modulated
• Fig. 26 is a block diagram of a PWM generation circuit having a parallel architecture
• Fig. 27 is a block diagram of a PWM generation circuit having a cascade architecture
• Fig. 28 is a block diagram of a PWM generator circuit having a dual- pulse PWM generation architecture
• Fig. 29 is a block diagram of a PWM generation circuit having a parallel PWM generation architecture with two phase-shifting elements and a phase detector feedback loop;
• Fig. 30 is a block diagram of a system having an architecture capable of generating multiple PWM waveforms that are phase- and frequency- locked to a common reference signal;
• Fig. 31 is a block diagram of a PWM generation circuit having an in- phase / quadrature-phase (IQ) modulator;
• Fig. 32 is a phase diagram illustrating a phase shift according to baseband inputs of an IQ modulator;
• Fig. 33 is a block diagram of a PWM generation circuit having a parallel PWM generation architecture with two phase-shifters implemented as IQ modulators;
• Fig. 34 is a plot of phase shift command vs. measured phase shift error for a pair of output signals from respective ones of IQ modulators of the PWM generation circuit of FIG. 33;
• Fig. 35 is a plot of phase shift command vs. measured phase shift standard deviation for a pair of output signals from respective ones of IQ modulators of the PWM generation circuit of FIG. 33;
• Fig. 36 is a block diagram of a cascaded PWM waveform generator having phase-shifting elements implemented using phase-locked loop (PLL) modules coupled to a waveform combiner;
• PLL phase-locked loop
• Fig. 37 is a block diagram of the cascaded phase-locked PWM generator of Fig. 36 having a waveform combiner provided from a D-type flip-flop and edge detectors;
• Fig. 38 is a block diagram of a PWM signal generation system implemented with a PLL
• Fig. 39 is a block diagram of a PWM generation system having a nested PLL architecture with feedback
• Fig. 40 is a flowchart of a method of generating PWM signals with desired phase shifts and pulse widths;
• Fig. 41 A is a block diagram of an impedance matching system comprising a plurality of phase-switched, impedance (PSIM) elements driven by PWM generators;
• PSIM phase-switched, impedance
• Fig. 41 B is a block diagram of a radio frequency (”RF”) amplifier having a phase-switched tunable impedance network coupled to a system for generating PWM signals with desired phase shifts and pulse widths;
• RF radio frequency
• Fig. 42 is a block diagram of a system having a phase-switched tunable impedance network having one phase-switched tunable impedance element coupled to a PWM generator;
• Fig. 43 is a block diagram of a system having a phase-switched tunable impedance network having two phase-switched tunable impedance elements coupled to two PWM generators.
• Described embodiments are directed toward phase-switched, tunable matching networks (PS-TMNs) and phase-switched, impedance
• phase-switched, tunable matching networks and the phase-switched, impedance modulation amplifiers include phase-switched variable network reactance elements.
• phase-switched variable network reactance elements provide rapid, high bandwidth, continuous impedance matching over a wide impedance range, while operating efficiently at high power levels without requiring high bias voltages or currents.
• PS-TMNs might be employed alone, or might also be employed in combination with other matching techniques such as discrete switched reactance banks.
• PS-TMNs might be employed in a variety of reconfigurable and adaptive RF systems, for example, RF front ends for software-defined radio (SDR) and cognitive radio (CR) applications that operate over a wide range of frequency bands, at different bandwidths, and in accordance with a variety of communication standards.
• PS-TMNs might also be employed in other RF applications, such as drivers for RF plasma loads to compensate for rapid load variations, or in wireless power transfer (WPT) systems to compensate for impedance mismatches between the transmitter and receiver to maximize transferred power and/or efficiency.
• WPT wireless power transfer
• the PSIMs may be operable as zero voltage switching (ZVS) radio frequency (RF) amplifiers.
• ZVS zero voltage switching
• RF radio frequency
• Such PSIM amplifiers might employ a PS-TMN to operate over a large frequency range by efficiently modulating output power over a wide frequency range and/or matching into highly variable loads (e.g., loads that are variable over a wide impedance range).
• a radio frequency (RF) system 100 includes a phase-switched tunable impedance matching network (PS-TMN) 112 coupled between a source 102, having an impedance Zs, and a load 114, having an impedance ZL.
• PS-TMN phase-switched tunable impedance matching network
• source 102, control circuit 106 and PS-TMN 112 are coupled to a power supply voltage (e.g., VDC) and ground.
• Control circuit 106 is coupled to PS-TMN 112 and provides control signals to PS-TMN 112 so as to control operation of PS-TMN 112. In response to such control signals, PS-TMN 112 provides a desired impedance transformation characteristic.
• control circuit 106 might be an internal component to PS-TMN 112, or might be an external component coupled to PS-TMN 112 or some portions of control circuit 106 (or functions provided by control circuit 106 may be internal to PS-TMN 112 while other portions of control circuit 106 may be external to PS-TMN 112).
• control circuit 106 controls operation of PS- TMN 112 based, at least partially, upon information received from an optional feedforward circuit 104 coupled to source 102 and/or an optional feedback circuit 110 coupled to load 114.
• optional feedforward circuit 104 includes adaptive predistortion circuit 107 and control circuit 106 includes look up table (LUT) 108.
• LUT look up table
• some embodiments might employ one or more non-linear control techniques (e.g., by control circuit 106) to determine appropriate control signals for PS-TMN 112, such as employing fixed or adaptable look-up tables (e.g., LUT 108) to store
• predetermined control signal information feedback (e.g., by feedback circuit 110) and/or feedforward compensation (e.g., by feedforward circuit 104) to adaptively adjust control signal information, or performing digital predistortion of the control signals (e.g., by predistortion circuit 107), or other similar techniques.
• PS-TMN 112 includes one or more phase-switched reactance elements 116(1) - 116 ⁇ N).
• phase- switched reactance elements 116(1) - 116 ⁇ N might be implemented using one or more capacitive elements (e.g., capacitors), one or more inductive elements (e.g., inductors), or a combination of both.
• Phase-switched reactance elements 116(1) - 116(W) can be controlled to adjust the effective impedance (ZS.IN and ZL.IN) presented to the terminals of PS-TMN 112 at a desired frequency.
• phase- switched reactance elements 116(1) - 116 ⁇ N) are switched, for example by either a shunt or a series switch, and the effective impedance of the phase-switched reactance elements is controlled by adjusting the phase and/or duty-cycle of the shunt or series switch.
• the desired frequency might be the RF frequency of operation of RF source 102 (e.g., the frequency of the signal provided from RF source 102 to PS-TMN 112).
• phase-switched reactance elements 116(1) - 116(W) allow PS-TMN 112 to present a desired impedance (ZS.IN) to PS-TMN 112 from source 102 and a desired impedance (ZL.IN) into PS-TMN 112 from load 114.
• the control signals provided to PS-TMN 112 operate to control the timing of turning on and/or off the switches of phase-switched reactance elements 116(1) - 116 ⁇ N) with respect to the RF signal provided from source 102.
• the switching provides the effective reactance values of phase-switched reactance elements 116(1) - 116 ⁇ N) that effect the desired impedance transformation of PS- TMN 112.
• Feedforward information might include information about the effective input impedance of PS-TMN 112, the timing of RF waveforms, specified signal levels and/or impedance levels, etc.
• Feedback information might include measured information about the effective load impedance and/or power reflected from the load, the timing of RF waveforms, etc.
• PS-TMN 112 might be employed to provide a desired impedance transformation between source 102 and load 114.
• PS-TMN 112 might provide an impedance match between source 102 and load 114.
• the impedance of PS-TMN 112 might be adjusted to compensate for variations in the impedance (ZL) of load 114 such that source 102 is coupled to a more stable impedance (e.g. , ZS.IN) provided by PS-
• sinusoidal current source 202 having a current I, drives an illustrative phase-switched variable reactance 200.
• the phase- switched variable reactance is here shown as including a parallel combination of a capacitor 204 and switch 206 to provide the phase-switched variable reactance as phase-switched variable capacitance 200.
• Capacitor 204 has a physical capacitance Co, and a voltage Vc.
• the state of switch 206 is controlled by a characteristic of signal Q.
• switch 206 provides a low impedance signal path between its terminals (e.g., switch 206 is“on” or“closed”) when signal Q has a logic high value, and switch 206 provides a high impedance signal path between its terminals (e.g., switch 206 is“off” or“open”) when signal Q has a logic low value.
• switch 206 could be considered to switch capacitor 204 into the circuit when the switch is open (current I flows into capacitor 204), and out of the circuit when the switch is closed (current I flows through the closed switch and bypasses capacitor 204).
• switch 206 If switch 206 is always off (open), then the effective capacitance, CEFF, of phase-switched variable capacitance 200 presented to source 202 is equivalent to the physical capacitance, Co, of capacitor 204.
• switch 206 if switch 206 is always on (closed), then the low impedance path between the terminals of switch 206 effectively“shorts” capacitor 204, and phase-switched variable capacitance 200 behaves as an infinite capacitor in the sense that the voltage across capacitor 204 remains zero irrelevant of current I.
• the effective capacitance, CEFF, of capacitor 204 can theoretically be controlled between Co and infinity by controlling the conduction angle of switch 206 over an AC cycle of sinusoidal current source 202 from 0 to 2TT.
• a conduction angle is the angle of the sinusoidal signal at which switch 206 is turned on.
• conduction angle with which the switch is turned on may be entirely determined by a switching signal Q (e.g., the switching angle) or partly determined by switching signal Q and partly by circuit waveforms such as voltage Vc and current I.
• a switching signal Q e.g., the switching angle
• circuit waveforms such as voltage Vc and current I.
• illustrative waveforms of the current I and capacitor voltage Vc are shown with respect to the switch control signal, Q, as a function of a cycle angle Q.
• curve 302 shows 1(0)
• curve 306 shows Vc(0)
• curve 304 shows Q(0) for a half-wave switched capacitor.
• switch 206 is turned off (opened) a radians after 1(0) transitions from negative to positive (e.g., switch 206 is on/closed until a radians into the positive half-cycle of 1(0)).
• Switch 206 remains off (open) until after the capacitor voltage rings down to zero. Biasing the switch into its conductive state (e.g., turning the switch on or closing the switch) after the capacitor voltage rings down to zero ensures zero-voltage-switching (ZVS) turn on of switch 206.
• ZVS zero-voltage-switching
• the switch includes a diode that naturally prevents the voltage from going negative, the timing of actively turning switch Q on may be relaxed, since it will naturally commutate ON” when the switch voltage reaches zero and the active turn-on signal can be issued while the diode conducts.
• the capacitor Co across the switch provides snubbing of the turn off transition, providing zero- voltage-switching (ZVS) turn off of switch 206.
• switch 206 when l(0) is a purely sinusoidal current source, switch 206 remains off (open) until the conduction angle of the switch is reached (e.g., at 2a). Thus, for a half-wave switched capacitor, switch 206 is turned on and off once per cycle of the RF signal from source 102 (e.g., I(0) as shown by curve 302)
• phase-switched variable inductance 400 includes a series combination of inductor 404 and switch 406 being driven by a sinusoidal voltage source 402 with a voltage V.
• Inductor 404 has a physical inductance Lo, and an inductor current II.
• the state of switch 406 is controlled by the signal Q, for example, switch 406 might be on (e.g., closed) when signal Q has a logic high value, and off (e.g., open) when signal Q has a logic low value.
• switch 406 could be considered to switch inductor 404 into the circuit when the switch is closed (applying voltage V to inductor 404), and out of the circuit when the switch is open (no voltage is applied to inductor 404).
• the effective inductance LEFF of phase-switched variable inductance 400 at the switching frequency can be modulated from a base value Lo to infinity.
• the effective inductance, LEFF, of phase-switched variable inductance 400 seen by source 402 is equivalent to the physical inductance, Lo, of inductor 404.
• switch 406 is always off (open)
• inductor 404 behaves as an infinite inductor in the sense that the current through inductor 404 remains zero irrelevant of voltage V.
• the effective inductance, LEFF, of inductor 404 can ideally be controlled between Lo and infinity by controlling the conduction angle of switch 406 over an AC cycle of sinusoidal voltage source 402 from 0 to 2TT.
• FIG. 5 illustrative waveforms of the current I and voltage Vc of capacitor 204 are shown with respect to the switch control signal, Q, as a function of a cycle angle Q.
• the voltage waveform of the switched capacitor network shown in FIG. 3 is analogous to the current waveform of the switched inductor network shown in FIG. 5, and vice versa.
• curve 502 shows Ii_(q)
• curve 506 shows V(0)
• curve 504 shows Q(0) for a half-wave switched inductor.
• switch 406 is turned on (closed) a radians after V(0) transitions from negative to positive (e.g., switch 406 is off/open until a radians into the positive half-cycle of V(0)).
• Switch 406 remains on (closed) until after the inductor current rings down to zero. Since the switch has an inductor in series with it, zero- current-switching (ZCS) turn on of the switch can be achieved.
• ZCS zero- current-switching
• switch 406 turns off at the time when the inductor current rings down to zero ensures zero-current- switching (ZCS) turn off of switch 406.
• ZCS zero-current- switching
• expression (1 b) for the effective inductance is the same as that of expression (1 a) for the effective capacitance.
• the effective capacitance CEFF or the effective inductance LEFF at the switching frequency can be modulated by controlling the conduction angle of the switch associated with the capacitor or inductor.
• the normalized effective capacitance, CEFF/CO, or the normalized effective inductance LEFF/LO is shown by curve 602 at the switching frequency.
• the normalized admittance YEFF/YO while for the inductive circuit this is the same as the normalized reactance, XEFF/XO.
• the normalized effective admittance YEFF/YO of the phase-switched capacitor circuit of Fig. 2 is the same as the normalized reactance, XEFF/XO of the phased-switched inductor network shown in FIG. 4.
• the normalized effective capacitance CEFF (or inductance LEFF) increases rapidly with a and approaches infinity as a approaches p (e.g., 180 degrees).
• curve 702 shows the total harmonic distortion of the capacitor voltage (inductor current) versus a for a purely sinusoidal current (voltage) excitation source.
• the practical range over which CEFF or LEFF can be modulated depends on the amount of harmonic distortion that can be present in the network.
• p e.g., the conduction angle of the switch increases
• the ringing of the capacitor voltage Vc e.g., curve 306
• the inductor current II e.g., curve 502
• FIG. 7 shows the harmonic distortion of the phase- switched variable reactance (e.g., the harmonic distortion of the capacitor voltage of phase-switched variable capacitance 200, or the harmonic distortion of the inductor current of phase-switched variable inductance 400), and not the harmonic content that is actually injected into the source and/or load of the RF system (e.g., source 102 and load 114).
• the phase-switched variable reactance e.g., phase-switched variable capacitance 200 or phase-switched variable inductance 400
• additional filtering components not shown in FIGs. 2 and 4 to reduce harmonic content injected into the source and/or load (e.g., source 102 and load 114).
• phase-switched variable reactance e.g., phase-switched variable capacitance 200 or phase-switched variable inductance 400
• the switch is operated so that the capacitor voltage (curve 306 of FIG. 3) and inductor current (curve 502 of FIG. 5) are unipolar.
• FIGs. 8 and 9 show illustrative waveforms of the current I and voltage V with respect to the switch control signal, Q, as a function of a cycle angle Q, for the switched capacitor network shown in FIG. 3 and the switched inductor network shown in FIG. 5, respectively.
• curve 802 shows I(q)
• curve 806 shows Vc(0)
• curve 804 shows Q(0) for a full-wave switched capacitor.
• curve 902 shows IL(0)
• curve 906 shows V(0)
• curve 904 shows Q(0) for a full-wave switched inductor.
• the switch e.g., switch 206
• the switch is turned off twice every cycle of l(0) (e.g., Q(0) is zero), with the off periods being centered around the instants when the current l(0) is zero.
• Capacitor voltage Vc(0) has zero DC average value.
• the switch e.g., switch 406 is turned on twice every cycle of V(0) (e.g., Q(0) has a logic high value), with the on periods being centered around the instants when the voltage V(0) is zero. For a purely sinusoidal excitation voltage V(0), this results in a bipolar inductor current waveform IL(0), which also has zero DC average value.
• switch 206 is turned on and off twice per cycle of the RF signal from source 102 (e.g., I(0) as shown by curve 802).
• the effective capacitance CEFF and the effective inductance LEFF at the switching frequency can be modulated by controlling the switching angle, a, of the switch.
• the effective capacitance, CEFF, of capacitor 204 can be represented as a function of a for a full-wave switched capacitor:
• the effective inductance, LEFF, of inductor 404 can be represented as a function of a:
• the effective capacitance/inductance that can be achieved for a given switching angle, a is half the effective capacitance/inductance that can be achieved with half-waved switched networks (e.g., relationships (1 a) and (1 b)).
• full-wave switched networks inherently result in reduced harmonic content of the capacitor voltage and inductor current compared to half-wave switched networks for the same switching angle, a (i.e. the switching angle which controls the total switch conduction angle).
• implementing full-wave switching requires the switch has to operate at twice the operating frequency (e.g., to switch twice per cycle).
• Relationships (1 ) and (2) above show that the effective capacitance and inductance for the switched networks shown in FIGs. 2 and 4 can be based upon the switching angle, a, for purely sinusoidal excitation signals.
• the effective reactance can be controlled by appropriately selecting the timing or switching angle, a, at which the switch turns off (or on) although relationships (1 ) and (2) cannot calculate an exact value of a.
• switching angle a determines the total conduction angle of the switch during the cycle.
• an adaptable look-up table e.g., LUT 108
• feedback circuit 110 or feedforward circuit 104 (including optional digital predistortion circuit 107) might be employed to determine the required value of a for a given desired effective reactance.
• Phase-switched variable capacitance 200 and phase-switched variable inductance 400 can be employed as building blocks for implementing phase-switched variable reactances and other adjustable circuits such as TMNs. Particularly, some applications could benefit substantially from variable
• phase-switched variable capacitance 200 and/or phase-switched variable inductance 400 with additional reactive components can provide a wider range of variable reactances.
• FIGs. 10A-10D show illustrative embodiments of phase-switched reactance circuits that include both capacitive and inductive elements, thereby expanding a range over which the impedance of the phase-switched reactance circuit can be tuned as compared to the single-element circuits shown in FIGs. 2 and 4.
• FIG. 10A shows phase-switched reactance circuit 1002 that includes inductor 1012 in series with phase-switched capacitor 1013.
• Phase-switched capacitor 1013 includes switch 1016 in parallel with capacitor 1014, similarly as described in regard to FIG. 2.
• FIG. 10B shows phase-switched reactance circuit 1004 that includes inductor 1024 in series with capacitor 1022, with the series combination of inductor 1024 and capacitor 1022 arranged in parallel with phase-switched capacitor 1025.
• Capacitor 1022 is not phase- switched and, thus, is shown as CDC.
• Phase-switched capacitor 1025 includes switch 1028 in parallel with capacitor 1026, similarly as described in regard to FIG. 2.
• FIG. 10C shows phase-switched reactance circuit 1006 that includes capacitor
• phase-switched inductor 1032 1032 in parallel with phase-switched inductor 1033.
• FIG. 1033 includes switch 1036 in series with inductor 1034, similarly as described in regard to FIG. 4.
• FIG. 10D shows phase-switched reactance circuit 1008 that includes inductor 1042 in parallel with capacitor 1044, with the parallel
• phase-switched inductor 1045 includes switch 1048 in series with inductor 1046, similarly as described in regard to FIG. 4.
• circuit variants other than the ones illustrated in FIGs. 10A-10D are also possible. For example, placing a capacitor in series with a phase-switched capacitor provides a net effective impedance having a maximum capacitance equal to the series
• phase- switched variable capacitance 200 and phase-switched variable inductance 400 between their variable reactance range and the amount of harmonic content injected into the rest of the system.
• the range over which the effective reactance can be controlled is limited by the amount of harmonic content that can be tolerated within the system (e.g., by source 102 and/or load 114).
• Some embodiments might employ additional or external filtering components to reduce harmonic content injected to source 102 and/or load 114. Flowever, in some embodiments, it might not be possible to employ additional filtering components.
• the harmonic content can be reduced by combining phase-switched variable capacitance 200 and phase-switched variable inductance 400 with one or more digitally controlled capacitor or inductor matrices that are not phase-switched.
• Such hybrid switched networks include an RF switch operated at the RF frequency of operation and with controlled phase and duty cycles with respect to the RF waveform.
• the hybrid switched network also includes digital switches associated with one or more capacitors or inductors in the switched matrix. The digital switches are typically operated at a much lower frequency than the RF frequency, but could be operated up to the RF frequency (e.g., on a cycle-by-cycle basis) determined by the control bandwidth of the effective reactance CEFF or LEFF.
• hybrid switched network 1100 includes a phase-switched reactance (e.g., capacitor Co 1116 and parallel switch 1118) and digitally controlled capacitor network 1102.
• phase-switched reactance e.g., capacitor Co 1116 and parallel switch 1118
• digitally controlled capacitor network 1102. Although shown as a phase-switched variable capacitance (e.g., capacitor Co 1116 and parallel switch 1118) coupled in parallel with digitally controlled capacitor network 1102 and load 114, in other embodiments, the phase-switched reactance might be implemented as a phase- switched variable inductance (e.g., such as shown in FIG. 4) coupled in series with digitally controlled capacitor network 1102 and load 114, or as one of the phase-switched reactance circuits shown in FIGs. 10A-D, or other equivalent circuits.
• Digitally controlled capacitor network 1102 includes a plurality of capacitors and associated switches, shown as capacitors 1104, 1108, and 1112, and switches 1106, 1110, and 1114.
• each of capacitors 1104, 1108, and 1112 have a unique capacitance value, allowing the capacitance value of digitally controlled capacitor network 1102 to be varied across a large capacitance range. For example, as shown in FIG. 11 , capacitors 1104, 1108, and 1112 might increase from the phase-switched capacitor base value (e.g., Co) in increments of Co until reaching a maximum capacitance value (e.g.,( 2-2 /v -1 ) Co), where N is the number of capacitors in digitally controlled capacitor network
• Switches 1106, 1110, and 1114 are coupled in series with
• switches 1106, 1110, and 1114 are operable to adjust the capacitance of digitally controlled capacitor network 1102 by connecting (or disconnecting) the respective capacitors.
• Switches 1106, 1110, and 1114 might operate based upon one or more control signals from control circuit 106. As described, switches 1106, 1110, and 1114 generally operate at a frequency less than the RF frequency to adjust the capacitance value of digitally controlled capacitor network 1102.
• hybrid switched network 1200 includes a phase-switched reactance (e.g., inductor Lo 1216 and series switch 1218) and digitally controlled inductor network 1202.
• phase-switched reactance e.g., inductor Lo 1216 and series switch 1218
• digitally controlled inductor network 1202. Although shown as a phase-switched variable inductance (e.g., inductor Lo 1216 and series switch 1218) coupled in series with digitally controlled inductor network 1202 and in parallel with load 114, in other embodiments, the phase-switched reactance might be implemented as a phase-switched variable capacitance (e.g., such as shown in FIG. 2), or as one of the phase-switched reactance circuits shown in FIGs. 10A-D, or other equivalent circuits.
• Digitally controlled inductor network 1202 includes a plurality of inductors and associated switches, shown as inductors 1206, 1210, and 1214, and switches 1204, 1208, and 1212.
• each of inductors 1206, 1210, and 1214 have a unique inductance value, allowing the inductance value of digitally controlled inductor network 1202 to be varied across a large inductance range. For example, as shown in FIG. 12, inductors 1206, 1210, and 1214 and 1218 might increase from the phase-switched inductor base value (e.g., Lo) by increments of Lo until reaching a maximum inductance value.
• phase-switched inductor base value e.g., Lo
• Switches 1204, 1208, and 1212 are coupled in parallel with corresponding ones of inductors 1206, 1210, and 1214 and are operable to adjust the inductance of digitally controlled inductor network 1202 by connecting (or shorting, e.g., providing a low-impedance path to bypass the inductor) the respective inductors.
• Switches 1204, 1208, and 1212 might operate based upon one or more control signals from control circuit 106. As described, switches 1204, 1208, and 1212 generally operate at a frequency less than the RF frequency to adjust the capacitance value of digitally controlled inductor network 1202.
• Digitally controlled capacitor network 1102 and digitally controlled inductor network 1202 expand the range over which the reactance of the phase- switched reactance (e.g., capacitor Co 1116 and parallel switch 1118, or inductor Lo 1216 and series switch 1218) can be continuously varied without introducing excessive harmonic content to source 102 and/or load 114.
• the embodiments shown in FIGs. 11 and 12 employ digitally controlled capacitor network 1102 (or digitally controlled inductor network 1202) to control the base value Co (or Lo) of the switched networks 1100 (or 1200).
• the switch of the phase-switched reactance e.g., switch 1118 or switch 1218
• the effective capacitance CEFF at the switching frequency of hybrid switched capacitor network 1100 can be controlled between a lower capacitance value Co and an upper capacitance value by half-wave switching the RF switch with the switching angle, a, varying from 0 to
• the hybrid switched networks (e.g., 1100 and 1200) allow continuous control of the effective reactance at the switching frequency over a wide capacitive (or inductive) range with minimum harmonic distortion and without the need for adjustable bias voltages or currents.
• the RF switch of TMN 112 e.g., switch 206 or switch 406
• the RF switch of TMN 112 can be implemented as one of or a combination of various types of switching elements, for example based upon the RF frequency or other operating parameters of RF system 100. For example, lateral or vertical FETs, FIEMTs, thyristors, diodes, or other similar circuit elements might be employed.
• Phase-switched variable capacitance 200 and phase-switched variable inductance 400 can be employed as circuit elements within more complex phase-switched tunable matching networks (PS-TMNs), for example a Pi-network topology PS-TMN (Pi-TMN), although other network topologies are possible, such as L-networks, T-networks, or other similar networks.
• FIG. 13 shows a schematic of illustrative RF system 1300 including an RF source 1301 coupled to Pi-TMN 1302, which is coupled to an RF load 1303.
• Pi-TMN 1302 includes two variable shunt capacitive susceptances Bi 1310 and B2 1314.
• RF source 1301 is commonly a power amplifier or the output of another RF system. As shown in FIG. 13, RF source 1301 can be represented by its Norton equivalent circuit as including current source 1304 in parallel with source resistance Rs 1306 and source susceptance Bs 1308. Similarly, RF load 1303 can be represented as including load resistance RL 1318 in parallel with load susceptance BL 1316.
• the source and load impedances, Zs and ZL, respectively, can be expressed as:
• susceptances B1 and B2 required to match the load impedance ZL to the source impedance Zs are given by:
• Pi-TMN 1302 can be employed to match load impedance ZL to source impedance Zs by adjusting the values of variable shunt capacitive susceptances
• Pi-TMN 1302 include two variable shunt capacitive susceptances Bi 1310 and B2 1314, and a fixed inductive reactance X 1312, although numerous other implementations of a Pi- TMN are possible, such as employing variable shunt inductive susceptances and a fixed capacitive reactance, implementing all three reactive branches as variable components, etc. It should, of course, be appreciated that it is also possible to realize an L-section TMN having one variable shunt-path element and one variable series-path element. Other types of networks, might also be employed.
• ground-referenced variable capacitors are highly suitable for realization with phase-switched variable reactance networks at RF frequencies.
• an illustrative range of load impedances that can be matched by Pi-TMN 1302 is shown as shaded region 1402 in Smith chart plot 1400 (normalized to Rs).
• Pi-TMN 1302 is able to match the impedance of RF source 1301 to a load impedance that varies over approximately a 10:1 resistance range and a 5: 1 reactance range (both capacitively and inductively). To do so, Pi-TMN 1302 modulates B1 over a 1 :4 range and B2 over a 1 :2 range, which can be achieved employing a phase- switched variable reactance network such as shown in FIGs. 2 and 4.
• FIG. 15 shows an illustrative embodiment of phase-switched Pi-TMN circuit 1502 to achieve the matching range shown in FIG. 14 for a source impedance (e.g., Rs 1506) of 50W.
• the inductive reactance X is chosen to be equivalent in value to the Norton-equivalent source resistance Rs (e.g., 50W).
• the variable capacitive susceptances B1 and B2 are
• Variable capacitive susceptance B1 includes phase- switched capacitor CP2 1514 and FET switch 1512, which is controlled by switching control signal q2, which has a switching angle, 02.
• Variable capacitive susceptance B2 includes phase-switched capacitor CPI 1520 and FET switch
• switching control signal q1 which has a switching angle, CM .
• phase-switched Pi-TMN circuit 1502 operates at 27.12 MHz and is capable of matching a 50W source impedance to a load impedance that varies over approximately a 10:1 resistance range and a 5:1 reactance range (both capacitively and inductively), by properly adjusting the switching angles (CM and 02) of the switches and the phase shift between them (e.g., by adjusting switching control signals q1 and q2).
• variable capacitive susceptances B1 and B2 as half- wave FET-switched capacitor networks provides zero-voltage-switched (ZVS) operation of the switches, and allows each variable reactance to be implemented with a single, ground-referenced switch (e.g., FET 1512 for variable capacitive susceptance B1 and FET 1522 for variable capacitive susceptance B2).
• ZVS operation is desired in switched systems as it reduces switching power loss and improves the overall system efficiency.
• the output (drain-to-source) capacitance of FETs 1512 and 1522 are in parallel with phase-switched capacitors CPI and CP2 and, thus can be added to the shunt capacitances and utilized as part of the TMN.
• inductive reactance X 1312 shown in FIG. 13 is implemented as a series-resonant circuit including inductor I_s2 1516 and capacitor Cs2 1518 disposed in series between variable susceptances B1 and B2, which are disposed as shunt elements (e.g., coupled to ground).
• Inductor I_s2 1516 and capacitor Cs2 1518 are selected to have an inductive impedance approximately equal to the source impedance (e.g., 50W) at the desired
• capacitor Csi 1508 and inductor Lsi 1510 act as a series-resonant input filter between source 1504 and Pi-TMN circuit 1502.
• inductor I_s3 1524 and capacitor Cs3 1526 act as a series-resonant output filter between load 1528 and Pi-TMN circuit 1502.
• the quality factor, Q, of the series-resonant circuit of I_s2 1516 and Cs2 1518 controls the interaction between phase-switched capacitor CPI 1520 and phase-switched capacitor CP2 1514.
• increasing the quality factor Q e.g., by increasing the values of I_s2 1516 and Cs2 1518 reduces the interaction between phase-switched capacitor CPI 1520 and phase-switched capacitor CP2 1514, although increasing the quality factor Q also reduces the effective bandwidth of the network.
• phase-switched Pi-TMN circuit 1502 For phase-switched Pi-TMN circuit 1502 to achieve the matching range shown in FIG. 14 for a source impedance (e.g., Rs 1506) of 50W at an illustrative desired frequency in the range of about 27 MFIz, phase-switched capacitor CPI 1520 might have a physical value, Co, of 130pF, and phase- switched capacitor CP2 1514 might have a physical value, Co, of 100pF.
• capacitor Cs2 1518 might have a value of 0.01 pF
• inductor I_s2 1516 might have a value of 297nFI.
• capacitors Csi 1508 and Cs3 1526 might have a value of 23.4pF, and inductors Lsi 1510 and I_s3 1524 might have a value of 1.47mH.
• FETs 1512 and 1522 might have an on-state resistance of 10mQ, and the body diode of each FET might have a forward voltage of 0.4V and an on-state resistance of 10mQ.
• Switching of FETs 1512 and 1522 is synchronized to their drain current based upon the switching angle a, which is based upon the desired effective capacitance of capacitors CPI and CP2.
• a the switching angle
• FETs 1512 and 1522 are turned off after their drain current crosses from negative to positive, and then turned on again once their respective drain voltages ring down to zero.
• the appropriate value of a for each of FETs 1512 and 1522 can be calculated by determining the required Bi and B2 susceptances for a desired load impedance ZL as given by relationships (5) and (6).
• CEFF CEFF
• 1 a for a half-wave phase-switched capacitor
• 2a for a full-wave phase-switched capacitor
• some embodiments employ non-linear control techniques (e.g., by control circuit 106) to determine the appropriate values of a, such as fixed or adaptable look-up tables (e.g., LUT 108), feedback (e.g., by feedback circuit 110), feedforward compensation (e.g., by feedforward circuit 104), digital predistortion of the switching angles (e.g., by predistortion circuit 107), or other similar techniques.
• non-linear control techniques e.g., by control circuit 106
• control circuit 106 employ non-linear control techniques to determine the appropriate values of a, such as fixed or adaptable look-up tables (e.g., LUT 108), feedback (e.g., by feedback circuit 110), feedforward compensation (e.g., by feedforward circuit 104), digital predistortion of the switching angles (e.g., by predistortion circuit 107), or other similar techniques.
• LUT 108 might store predetermined switching angles (e.g., CM and 02) corresponding to various load impedances.
• table 2 shows an illustrative list of possible load impedances that Pi-TMN circuit 1502 can match to a 50W source and the corresponding values of switching angles CM and 02 for the switch control signals q1 and q2:
• Table 2 shows that it is possible for Pi-TMN circuit 1502 to match a 50W source impedance to a load impedance that varies resistively over at least a factor of 10:1.
• CM and 02 switching angles listed in Table 2
• the plot of effective reactance e.g., CEFF/CO or LEFF/LO
• a 2:1 modulation of the effective capacitances can achieve impedance matching for a load impedance varying resistively over a 10:1 range.
• phase-switched networks can also employ the phase-switched networks described herein.
• a wide range of systems can benefit from RF power amplifiers (PA) that deliver power at a particular frequency or over a particular band of frequencies.
• PAs might beneficially control output power over a wide range and maintain high efficiency across its operating range.
• Conventional linear amplifiers e.g., class A, B, AB, etc.
• switching PAs e.g., inverters such as class D, E, F, F, etc.
• One technique for output power control in a switching PA is through load modulation, where the load of the PA is modulated by an external network.
• the load of the PA is modulated by a phase-switched tunable matching network (TMN) (e.g., a network including one or more phase- switched variable capacitances 200 or phase-switched variable inductances 400, such as Pi-TMN circuit 1502).
• TNN phase-switched tunable matching network
• an impedance transformation of a phase-switched TMN might control the output power of a PA.
• PSIM phase-switched impedance modulation
• PSIM amplifier 1600 includes RF power amplifier (or inverter) 1602 that generates RF power at a particular frequency, or over a particular range of frequencies.
• RF PA 1602 is coupled to a power supply (e.g., voltage VDC and ground) and phase-switched TMN 1604.
• Phase-switched TMN 1604 is coupled to RF load 1606, which has a load impedance ZL.
• Phase-switched TMN 1604 is coupled to controller 1608, which controls operation of the TMN, for example by providing control signals to switches of the TMN based upon the switching angles (e.g., a) to achieve a desired impedance.
• controller 1608 is coupled to RF PA 1602 and also controls operation of the PA.
• Phase-switched TMN 1604 adaptively controls transforming the load impedance ZL to an impedance presented to PA 1602. For example, phase-switched TMN 1604 may control the output power of PA 1602 by modulating the load presented to PA 1602 (e.g., ZTMN) and/or to compensate for frequency and/or load
• PA 1602 is (1 ) a switching inverter, (2) an amplitude-modulated linear PA, or (3) a combination of these (e.g., depending on desired output).
• FIG. 17 shows a block diagram of illustrative PSIM amplifier, 1700, that includes switching PA 1702 (e.g., a class E, F or F PA, etc.) that includes a single switch (e.g., FET 1706).
• switching PA 1702 e.g., a class E, F or F PA, etc.
• FET 1706 single switch
• other types of PAs might be employed, such as linear PAs (e.g., class A, B, AB or C) or other switching PAs that use more than one switch to convert DC power to RF power (e.g., class D, inverse-D, etc.).
• modulating the effective loading impedance ZTMN seen by the PA looking into the phase-switched TMN controls the output power over the operating power range of the PSIM amplifier (e.g., amplifiers 1602 and 1702). Additionally, the operating power range of the PSIM amplifier can be further extended by also employing amplitude modulation of the PA drive signal for large output power back off.
• Some embodiments might also employ other power modulation techniques such as discrete or continuous drain modulation of the power amplifier. Drain modulation of the PA modulates (e.g., switches) a bias voltage applied to a bias terminal of the PA. For example, one drain modulation technique might switch the bias voltage among multiple discrete voltage levels or continuously adjusting the bias voltage across a voltage range.
• a phase-switched TMN (e.g., TMN 1604 or 1710) can also compensate for variation in the load impedance ZL.
• the phase- switched TMN can be continuously tuned to match a variable load impedance to a desired RF inverter loading impedance, ZTMN, for a given output power level, by employing the phase-switched TMN to compensate for variations in the amplifier's loading network impedance as the operating frequency changes and, thus, maintain ZVS operation.
• a PSIM amplifier e.g., PSIM amplifiers 1600 and 1700
• a PSIM amplifier e.g., PSIM amplifiers 1600 and 1700
• a PSIM amplifier allows (1 ) efficient dynamic control of output power over a wide power range; (2) the ability to impedance match and deliver power into a wide-ranging load, and (3) fully zero-voltage-switching (ZVS) operation across a frequency range for frequency-agile operation.
• ZVS zero-voltage-switching
• PSIM amplifiers 1600 and 1700 shown in FIGs. 16 and 17 show PSIM amplifiers as a cascade combination of an RF PA (e.g., RF PAs 1602 and 1702) with a phase-switched TMN (e.g., phase- switched TMNs 1604 and 1710), other embodiments integrate the PS-TMN into the design of the RF PA.
• RF PA e.g., RF PAs 1602 and 1702
• phase-switched TMN e.g., phase- switched TMNs 1604 and 1710
• such integrated PSIM amplifiers can be viewed as an RF amplifier including two or more switches, where a first switch (or group of switches) is principally responsible for generating RF power from DC input power, and a second switch (or group of switches) is principally responsible for modulating the effective impedance presented by a load network to the RF amplifier.
• the second switch (or group of switches) will not convert DC power to RF power (e.g., the second switch provides zero power conversion from DC to RF), although in some embodiments, the second switch may convert some power from DC to RF or RF to DC.
• a PSIM amplifier can be a zero-voltage switching (ZVS) amplifier with the switching transistors operating substantially in switched-mode and turning on and off under zero-voltage switching, enabling high efficiency to be achieved.
• ZVS zero-voltage switching
• a PSIM amplifier might provide switched-mode operation (e.g., saturated operation) over some of its operating range (e.g., while delivering high output power) and utilize linear-mode operation over other portions of its range.
• FIG. 18A shows a schematic of an illustrative topology for PSIM amplifier 1800A.
• PSIM amplifier 1800A is coupled to DC source 1802 coupled in series with inductor LF, which is in turn coupled to the parallel combination of transistor 1804 and capacitor CF.
• Inductor LF, capacitor CF, and FET 1804 generally operate to generate RF output power to the rest of the network from the DC source.
• Branch reactance Xi is coupled between capacitor CF and node N2, which is coupled to a Pi-TMN including reactance X2 coupled between a first phase-switched reactance (e.g., FET 1806, branch reactance Xs2, and phase-switched variable reactance XP2) and a second phase- switched reactance (e.g., FET 1808, branch reactance Xs3, and phase-switched variable reactance XP3).
• Branch reactance X1 is coupled between the Pi-TMN at node Ni and the load impedance ZL.
• the branch reactances X1, X2, X3, Xs2, Xs3, and the phase-switched variable reactances XP2 and XP3 can be implemented as various different reactive networks depending on the required functionality of the design.
• FIG. 18B shows an illustrative design 1800B of the PSIM amplifier topology shown in FIG. 18A.
• the phase-switched variable reactances comprising FET switches 1806 and 1808 and phase-switched capacitors CP2 and CP3 are implemented with half-wave phase-switched capacitor network such as described in regard to FIGs. 2 and 3.
• the three switches 1814, 1816 and 1818 are mutually isolated at DC (e.g., by capacitors Cs-i, Cs2 and Cs3, respectively.
• FET switch 1814 is responsible for generating all the RF power, while FET switches 1816 and 1818 are responsible for transforming and modulating the impedance presented by load ZL to the DC- to-RF portion of the circuit (e.g., at the output port of switch 1814 at node N2).
• FIG. 18C shows an illustrative design 1800C of the PSIM amplifier topology shown in FIG. 18A.
• Network 1800C is similar to network 1800B,
• phase-switched capacitor networks e.g., FET 1826 and capacitor CP2 and FET 1828 and capacitor CP3 are connected in series with capacitors CP4 and CPS, respectively. This decreases the sensitivity of the PSIM amplifier to variations in the effective reactance of the switched capacitor networks.
• FIG. 18D shows an illustrative design 1800D of the PSIM amplifier topology shown in FIG. 18A where FET switches 1834 and 1836 are DC coupled (e.g., via inductor Lsi), and thus, potentially, one or both of FET switches 1834 and 1836 can be used to convert DC power into RF power or vice-versa.
• FET switch 1838 is DC-isolated (e.g., by capacitors Cs2 and Cs3) and, thus, is used only for impedance matching to the load impedance ZL.
• FIG. 18E shows an illustrative design 1800E of the PSIM amplifier topology shown in FIG. 18A where all three FET switches 1844, 1846 and 1848 are DC coupled (e.g., via inductor I_s2), while only the load is DC-isolated (e.g., by capacitor Cs3).
• all three FET switches 1844, 1846 and 1848 can potentially be used to convert between DC power and RF power and/or be responsible for impedance matching of the network to the load, though it is not necessary that all three provide each function.
• the switched capacitor network of capacitor CF and FET switch 1844 is in parallel with the phase-switched network of capacitor CP2, inductor l_2 and FET switch 1846.
• some embodiments could combine these two networks into a single switched reactive network having an input current that matches the sum of the input currents of the two switched reactive networks associated with FETs 1844 and 1846.
• the three-switch PSIM shown in FIG. 18E can be implemented as a two-switch PSIM, such as shown in FIGs. 19 and 20.
• Two-switch PSIM 1900 is coupled to RF source 1902 coupled in series with inductor LF, which is in turn coupled to the parallel combination of FET 1904 and capacitor CF.
• Branch reactance Xi is coupled between capacitor CF and a phase-switched reactance network including reactance Xs2 coupled in series with the parallel combination of phase-switched reactance XP2 and FET 1906.
• Branch reactance X2 is coupled between the phase-switched reactance network and the load impedance ZL.
• the branch reactances X1 , X2 and Xs2, and the phase-switched variable reactance XP2 can be implemented as various different reactive networks depending on the required functionality of the design. Either one of switch FETs 1904 and 1906, or both of switches 1904 and 1906, can be used to convert between DC power and RF power.
• FIG. 20 an illustrative implementation of two-switch PSIM 2000 is shown having branch reactance X1 implemented as inductor Lsi and capacitor Csi .
• Capacitor CS1 provides DC isolation between FET switches 2004 and 2006.
• FET switch 2004 generates RF power
• FET switch 2006 modulates the impedance presented to the source.
• FIG. 21 shows an illustrative implementation of a three-switch PSIM amplifier 2100.
• PSIM amplifier 2100 operates over a 20.86MFIz to 27.12MFIz frequency range (a factor of 1.3 in frequency). Further, PSIM amplifier 2100 provides the ability for 10: 1 dynamic control of the output power delivered to the load having an impedance, ZL, of 50W with a ⁇ 10% impedance variation (resistive and reactive).
• PSIM amplifier 2100 includes RF PA (inverter) 2102, Pi-TMN 2104, branch filter 2106, and load impedance ZL.
• RF PA 2102 includes FET switch 2108, inductor LF and an output network formed by capacitors CF and Csi and inductor Lsi.
• RF PA 2102 is a modified class E inverter with FET switch 2108 converting between DC power and RF power.
• Pi-TMN 2104 includes a first phase-switched capacitor (e.g., CP2 and FET 2110) and a second phase-switched capacitor (e.g., CPI and FET 2112).
• Branch filter 2106 includes inductor I_s3 and capacitor Cs3 coupled between Pi-TMN 2104 and load ZL.
• RF PA 2102 maintains zero-voltage-switching (ZVS) and high efficiency at different output power levels when Pi-TMN 2104 maintains the inverter load impedance ZTMN as an approximately resistive load at the frequency of operation of RF PA 2102.
• RF PA 2102 generates peak RF power when ZTMN is 50W (e.g., matches load impedance ZL). Dynamic control of power back off of RF PA 2102 can be achieved by Pi-TMN 2104 modulating ZTMN.
• the illustrative embodiment of PSIM amplifier 2100 shown in FIG. 21 employs inductor LF having a value of 113nH, capacitor CF having a value of 180pF, capacitor Csi having a value of 15.2pF, inductor Lsi having a value of 3.81 pH, phase-switched capacitor CP2 having a physical value, Co, of 152pF, inductor Ls2 having a value of 381 nH, capacitor Cs2 having a value of 0.01 pF, phase-switched capacitor CPI having a physical value, Co, of 152pF, inductor Ls3 having a value of 3.81 pH, and capacitor Cs3 having a value of 15.2pF.
• Pi-TMN 2104 employs half-wave switched capacitor networks (e.g., capacitor CP2 and FET 2110 and capacitor CPI and FET 2112).
• the series reactive network branch formed by capacitor Cs2 and inductor Ls2 has a 50W inductive impedance at a frequency of 20.86MHz and also DC isolates the two switched networks (e.g., capacitor CP2 and FET 2110 and capacitor CPI and FET 2112).
• the impedance of capacitor Cs2 and inductor Ls2 sets the resistive range over which ZTMN of Pi-TMN 2104 can be modulated.
• the series resonant network formed by capacitor Cs3 and inductor I_s3 provides additional filtering of the load current II and prevents DC currents and high- frequency harmonic content being coupled to the load ZL.
• Pi-TMN 2104 can modulate the impedance, ZTMN, presented to RF PA 2102 by appropriately driving FET switches 2110 and 2112, for example by adjusting the conduction angles of the FETs. By modulating the impedance ZTMN presented to RF PA 2102, Pi-TMN 2104 can control the output power that is delivered from RF PA 2102 to load ZL.
• FIG. 22 shows an illustrative impedance range (e.g., shaded region 2202) over which ZTMN of Pi-TMN 2104 can be adjusted at 20.86MFIz.
• FIG. 23 shows an illustrative impedance range (e.g., shaded region 2302) over which ZTMN of Pi-TMN 2104 can be adjusted at 27.12MFIz. Smith charts 2200 and 2300 are normalized to 50W.
• Pi-TMN 2104 can match load impedance ZL over a 10:1 range by varying phase-switched capacitor CPI over a 1 :6 impedance range (e.g., varying the switching angle, CM , of FET 2112 over approximately 0 degrees to 125 degrees) and varying phase- switched capacitor CPI over a 1 :10 impedance range (e.g., varying the switching angle, 02, of FET 2110 over approximately 0 degrees to 135 degrees).
• ZTMN can be modulated to account for a ⁇ 10% variation in the load impedance ZL (both resistive and reactive) at the frequency of operation of RF PA 2102
• LUT 108 might store predetermined switching angles (e.g., cu and 02)
• table 3 shows an illustrative list of possible impedances ZTMN that can be matched to a 50W load impedance ZL and the corresponding switching angles (e.g., cu and 02).
• the values of table 3 might be determined based upon simulation of PSIM amplifier 2100, where FETs 2110 and 2112 are modeled having an on-state resistance of 10GPW and a body diode having a 0.4V forward voltage drop.
• the output power listed in table 3 includes power delivered at the fundamental and higher frequencies when the PSIM amplifier is supplied with a 48 VDC power supply.
• FET switches 2110 and 2112 are off during the entire cycle and the drain voltage waveforms of FET switches 2110 and 2112 would be sinusoidal.
• TMN 2102 is required to provide an impedance ZTMN of approximately 50W (as shown in Table 3). Under this operating condition, the required effective shunt capacitance at nodes N1 and N2 is higher than the CPI and CP2
• PSIM amplifier 2100 is capable of providing dynamic output power control while matching into a variable load across a range of switching frequencies.
• a pulse width modulation (PWM) generator 2500 includes a phase shifting circuit 2504 which includes one or more phase-shifting elements 2504a-2504N with each phase shifting element having inputs and outputs.
• PWM shifting circuit 2504 receives one or more reference signals from reference signal source 2502 and provides one or more phase shifted signals 2510 at outputs thereof.
• PWM generator further includes a PWM waveform combiner 2506 configured to receive signals provided thereto from phase-shifting circuit 2504, combine such signals and provide a PWM signal at an output thereof.
• PWM generator 2500 receives one or more reference signals 2508 and generates one or more PWM signals 2508 with the ability to dynamically control pulse width and phase with respect to reference signal 2502.
• PWM generator 2500 is configured to generate one or more PWM signals 2508 having predetermined pulse widths and phase shifts relative to reference signals 2502.
• Reference signal source 2502 and PWM signal 2508 are here shown in phantom since they are not properly a part of PWM generator 2500.
• Reference signals provided by 2502 may be provided as any arbitrary, periodic waveform including, but not limited to, periodic voltage and current waveforms having a variety of waveform shapes including but not limited to, sinusoidal waveforms (e.g. sine waves, cosine waves, or portions there of etc.), rectangular waveform, square waveforms, triangular waveforms, or any combination thereof.
• sinusoidal waveforms e.g. sine waves, cosine waves, or portions there of etc.
• rectangular waveform e.g. sine waves, cosine waves, or portions there of etc.
• square waveforms e.g. sine waves, cosine waves, or portions there of etc.
• triangular waveforms e.g., triangular waveforms, or any combination thereof.
• an input of at least one phase-shifting element in phase shifting circuit 2504 is configured to receive at least one reference signal 2502.
• inputs of two or more phase shifting elements 2504 may be configured to receive at least one reference signal 2502. Examples of different phase-shifting circuit architectures will be discussed below with reference to FIGs. 26 and 27.
• each phase-shifting element of phase-shifting circuit 2504 is configured to generate a phase-shifted signal 2510 relative to received reference signals 2502 at its respective output based upon a respective phase-shift parameter.
• Phase shift parameters are provided from a controller 2509 which is here shown in phantom since it is not properly a part of PWM generator 2500.
• Each phase-shifting element can include analog and/or digital circuitry configured to apply a phase shift to a signal received at its input to generate the phase-shifted signal at its output phase-shifting elements may comprise, for example, any of ln-phase/ln- quadrature (“IQ”) circuits, phase-locked loop (“PLL”) circuits, or any combination thereof.
• IQ ln-phase/ln- quadrature
• PLL phase-locked loop
• a phase-shift parameter can include a
• each phase-shifting element 2504 is configured to receive a respective predetermined phase-shift parameter from controller 2509.
• Controller 2509 may be provided, for example, as any type of processing circuitry including, but not limited to, a digital signal processor (“DSP”), a computer, a microprocessor, a microcontroller, or any combination thereof.
• DSP digital signal processor
• a first phase-shifting element 2504a can be configured to receive at least one reference signal 2502 at its input while a second phase- shifting element 2504b can be configured to receive at its input a generated phase-shifted signal (e.g. one of signals 2510) from another (i.e. a different) phase-shifting element (e.g. the first phase-shifting element 2504a).
• each phase-shifting element 2504a-2504N is configured to shift the phase of signals received at its input based upon a respective phase-shift parameter in order to generate a corresponding one of phase-shifted signals 2510a-2510N generally denoted 2510.
• phase-shifting elements may be configured to shift the phase of a received reference 2502 in order to generate a phase-shifted signal 2510 while others may be configured to shift the phase of generated phase-shift signals 2510 received from another phase-shifting element 2504.
• a phase-shifting element 2504 can receive a phase-shift parameter comprising a phase shift f. This phase- shifting element 2504 may then generate a phase-shifted signal 2510 at its output by shifting the phase of a signal received at its input (e.g. a reference signal 2502 or generated phase-shifted signal) according to the phase shift f.
• Waveform combiner 2506 is configured to receive the one or more generated phase-shifted signals 2510A-2510N generated by phase-shifting elements 2504A-2504N. Waveform combiner 2506 is configured to combine the phase-shifted signals provided (e.g. phase-shifted signals 2510) thereto and generate PWM signals 2508. Waveform combiner 2506 can include analog/digital circuitry configured to generate, compare, summate, combine, detect, or amplify PWM signals 2508. Such circuitry may include, but is not limited to, edge detectors, analog or digital logic gates, operational amplifier, comparators, or any combination thereof.
• waveform combiner 2506 is configured to generate one or more PWM signals 2508 according to received phase-shifted signals 2510, while in other embodiments waveform combiner 2506 can be configured to generate two or more PWM signals 2508 according to received phase-shifted signals 2510.
• phase-shift parameters are determined and stored in a memory or other storage device (e.g. a memory which may be part of or separate form controller 2509, for example). It should be appreciated that in some embodiments the phase shift parameters are determined based on the PWM signal duty-cycle and phase shift that is required by a particular application of the PWM generator. These parameters may be pre-stored in the controller 2509 or in a separate external controller / memory. Typically, the phase shift parameters need to be dynamically adjusted depending upon the specific application, and so, an external system controller could be tasked with estimating / calculating these parameters based on various inputs from the system and passing them to PWM controller 2509.
• phase-shifts and pulse widths of the generated PWM signals 2508 relative to reference signals 2502 can be achieved through selecting the phase-shift parameters necessary to achieve the desired phase-shifts and pulse widths.
• controller 2509 can be configured to determine phase-shift parameters for respective phase-shifting elements 2504 based upon desired phase-shift and pulse widths for generated PWM signals 2508. For example, controller 2509 can be configured to determine a desired phase shift and pulse width for a generated PWM signal 2508 relative to a reference signal 2502. Based on the desired phase shift and pulse width, controller 2509 can determine phase-shift parameters using empirical or analytical techniques In more detail, the phase shift parameters may be determined based upon feedback or feedforward techniques or a combination of both for one or more phase-shifting elements 2504 so that the phase-shifting elements generate phase-shifted signals 2510 that can, in turn, be used to generate a PWM signal 2508 having the desired phase shift and pulse width relative to a reference signal 2502.
• PWM generator 100 is suitable for generating accurate and dynamically adjustable PWM waveforms for high-frequency and very-high-frequency applications. PWM generator 100 has particular value in applications in which reference signal 2508 is derived from some radio frequency (“RF”) input source with respect to which precise timing of the PWM signal must be maintained, including PSIM-based tunable matching networks and PSIM amplifiers.
• RF radio frequency
• a portion of an illustrative PWM signal Q(0) 2508 generated by PWM generator (e.g. such as PWM generator 2500 described in conjunction with Fig. 25A), has a pair of pulses 2508a, 2508b.
• PWM generator e.g. such as PWM generator 2500 described in conjunction with Fig. 25A
• Each of the pulses 2508a, 2508b has a pulse width w 2512 and is locked in phase and frequency to a reference signal VREF(0) 2502.
• PWM signal Q(0) 2508 can be generated as discussed above in conjunction with FIG. 25A.
• phase shift f 2514 is defined between the rising edge of PWM signal Q(0) 2508 and the negative-to-positive transition of reference signal VREF(0) It should be noted that this definition of PWM phase shift is used throughout this disclosure.
• the phase shift 2514 illustrated in Fig. 25B is considered a positive phase shift. It should also be noted that the definition of phase shift is only truly unique between two sinusoidal signals at the same frequency. When describing the relationship between a PWM and sinusoidal signal such as in Fig. 25B, the definition of phase shift is arbitrary.
• phase shift definition used herein is only chosen for the sake of convenience. Flowever, if one desires, one can define phase shift any other way, as long as the definition uniquely describes the relationship between the two signals in Fig. 25B. If that is the case, phase shift based on one definition can always be converted to phase shift based on another definition without loss of generality.
• the phase shift definition has no effect on the circuit implementation.
• desired pulse widths w 2512 and phase shifts f 2514 relative to a reference signal 2502 can be achieved via selected values of phase-shift parameters provided to PWM generator 2504 necessary for phase-shifting elements 2504 to achieve the desired phase shift.
• a PWM generator circuit 2600 includes a pair of phase-shifting elements 2016, 2018 coupled such that processing of a reference signal 2602 occurs in parallel.
• Such an architecture is referred to herein as a“parallel architecture.”
• Phase shifting elements 2620, 2622 may be the same as or similar to phase shifting elements 2504a-2504N described above in conjunction with Fig. 25.
• inputs of at least two phase-shifting elements are configured to receive a common reference signal (here reference signal 2602), which may be the same as or similar to reference signals 2502.
• Each phase- shifting element 2616, 2618 is configured to generate a respective phase-shifted signal at its output based upon the received reference signal 2602 and a received predetermined phase-shift parameter provided from control signals 2620, 2632 which may be provided from one or more controllers (such as controller 2509 described above in conjunction with Fig. 25).
• Phase-shifting elements 2616, 2618 are each configured to generate a phase-shifted signal by applying a phase-shift to a received reference signal 2602 according to a respective phase-shift parameter included in respective ones of controller signals 2620, 2622.
• each phase-shifting element 2616, 2618 can be configured to receive a respective one of control signals 2620, 2622.
• Control signals 2620, 2622 can include one or more predetermined phase-shift parameter for each of the respective phase-shifting element 2616, 2618.
• control signals 2620, 2622 can be generated by a processing circuitry such as, but not limited to, a DSP, a computer, a microprocessor, a microcontroller, or any combination thereof.
• phase-shifting element 2616 is configured to receive control signal 2620 which includes a phase-shift parameter including a phase-shift of f.
• phase-shifting element 2618 can be configured to receive control signal 2622 which includes a phase-shift parameter including a phase-shift of f and a pulse width of w. Phase-shifting elements produce phase-shifted signals A, B at respective outputs thereof.
• Waveform combiner 2606 is configured to receive the phase-shifted signals A, B generated at the outputs of phase-shifting elements 2616, 2618. Waveform combiner 2606 can be the same as or similar to waveform combiner 2506 (FIG. 25A). In response to phase-shifted signals A, B provided thereto, waveform combiner 2606 generates a PWM signal 2608. PWM signal 2608 has phase-shift and pulse width characteristics according to the received phase- shifted signal. A generated by phase-shifting element 2616 and phase-shifted signal B generated by phase-shifting element 2618.
• phase-shifted signals A and B are phase-locked to the reference signal 2602 and phase-shifted according to the respective phase shift valves (f and w+f) of the phase-shifting element from which they were generated.
• phase-shifted signals A and B can then be appropriately combined e.g. via waveform combiner 2606 to synthesize PWM signal 2608 with pulse width w and phase f that is phase-locked to reference signal 2602.
• waveform combiner 2606 can be appropriately combined e.g. via waveform combiner 2606 to synthesize PWM signal 2608 with pulse width w and phase f that is phase-locked to reference signal 2602.
• FIG. 26 shows a parallel architecture with only two phase-shifting elements
• the parallel architecture can implemented using three or more phase-shifting elements.
• the number of phase shifting elements to include in a phase-shifter circuit is selected in accordance with the needs of a particular application. Factors to consider in selecting the number of phase shifting elements to include in a PWM generator include but is not limited to the number of rising/falling edges that the PWM waveform must have during a single period. In the simplest terms, each phase-shifting element controls the position of one rising or falling edge of the of the PWM waveform in relation to the start of its period. For example, in Fig.
• the PWM waveform has a single pulse every period and hence, it has only one rising and one falling edge; phase shifting element 2616 sets the position of the rising edge, and phase shifting element 2618 sets the position of the falling edge.
• phase shifting element 2616 sets the position of the rising edge
• phase shifting element 2618 sets the position of the falling edge.
• Q has two pulses repeating every single period and a total of four edges in a period. Flence, to control the relative position of each of these edges, four phase-shifting elements are required.
• the waveform combiner can automatically select the other copy of signal A.
• PWM generator circuit 2700 includes a pair of phase shifting elements 2716, 2718 with a first one of the phase shifting elements (here phase shifting elements 2716) having an input configured to receive a reference signal 2702 and having an output coupled to both an input of a waveform combiner 2706 and an input of a second phase-shifting element (here phase-shifting element 2718).
• An output of the second phase shifting element is coupled to a second input of waveform combiner 2706.
• Such an architecture is referred to herein as a“cascade architecture.”
• a first phase-shifting element 2716 which may be the same as or similar to phase-shifting elements 2504 (FIG. 1 ) is configured to receive reference signal 2702 at its input.
• the first phase-shifting element 2716 is configured to generate phase-shifted signal A at its output based upon reference signal 2702 and a respective predetermined phase shift parameter (provided, for example, by a controller such as controller 2509 described above in conjunction with Fig. 25A).
• phase-shifting element 2716 can be configured to generate phase-shifted signal A by shifting the phase of reference signal 2702 according to a predetermined phase-shift parameter.
• a phase-shift element may be configured to receive a control signal that includes a
• phase-shifting element 2716 is configured to receive control signal 2720 that includes a phase-shift parameter f.
• the cascaded architecture further includes a second phase-shifting element 2718 configured to receive, at its input, phase-shifted signal A generated by phase-shifting element 2716.
• the second phase-shifting element 2718 is configured to generate phase-shifted signal B at its output based upon phase- shifted signal A and a respective phase-shift parameter.
• phase-shifting element 2718 is configured to generate phase-shifted signal B by shifting the phase of phase-shifted signal B according to a predetermined phase-shift parameter here shown as (f + w).
• Waveform combiner 2706 which may be the same as or similar to waveform combiner 2506 (FIG. 25A), is configured to receive the phase-shifted signals generated at the outputs of phase-shifting elements 2716, 2718 and to generate PWM signal 2708 having a desired pulse width and a phase-shift relative to reference signal 2702.
• phase-shifting elements 2716, 2718 are configured to generate phase-shifted signals A and B phase- locked to the reference signal 2702 and phase-shifted with respect to reference signal 2702 by phase-shifts f and f + w respectively.
• the phase-shifting elements 2716, 2718 in the cascade architecture introduce a phase shift of only f and w (i.e. phase shifting element 2716 introduces phase shift f and phase shifting element 2718 introduces phase shift w).
• phase-shifting elements phase shift the reference signal by f and f+ w (e.g. in Fig. 26, phase shifting element 2616 introduces phase shift f and phase shifting element 2618 introduces phase shift f + w).
• phase- shifting elements in a parallel architecture need to be able to introduce larger phase shifts and operate over a wider phase-shifting range compared to those in a cascaded architecture.
• a cascade architecture on the other hand, a generated-PWM waveform may suffer from more jitter compared to the PWM waveform generated with a parallel architecture.
• the choice of one system architecture over the other is dependent upon a variety of factors including but not limited to the specific application and the requirements for the generated PWM waveform, and on the characteristics of the circuits available to implement them.
• the range of phase shift that each phase-shifting element can produce is an important deciding factor in the choice of cascaded versus paralleled architecture, dynamic behavior and transient response of the PWM generator is also highly dependent on the generator architecture.
• Paralleled architectures allow one to independently control the dynamics with which the rising and falling edges of the PWM waveform can be adjusted.
• the dynamics with which one can control the pulse of the PWM waveform is a combination of the dynamic responses of all the phase shifting elements.
• a PWM generator 2800 is configured to generate a dual-pulse PWM waveform 2808 and includes at least four phase- shifting elements 2824-2830 each having outputs coupled to inputs of a waveform combiner 2806.
• a first set of phase-shifting elements 2824, 2826 are each configured to received reference signal 2802 at their respective inputs.
• Phase- shifting elements 2824, 2826 are each configured to generate a phase-shifted signal at their respective outputs according to reference signal 2802 and a respective phase-shift parameter.
• FIG. 1 in the illustrative embodiment of FIG.
• phase-shifting element 2824 is configured to generate a phase-shifted signal at its output by shifting the phase of reference signal 2802 according to phase-shifting element’s 2824 respective phase-shift parameter (f).
• phase-shifting element 2826 is configured to generate a phase-shifted signal at its output by shifting the phase of reference signal 2802 according to phase-shifting element’s 2826 respective phase-shift parameter (f+a+g).
• a second set of phase-shifting elements 2828, 2830 are each configured to receive, at their inputs, a phase-shifted signal generated by respective ones of the first set of phase-shifting element 2824, 2826.
• phase-shifting element 2828 is
• phase-shifting element 2830 is configured to receive, at its input, the phase-shifted signal generated by phase-shifting element 2826.
• phase-shifting elements 2828, 2830 of the second set are each configured to generate a phase-shifted signal at their respective outputs based upon a phase-shifted signal generated by a phase-shifting element of the first set and a respective phase-shift parameter.
• phase-shifting element of the first set and a respective phase-shift parameter.
• phase-shifting element 2828 is configured to generate a phase-shifted signal by further shifting the phase of the phase-shifted signal generated by phase-shifting element 2824 provided to the input of phase-shifting element 2828.
• Phase-shifting element 2828 shifts the phase of the signal provided thereto by a phase of (oc).
• phase-shifting element 2830 is configured to generate a phase-shifted signal by shifting the phase of the phase-shifted signal generated by phase-shifting element 2826 according to phase-shifting element’s 2830 respective phase-shift parameter (b).
• Waveform combiner 2806 receives the phase-shifted signals generated at the output of phase-shifting elements 2824-2830 at inputs thereof, combines the signals provided thereto and generates PWM signal 2808 according to the received phase-shifted signal.
• PWM signal 2808 is a dual- pulse PWM waveform (i.e. a pair of pulses which occur within a single cycle of a reference signal waveform) having a first pulse width and phase-shift relative to reference signal 2802 and a second pulse width and phase-shift relative to reference signal 2802.
• PWM waveform 2808 includes a dynamically and independently controlled phase f with pulse widths a and b, and spacing between the pulses g while maintaining phase and frequency lock to the reference signal 2802.
• phase-shifting elements 2826 and 2830 cause another pulse of width b to follow the first one with a pulse spacing of g.
• very complex multi- pulse PWM waveforms can be generated that remain phase- and frequency- locked to a reference signal input. Note that in the example of Fig. 28, both paralleling and cascading of phase-shifting elements is employed - i.e. it is a hybrid architecture.
• a PWM generator 2900 includes a pair of phase-shifting elements 2916, 2918 coupled in a parallel architecture. Phase shifting elements 2916, 2918 may be the same as or similar to the phase shifting elements described above in conjunction with FIGs. 25Am 26. PWM generator 2900 also includes a phase detector 2932 which receives a portion of the reference signal at an input thereof. Phase detector 2932 also receives at an input thereof, a feedback signal from an output of a waveform combiner 2906. Outputs of phase detector 2932 are coupled to phase shifting elements 2916, 2918.
• phase detector 2932 is configured to receive a portion of reference signal 2902 and a portion of PWM output signal 2908 and is configured to monitor (i.e. measure, detect, compute or otherwise determine) the phase between PWM signal 2908 and reference signal 2902.
• Phase detector 2932 can include analog and/or digital circuitry configured to detect and compare the phases of two or more signals and can include a DSP, microprocessor, computer, microcontroller.
• Waveform combiner 2908 may be the same as or similar to waveform combiner 2508 (Fig. 25). In embodiments, there may be significant propagation delays associated with the circuitry of waveform combiner 2908.
• phase detector 2932 can be configured to compare the phase between PWM signal 2908 and reference signal 2902 to a phase threshold.
• a phase threshold corresponds to a value for a phase indicating that the phase between PWM signal 2908 and reference signal 2902 has become too great.
• a phase threshold can include a value that indicates that PWM signal 2908 and reference signal 2902 are no longer in phase lock.
• phase detector 2932 can be configured to generate one or more phase correction signals when PWM signal 2908 and reference 2902 are determined to be no longer in phase lock.
• Phase correction signals can include data indicating an adjustment to one or more phase-shift parameters of respective phase-shifting elements in order to place PWM signal 2908 and reference signal 2902 in phase lock.
• phase correction signals include data to correct for the propagation delays causing PWM signal 2908 and reference signal 2902 to no longer be in phase lock.
• each phase-shifting element 2916, 2918 is configured to receive a phase correction signal and, in response to the phase correction signal, adjust its phase-shift parameter.
• the phase-shift parameter of a phase-shifting element 2916, 2918 By adjusting the phase-shift parameter of a phase-shifting element 2916, 2918, the phase-shifted signal generated by the phase-shifting element 2916, 2918 is also adjusted. Because PWM signal 2902 is generated by waveform combiner 2908 according to received phase-shifted signals, adjusting the phase-shift parameters allows for a correction in the PWM signal 2902 generated by waveform combiner 2906.
• PWM generation system 3000 includes a plurality of PWM generators 3036a-3036N each of which may be the same as or similar to any of PWM generators 2500, 2600, 2700, 2800, 2900 described above in conjunction with Figs. 25A, 26, 27, 28 and 29, respectively.
• Each PWM generators 3036a-N is configured to receive reference signal 3002.
• each PWM generator 3036a-N includes at least two phase-shifting elements 3016a-N, 3018a-N configured to generate one or more phase shifted signals based upon reference signal 3002 and phase-shift parameters associated with each phase-shifting element 3016a-N, 3018a-N.
• PWM generator 3036a includes phase-shifting elements 3016a, 3018a which are configured to generate two or more phase- shifted signals based upon reference signal 3002 and phase-shift parameters associated with phase-shifting elements 3016a, 3018a.
• Each phase-shifted signal generated by a phase-shifting element A-N 3016a-N, 3018a-N, is provided to a respective waveform combiner 3006a-N in order to generate a respective PWM signal 3008a-N.
• each phase-shifting element 3016a-N, 3018a-N is configured to receive a phase-shift parameter from a controller 3034.
• Controller 3034 can include a processing circuitry such as, but not limited to, a DSP, a computer, a microprocessor, a microcontroller, or any combination thereof.
• controller 3034 is configured to receive an input comprising desired pulse widths and phase shifts relative to a reference signal 3002 for one or more desire PWM signals 3008 It should be appreciated that desired PWM pulse widths / phases can also be an input supplied by a user, or be pre-determ ined and stored in some look-up table in memory.
• controller 3034 can receive an input comprising desired pulse widths and phase shifts relative to a reference signal 3002 from a computer, a microcontroller, a processor, a graphic user interface, an interaction device (i.e. a keyboard, a mouse, a touchscreen, etc.), or any combination thereof— to name a few. Based upon these desired pulse widths and phase shifts relative to a reference signal 3002, controller 3034 is configured to determine the phase-shift parameters for each phase-shifting element necessary to achieve the desired pulse widths and phase shifts and provide them to the respective phase- shift elements.
• each PWM waveform 3008A-N generated by PWM generation system 300 can be dynamically and independently adjusted by controller 3034.
• controller 3034 determines and provide the phase-shift parameters to the phase-shifting elements necessary to achieve the desired pulse widths and phase shifts.
• Both the phase f and pulse width w of each PWM waveform can be dynamically and
• FIG. 30 shows all N of PWM generators 3036a-N being based on the paralleled architecture (FIG. 26), other architectures may be used, such as a cascading architecture, or any combination of the two. Depending on the specific requirements of an application, PWM generators with different architectures and/or implementations can be connected together and fed with a common reference signal.
• phase-shifting element implementations based on both IQ modulators and phase-locked loops, as discussed below.
• Designs based on IQ modulators and phase-locked loops often allow one to control phase shift over a wide operating frequency range while preventing phase shift modulation with frequency variation.
• phase-shifting elements such as programmable / voltage-controlled delay lines and delay-locked loops.
• embodiments of PWM generators are provided based on phase-shifting elements implemented with IQ modulators.
• IQ modulators allow for an RF carrier signal to be modulated according to a diverse range of amplitude, frequency and phase modulation operations.
• PWM generation circuit 3100 implemented as an IQ modulator that includes an amplitude and phase shifting circuit 3152 having a first input configured to receive a local oscillator (LO) signal 3140.
• PWM generation circuit further comprises a pair of optional amplifiers 3144, 3146.
• a first one of the amplifiers is configured to receive an in- phase signa component I (also referred to herein a IBB and identified with reference numeral 3138) and a second one of the pair of amplifiers is configured to receive a quadrature-phase signal component Q (also referred to herein as QBB and identified with reference numbered 3140).
• Amplifiers 3144, 316 receive the respective ones of IQ signals provided thereto and provide appropriately amplified signals to inputs of respective ones of a pair of mixers (or multipliers) 3418, 3150.
• Mixers 3148, 3150 receive on second inputs thereof appropriately phase and amplitude adjusted LO signals from amplitude and phase shifting circuit 3152.
• Outputs of mixers 3148, 3150 are coupled to inputs of a summing circuit 3154.
• Summing circuit 3154 appropriately sums the signals provided thereto provide a phase shift signal 3110 (an example of which is illustrated and described in conjunction with FIG. 25B above)
• IQ modulator is configured to receive a local oscillator (“LO”) 3140 which may be a signal the same or similar as reference signal 2502.
• IQ modulator 3100 is configured to split LO 3140 into two orthogonal signal components I 3138 and Q 3132.
• Signal Component I 3138 represents an in-phase component relative to LO 3140, in other words component I 3138 and LO 3140 have the same phase.
• Component Q 3132 represents the quadrature component of LO 3140 which has a phase shift with reference to LO 3140.
• component Q 3132 can have a phase shift of 90° or TT/2 radians with respect to LO 3140.
• one or more signals derived from LO 3140 can be generated by amplitude and phase-shifting circuit 3152.
• Amplitude and phase- shifting circuit 3152 can include analog and/or digital circuits configured to shift the phase and/or amplitude of LO 3140 in order to generate one or more signals derived from LO 3140.
• amplitude and phase-shifting circuit 3152 is configured to generate signals derived from LO 3140 to be applied to
• amplitude and phase-shifting circuit 3152 is configured to generate baseband signals in order to achieve a desired phase shift of LO 3140.
• component I 3138 is provided to multiplier 3148.
• component I 3138 may first be provided to an amplifier 3144 before being provided to multiplier 3148.
• amplifiers 3144, 3146 can be used in general for any input signal conditioning, buffering or amplification / attenuation. It should be understood that although in this illustrative embodiment circuits 3144, 3146 are schematically illustrated as amplifiers, the actual function of circuits 3144/3146 is highly dependent on the specific
• a signal derived from LO 3140 generated by amplitude and phase-shifting circuit 3152 is also provided to multiplier 3148.
• Multiplier 3148 is configured to multiply component I 3138 and the signal derived from LO 3140 provide the product to adder 3154.
• component Q 3142 is provided to multiplier 3150.
• component Q 3142 may be provided to an amplifier 3146 before being provided to multiplier 3150.
• a second signal derived from LO 3140 generated by amplitude and phase-shifting circuit 3152 is provided to multiplier 3150.
• Multiplier 3150 is configured to multiply component Q 3142 and the signal derived from LO 3140 and provide the product to adder 3154.
• Adder 3154 includes analog and/or digital circuits configured to summate two or more signals together. Adder 3154 is configured to generate a phase shifted signal 3110 by summating the products provided by multiplier 3148 and multiple 3150. In other words, adder 3154 is configured to generate a phase- shifted signal according to LO 3140 and the generated baseband signals IBB and QBB.
• the output of an IQ modulator can be expressed as:
• RF(t) represents the phase-shifted signal generated by the
• phase shift Q can be controlled between the local oscillator input and the RF output, while maintaining a constant RF magnitude.
• using the IQ modulator in this fashion - strictly as a phase modulator - is particularly suitable for implementing the phase-shifting elements required for PWM generation.
• a phasor diagram (i.e. a polar plot) of an example l/Q modulation is provided.
• QBB 3242 along the Y-axis
• IBB 3238 along the X-axis of the plot
• the phase shifted signal 3210 generated by an l/Q modulator represented as a phasor between the two.
• IBB 3238 essentially controls the real component of the phase-shifted signal phasor, while QBB sets its imaginary component.
• frequency modulation is also possible by appropriately modulating the phase of the output.
• phase shift Q can be controlled between the LO 3240 input and the phase-shifted signal output 3110, while maintaining a constant phase-shifted signal magnitude.
• Using the IQ modulator in this fashion - strictly as a phase modulator - is particularly suitable for implementing the phase shifting elements required for PWM generation.
• phase of the PWM waveform may vary with frequency for a fixed set of baseband inputs I and Q
• pulse width 1 in electrical degrees
• the pulse width 1 remains constant and is not affect by frequency modulation. This is mainly due to the symmetric structure and the balanced path delays of the architecture of Fig. 33 (referred to herein as a parallel architecture).
• the pulse width of the PWM waveform is equal to the differential phase of the two logic gate inputs with respect to the REF signal.
• I and Q can be tuned in response to a frequency variation to correct for any phase error in f.
• This approach requires an accurate measure of the frequency-phase response of the IQ modulators and the propagation delays associated with the waveform combiner circuitry.
• the controller that synthesizes the I and Q signals must keep track of the operating frequency - this may be undesirable and cumbersome for some applications.
• a look-up table is implemented into a controller, the same or similar as controller 3034, which maps a set of base-band I and Q values to a phase shift between the IQ output of the phase shifting element and its reference signal.
• the I and Q values are synthesized with 12-bit OACs, and so they can only take one of 4096 discrete values.
• one of the baseband inputs is swept over its entire digital range, while the other one is adjusted to keep the magnitude of I 2 + Q 2 roughly constant as suggested by (I).
• the phase shift between REF and IQ is measured for each of the 4096 pairs of base-band inputs and stored in the look-up table. This control approach corrects for any non-linarites in the DAC transfer functions, mismatches in the gain of the base-band channels of the IQ modulator, and the insertion phase of the output band-pass filter at a particular operating frequency.
• a PWM generator 3300 includes one or more phase-shifting elements realized as a pair of IQ modulators as shown.
• the reference signal to which the PWM waveform is synchronized is fed to both IQ modulators and serves as their local oscillator input.
• a pair of DACs controlled with a microcontroller can be used to synthesize the appropriate values for the I and Q signals for each IQ modulator and thus control the Phase shift of their out outputs IQ1 and IQ2 with respect to the REF signal.
• PWM generator 3300 includes a waveform combiner 3306 implemented with a pair of comparators and a single logic gate here shown as an gate, here provided as an AND gate.
• the logic AND gate has one inverting input.
• the gate is shown like this merely to simplify circuit complexity. In reality, however, the circuitry may be implemented with an AND gate with two non-inverting inputs along with a NOT gate at one of its inputs.
• the resolution with which w and f can be controlled depends upon the resolution with which the DACs can synthesize the I and Q inputs of the two IQ modulators. It should be noted that the implementation of the waveform combiner in Fig. 33 limits the pulse width of the output PWM waveform to a maximum of 1800 which corresponds to IQi and IQ2 being 1800 out-of-phase. As described below, however, this limitation can be alleviated with a different realization of the waveform combiner.
• an IQ modulator-based implementation of a single phase-shifting element utilizes an L TC5598 (Analog Devices Inc.) chip which provides an integrated realization of an IQ modulator having differential base-band I and Q inputs and differential LO input.
• the differential voltages at the I and Q inputs are converted to currents that in turn drive double-balanced mixers.
• the outputs of these mixers are summed and applied to a buffer, which converts the differential mixer signals to a 50n single-ended buffered RF output.
• the L TC5598 allows operation over a 5 MHz to 1600 MHz local oscillator frequency range, while supporting more than 400 MHz of base-band bandwidth, which enables very fast adjustment of a PWM waveform.
• the I and Q inputs are synthesized with a pair of 12-bit DACs (AD5624, Analog Devices Inc.); their single-ended outputs are buffered and converted to differential signals with a pair of fully differential operational amplifiers (L TC6362, Linear Technology).
• the DACs are controlled with a microcontroller through a standard SPI serial interface.
• a passive impedance matching network and a I: 1 balun (TC l-l TG2+, Mini- Circuits) convert the differential LO input of the IQ modulator to a single-ended 50 n reference input REF.
• phase-shifting element to control the phase shift produced by an IQ modulator-based phase-shifting element, the appropriate I and Q inputs must be provided to the IQ modulator.
• One way to determine these inputs is through the use of a look-up table.
• a pre-determ ined look-up table stored in the controller’s memory lists the I and Q signal values that are required to produce a certain commanded phase shift.
• This look-up table can be pre- computed or measured empirically. As Fig. 34 suggests, with this look-up table approach one can control the phase of the phase-shifting element outputs (e.g. phase-shifted signals IQ1 and IQ2 in the circuit of Fig.
• Fig. 35 a plot of phase shift command vs.
• measured phase shift standard deviation illustrates the standard deviation of the measured phase error achieved in a prototype circuit.
• the standard deviation of the measured phase error in Fig. 35 can be thought of as an indirect measure of the jitter in the output of the prototype IQ modulator-based phase- shifting element.
• Fig. 35 shows the certainty with which the phase error
• Fig. 35 serves as an important metric that validates the phase error measurements of Fig. 34.
• the standard deviation of the measured phase error in Fig. 35 can be thought of as a measure of the jitter in the outputs of the phase- shifting elements and it is mainly attributed to jitter in the reference signal and the oscilloscope acquisition system with which the phase measurements were performed.
• Fig. 35 serves to validate the measurements of phase error in Fig. 34.
• Fig. 35 basically illustrates that the measured phase errors shown in Fig. 34 are accurate to within approximately ⁇ 0.1 °.
• Fig. 34 shows the measured phase error
• Fig. 35 shows how certain that measurement is (what is known as standard deviation).
• phase-shifting elements for PWM waveform generation. Also described is a design example of a cascaded PWM generation architecture having a plurality of phase-shifting elements comprising PLL’s.
• Angular pulse width refers to the width of the pulse of the PWM waveform expressed in degrees out of a 360° cycle (one full period).
• a PWM waveform with a 100nsec period and a 25nsec pulse width has a 90° angular pulse width (a quarter of a single period).
• a circuit 3600 capable of generating a variable duty cycle waveform includes a phase shifting circuit 3604 comprising a pair of phase-shifting elements 3604a, 3604b.
• Phase-shifting elements 3604a, 3604b each comprise a PLL 3616, 3618 with a first one of the PLLs 3616 having an input 3616a configured to receive a reference signal 3602.
• PLL 3616 provides a phase-shifted signal A at an output 3616b thereof.
• PLL output 3616b is coupled though a signal path to a first input of a waveform combiner 3606.
• a portion of PLL output signal A is also coupled to both an input 3618a of a second PLL 3618 as well as through a time delay circuit 3674 to a feedback input 3616c of PLL 3616.
• the first and second phase-shifting element 3604a, 3604b are coupled such that a phase-shifted output signal generated by a first phase-shifting element 3604a serves as a reference signal (i.e. an input signal) of a second phase-shifting element 3604b.
• the phase-shifting elements 3604a, 3604b are said to be coupled in a so-called“cascade” architecture.
• Time delay element 3674 introduces a time delay t in the feedback path of PLL 3616.
• the time delay t is selected to match a propagation delay through the waveform combiner circuitry 3603 from input 3606a (i.e. signal A input in FIG. 36) to output 3606C (i.e. signal Q output in FIG. 36).
• Such delay may possibly include switch gate driver delay as well as any other delay.
• time delay element 3674 introduces a time delay t selected to substantially reduce (and ideally eliminate) the dependence of phase shift f on frequency modulation.
• 3618 provides a phase-shifted signal B at an output 3618b thereof.
• Output 3618b of PLL 3618 is coupled though a signal path to a second input of waveform combiner 3606.
• a portion of PLL output signal B is also coupled to a feedback input 3618c of PLL 3618.
• Waveform combiner 3606 combines the signals provided thereto at inputs 3606a, 3606b and provides a PWM signal 3608 having a desired waveform at output 3606c. Waveform combiner 3606 combines the signals provided thereto using any of the techniques described herein or any other technique suitable to produce the PWM signal 3608.
• Each PLL module 3616, 3618 generates a respective output signal A, B at the respective outputs 3616b, 3618b such that the signals fed back to the respective feedback inputs are frequency-locked to the input signal provided to the respective input 3616a, 3618a and is phase-shifted with respect to it (i.e. phase-shifted with respect to the respective input signal) by a certain amount.
• the PLL modules 3616, 3618 thus allow direct control the of the phase shift between the input and the feedback signals.
• This phase shift may be digitally controlled (e.g., via a
• the resolution may depend, for example, upon the implementation of the PLLs.
• the phase shift it produces is typically controlled by the means of an analog current or voltage signal. It is the resolution with which this analog signal can be synthesized that ultimately determines the resolution with which phase shift can be controlled.
• the analog control signal is synthesized with a digital-to-analog converter (DAC).
• the DAC itself could be a part of the microcontroller, or can be a part of the design of the PLL phase-shifting element.
• the microcontroller directly synthesizes the analog control signal, and in this case it is indeed the resolution of the analog control signal
• microcontroller that determines the resolution with which phase shift can be controlled.
• the microcontroller can digitally control the DAC that is part of the PLL phase-shifting element.
• the PLL implementation determines the resolution with which one can control phase shift.
• Fig. 36 is thus an example of a cascaded PWM waveform generator having phase-shifting elements implemented using phase-locked loop modules coupled to a waveform combiner.
• the waveform combiner may be implemented using one or more logic gates such as a single AND gate. Such an approach allows the generation of a PWM waveform having a dynamically adjustable duty-cycle and phase cp. It should be noted that with a waveform combiner provided from a single logic gate, the angular pulse width w of the PWM waveform may be limited to a maximum of 180°.
• PLL 3618 PLL2
• PLL2 PLL2
• signal B has a phase shift of w with respect to signal A and hence lags the reference signal REF by a phase shift of f +w.
• signals A and B may be combined with a logic AND gate to produce the output signal Q having an angular pulse width n / and a phase shift f between its rising edge and the negative-to-positive transition of the REF signal.
• signal B is first inverted before being logically combined (i.e. via an AND logic gate) with signal A.
• any frequency modulation of the REF signal will cause a corresponding change in the phase shift f of the PWM waveform.
• This dependence of the PWM waveform phase on frequency may be substantially reduced (and ideally eliminated) by tuning the time delay t in the feedback path of PLL1 to match the propagation delay of the waveform combiner logic gate(s) (e.g. an AND gate).
• the amount of propagation delay that can be compensated by the feedback loop in this fashion while guaranteeing PLL stability depends upon the phase margin and bandwidth of the PLL feedback loop.
• PLL designs having high loop bandwidth can tolerate only small amount of loop delay and hence require the use of logic circuitry in the waveform combiner having a sufficient operational speed to support such operation.
• being able to fully compensate the propagation delay of waveform combiners having large propagation delays necessitates the design of a PLL with slow loop bandwidth and thus limits the speed with which phase of the PWM waveform can be adjusted.
• a waveform combiner comprising only a single logic gate (e.g. a single AND logic gate having an inverted input coupled to PLL output 3618b) is relatively simple to implement, it only allows generation of a PWM waveform having a maximum angular pulse width of 180 degrees (50 % duty cycle) which corresponds to signals A and B being 180 degrees out-of-phase. Furthermore, this is only possible if both signals A and B have 50% duty-cycle. Many applications, however, require the ability to control the duty-cycle of PWM waveforms over a wider range. Thus, an alternative implementation of a waveform combiner which alleviates the above-noted limitations is described below in conjunction with Fig. 37.
• Fig. 37 is a cascaded phase-locked PWM generator 3700 having a waveform combiner provided from edge detectors coupled to a D-type flip-flop. This approach allows dynamic adjustment of PWM phase f and angular pulse width w over a 360° range.
• time delay element t included in a feedback path of a first PLL receiving a reference signal is selected to substantially match the propagation delay through the waveform combiner circuitry from an input A to an output Q and thus eliminate the dependence of cp on frequency modulation.
• an illustrative circuit for PWM waveform generation includes a pair of phase shifting elements 3704, 3704 coupled to a waveform combiner 3706.
• Phase shifting elements 3704, 3704 may be the same as or similar to the phase shifting elements 3604a, 3604b described above in conjunction with Fig. 36.
• waveform combiner 3706 comprises a pair of edge detectors 3778, 3780 each of which receives inputs from respective ones of phase shifting elements 3704, 3704.
• Edge detectors 3778, 3780 are here implemented with a logic gate (here illustrated as an AND logic gate having an inverter coupled to one input thereof).
• edge detectors may be implemented using any type of circuits.
• any type of circuit capable of detecting signal edges e.g. rising and/or falling edges of a signal
• any type of circuit capable of detecting signal edges e.g. rising and/or falling edges of a signal
• the output of a first one of the edge detectors is coupled to a clock input CLK of a D-type flip-flop 3782.
• the output of a second one of the edge detectors, here edge detector 3780 is coupled to a reset input RESET of the D -flip-flop 3782.
• the D input of flip-flop 3782 is coupled to a reference signal (here a logic signal has a value of a logic 1 ).
• This D-type flip-flop arrangement alleviates the above-noted limitation of the circuit of Fig. 36. Since the D input of the flip-flop is coupled to a signal having a logic-high signal level, a rising edge on the CLK input sets output signal Q high (i.e. a logic-high signal level), while a rising edge on the RES input clears Q (i.e. sets the output signal Q to a logic-low signal level).
• the edge detectors 3778, 3780 at the inputs of the combiner generate a pulse to drive the flip-flop when a rising edge occurs on signals A or B.
• a PWM waveform can comprise multiple pulses in a single period with various pulse widths and spacing between the pulses.
• the pulse pattern repeats every cycle at the PWM waveform frequency.
• each 360° cycle of the generated PWM waveform has two pulses with widths a and b.
• a PWM waveform comprising only a single pulse every 360° cycle (one full period) is termed here“single-pulse PWM waveform”.
• Circuits and systems capable of generating such a plurality of such single-pulse PMW waveforms might be used, for example, to drive complementary switches in a half- bridge with controllable duty ratio and separately controllable dead-times between switches. In other applications, it may be desirable or necessary to provide controllable overlap on times, rather than controllable dead times, or more than two related single-pulse waveforms.
• Fig. 38 shows an example design of a PWM generation system capable of generating a plurality of, here two, PWM waveforms that are phase- and frequency-locked to a common reference signal REF.
• a PWM generation system 3800 includes a reference signal source 3802 which generates a reference signal.
• the reference signal is provided to inputs of each of a plurality of PLL-based PWM generators 3836a-3836N.
• PLL-based PWM generators 3836a-3836N may be the same as or similar to PWM generator 3700 described above in conjunction with Fig. 37.
• PWM generator 3836a As representative of PWM generators 3836a-3836N, PWM generator includes a pair of PLLs 3816a, 3816b coupled in a cascade configuration. As described above, in a cascade configuration, a first one of the PLL’s 3816a receives reference signal from reference signal source 3802 at an input thereof and output of PLL 3816a is coupled to an input of a second, different PLL 3818 such that a phase-shifted output signal from PLL 3816a serves as a reference signal (i.e. an input signal) of PLL 3818a. As described above, an output of PLL 3816a is coupled through a time delay circuit 3874a to a feedback input of PLL 3816a. The phase-shifted signals generated by PLLs 3816a, 3818a are provided to inputs of a waveform combiner to generate a PWM output signal Q at an output 3808a of PWM generator 3836a.
• PMW generation system 3800 further includes a controller 3834.
• Controller 3834 provides phase-shift parameter values to phase-shifting elements in each of the PWM generators 3836a-3836N.
• controller 3834 provides phase-shift parameter values 3812a-3812N to respective ones of PLLs 3816a-3816N, 3838a-3838N.
• system 3800 comprises two of the PLL- based PWM generators 3836 fed with the same reference signal
• the system is capable of independently controlling the phase shift 1, 2 and the pulse width wi, W2 of two PWM waveforms Q1 and Q2, respectively.
• the circuit of Fig. 38 can be used, for example, to generate drive signals for two complimentary switches in a half-bridge circuit with controllable duty-cycle and dead time.
• the PWM waveforms Q1 and Q2 may be provided having approximately 25% duty-cycle and 25% symmetric dead time, i.e. the dead time at each transition is about 25% of the PWM period.
• the rising edges of Q1 and Q2 may be 180° apart and aligned with the maximums and minimums of the reference signal
• an illustrative PWM generation system 3900 includes first and second phase shifting elements 3904a, 3904b coupled such that a phase-shifted output signal generated by a first PLL 3916 serves as a reference signal (input) of a second PLL 3918.
• PLLs 3916, 3918 are coupled in the so-called cascade architecture described above in conjunction with Fig. 36.
• a feedback signal provided to FB input 3916c of PLL 3916 is taken directly from an output of a waveform combiner 3906 (i.e. a portion of output signal Q is provided to a feedback input 3916c of PLL 3916).
• System controller 3934 provides phase-shift parameters to phase shifting elements 3904a, 3904b and in particular, to PLLs 3916, 3918.
• the phase- shift parameters comprise at least one or more phase shift values.
• system controller 3934 provides a phase-shift value of f to phase shifting element 3904a and provides a phase-shift value of w to phase shifting element 3904b.
• phase-shifting element 3904a with a predetermined phase-shift value of f forces PLL 3916 to adjust the phase of its output signal (i.e. signal A in Fig. 39) until the phase shift between the reference signal REF and the feedback signal provided to the FB input of PLL 3916 is a phase of f.
• phase-shifting elements 3916, 3918 are coupled in the so-called cascade configuration, this results in phase-shifting element 3904b producing a phase-shifted signal B having a phase shift of f + w.
• the phase- shifted signal produced by phase-shifting elements 3904a, 3904b are combined in the waveform combiner 3906 to generate PWM signal 3908 (i.e. output signal Q) having a phase shift f and a pulse width w.
• PWM signal 3908 i.e. output signal Q
• a flow diagram of process for generating a PWM signal having a desired pulse width and phase shift relative to a reference signal begins in processing block 4002, in which a PWM generator receives a reference signal.
• a PWM generator may be the same as or similar to any of the PWM generators described herein and is configured to receive at least one reference signal.
• the reference signal may be the same as or similar to any of the reference signals described herein (including, but not limited to, reference signal) 2502 described above in conjunction with Fig. 25B).
• the PWM generator can include at least one phase-shifting element, which may be the same as or similar to phase-shifting elements 2504.
• the phase-shifting elements of the PWM generator may have either a parallel architecture, a cascade architecture, or both, as discussed above with reference to FIGs. 26 and 27.
• Processing then proceeds to processing block 4004 in which at least one phase-shifting element of the PWM generator generates a phase-shifted signal at an output thereof.
• a phase-shifted signal may be the same as or similar to phase-shifted signals 2508 described in conjunction with Fig. 25B.
• the phase shift of the phase-shifted signal may be based upon the reference signal(s) provided in processing block 4002 as well as based upon a respective
• phase-shift parameter can include a predetermined phase shift and/or predetermined pulse width used in the generation of the phase-shifted signal.
• the predetermined phase- shift parameter can include a desired phase-shift for a respective phase-shifting element to apply to a reference signal in order to generate a phase-shifted signal.
• some phase-shifting elements can be configured to generate a phase-shifted signal by phase-shifting a reference signal according to a
• phase-shifting elements can be configured to generate a phase-shifted signal by phase-shifting a phase-shifted signal generated by another phase-shifting element.
• the predetermined phase-shift parameters can be generated by a controller which may be the same as or similar to any of the controllers described herein.
• the controller can be configured to generate the predetermined phase-shift parameters based upon desired pulse widths and phases relative to a reference signal for a PWM signal generated by the PWM generator.
• the controller is configured to provide the generated, predetermined phase-shift parameters to respective phase-shifting elements.
• phase-shifted signals generated in processing block 4004 are combined to generate one or more PWM signals.
• the phase-shifted signals generated in processing block 4004 may be combined using a variety of techniques including any of the techniques described herein.
• the phase-shifted signals maybe combined by providing the phase-shifted signals to a waveform combiner which may be the same as or similar to any of the waveform combiners described herein.
• the waveform combiner can operate to compare, summate, detect, divide, (or any combination thereof) the received shifted signals to generate PWM signals.
• the generated PWM signals have a desired pulse width and phase shift relative to the reference signal based upon the predetermined phase-shift parameters of the phase shifting elements.
• an illustrative power generation and delivery system 4100 having first and second ports 4127, 1429 includes a phase- switched and tunable impedance matching network 4188 (PSIM TMN) having an input coupled to port 4127 and having an output coupled to port 4129.
• PSIM TMN phase- switched and tunable impedance matching network 4188
• a means for monitoring impedance at port 4127 is coupled between port 4127 and PSIM TMN input 4188a and a means for monitoring impedance 4196 is coupled between PSIM TMN output 4188b and port 4129.
• the means for monitoring impedance 4194, 4196 may measure, detect compute or otherwise determine impedances at one or both of ports 4127 4129. Use of such means allows impedance to be determined dynamically.
• PSIM TMN 4188 includes one or more phase-switched impedance (PSIM) elements with N PSIM elements 4190a-N here being shown.
• PSIM elements 4190a-N may be the same as or similar to the phase-switched elements described herein (e.g. phase-switched reactance elements 116 discussed above with reference to FIG. 1 ).
• Each PSIM element 4190a-N is coupled to a PWM generation circuit 4136 which comprises at least one PWM generator.
• PWM generators in PWM generation circuit 4136 may be the same as or similar to the PWM generators described herein.
• PSIM element 4190a-N are configured to be responsive to PWM signals provided by PWM generation circuit 4136.
• PSIM TMN 4088 adjusts an impedance present at (i.e. looking into) either, or both of, the first and second ports 4127, 4129.
• portions of signals provided to and from PSIM TMN 4188 are coupled to PWM generators 4136.
• PWM generators 4136 the input/output signals of the TMN in Fig. 41 A can be used as reference signals for the PWM generators to properly synchronize the switching of the PSIM elements to currents/voltages in the TMN network.
• Fig. 41 A one can also use external SYNC signals as reference for the PWM generator.
• PWM generators 4136 are each configured to receive at least one reference signal and at least one control signal. Control signals may be provided, for example, by a controller 4184 which may be the same as or similar to any of the controllers described herein.
• M reference signals designated as SYNC 1 -M are shown (with M ⁇ N) where N refers to the number of PSIM elements.
• the PWM generator can take-in an arbitrary number M of SYNC signals, and there is no real need to constraint M ⁇ N (i.e. in some embodiments, it may be desirable or even necessary for M>N).
• the PWM generator can take in more SYNC signals than there are PSIM elements and dynamically switch which SYNC signal to use for which PSIM element based on internal control or some command from the system controller.
• PWM generator, circuit 4136 In response to the signals provided thereto, PWM generator, circuit 4136 generates at least one PWM signal having a pulse width and a phase shift relative to a reference signal.
• Reference signals can include signals which may be the same as or similar to reference signals described herein (such as, for example, reference signal 2502 described above in conjunction with FIG. 25).
• PWM signals generated by PWM signal generators 4136 are provided to the at least one PSIM elements 4190a-N.
• Each PWM generator 4136 can include one or more phase-shifting elements configured to generate phase-shifted signals (based, at least in part, upon phase-shift parameters provided from controller 4184) and one or more waveform combiners configured to generate at least one PWM signal based upon the generated phase-shifted signals.
• PSIM TMN 4188 is configured to adjust the impedances presented at PORT 1 and/or PORT 2 according to the pulse widths and phase shifts relative to reference signals of the PWM signals generated by PWM signal generators 4136.
• the impedances presented at PORT 1 and/or PORT 2 are determined based upon the pulse widths and phase shifts (relative to reference signals) of the PWM signals generated by PWM signal generator circuit 4136.
• the desired impedance values presented at PORT 1 and/or PORT 2 may be achieved by appropriately selecting the values for the pulse widths and phase shifts of the PWM signals provided to PSIM TMN. After reading the description provided herein, one of ordinary skill in the art will further appreciate that desired values for the impedance presented at PORT 1 and/or PORT 2 may be achieved by selecting appropriate phase-shift parameters that are provided to the phase-shifting elements of PWM generators included in PWM generation circuit 4136.
• predetermined phase-shifting parameters can be provided to the phase-shifting elements of PWM generators by system controller 4184.
• System controller 4184 can include a DSP, processor, microprocessor, computer, microcontroller, or any combination thereof— to name a few.
• system controller 4184 is configured to generate predetermined phase-shift parameters based upon desired values for the pulse widths and phase shifts relative to reference signals of the PWM signals generated by PWM generators 4136.
• system controller 4184 is configured to generate predetermined phase-shift parameters based upon desired values for the impedance presented at PORT 1 and/or PORT 2.
• the means for monitoring impedance 4149, 4196 may be provided as one or more current and/or voltage (l-V) probes with at least one l-V probe coupled to PORT 1 and at least one l-V probe coupled to PORT 2.
• Each l-V probe is configured to monitor (e.g. measure, detect compute or otherwise determine) a load impedance and/or impedance loading of PORTs 1 and 2 and provide a signal representative of the monitored load impedance and/or impedance loading to system controller 4184.
• system controller 4184 is configured to adjust generated, predetermined phase-shift parameters provided to the phase-shifting elements 4190a-4190N so as to adjust the values of the impedances at PORT 1 and/or PORT 2 to desired values.
• system controller 4184 can control the PWM generators and PSIM TMN 4188 based upon the monitored load impedance and/or impedance loading monitored (e.g. measured, detected, or otherwise determined) at PORT 1 and/or PORT 2.
• an illustrative RF power generation and delivery system 4100 includes a system controller having a first output coupled to an RF input of an inverter 4186 and a second output coupled to an input of a PWM generation circuit 4136.
• PWM generation circuit 4136 includes one or more PWM generators each of which may be the same as or similar to any of the PWM generators described herein.
• An output of RF inverter 4186 is coupled to an input of a PSIM TMN 4188.
• An output of PSIM TMN 4188 is coupled to a load 4192.
• PSIM TMN 4188 includes a plurality of PSIM elements 4190a-N. Each PSIM element 4190a-N is coupled to at least one PWM generator of PWM generation circuit 4136. PWM generators in PWM generation circuit 4136 are configured to generate PWM signals having pulse widths and phase shifts relative to a reference signal.
• the PWM generators in Fig. 41 B can take a reference signal from the control system, from the input / output of the TMN, any internal current/voltage signal from the TMN, or any other externally provided SYNC signal similar to Fig. 41 A (as indicated by the dashed lines).
• phase shift parameters provided by system controller 4184. Some of the phase shift parameters provided by the control system are responsible for controlling the phase of the generated PWM waveform with respect to a reference signal, and other phase shift parameters control the pulse width of the PWM waveforms.
• phase-shift parameters that control PWM pulse width have to be adjusted dynamically and are often determined through some sort of feedback (e.g. measurements of TMN input / load impedance, reflected power at the TMN ports, etc.). These can also be controlled / overwritten directly by a user.
• phase shift parameters that control the phase of the PWM waveforms typically do not need to be dynamically adjusted and can be pre-stored in a look-up table which can be obtained by a system calibration. In general, however, these phase shift parameters can also be determined based on feedback (e.g. voltage and current waveforms in the TMN, power lost in the PSIM devices, etc.) and may be dynamically adjusted by the control system (or overwritten by a user) to meet the demands of the system. In response to signals provided to and/or from PWM generation circuit, PSIM TMN 4188 adjusts impedances presented at its input and output.
• feedback e.g. voltage and current waveforms in the TMN, power lost in the PSIM devices, etc.
• PSIM TMN 4188 adjusts impedances presented at its input and output.
• system controller 4184 may generate values of predetermined phase-shift parameters provided to PWM generation circuit 4136 such that desired values for impedances presented to RF inverter 4186 and/or load 4092 may be achieved.
• desired values for impedances presented to RF inverter 4186 and/or load 4092 will depend on the operation, use, design, etc. of the RF power generation and delivery system.
• an illustrative rf power generation and delivery system 4200 includes an RF inverter or amplifier 4286 having an output coupled to an input of a PSIM TMN 4288.
• PSIM TMW 4288 includes at least one PSIM element.
• RF inverter 4286 is here illustrated as a voltage source 4203 and resistor Rs 4205.
• An l-V probe 4294 is coupled between the RF inverter and the PSIM TMN.
• a load 4298 having a load impedance ZL is coupled to the output of PSIM TMN 4288.
• An l-V probe is coupled between PSIN TMN 4288 and load 4298.
• the system further includes a PWM waveform generator 4236 (including phase-shifting element A 4216, phase-shifting element B 4218, and waveform combiner 4206), l-V probes 4294, 4296, and system controller 4284.
• PSIM TMN 4288 is coupled, at its input, to RF inverter or amplifier 4286 and, at its output, to a load 4298 and is configured to adjust an impedance presented to RF inverter or amplifier 4286 and an
• the PSIM element includes capacitors Csi 4207, Cs2 4217, and CPI , inductors Lsi 4209 and I_s2 4215, and transistor qi.
• Transistor qi is configured to receive a drive signal 4208 from PWM generator 4236, and in response thereto adjust the impedances presented at the input and/or output terminals of PSIM TMN 4288 (i.e. adjust the impedances presented to RF inverter or amplifier 4286 and/or load 4298).
• the drive signal can be provided as a PWM signal generated by PWM generator 4236 using any of the techniques described herein.
• An input of PSIM TMN 4288 is coupled to an input of PWM generator 4236 (here through a level adjust circuit 4233 which may comprise, for example, an attenuator) so that a signal (e.g. voltage signal) at the input of PSIM TMN 4288 is provided to PWM 4236 as a reference signal 4202.
• a signal e.g. voltage signal
• the signal at the input of PSIM TMN 4288 may first be provided to attenuator 4284 before being provided as reference signal 4202 ensure compatibility with the PWM generator’s 4236 internal circuitry.
• PWM generator 4236 is provided having a parallel architecture.
• reference signal 4202 is provided to both phase-shifting elements A, B 4216, 4218 with each phase-shifting element configured to generate a phase-shifted signal 4210A,
• phase-shifting elements 4216, 4218 can be provided to phase-shifting elements 4216, 4218 by system control 4284. It should, of course, be appreciated that in other embodiments it may be desirable or necessary to provide PWM generator 4236 having a cascade architecture.
• l-V probes 4294, 4296 are configured to monitor (e.g. detect, measure, compute or otherwise determine) the impedances presented to load 4298 and RF inverter 4286 and provide the monitored impedances to system control 4284.
• system control 4284 is configured to generate predetermined phase-shift parameters based upon the monitored impedances to achieve desired values for the monitor the impedances presented to load 4298 and RF inverter 4286.
• an illustrative rf power generation and delivery system 4300 includes a PSIM TMN 4388 with input and output terminals and two PSIM elements; an RF inverter or amplifier 4386 (including voltage source 4303 and resistor Rs 4305); PWM waveform generators A, B 4236A, 4326B (each including a first phase-shifting element 4316A,B and a second phase-shifting element 4318A,B, and waveform combiner 4306A,B); l-V probes 4394, 4396, and a system controller 4384.
• PSIM TMN 4388 with input and output terminals and two PSIM elements
• an RF inverter or amplifier 4386 including voltage source 4303 and resistor Rs 4305
• PWM waveform generators A, B 4236A, 4326B each including a first phase-shifting element 4316A,B and a second phase-shifting element 4318A,B, and waveform combiner 4306A,B
• l-V probes 4394, 4396
• PSIM TMN 4388 is coupled, at its input, to RF inverter or amplifier 4386 and, at its output, to a load 4398 and is configured to adjust an impedance presented to RF inverter or amplifier 4386 and an impedance presented to load 4298.
• a first PSIM element includes a transistor qi 4321 configured to receive a drive signal and in response thereto adjust an impedance presented at the output terminal of PSIM TMN 4288 (i.e. adjust the impedance presented to load 4398).
• the drive signal for qi 4321 can be provided as a PWM signal generated by PWM generator 4336A.
• a second PSIM element includes a transistor q2 4311 configured to receive a drive signal and in response thereto adjust the impedance presented at the input terminal of PSIM TMN 4388 (i.e. adjust the impedance presented to RF inverter or amplifier 4386).
• the drive signal for q2 4311 can be provided as a PWM signal generated by PWM generator 4336B.
• PWM generator 4336 is configured to generate a PWM signal based upon predetermined phase-shift parameters provided to its phase-shifting elements 4316, 4318.
• these phase-shifting parameters can be generated by system control 4384, with system control 4384 configured to generate predetermined phase-shift parameters based upon desired values for the impedance presented at the inputs and outputs of PSIM TMN 4388.
• Each PWM signal generated by PWM generators 4336A,B has a pulse width and phase shift relative to a respective reference signal provided to the PWM generator.
• the reference signal provided to PWM generator A 4336A can include one or more signals (e.g. a voltage signal) at the output of PSIM TMN 4388 and the reference signal provided to PWM generator B 4336B can include one or more signals (e.g. a voltage signal) at the input of PSIM TMN 4388.
• PWM generator A 4336A generates a PWM signal with a pulse width and phase shift relative to the signals at the output of PSIM TMN 4388 and PWM generator B 4336B generates a PWM signal with a pulse width and phase shift relative to the signals at the input of PSIM TMN 4388.
• l-V probes 4396, 4398 on the input and output ports of the PSIM TMN 4338 monitor the impedances presented at the inputs and outputs of PSIM TMN 4338 based on which system control 4384 can control each PWM generator 4336 and the operation of RF inverter or amplifier 4386 (e.g. operating frequency, output power).
• X employs A or B is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then“X employs A or B” is satisfied under any of the foregoing instances.
• the articles “a” and“an” as used in this application and the appended claims should generally be construed to mean“one or more” unless specified otherwise or clear from context to be directed to a singular form.
• each numerical value and range should be interpreted as being approximate as if the word“about”,“substantially” or“approximately” preceded the value of the value or range.
• embodiments might also be implemented in the form of program code embodied in tangible media, such as magnetic recording media, hard drives, floppy diskettes, magnetic tape media, optical recording media, compact discs (CDs), digital versatile discs (DVDs), solid state memory, hybrid magnetic and solid state memory, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the claimed invention.
• tangible media such as magnetic recording media, hard drives, floppy diskettes, magnetic tape media, optical recording media, compact discs (CDs), digital versatile discs (DVDs), solid state memory, hybrid magnetic and solid state memory, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the claimed invention.
• Described embodiments might also be implemented in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium or carrier, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the claimed invention.
• program code segments When implemented on a processing device, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits.
• Such processing devices might include, for example, a general purpose microprocessor, a digital signal processor (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a microcontroller, an embedded controller, a multi-core processor, and/or others, including
• Described embodiments might also be implemented in the form of a bitstream or other sequence of signal values electrically or optically transmitted through a medium, stored magnetic-field variations in a magnetic recording medium, etc., generated using a method and/or an apparatus as recited in the claims.
• the terms“couple,”“coupling,” “coupled,”“connect,”“connecting,” or“connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms“directly coupled,” “directly connected,” etc., imply the absence of such additional elements. Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here. [00324] It should be understood that the steps of the methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely illustrative. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments.

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