WO2020042868A1 - 一种静态随机存储器sram单元以及相关装置 - Google Patents

一种静态随机存储器sram单元以及相关装置 Download PDF

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Publication number
WO2020042868A1
WO2020042868A1 PCT/CN2019/099132 CN2019099132W WO2020042868A1 WO 2020042868 A1 WO2020042868 A1 WO 2020042868A1 CN 2019099132 W CN2019099132 W CN 2019099132W WO 2020042868 A1 WO2020042868 A1 WO 2020042868A1
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Prior art keywords
transistor
pull
read
sram
data
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PCT/CN2019/099132
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English (en)
French (fr)
Inventor
许晗
乔飞
郑淼
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华为技术有限公司
清华大学
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Application filed by 华为技术有限公司, 清华大学 filed Critical 华为技术有限公司
Priority to EP19855032.9A priority Critical patent/EP3832648A4/en
Publication of WO2020042868A1 publication Critical patent/WO2020042868A1/zh
Priority to US17/187,455 priority patent/US11456030B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a static random access memory (SRAM) unit and related devices.
  • SRAM static random access memory
  • Static random access memory is a kind of storage device with static access function. It can save its internal data without refreshing the circuit. It is widely used in digital and various electronic circuit product designs. When performing read / write operations on the SRAM, the SRAM bit lines need to be charged and discharged. Therefore, frequent read / write operations on the SRAM will result in a large power consumption of the SRAM, which in turn restricts processors that require frequent access to the SRAM. Processing speed.
  • the 6T-SRAM cell includes 6 transistors, which are transistors M1 to M6.
  • the two differential bit lines BL and BLB are in advance
  • the bit line BL is pulled down to low by the transistors M1 and M3, and the bit line BLB remains high and reads "0"
  • the two differential bit lines BL and BLB are precharged to VDD, and the transistor M1 and the transistor M2 are turned on.
  • Line BLB is pulled down to low level by transistors M2 and M4, while bit line BL remains high and reads "1", that is, when a read operation is performed on the SRM, the level of one bit line always drops and decreases in advance. Power is consumed while charging.
  • the application provides a static random access memory SRAM unit and related devices to reduce the power consumption of the SRAM when accessing the static random access SRAM.
  • the present application provides a SRAM cell, where the SRAM cell is located in a SRAM memory, and the SRAM memory includes a SRAM memory array composed of a plurality of the SRAM cells.
  • the SRAM cell includes a storage circuit, a write circuit, and a read circuit.
  • the storage circuit is connected to the writing circuit and the reading circuit, respectively, for storing data, where the data is first data or second data, and the first data is represented by a high level, The second data is represented by a low level; the writing circuit is also connected to a writing line and a writing bit line for writing data into the storage circuit; the reading circuit is also connected to a read enable The signal terminal and the read bit line are connected, wherein when the first number of SRAM cells storing the first data in a column where the SRAM cells in the SRAM memory array are located is greater than that of the SRAM cells storing the second data At the second count, the read bit line is charged to a high level after the SRAM memory receives a read command and before the read enable signal on the read enable signal terminal is valid; when the first When a number is less than the second number, the read bit line is discharged to a low level after receiving a read command from the SRAM memory and before the read enable signal is valid, and the read A circuit for enabling the read bit line after the read enable signal is valid
  • the read bit lines connected to the SRAM cells are Charge in advance to a high level, so that when the readout circuit reads out the first data next time, charging the read bit line does not consume energy; when the first data is stored in a column where the SRAM cell is located
  • the read bit line is discharged to a low level in advance, so that the next time the readout circuit reads out the second data Does not consume energy.
  • the SRAM memory can adjust the working structure of the SRAM memory according to the number of first data and the number of second data stored in a column of SRAM cells of the SRAM memory, so as to avoid as much as possible from the SRAM memory.
  • the energy consumed by charging the read bit line connected to the SRAM cell is reduced, thereby reducing the power consumption of the SRAM memory.
  • the readout circuit may be implemented by, but not limited to, the following two ways:
  • the readout circuit includes a first pull-up transistor, a first pull-down transistor, a first read-transistor, and a second read-transistor.
  • the gates of the first pull-up transistor are respectively connected to the first pull-down transistor.
  • the gate of the pull-up transistor and the storage circuit are connected, the source of the first pull-up transistor is connected to the drain of the second pull-up transistor, and the drain of the first pull-up transistor is respectively connected to the first pull-down transistor.
  • the drain of the pull-down transistor, the source of the first read-transmission transistor, and the drain of the second read-transmission transistor are connected, and the source of the first pull-down transistor is connected to the drain of the second pull-down transistor.
  • the source of the second pull-down transistor is grounded, the source of the second pull-up transistor is connected to a power source, the gate of the second pull-up transistor and the gate of the second pull-down transistor are used to receive the first pull-down transistor.
  • a read control signal or the second read control signal, the drain of the first read transfer transistor is respectively connected to the source of the second read transfer transistor and the read bit line, and the first read transfer transistor Gate with first read.
  • the signal enable terminal is connected, and the gate of the second read transmission transistor is connected to a second read enable signal terminal.
  • the read enable signal terminal includes the first read enable signal terminal and the second read enable signal. Signal end.
  • the second pull-up transistor when the gate of the second pull-up transistor and the gate of the second pull-down transistor receive the first read control signal, the second pull-up transistor is in an off state, and the second The pull-down transistor is in a conductive state; when the gate of the second pull-up transistor and the gate of the second pull-down transistor receive the second read control signal, the second pull-up transistor is in a conductive state The second pull-down transistor is in an off state; when the first read enable signal on the first read enable signal terminal is valid, and the second read enable signal on the second read enable signal terminal When the read enable signal is valid, the first read transmission transistor and the second read transmission transistor are both in an on state, and the read enable signal includes the first read enable signal and the second read enable Enable signal, the second read enable signal is an inverted signal of the first read enable signal.
  • first read control signal and the second read control signal are two different levels of the read control signal input from the same read control signal terminal, that is, the first read enable signal terminal And the second read enable signal terminal is the same input terminal.
  • the first read enable signal and the second read enable signal are two signals.
  • the readout circuit may include a first pull-up transistor, a first pull-down transistor, a first read-transistor, and a second read-transistor.
  • the gates of the first pull-up transistor are respectively connected to the first pull-up transistor.
  • the gate of the pull-down transistor and the storage circuit are connected, the source of the first pull-up transistor is connected to the drain of the second pull-up transistor, and the drain of the first pull-up transistor is respectively connected to the first
  • the drain of the pull-down transistor and the source of the third read transfer transistor are connected, the source of the first pull-down transistor is connected to the drain of the second pull-down transistor, and the source of the second pull-down transistor is grounded,
  • a source of the second pull-up transistor is connected to a power source, and a gate of the second pull-up transistor and a gate of the second pull-down transistor are used to receive the first read control signal or the second read
  • a drain of the third read transfer transistor is connected to the read bit line, and a gate of the third read transfer transistor is connected to a read enable signal terminal.
  • the second pull-up transistor when the gate of the second pull-up transistor and the gate of the second pull-down transistor receive the first read control signal, the second pull-up transistor is in an off state, and the second The pull-down transistor is in a conductive state; when the gate of the second pull-up transistor and the gate of the second pull-down transistor receive the second read control signal, the second pull-up transistor is in a conductive state The second pull-down transistor is in an off state; when the read enable signal on the read enable signal terminal is valid, the third read transfer transistor is in an on state.
  • first pull-up transistor, the second pull-up transistor, and the first read transfer transistor are P-channel field effect transistors; the first pull-down transistor, the second pull-down transistor, and the first The second read transmission transistor is an N-channel field effect transistor.
  • the storage circuit includes a third pull-up transistor, a fourth pull-up transistor, a third pull-down transistor, and a fourth pull-down transistor.
  • the sources of the third pull-up transistor and the fourth pull-up transistor are connected to a power source; the gates of the third pull-up transistor are respectively connected to the gate of the third pull-down transistor and the first pull-up transistor.
  • the drains of the four pull-up transistors, the drains of the fourth pull-down transistors, the readout circuit, and the write circuit are connected; the gates of the fourth pull-up transistors are respectively connected to the fourth pull-down transistors.
  • the gate, the drain of the third pull-up transistor, the drain of the third pull-down transistor, and the write circuit are connected; the source of the third pull-down transistor and the source of the fourth pull-down transistor Both are grounded.
  • the third pull-up transistor and the fourth pull-up transistor are P-channel field effect transistors; the third pull-down transistor and the fourth pull-down transistor are N-channel field effect transistors.
  • the writing circuit includes a first write transfer transistor and a second write transfer transistor, a source of the first write transfer transistor is connected to a first write bit line, and the first write transfer transistor
  • the gate of is connected to the writing line
  • the drain of the first write transfer transistor is connected to the drain of the third pull-up transistor and the gate of the fourth pull-up transistor, respectively
  • the second write The source of the transfer transistor is connected to the drain of the fourth pull-up transistor and the gate of the third pull-up transistor
  • the source of the second write-transistor is connected to the second write bit line.
  • the gate of the second write transfer transistor is connected to the write line.
  • the write bit line includes the first write bit line and the second write bit line; when the write circuit writes data to the storage circuit, the first write transfer transistor and the write bit line The second write transfer transistors are all in an on state; the first write bit line is opposite to the second write bit line.
  • first write transfer transistor and the second write transfer transistor are both N-channel field effect transistors.
  • the present application provides a SRAM memory, which includes a plurality of SRAM cells according to any one of the first aspects.
  • the SRAM memory can adjust the working structure of the SRAM memory according to the number of first data and the number of second data stored in a column of SRAM cells of the SRAM memory, so as to reduce When a read operation is performed on the SRAM cell, the energy consumed by charging the read bit line connected to the SRAM cell is reduced, thereby reducing the power consumption of the SRAM memory.
  • the SRAM memory further includes N data statistics circuits, N multiplexers, and M ⁇ N read control signal storage circuits; wherein N is equal to a data bit width, and N is equal to data Bit width, each bit in the data corresponding to the data bit width corresponds to M columns in the SRAM memory array, the N data statistics circuits correspond one-to-one with the multiplexer, and the SRAM memory array includes M ⁇ N columns of the SRAM cells; each of the N data statistics circuits is connected to M of the read control signal storage circuits through a corresponding multiplexer, and M ⁇ N of the read control signal storage circuits Each is connected to a column of SRAM cells in the SRAM memory array.
  • the data statistics circuit is configured to count the number of the first data and the number of the second data in the data to be written into the target SRAM cell, and the target SRAM cell is connected to the data statistics circuit in the SRAM storage array A row of the SRAM cells; when the number of the first data is greater than the number of the second data, a first read control signal for controlling the charge of the read bit line to a high level is generated, and when When the number of the first data is less than the number of the second data, generating a second read control signal for controlling the read bit line to discharge to a low level;
  • the read control signal storage circuit connected to the target SRAM cell is configured to store the first read control signal or the second read control signal; wherein the first read control signal is at a high level and the second The read control signal is low.
  • the SRAM memory further includes: M ⁇ N data statistics circuits and M ⁇ N read control signal storage circuits, where N is equal to a data bit width, and data corresponding to the data bit width
  • N is equal to a data bit width
  • the SRAM memory array includes M ⁇ N columns of the SRAM cells, the M ⁇ N data statistics circuits, and the M ⁇ N columns of the SRAM cells and M ⁇ N the data statistics circuits correspond one-to-one, and each of the data statistics circuits is connected to one column of the SRAM cells through one of the read control signal storage circuits.
  • the data statistics circuit is configured to count the number of the first data and the number of the second data in the data to be written into the target SRAM cell, and the target SRAM cell is the one in the SRAM storage array.
  • a row of the SRAM cells connected to the data statistics circuit when the number of the first data is greater than the number of the second data, a first read control for controlling the read bit line to be charged to a high level is generated
  • the read control signal storage circuit connected to the target SRAM cell is configured to store the first read control signal or the second read control signal; wherein the first read control signal is at a high level and the second The read control signal is low.
  • the data statistics circuit includes a counting circuit and a comparison circuit.
  • the counting circuit is configured to count the first number of the first data and the second number of the second data in the data to be written into the target SRAM cell
  • the comparison circuit is configured to compare the first data Compare the number and the second number, and output the first read control signal when the first number is greater than the second number, and when the first number is less than the second number And outputting the second read control signal.
  • the counting circuit is configured to count the first number of the first data in the data that needs to be written into the target SRAM cell
  • the comparison circuit is configured to compare the first number and For comparison, L is the total number of data that needs to be written into the target SRAM cell (when the data bit width of the SRAM and the number of SRAM cells included are constant, the total number of data that needs to be written to the target SRAM cell Is known), when the first number is greater than the Output the first read control signal when the first number is less than the Output the second read control signal at time.
  • the counting circuit is configured to count a second number of the second data in the data that needs to be written in the target SRAM cell
  • the comparison circuit is configured to compare the first number and the second number. Compare when the second number is less than the Output the first read control signal when counting, when the second number is greater than the Output the second read control signal at time.
  • the read control signal storage circuit is a latch.
  • the data statistics circuit is further configured to: when the first number is equal to the second number, generate the first read control signal or the second read control signal.
  • the SRAM memory further includes M ⁇ N read control circuits, and each of the M ⁇ N read control circuits is respectively connected to a column in the SRAM memory array through a corresponding read bit line. SRAM cell connection.
  • the read control circuit is configured to, after the SRAM memory receives a read command, before the read enable signal of a column of SRAM cells connected to the read control circuit is valid, the first read control signal And under the control of an inverted signal of a precharge signal, charging a read bit line corresponding to a column of SRAM cells connected to the read control circuit to a high level; or the read control circuit is configured to receive After the read command, before the read enable signal of a column of SRAM cells connected to the read control circuit is valid, the read control circuit is connected under the control of the second read control signal and the precharge signal. The read bit line corresponding to a column of SRAM cells is discharged to a low level.
  • the read control circuit includes a fifth pull-up transistor, a fifth pull-down transistor, a first-choice switch and a second-choice switch;
  • a source of the fifth pull-up transistor is connected to a power source, a gate of the fifth pull-up transistor is connected to an output terminal of the first alternative, and a drain of the fifth pull-up transistor is connected to all In the SRAM memory array, one end of a read bit line corresponding to a column of SRAM cells connected to the read control circuit is connected, a first input end of the first two alternative switch is connected to a power source, The second input terminal is used to input the inverted signal of the precharge signal, and the control terminal of the first two-to-one switch is used to input the first read control signal or the second read control signal;
  • the drain of the fifth pull-down transistor is connected to the other end of the read bit line corresponding to a column of SRAM cells connected to the read control circuit in the SRAM memory array.
  • the gate of the fifth pull-down transistor is one of the second and second options.
  • the output end of the switch is connected, the source of the fifth pull-down transistor is grounded, the first input end of the second alternative switch is used to input the precharge signal, and the second alternative switch is second.
  • the input terminal is grounded, and the second or second switch is selected.
  • the control terminal is used to input the first read control signal or the second read control signal.
  • the The output terminal of the first alternative switch is in communication with the first input terminal of the first alternative switch, the fifth pull-up transistor is in an on state, and the output terminal of the second alternative switch is connected to all The first input terminal of the second alternative switch is connected, and the fifth pull-down transistor is in an off state; when the control terminal of the first alternative switch and the control terminal of the second alternative switch are input, When the second read control signal and the precharge signal are valid, the output terminal of the first two-select-one switch is in communication with the second input terminal of the first two-select-one switch, and the fifth pull-up The transistor is in an off state, the output terminal of the second alternative switch is in communication with the second input terminal of the second alternative switch, and the fifth pull-down transistor is in an on state.
  • the fifth pull-up transistor is a P-channel field effect transistor
  • the fifth pull-down transistor is an N-channel field effect transistor
  • the present application further provides a processing circuit chip, which includes any one of the SRAM memories in the second aspect and one or more processing circuits, and the SRAM memory is configured to store the one or more Data required for multiple processing circuits to operate.
  • the SRAM processor included in the processing circuit chip can adjust the number of first data and the number of second data stored in each column of SRAM cells in the SRAM memory.
  • the working structure of each column of SRAM cells is to avoid as much as possible the energy consumed by charging the read bit lines connected to the SRAM cells when performing read operations on the SRAM cells, so as to reduce the power consumption of the SRAM memory, thereby improving the The performance (such as processing speed) of the processing circuit chip.
  • the present application further provides an electronic device.
  • the electronic device includes a power source and the processing circuit chip according to the third aspect, wherein the power source is used to supply power to the processing circuit chip.
  • FIG. 1 is a schematic structural diagram of a 6T-SRAM cell in the prior art
  • FIG. 2 is a schematic structural diagram of a system on a chip applied to a neural network according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a SRAM cell according to an embodiment of the present application.
  • 4a is a schematic structural diagram of a readout circuit in an SRAM cell according to an embodiment of the present application.
  • 4b is a schematic structural diagram of a readout circuit in another SRAM cell according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a storage circuit in a SRAM cell according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a write circuit in a SRAM cell according to an embodiment of the present application.
  • FIG. 7a is a schematic structural diagram of a circuit for charging and discharging a read bit line in an SRAM cell according to an embodiment of the present application
  • FIG. 7b is a working timing diagram of a SRAM cell provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a SRAM according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another SRAM according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of still another SRAM according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a specific structure of an SRAM according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a processing circuit chip according to an embodiment of the present application.
  • CNNs convolutional neural networks
  • the present application proposes a SRAM unit, a SRAM memory, a processing circuit chip, and an electronic device.
  • the technical solutions provided in the embodiments of the present application are applicable to a scenario where an SRAM memory is accessed to read data or store data, such as an access to the SRAM during a neural network calculation process.
  • a system on chip SoC
  • the SoC includes a core 201, an accelerator array 202, a cache 203, an input circuit 204, and an output circuit 205. .
  • the kernel 201 is responsible for global task scheduling and management during the operation of the neural network; the accelerator array 202 is responsible for performing large-scale neural network calculations according to the scheduling of the kernel 201; and the cache 203 is responsible for temporarily storing the neural network
  • the data used in the calculation is realized by SRAM; the input circuit 204 is used to obtain data to be processed from the outside; the output circuit 205 is used to output the calculation result obtained by the accelerator array 202 to other external units, Such as external storage.
  • Logic level The voltage level in digital circuits is expressed by logic levels, including high level and low level. The high level is represented by “1” and the low level is represented by “0". Digital circuits formed by different components have different logic levels corresponding to voltage.
  • a transistor is a semiconductor device capable of controlling output current based on an input voltage, and includes a bipolar transistor (BJT) and a field effect transistor (FET).
  • BJT bipolar transistor
  • FET field effect transistor
  • Word lines Each memory cell in the memory array shares electrical connections with other cells in rows and columns.
  • the horizontal line is called a "word line”
  • the data in the vertical direction flows into and out of the memory cell.
  • the connection is called a "bit line”.
  • An embodiment of the present application provides a SRAM unit, where the SRAM unit is located in a SRAM memory, and the SRAM memory includes a SRAM memory array composed of a plurality of the SRAM units, and the SRAM memory can be based on the SRAM memory array.
  • a corresponding scheme is used to read the data stored in the SRAM cell to reduce the power consumption of the SRAM memory in the process of reading data.
  • the SRAM cell 300 includes a memory circuit 301, a write circuit 302, and a read circuit 303. among them,
  • the storage circuit 301 is connected to the writing circuit 302 and the reading circuit 303, respectively, for storing data; wherein the data is the first data or the second data, and the first data is powered by high voltage.
  • Flat indicates that the second data is represented by a low level.
  • the writing circuit 302 is also connected to a writing line and a writing bit line, and is used to write data into the storage circuit 301.
  • the readout circuit 303 is further connected to a read enable signal terminal and a read bit line, and is configured to, when the SRAM cell 300 in the column of the SRAM storage array, stores the first When the number is greater than the second number of the SRAM cell storing the second data, the read bit line is a read enable signal on the read enable signal terminal after the SRAM memory receives a read command Before being valid, it is charged to a high level; when the first number is less than the second number, the read bit line is valid after the read enable signal is received after the SRAM memory receives a read command Previously, it was discharged to a low level.
  • the readout circuit 303 is configured to make the data on the read bit line the data stored in the storage circuit 301 after the read enable signal is valid.
  • the read bit line is reset. Charged to high level or discharged to low level.
  • the readout circuit 303 includes a first pull-up transistor P1, a first pull-down transistor N1, a first read transfer transistor TR1, and a second read transfer transistor TR2, as shown in FIG. 4a.
  • the gate of the first pull-up transistor P1 is connected to the gate of the first pull-down transistor N1 and the storage circuit 301, and the source of the first pull-up transistor P1 is connected to the second pull-up.
  • the drain of the transistor P2 is connected.
  • the drain of the first pull-up transistor P1 is connected to the drain of the first pull-down transistor N1, the source of the first read transfer transistor TR1, and the second read transfer.
  • the drain of the transistor TR2 is connected.
  • the source of the first pull-down transistor N1 is connected to the drain of the second pull-down transistor N2.
  • the source of the second pull-down transistor N2 is grounded.
  • the source is connected to the power source, and the gate of the second pull-up transistor P2 and the gate of the second pull-down transistor N2 are used to receive the first read control signal MODE1 or the second read control signal MODE2;
  • the drain of the first read transfer transistor TR1 is connected to the source of the second read transfer transistor TR2 and the read bit line RBL, and the gate of the first read transfer transistor TR1 is connected to a first read enable signal.
  • the gate of the second read transfer transistor TR2 is connected to the first
  • the second read enable signal terminal is connected, and the read enable signal terminal includes the first read enable signal terminal and the second read enable signal terminal.
  • the second pull-up transistor P2 When the gate of the second pull-up transistor P2 and the gate of the second pull-down transistor N2 receive the first read control signal MODE1, the second pull-up transistor P2 is in an off state.
  • the second pull-down transistor N2 is in an on state; when the gate of the second pull-up transistor P2 and the gate of the second pull-down transistor N2 receive the second read control signal MODE2, the second pull-up transistor N2 is turned on.
  • the pull-down transistor P2 is in an on state, and the second pull-down transistor N2 is in an off-state; when the first read enable signal RE on the first read enable signal terminal is valid, and the second read enable signal Second read enable signal When valid, the first read transmission transistor TR1 and the second read transmission transistor TR2 are both in an on state, and the read enable signal includes the first read enable signal RE and the second read enable. signal
  • the second read enable signal Is the inverted signal of the first read enable signal RE.
  • the first read enable signal RE and the second read enable signal Are two signals, the second read enable signal An inverted signal of the first read enable signal.
  • the first pull-up transistor P1, the second pull-up transistor P2, and the first read transfer transistor TR1 are P-channel field effect transistors; the first pull-down transistor N1, and the second pull-down transistor The transistor N2 and the second read transfer transistor TR2 are N-channel field effect transistors.
  • the first pull-up transistor P1, the second pull-up transistor P2, and the first read transfer transistor TR1 use a P-channel metal-oxide semiconductor field-effect transistor (metal-oxide-semiconductor field-effect Transistor (MOSFET), that is, a PMOS transistor, the first pull-down transistor N1, the second pull-down transistor N2, and the second read transfer transistor TR2 are NMOS transistors.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • the functions of the first read transmission transistor TR1 and the second read transmission transistor TR2 may also be implemented by a third read transmission transistor TR3, as shown in FIG. 4b.
  • the gate of the first pull-up transistor P1 is connected to the gate of the first pull-down transistor N1 and the storage circuit 301, and the source of the first pull-up transistor P1 is connected to the second pull-up transistor P2.
  • the drain of the first pull-up transistor P1 is connected to the drain of the first pull-down transistor N1 and the source of the third read transfer transistor TR3, respectively.
  • the first pull-down transistor A source of N1 is connected to a drain of a second pull-down transistor N2, a source of the second pull-down transistor N2 is grounded, a source of the second pull-up transistor P2 is connected to a power source, and the second pull-up transistor P2 And a gate of the second pull-down transistor N2 is configured to receive the first read control signal MODE1 or the second read control signal MODE2;
  • the second pull-up transistor P2 When the gate of the second pull-up transistor P2 and the gate of the second pull-down transistor N2 receive the first read control signal MODE1, the second pull-up transistor P2 is in an off state.
  • the second pull-down transistor N2 is in an on state; when the gate of the second pull-up transistor P2 and the gate of the second pull-down transistor N2 receive the second read control signal MODE2, the second pull-up transistor N2 is turned on.
  • the pull-down transistor P2 is in an on state, and the second pull-down transistor N2 is in an off state;
  • a drain of the third read transmission transistor TR3 is connected to the read bit line RBL, and a gate of the third read transmission transistor TR3 is connected to the read enable signal terminal; when the read enable signal terminal is connected to When the read enable signal is valid, the third read transfer transistor TR3 is in an on state.
  • the third read transfer transistor TR3 may be a P-channel transistor or an N-channel transistor.
  • the storage unit 301 includes a third pull-up transistor P3, a fourth pull-up transistor P4, a third pull-down transistor N3, and a fourth pull-down transistor N4, as shown in FIG. 5.
  • the sources of the third pull-up transistor P3 and the fourth pull-up transistor P4 are both connected to a power source; the gates of the third pull-up transistor P3 and the gate of the third pull-down transistor N3 are respectively connected to a power source.
  • the drain of the fourth pull-up transistor P4, the drain of the fourth pull-down transistor N4, the readout circuit 303, and the write circuit 302 are connected; the gate of the fourth pull-up transistor P4 Connected to the gate of the fourth pull-down transistor N4, the drain of the third pull-up transistor P3, the drain of the third pull-down transistor N3, and the writing circuit 302, respectively; the third pull-down transistor
  • the source of N3 and the source of the fourth pull-down transistor N4 are both grounded. That is, the third pull-up transistor P3, the fourth pull-up transistor P4, the third pull-down transistor N3, and the fourth pull-down transistor N4 constitute two cross-coupled inverters.
  • the third pull-up transistor P3 and the fourth pull-up transistor P4 are P-channel field effect transistors; the third pull-down transistor N3 and the fourth pull-down transistor N4 are N-channel field effect transistors.
  • the third pull-up transistor P3 and the fourth pull-up transistor P4 are PMOS tubes, and the third pull-down transistor N3 and the fourth pull-down transistor N4 are NMOS tubes.
  • the writing circuit 302 includes a first write transfer transistor TW1 and a second write transfer transistor TW2, as shown in FIG. 6. among them.
  • a source of the first write transfer transistor TW1 is connected to a first write bit line WBL
  • a gate of the first write transfer transistor TW1 is connected to a write line WL
  • a drain of the first write transfer transistor TW1 is respectively connected to The drain of the third pull-up transistor P3 and the gate of the fourth pull-up transistor P4 are connected; the source of the second write transfer transistor TW2 and the drain of the fourth pull-up transistor N4 and
  • the gate of the third pull-up transistor P3 is connected, the drain of the second write transmission transistor TW2 is connected to the second write bit line WBLB, and the gate of the second write transmission transistor TW2 is connected to the writing line WL.
  • the drain of the second write transfer transistor TW2 is respectively connected to the source of the fourth pull-up transistor N4 and the gate of the third pull-up transistor P3;
  • the write bit line includes the first A write bit line and the second write bit line; when the write circuit 302 writes data to the storage circuit 301, the first write transfer transistor TW1 and the second write transfer transistor TW2 are both in a conductive state In the on state, the first write bit line is inverted from the second write bit line.
  • first write transfer transistor TW1 and the second write transfer transistor TW2 are both N-channel field effect transistors.
  • first write transfer transistor TW1 and the second write transfer transistor TW2 are both NMOS transistors.
  • the SRAM cell 300 may implement the read bit line through a fifth pull-up transistor P5, a fifth pull-down transistor N5, a first-choice switch Q1, and a second-choice switch Q2. Charging and discharging of RBL.
  • a source of the fifth pull-up transistor P5 is connected to a power source, and a gate of the fifth pull-up transistor P5 is connected to an output terminal of the first or second alternative switch Q1.
  • the drain of the five pull-up transistors P5 is connected to one end of a read bit line corresponding to a column of SRAM cells connected to the read control circuit 804 in the SRAM memory array.
  • the first input terminal of the first two alternative switch Q1 is connected to The power source VCC is connected, and the second input terminal of the first alternative switch Q1 is used to input the inverted signal of the precharge signal.
  • the control terminal of the first two alternative switch is used to input the first read control signal MODE1 or the second read control signal MODE2; the drain of the fifth pull-down transistor N5 is connected to the read bit line RBL
  • the gate of the fifth pull-down transistor N5 is connected to the output of the second alternative Q2 switch, the source of the fifth pull-down transistor N5 is grounded, and the first of the second alternative Q2
  • An input terminal is used to input the precharging signal PRECHARGE, a second input terminal of the second alternative switch Q2 is grounded, and a control terminal of the second alternative switch Q2 is used to input the first read control signal MODE1 or the second read control signal MODE2.
  • the fifth pull-up transistor is a P-channel field effect transistor
  • the fifth pull-down transistor is an N-channel field effect transistor.
  • the precharging signal PRECHARGE is active at a high level.
  • the first read control signal MODE1 is input to the control terminal of the first alternative switch Q1 and the control end of the second alternative switch Q2, the inverse signal of the precharge signal PRECHARGE After being valid and before the read enable signal is valid, the precharge signal PRECHARGE signal is high level, and the precharge signal PRECHARGE signal is an inverted signal Low level, the pre-charge signal is the inverted signal of the PRECHARGE signal
  • the first read control signal MODE1 turns on the fifth pull-up transistor P5, the precharge signal PRECHARGE signal and the first read control signal MODE1 turns off the fifth pull-down transistor N5, turning off all the The read bit line RBL is charged to a high level.
  • the precharge signal PRECHARGE signal changes from a high level to a low level, so that the fifth pull-up transistor P5 is turned off.
  • the control terminal of the first alternative switch Q1 and the control terminal of the second alternative switch Q2 input the second read control signal MODE2
  • the read enable Before the signal is valid the precharge signal PRECHARGE signal is at a high level, and the precharge signal PRECHARGE signal is an inverted signal Low level, the reverse signal of the precharge signal PRECHARGE signal
  • the second read control signal MODE2 turns off the fifth pull-up transistor P5, the fifth pull-down transistor N5 is turned on, and the read bit line RBL is brought to a low level.
  • the precharging signal PRECHARGE signal changes from a high level to a low level, so that the fifth pull-down transistor N5 is turned off.
  • the storage unit 301 has a structure as shown in FIG. 5, and when the write circuit 302 has a structure as shown in FIG. 6, the read
  • the pre-charging and discharging of the bit line RBL is implemented by the fifth pull-up transistor P5, the fifth pull-down transistor N5, the first alternative switch Q1, and the second alternative switch Q2 in FIG. 7a.
  • the SRAM cell 300 has a structure as shown in FIG. 7b, the working principle of the SRAM cell 300 will be described in detail.
  • the second pull-up transistor P2 is in an off state, and the second pull-down transistor N2 is in an on state.
  • the AND charging signal PRECHARGE After the AND charging signal PRECHARGE is valid, the first read enable signal RE and the second read enable Energy signal Before being effective, the fifth pull-up transistor P5 is in an on state, the fifth pull-down transistor N4 is in an off state, and the read bit line RBL is charged to a high level.
  • the first read enable signal RE and the second read enable signal When valid, that is, when a read operation is performed on the SRAM cell 300, the first read enable signal RE is high and the second read enable signal The first read transfer transistor TR1 and the second read transfer transistor TR2 are turned on.
  • the second pull-up transistor P2 is in an on state, and the second pull-down transistor N2 is in an off state.
  • the fifth pull-up transistor P5 is in an off state
  • the fifth pull-down transistor N4 is in an on state
  • the read bit line RBL is discharged to a low level.
  • the first read enable signal RE and the second read enable signal When valid, that is, when performing a read operation on the SRAM cell 300, the first read enable signal RE is high, the second read enable signal is low, and the first read transfer transistor TR1 And the second read transfer transistor TR2 is turned on.
  • the first pull-up transistor P1 is turned off, and the read bit line RBL is kept at a low level, indicating that “0” is read out.
  • the SRAM cell The read bit line connected to 300 is precharged to a high level before the read circuit 303 reads the data stored in the storage circuit 301, so that the read circuit 301 reads the first data next time Charging the read bit line RBL does not consume energy; when the number of SRAM cells storing the first data in the column where the SRAM cell 300 is located is less than the number of SRAM cells storing the second data The read bit line is discharged to a low level before the read circuit 303 reads the data stored in the storage circuit 301, so that the read circuit 301 reads the second data next time.
  • the SRAM memory where the SRAM unit 300 is located can adjust the working structure of the SRAM memory according to the number of first data and the number of second data stored in a column of SRAM cells in the SRAM memory array to avoid as much as possible
  • the energy consumed by charging the read bit lines connected to the SRAM cell 300 thereby reducing the power consumption of the SRAM memory, especially in the scenario where there are many read operations on the SRAM memory In a neural network scenario, the power consumption of the SRAM memory can be significantly reduced.
  • the present application further provides a SRAM memory.
  • the SRAM memory 800 includes a plurality of the SRAM cells 300, as shown in FIG. 8.
  • the plurality of SRAM cells 300 are connected through a plurality of writing lines, a plurality of writing bit lines, and a plurality of reading bit lines to form an SRAM memory array.
  • each column of SRAM cells in the SRAM memory array composed of the plurality of SRAM cells 300 may share the second pull-up transistor P2 and the second pull-down transistor N2.
  • the SRAM memory 800 further includes N data statistics circuits 801, M ⁇ N read control signal storage circuits 802, and N multiplexers 803, where N is equal to that of the SRAM memory 800.
  • N is equal to that of the SRAM memory 800.
  • Data bit width, the N data statistics circuits 801 correspond to the multiplexers 803 one by one
  • the SRAM memory array includes M ⁇ N columns of the SRAM cells 300;
  • Each data statistics circuit 801 is connected to M of the read control signal storage circuits 802 through a corresponding multiplexer 803, and each of the M ⁇ N of the read control signal storage circuits 802 and A row of SRAM cells in the SRAM memory array is connected, as shown in FIG. 9.
  • the data statistics circuit 801 is configured to count the number of the first data and the number of the second data in the data to be written into the target SRAM cell, and the target SRAM cell is the data statistics circuit in the SRAM storage array.
  • the control signal MODE1 generates the second read control signal MODE2 for controlling the read bit line to discharge to a low level when the number of the first data is less than the number of the second data.
  • the read control signal storage circuit 802 connected to the target SRAM cell is configured to store the first read control signal MODE1 or the second read control signal MODE2; wherein the first read control signal is at a high level, so The second read control signal is at a low level.
  • the SRAM memory 800 further includes: M ⁇ N data statistics circuits 801 and M ⁇ N read control signal storage circuits 802, where N is equal to a data bit width, and the data bits Each bit in the wide corresponding data corresponds to M columns in the SRAM memory array, the SRAM memory array includes M ⁇ N columns of the SRAM cell 300, the M ⁇ N data statistics circuit 801, and the M ⁇ N columns
  • the SRAM cells 300 correspond one-to-one, and each of the data statistics circuits 801 is connected to a column of the SRAM cells through a read control signal storage circuit 802.
  • the data statistics circuit 801 is configured to count the number of the first data and the number of the second data in the data that needs to be written into the target SRAM cell, and the target SRAM cell is the one in the SRAM storage array.
  • a row of the SRAM cells connected to the data statistics circuit when the number of the first data is greater than the number of the second data, a first read for controlling the charge of the read bit line to a high level is generated
  • a control signal MODE1 when the number of the first data is less than the number of the second data, generating a second read control signal MODE2 for controlling the read bit line to discharge to a low level;
  • the read control signal storage circuit 802 connected to the target SRAM cell is configured to store the first read control signal MODE1 or the second read control signal MODE2; wherein the first read control signal is at a high level, so The second read control signal is at a low level.
  • the data statistics circuit 801 is further configured to generate the first read control signal MODE1 or the second read control signal MODE2 when the first number is equal to the second number.
  • the N data statistics circuits 801 may select a column corresponding to the column address in the SRAM memory array in the multiplexer 803 according to the column address of the SRAM memory array, and the statistics need to be written. The number of first data and second data in the data of the SRAM cells in the column.
  • the data statistics circuit 801 includes a counting circuit and a comparison circuit, and the counting circuit is configured to count a first number of the first data in the data that needs to be written in a target SRAM cell and the first data. A second number of two data, the comparison circuit is configured to compare the first number and the second number, and output the first number when the first number is greater than the second number A read control signal MODE1 outputs the second read control signal MODE2 when the first number is less than the second number.
  • the counting circuit is configured to count the first number of the first data in the data that needs to be written into the target SRAM cell, and is determined according to the first number and the data that needs to be written into the target SRAM cell.
  • a second number of second data the comparison circuit is configured to compare the first number with
  • L is the total number of data that needs to be written into the target SRAM cell (when the data bit width of the SRAM and the number of SRAM cells included are constant, the total number of data that needs to be written to the target SRAM cell Is known), when the first number is greater than When the first read control signal MODE1 is output, when the first number is less than When it is, the second read control signal MODE2 is output.
  • the counting circuit is configured to count a second number of the second data in the data to be written into the target SRAM cell
  • the comparison circuit is configured to compare the second number and the second number Compare when the second number is less than the When the first read control signal MODE1 is output, when the second number is greater than the When it is, the second read control signal MODE2 is output.
  • the SRAM 800 further includes M ⁇ N read control circuits 804, and each of the M ⁇ N read control circuits 804 is respectively connected to the SRAM memory array through a corresponding read bit line.
  • a row of the SRAM cells 300 is connected as shown in FIG. 10. among them,
  • the read control circuit 804 is configured to, after the SRAM memory 800 receives a read command, before the read enable signal of a column of SRAM cells connected to the read control circuit 804 is valid, the first read control Signal MODE1 and inverted signal of precharge signal Charge the read bit line corresponding to a column of SRAM cells connected to the read control circuit to a high level under
  • the read control circuit 804 is configured to, after the SRAM memory receives a read command, before the read enable signal of a column of SRAM cells connected to the read control circuit 804 is valid, the second read control signal Under the control of MODE2 and the precharge signal PRECHARGE, the read bit lines corresponding to a column of SRAM cells connected to the read control circuit are discharged to a low level.
  • the read control circuit 804 includes a fifth pull-up transistor P5, a fifth pull-down transistor N5, a first alternative switch Q1, and a second alternative switch Q2 shown in FIG. 7b.
  • a source of the fifth pull-up transistor P5 is connected to a power source
  • a gate of the fifth pull-up transistor P5 is connected to an output terminal of the first alternative Q1
  • the fifth pull-up transistor The drain of P5 is connected to one end of a read bit line corresponding to a column of SRAM cells connected to the read control circuit 804 in the SRAM memory array.
  • the first input of the first or second alternative switch Q1 is connected to the power source VCC.
  • the second input terminal of the first two alternative switch Q1 is used to input an inverted signal of the precharge signal.
  • a control terminal of the first two alternative switch is used to input the first read control signal MODE1 or the second read control signal MODE2; a drain of the fifth pull-down transistor N5 and a position in the SRAM memory array
  • the read bit line corresponding to a column of SRAM cells connected to the read control circuit 804 is connected.
  • the gate of the fifth pull-down transistor N5 is connected to the output terminal of the second alternative switch Q2.
  • the source is grounded, the first input terminal of the second alternative switch Q2 is used to input the precharge signal PRECHARGE, the second input terminal of the second alternative switch Q2 is grounded, and the second alternative A control terminal of a switch Q2 is used to input the first read control signal MODE1 or the second read control signal MODE2.
  • the SRAM memory 800 has a data statistics circuit 801, a read control signal storage circuit 802, and N multiplexers 803 as shown in FIG. 9, and a read control circuit 804 as shown in FIG. 10, the structure As shown in FIG. 11, the read control circuit 804 obtains the first read control signal MODE1 or the second read control signal MODE2 through a corresponding read control signal storage circuit 802.
  • the SRAM memory 800 provided by the implementation of this application is used to simulate the circuit using SMIC 65nm technology in a Spectre simulation environment, and a typical convolutional neural network is taken as an example to address the characteristics of the initial image and neuron access to the SRAM.
  • the memory 800 performs an average read power consumption evaluation.
  • the experimental results show that, for reading the original image, the SRAM cell 300 provided in the embodiment of the present application saves an average of 64% of energy compared to the existing 6T-SRAM cell and 46% of energy compared to the 8T-SRAM cell.
  • the savings can reach 87% and 86%, respectively; for the reading of neuron data, the average saving of 67% compared to 6T-SRAM cells, and an average saving of 8T-SRAM cells 53% energy.
  • the SRAM unit 300 processes the AlexNet neural network, it can save 73% of energy compared to 6T-SRAM unit, as shown in Table 1, and can save 67% of energy compared to 8T-SRAM unit, as shown in Table 2. .
  • the SRAM memory 800 provided in the embodiment of the present application is a complete SRAM memory, and also has a known structure of the SRAM, such as a row address decoder, a column address decoder, a sense amplifier, and a buffer / driver. Circuits and the like, only the components involved in reducing the power consumption of the SRAM in the SRAM 800 are described here, and other components are not described in detail.
  • the SRAM memory 800 can adjust the working structure of the SRAM memory 800 according to the number of first data and the number of second data stored in a column of SRAM cells of the SRAM memory 800, so as to minimize
  • a SRAM cell in the SRAM memory 800 performs a read operation, the energy consumed by charging the read bit lines connected to the SRAM cell is reduced, thereby reducing the power consumption of the SRAM memory 800.
  • the connected power source, the power source connected to the source of the fifth pull-up transistor P5, and the power source connected to the first input terminal of the first or second alternative switch Q1 may be the same power source or different power sources.
  • the present application further provides a processing circuit chip.
  • the processing circuit chip 1200 includes the SRAM 800 and one or more processing circuits 1201.
  • the SRAM memory 800 is configured to store the one or more The data required for the multiple processing circuits 1201 to run is shown in FIG. 12.
  • the processing circuit 1201 may be a core (such as an ARM core), or an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. And so on to implement the hardware circuit.
  • the PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.
  • the processing circuit chip 1200 may be an application processor (AP) in a communication device (such as a mobile phone, a tablet computer, and a personal computer), or an accelerator in a neural network.
  • AP application processor
  • processing circuit chip 1200 provided in the embodiment of the present application may also have other structures that a known processor has, such as an input / output interface.
  • the SRAM 800 in the processing circuit chip 1200 can adjust each of the SRAM memory 800 according to the number of first data and the number of second data stored in each column of SRAM cells in the SRAM memory 800.
  • the working structure of a row of SRAM cells is to avoid as much as possible the energy consumed by charging the read bit lines connected to the SRAM cells when performing read operations on the SRAM cells, so as to reduce the power consumption of the SRAM memory, thereby improving the The performance (such as processing speed) of the processing circuit chip 1200 is described.
  • the present application also provides an electronic device.
  • the electronic device includes a power source and the processing circuit chip 1200, wherein the power source is used to supply power to the processing circuit chip 1200.

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  • Static Random-Access Memory (AREA)

Abstract

一种静态随机存储器SRAM单元（300）以及相关装置，以降低访问SRAM存储器时SRAM的功耗。所述SRAM单元（300）位于SRAM存储器中，SRAM存储器包括由多个所述SRAM单元（300）构成的SRAM存储阵列，所述SRAM单元（300）包括：存储电路（301），分别与写入电路（302）和读出电路（303）连接，用于存储数据；写入电路（302），用于向存储电路（301）中写入数据；读出电路（303），用于在读使能信号有效后使得SRAM单元（300）连接的读位线上的数据为存储电路（301）中存储的数据，其中，当SRAM单元（300）所在的列中存储第一数据的SRAM单元（300）的第一个数大于存储第二数据的SRAM单元（300）的第二个数时，读位线被预充电到高电平；当第一个数小于第二个数时，读位线被预放电到低电平。

Description

一种静态随机存储器SRAM单元以及相关装置
本申请要求于2018年8月31日提交中国专利局、申请号为201811014610.1、申请名称为“一种静态随机存储器SRAM单元以及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种静态随机存储器SRAM单元以及相关装置。
背景技术
静态随机存储器(static random access memory，SRAM)是一种具有静止存取功能的存储器件，不需要刷新电路即能保存其内部存储的数据，广泛用于数字与各种电子电路产品设计中。对SRAM进行读/写操作时，需要对SRAM的位线进行充电和放电，因此，频繁对SRAM进行读/写操作，会导致SRAM的功耗较大，进而限制了需要频繁访问SRAM的处理器的处理速度。
以SRAM中的存储单元为传统的6T-SRAM单元读取数据为例，如图1所示，6T-SRAM单元包括6个晶体管，分别为晶体管M1～M6。当6T-SRAM单元中存储的数据为Q＝0(即低电平)，QB＝1(即高电平)时，对6T-SRAM单元进行读操作时，两条差分位线BL和BLB预先充电到高电平，即电源电压VDD，晶体管M1和晶体管M2导通，位线BL被晶体管M1、M3下拉变为低电平，而位线BLB保持高电平，读出“0”；当6T-SRAM单元中存储的数据为Q＝1，QB＝0时，对6T-SRAM单元进行读操作时，两条差分位线BL和BLB预先充电到VDD，晶体管M1和晶体管M2导通，位线BLB被晶体管M2、M4下拉变为低电平，而位线BL保持高电平，读出“1”，即在对SRM进行读操作时，总有一条位线的电平下降并在预充电时消耗电能。
发明内容
本申请提供了一种静态随机存储器SRAM单元以及相关装置，以降低访问静态随机存储SRAM时SRAM的功耗。
第一方面，本申请提供了一种SRAM单元，所述SRAM单元位于SRAM存储器中，所述SRAM存储器包括由多个所述SRAM单元构成的SRAM存储阵列。具体地，所述SRAM单元包括：存储电路、写入电路以及读出电路。其中，所述存储电路，分别与所述写入电路以及所述读出电路连接，用于存储数据，所述数据为第一数据或第二数据，所述第一数据用高电平表示，所述第二数据用低电平表示；所述写入电路，还与写字线以及写位线连接，用于向所述存储电路中写入数据；所述读出电路，还与读使能信号端以及读位线连接，其中，当所述SRAM存储阵列中所述SRAM单元所在的列中存储所述第一数据的SRAM单元的第一个数大于存储所述第二数据的SRAM单元的第二个数时，所述读位线在所述SRAM存储器收到读命令之后、在所述读使能信号端上的读使能信号有效之前，被充电到高电平；当所述第一个数小于存储所述第二个数时，所述读位线在所述SRAM存 储器收到读命令之后、在所述读使能信号有效之前，被放电到低电平，所述读出电路用于在所述读使能信号有效后使得所述读位线上的数据为所述存储电路中存储的数据。
采用上述方案，当所述SRAM单元所在的列中存储所述第一数据的SRAM单元的个数大于存储所述第二数据的SRAM单元的个数时，所述SRAM单元连接的读位线被预先充电到高电平，使得所述读出电路下次读出所述第一数据时，对所述读位线充电不消耗能量；当所述SRAM单元所在的列中存储所述第一数据的SRAM单元的个数小于存储所述第二数据的SRAM单元的个数时，所述读位线被预先放电到低电平，使得所述读出电路下次读出所述第二数据时不消耗能量。也就是说，所述SRAM存储器能够根据SRAM存储器的一列SRAM单元中存储的第一数据的个数以及第二数据的个数，调整所述SRAM存储器的工作结构，以尽量避免对所述SRAM存储器中的SRAM单元进行读操作时，对所述SRAM单元连接的读位线进行充电消耗的能量，进而降低所述SRAM存储器的功耗。
一个可能的实施方式中，所述读出电路可以通过但不限于以下两种方式实现：
方式一、所述读出电路包括第一上拉晶体管、第一下拉晶体管、第一读传输晶体管和第二读传输晶体管，所述第一上拉晶体管的栅极分别与所述第一下拉晶体管的栅极以及所述存电路连接，所述第一上拉晶体管的源极与第二上拉晶体管的漏极连接，所述第一上拉晶体管的漏极分别与所述第一下拉晶体管的漏极、所述第一读传输晶体管的源极以及所述第二读传输晶体管的漏极连接，所述第一下拉晶体管的源极与第二下拉晶体管的漏极连接，所述第二下拉晶体管的源极接地，所述第二上拉晶体管的源极与电源连接，所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极用于接收所述第一读控制信号或所述第二读控制信号，所述第一读传输晶体管的漏极分别与所述第二读传输晶体管的源极以及所述读位线连接，所述第一读传输晶体管的栅极与第一读使能信号端连接，所述第二读传输晶体管的栅极与第二读使能信号端连接，所述读使能信号端包括所述第一读使能信号端以及所述第二读使能信号端。
其中，当所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极接收到所述第一读控制信号时，所述第二上拉晶体管处于关断状态，所述第二下拉晶体管处于导通状态；当所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极接收到所述第二读控制信号时，所述第二上拉晶体管处于导通状态，所述第二下拉晶体管处于关断状态；当所述第一读使能信号端上的所述第一读使能信号有效，且所述第二读使能信号端上的所述第二读使能信号有效时，所述第一读传输晶体管以及所述第二读传输晶体管均处于导通状态，所述读使能信号包括所述第一读使能信号以及所述第二读使能信号，所述第二读使能信号是所述第一读使能信号的反相信号。
需要说明的是，所述第一读控制信号以及所述第二读控制信号为从同一个读控制信号端输入的读控制信号的两种不同电平，即所述第一读使能信号端以及所述第二读使能信号端为同一个输入端。所述第一读使能信号以及所述第二读使能信号为两个信号。
方式二、所述读出电路可以包括第一上拉晶体管、第一下拉晶体管、第一读传输晶体管和第二读传输晶体管，所述第一上拉晶体管的栅极分别与所述第一下拉晶体管的栅极以及所述存储电路连接，所述第一上拉晶体管的源极与第二上拉晶体管的漏极连接，所述第一上拉晶体管的漏极分别与所述第一下拉晶体管的漏极以及所述第三读传输晶体管的源极连接，所述第一下拉晶体管的源极与第二下拉晶体管的漏极连接，所述第二下拉晶体管的源极接地，所述第二上拉晶体管的源极与电源连接，所述第二上拉晶体管的栅极以及所 述第二下拉晶体管的栅极用于接收所述第一读控制信号或所述第二读控制信号，所述第三读传输晶体管的漏极与所述读位线连接，所述第三读传输晶体管的栅极与读使能信号端连接。
其中，当所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极接收到所述第一读控制信号时，所述第二上拉晶体管处于关断状态，所述第二下拉晶体管处于导通状态；当所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极接收到所述第二读控制信号时，所述第二上拉晶体管处于导通状态，所述第二下拉晶体管处于关断状态；当所述读使能信号端上的所述读使能信号有效时，所述第三读传输晶体管处于导通状态。
进一步地，述第一上拉晶体管、所述第二上拉晶体管以及所述第一读传输晶体管为P沟道场效应管；所述第一下拉晶体管、所述第二下拉晶体管和所述第二读传输晶体管为N沟道场效应管。
一个可能的实施方式中，所述存储电路包括第三上拉晶体管、第四上拉晶体管、第三下拉晶体管和第四下拉晶体管。其中，所述第三上拉晶体管以及所述第四上拉晶体管的源极均与电源连接；所述第三上拉晶体管的栅极分别与所述第三下拉晶体管的栅极、所述第四上拉晶体管的漏极、所述第四下拉晶体管的漏极、所述读出电路以及所述写入电路连接；所述第四上拉晶体管的栅极分别与所述第四下拉晶体管的栅极、所述第三上拉晶体管的漏极、所述第三下拉晶体管的漏极以及所述写入电路连接；所述第三下拉晶体管的源极以及所述第四下拉晶体管的源极均接地。
进一步地，所述第三上拉晶体管和所述第四上拉晶体管为P沟道场效应管；所述第三下拉晶体管和所述第四下拉晶体管为N沟道场效应管。
一个可能的实施方式中，所述写入电路包括第一写传输晶体管和第二写传输晶体管，所述第一写传输晶体管的源极与第一写位线连接，所述第一写传输晶体管的栅极与所述写字线连接，所述第一写传输晶体管的漏极分别与所述第三上拉晶体管的漏极以及所述第四上拉晶体管的栅极连接；所述第二写传输晶体管的源极分别与所述第四上拉晶体管的漏极以及所述第三上拉晶体管的栅极连接，所述第二写传输晶体管的源极与第二写位线连接，所述第二写传输晶体管的栅极与所述写字线连接。其中，所述写位线包括所述第一写位线以及所述第二写位线；当所述写入电路向所述存储电路写入数据时，所述第一写传输晶体管以及所述第二写传输晶体管均处于导通状态；所述第一写位线与所述第二写位线反相。
进一步地，所述第一写传输晶体管和所述第二写传输晶体管均为N沟道场效应管。
第二方面，本申请提供了一种SRAM存储器，所述SRAM存储器包括多个上述第一方面中任意一种SRAM单元。
采用上述方案，所述SRAM存储器能够根据SRAM存储器的一列SRAM单元中存储的第一数据的个数以及第二数据的个数，调整所述SRAM存储器的工作结构，以尽量减少对所述SRAM存储器中的SRAM单元进行读操作时，对所述SRAM单元连接的读位线进行充电消耗的能量，进而降低所述SRAM存储器的功耗。
一个可能的实施方式中，所述SRAM存储器还包括N个数据统计电路、N个多路选择器、以及M×N个读控制信号存储电路；其中，N等于数据位宽，所述N等于数据位宽，所述数据位宽对应的数据中每个比特对应SRAM存储阵列中的M列，所述N个数据统计电路与所述多路选择器一一对应，所述SRAM存储阵列包括M×N列所述SRAM单元；所述N个数据统计电路中的每个通过对应的多路选择器与M个所述读控制信号存储电路 连接，M×N个所述读控制信号存储电路中的每个分别与所述SRAM存储阵列中的一列SRAM单元连接。
所述数据统计电路，用于统计需要写入目标SRAM单元的数据中第一数据的个数以及第二数据的个数，所述目标SRAM单元为所述SRAM存储阵列中所述数据统计电路连接的一列所述SRAM单元；当所述第一数据的个数大于所述第二数据的个数时，产生用于控制所述读位线充电到高电平的第一读控制信号，当所述第一数据的个数小于所述第二数据的个数时，产生用于控制所述读位线放电到低电平的第二读控制信号；
所述目标SRAM单元连接的读控制信号存储电路，用于存储所述第一读控制信号或者所述第二读控制信号；其中，所述第一读控制信号为高电平，所述第二读控制信号为低电平。
一个可能的实施方式中，所述SRAM存储器还包括：M×N个数据统计电路以及M×N个读控制信号存储电路，其中，所述N等于数据位宽，所述数据位宽对应的数据中每个比特对应SRAM存储阵列中的M列，所述SRAM存储阵列包括M×N列所述SRAM单元，所述M×N个数据统计电路与所述M×N列所述SRAM单元以及M×N个所述数据统计电路一一对应，每个所述数据统计电路通过一个所述读控制信号存储电路与一列所述SRAM单元相连。
所述数据统计电路，用于统计需要写入目标SRAM单元的数据中所述第一数据的个数以及所述第二数据的个数，所述目标SRAM单元为所述SRAM存储阵列中所述数据统计电路连接的一列所述SRAM单元；当所述第一数据的个数大于所述第二数据的个数时，产生用于控制所述读位线充电到高电平的第一读控制信号，当所述第一数据的个数小于所述第二数据的个数时，产生用于控制所述读位线放电到低电平的第二读控制信号；
所述目标SRAM单元连接的读控制信号存储电路，用于存储所述第一读控制信号或者所述第二读控制信号；其中，所述第一读控制信号为高电平，所述第二读控制信号为低电平。
一个可能的实施方式中，所述数据统计电路包括计数电路以及比较电路。所述计数电路用于统计需要写入目标SRAM单元的数据中所述第一数据的第一个数以及所述第二数据的第二个数，所述比较电路用于对所述第一个数以及所述第二个数进行比较，当所述第一个数大于所述第二个数时输出所述第一读控制信号，当所述第一个数小于所述第二个数时输出所述第二读控制信号。
或者，所述计数电路用于统计需要写入目标SRAM单元的数据中所述第一数据的第一个数，所述比较电路用于对所述第一个数以及
Figure PCTCN2019099132-appb-000001
进行比较，L为需要写入目标SRAM单元的数据的总个数(当所述SRAM的数据位宽以及包括的所述SRAM单元的个数一定时，需要写入所述目标SRAM单元的数据总数是已知的)，当所述第一个数大于所述
Figure PCTCN2019099132-appb-000002
时输出所述第一读控制信号，当所述第一个数小于所述
Figure PCTCN2019099132-appb-000003
时输出所述第二读控制信号。
或者，所述计数电路用于统计需要写入目标SRAM单元的数据中所述第二数据的第二个数，所述比较电路用于对所述第一个数以及所述
Figure PCTCN2019099132-appb-000004
进行比较，当所述第二个数小于所述
Figure PCTCN2019099132-appb-000005
数时输出所述第一读控制信号，当所述第二个数大于所述
Figure PCTCN2019099132-appb-000006
时输出所述第二读控制信 号。
进一步地，所述读控制信号存储电路为锁存器。
一个可能的实施方式中，所述数据统计电路还用于：当所述第一个数等于所述第二个数时，产生所述第一读控制信号或者所述第二读控制信号。
一个可能的实施方式中，所述SRAM存储器还包括M×N个读控制电路，所述M×N个读控制电路每个分别通过对应的读位线与所述SRAM存储阵列中的一列所述SRAM单元连接。
其中，所述读控制电路，用于在所述SRAM存储器收到读命令之后、在所述读控制电路连接的一列SRAM单元的所述读使能信号有效之前，在所述第一读控制信号以及预充电信号的反相信号的控制下，将所述读控制电路连接的一列SRAM单元对应的读位线充电到高电平；或者，所述读控制电路，用于在所述SRAM存储器收到读命令之后、在所述读控制电路连接的一列SRAM单元的所述读使能信号有效之前，在所述第二读控制信号以及预充电信号的控制下，将所述读控制电路连接的一列SRAM单元对应的读位线放电到低电平。
一个可能的实施方式中，所述读控制电路包括第五上拉晶体管、第五下拉晶体管、第一二选一开关和第二二选一开关；
所述第五上拉晶体管的源极与电源连接，所述第五上拉晶体管的栅极与所述第一二选一开关的输出端连接，所述第五上拉晶体管的漏极与所述SRAM存储阵列中所述读控制电路连接的一列SRAM单元对应的读位线的一端连接，所述第一二选一开关的第一输入端与电源连接，所述第一二选一开关的第二输入端用于输入所述预充电信号的反相信号，所述第一二选一开关的控制端用于输入所述第一读控制信号或所述第二读控制信号；所述第五下拉晶体管的漏极与所述SRAM存储阵列中所述读控制电路连接的一列SRAM单元对应的读位线的另一端连接，所述第五下拉晶体管的栅极与所述第二二选一开关的输出端连接，所述第五下拉晶体管的源极接地，所述第二二选一开关的第一输入端用于输入所述预充电信号，所述第二二选一开关的第二输入端接地，所述第二二选一开关的控制端用于输入所述第一读控制信号或所述第二读控制信号。
其中，当所述第一二选一开关的控制端以及所述第二二选一开关的控制端输入所述第一读控制信号，且所述预充电信号的反相信号有效时，所述第一二选一开关的输出端与所述第一二选一开关的第一输入端连通，所述第五上拉晶体管处于导通状态，所述第二二选一开关的输出端与所述第二二选一开关的第一输入端连通，所述第五下拉晶体管处于关断状态；当所述第一二选一开关的控制端以及所述第二二选一开关的控制端输入所述第二读控制信号，且所述预充电信号有效时，所述第一二选一开关的输出端与所述第一二选一开关的第二输入端连通，所述第五上拉晶体管处于关断状态，所述第二二选一开关的输出端与所述第二二选一开关的第二输入端连通，所述第五下拉晶体管处于导通状态。
进一步地，所述第五上拉晶体管为P沟道场效应管，所述第五下拉晶体管为N沟道场效应管。
第三方面，本申请还提供了一种处理电路芯片，所述处理电路芯片包括上述第二方面中任意一种SRAM存储器以及一个或多个处理电路，所述SRAM存储器用于存储所述一个或多个处理电路运行时所需的数据。
采用上述方案，所述处理电路芯片中包含的SRAM处理器能够根据所述SRAM存储 器中每一列SRAM单元中存储的第一数据的个数以及第二数据的个数，调整所述SRAM处理器中每一列SRAM单元的工作结构，以尽量避免对所述SRAM单元进行读操作时，对所述SRAM单元连接的读位线进行充电消耗的能量，以降低所述SRAM存储器的功耗，进而能够提高所述处理电路芯片的性能(如处理速度)。
第四方面，本申请还提供了一种电子设备，所述电子设备包括电源以及上述第三方面所述的处理电路芯片，其中，所述电源用于给所述处理电路芯片供电。
附图说明
图1为现有技术中6T-SRAM单元的结构示意图；
图2为本申请实施例提供的一种应用于神经网络的片上系统的结构示意图；
图3为本申请实施例提供的一种SRAM单元的结构示意图；
图4a为本申请实施例提供的一种SRAM单元中读出电路的结构示意图；
图4b为本申请实施例提供的另一种SRAM单元中读出电路的结构示意图；
图5为本申请实施例提供的SRAM单元中存储电路的结构示意图；
图6为本申请实施例提供的SRAM单元中写入电路的结构示意图；
图7a为本申请实施例提供的一种SRAM单元中为读位线充放电的电路结构示意图；
图7b为本申请实施例提供的一种SRAM单元的工作时序图；
图8为本申请实施例提供的一种SRAM的结构示意图；
图9为本申请实施例提供的另一种SRAM的结构示意图；
图10为本申请实施例提供的又一种SRAM的结构示意图；
图11为本申请实施例提供的一种SRAM的具体结构示意图；
图12为本申请实施例提供的一种处理电路芯片的结构示意图。
具体实施方式
随着人工智能的发展，机器学习(machine learning，ML)相关算法及理论广泛应用到各个领域，并取得了令人惊讶的效果。在众多机器学习算法中，神经网络算法模仿生物神经系统的行为特征对原始信息进行处理，并提取出高维特征，在模式识别领域受到了广泛的关注。其中，卷积神经网络(convolutional neural network，CNN)在分类与识别领域表现出突出的优势，如Szegedy等提出的ResNet深度卷积神经网络在同样的数据集上仅仅只有3.57％的错误率，这已经大大超过了人类进行识别的平均水平。
为了拟合出高性能的映射关系，神经网络往往采用极深的网络规模并进行大量的计算，随着近些年网络深度的增加，神经网络中涉及的参数以及计算量也成倍增加，使得访问SRAM的能量消耗成为CNN处理器的瓶颈。尽管单次写操作消耗的能量大于单次读操作的消耗，但是在CNN的场景下对SRAM的写操作次数远少于对SRAM的读操作，以视视觉几何组(visual geometry group，VGG)16第一层卷积层为例，对SRAM的进行的写操作为15万次，而对SRAM的读操作达到了850万次，多达70％的能量消耗在SRAM的位线充放电过程中。
目前，降低SRAM在数据存取过程中的功耗的方法主要有两种：一是在算法层面缩减神经网络的规模，以减少数据存取和运算代价，然而算法层面的压缩将直接导致神经网络 性能降低。二是在硬件层面减少数据存取时的能耗，以减少运算过程中与SRAM的通信。但是这种硬件上的改进与神经网络的算法有较强的相关性，CNN卷积核的大小、网络层数、以及每层神经元数量都将对应不同的电路映射结构，通用性较差。
为了解决上述访问SRAM时SRAM的功耗较大的问题，本申请提出了一种SRAM单元、SRAM存储器、处理电路芯片以及电子设备。
本申请实施例提供的技术方案适用于访问SRAM存储器以读取数据或存储数据的场景，例如神经网络计算过程中对SRAM的访问。以图2所示的一种应用于神经网络的片上系统(system on a chip，SoC)为例，所述SoC包括内核(core)201、加速器阵列202、缓存203、输入电路204以及输出电路205。其中，所述内核201负责神经网络运行过程中全局的任务调度和管理；所述加速器阵列202负责根据所述内核201的调度，执行大规模的神经网络计算；所述缓存203负责暂存神经网络计算中需要用到的数据，采用SRAM实现；所述输入电路204用于从外部获取待处理的数据；所述输出电路205用于将所述加速器阵列202得到的计算结果输出到外部其它单元，如外部的存储器。
以下，对本申请实施例涉及部分用语进行解释说明，以便于本领域技术人员理解。
(1)逻辑电平，数字电路中电压的高低用逻辑电平来表示，包括高电平和低电平两种，其中，高电平用“1”表示，低电平用“0”表示。不同的元器件形成的数字电路，电压对应的逻辑电平也不同。
(2)上拉，指将信号钳位在高电平；下拉，指将信号钳位在低电平。
(3)晶体管，是一种半导体器件，能够基于输入电压控制输出电流，包括双极性晶体管(bipolar transistor，BJT)和场效应晶体管(field effect transistor，FET)。
(4)字线，存储阵列中的每个存储单元都与其他单元在行和列上共享电学连接，其中水平方向的连线称为“字线”，而垂直方向的数据流入和流出存储单元的连线称为“位线”。
(5)多个，是指两个或两个以上。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
下面结合说明书附图对本申请各个实施例进行详细描述。需要说明的是，本申请实施例的展示顺序仅代表实施例的先后顺序，并不代表实施例所提供的技术方案的优劣。
本申请实施例提供了一种SRAM单元，所述SRAM单元位于SRAM存储器中，所述SRAM存储器包括由多个所述SRAM单元构成的SRAM存储阵列，所述SRAM存储器能够根据所述SRAM存储阵列中每一列所述SRAM单元存储的数据的特征，采用相应的方案读取所述SRAM单元中存储的数据，以减少所述SRAM存储器在读取数据过程中的功耗。如图3所示，所述SRAM单元300包括：存储电路301、写入电路302以及读出电路303。其中，
所述存储电路301，分别与所述写入电路302以及所述读出电路303连接，用于存储数据；其中，所述数据为第一数据或第二数据，所述第一数据用高电平表示，所述第二数据用低电平表示。
所述写入电路302，还与写字线以及写位线连接，用于向所述存储电路301中写入数据。
所述读出电路303，还与读使能信号端以及读位线连接，用于当所述SRAM存储阵列 中所述SRAM单元300所在的列中，存储所述第一数据的SRAM单元的第一个数大于存储所述第二数据的SRAM单元的第二个数时，所述读位线在所述SRAM存储器收到读命令之后、在所述读使能信号端上的读使能信号有效之前，被充电到高电平；当所述第一个数小于所述第二个数时，所述读位线在所述SRAM存储器收到读命令之后、在所述读使能信号有效之前，被放电到低电平。所述读出电路303，用于在所述读使能信号有效后使得所述读位线上的数据为所述存储电路301中存储的数据。
一个可能的实施方式中，当所述第一个数等于所述第二个数时，所述读位线在所述SRAM存储器收到读命令之后、在所述读使能信号有效之前，被充电到高电平或者被放电到低电平。
一个可能的实施方式中，所述读出电路303包括第一上拉晶体管P1、第一下拉晶体管N1、第一读传输晶体管TR1和第二读传输晶体管TR2，如图4a所示。
其中，所述第一上拉晶体管P1的栅极分别与所述第一下拉晶体管N1的栅极以及所述存储电路301连接，所述第一上拉晶体管P1的源极与第二上拉晶体管P2的漏极连接，所述第一上拉晶体管P1的漏极分别与所述第一下拉晶体管N1的漏极、所述第一读传输晶体管TR1的源极以及所述第二读传输晶体管TR2的漏极连接，所述第一下拉晶体管N1的源极与第二下拉晶体管N2的漏极连接，所述第二下拉晶体管N2的源极接地，所述第二上拉晶体管P2的源极与电源连接，所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极用于接收所述第一读控制信号MODE1或所述第二读控制信号MODE2；所述第一读传输晶体管TR1的漏极分别与所述第二读传输晶体管TR2的源极以及所述读位线RBL连接，所述第一读传输晶体管TR1的栅极与第一读使能信号端连接，所述第二读传输晶体管TR2的栅极与第二读使能信号端连接，所述读使能信号端包括所述第一读使能信号端以及所述第二读使能信号端。
当所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极接收到所述第一读控制信号MODE1时，所述第二上拉晶体管P2处于关断状态，所述第二下拉晶体管N2处于导通状态；当所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极接收到所述第二读控制信号MODE2时，所述第二上拉晶体管P2处于导通状态，所述第二下拉晶体管N2处于关断状态；当所述第一读使能信号端上的第一读使能信号RE有效，且所述第二读使能信号端上的第二读使能信号
Figure PCTCN2019099132-appb-000007
有效时，所述第一读传输晶体管TR1以及所述第二读传输晶体管TR2均处于导通状态，所述读使能信号包括所述第一读使能信号RE以及所述第二读使能信号
Figure PCTCN2019099132-appb-000008
所述第二读使能信号
Figure PCTCN2019099132-appb-000009
是所述第一读使能信号RE的反相信号。
需要说明的是，所述第一读控制信号MODE1以及所述第二读控制信号MODE2从同一个读控制信号端输入的读控制信号MODE的两种不同电平，即所述第一读控制信号端与所述第二读控制信号端为同一个信号输入端。所述第一读使能信号RE以及所述第二读使能信号
Figure PCTCN2019099132-appb-000010
为两个信号，所述第二读使能信号
Figure PCTCN2019099132-appb-000011
为所述第一读使能信号的反相信号。
进一步地，所述第一上拉晶体管P1、所述第二上拉晶体管P2以及所述第一读传输晶体管TR1为P沟道场效应管；所述第一下拉晶体管N1、所述第二下拉晶体管N2和所述第二读传输晶体管TR2为N沟道场效应管。通常情况下，所述第一上拉晶体管P1、所述第二上拉晶体管P2以及所述第一读传输晶体管TR1采用P沟道金属氧化物半导体场效应管(metal-oxide-semiconductor field-effect Transistor,MOSFET)，即PMOS管，所述第一下拉 晶体管N1、所述第二下拉晶体管N2和所述第二读传输晶体管TR2采用NMOS管。
在另一个可能的实施方式中，所述第一读传输晶体管TR1和所述第二读传输晶体管TR2的功能也可以由一个第三读传输晶体管TR3实现，如图4b所示。所述第一上拉晶体管P1的栅极分别与所述第一下拉晶体管N1的栅极以及所述存储电路301连接，所述第一上拉晶体管P1的源极与第二上拉晶体管P2的漏极连接，所述第一上拉晶体管P1的漏极分别与所述第一下拉晶体管N1的漏极以及所述第三读传输晶体管TR3的源极连接，所述第一下拉晶体管N1的源极与第二下拉晶体管N2的漏极连接，所述第二下拉晶体管N2的源极接地，所述第二上拉晶体管P2的源极与电源连接，所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极用于接收所述第一读控制信号MODE1或所述第二读控制信号MODE2；
当所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极接收到所述第一读控制信号MODE1时，所述第二上拉晶体管P2处于关断状态，所述第二下拉晶体管N2处于导通状态；当所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极接收到所述第二读控制信号MODE2时，所述第二上拉晶体管P2处于导通状态，所述第二下拉晶体管N2处于关断状态；
所述第三读传输晶体管TR3的漏极与所述读位线RBL连接，所述第三读传输晶体管TR3的栅极与所述读使能信号端连接；当所述读使能信号端上的读出使能信号有效时，所述第三读传输晶体管TR3处于导通状态。
进一步地，所述第三读传输晶体管TR3可以为P沟道晶体管，也可以为N沟道晶体管。
一个可能的实施方式中，所述存储单元301包括第三上拉晶体管P3、第四上拉晶体管P4、第三下拉晶体管N3和第四下拉晶体管N4，如图5所示。
其中，所述第三上拉晶体管P3以及所述第四上拉晶体管P4的源极均与电源连接；所述第三上拉晶体管P3的栅极分别与所述第三下拉晶体管N3的栅极、所述第四上拉晶体管P4的漏极、所述第四下拉晶体管N4的漏极、所述读出电路303以及所述写入电路302连接；所述第四上拉晶体管P4的栅极分别与所述第四下拉晶体管N4的栅极、所述第三上拉晶体管P3的漏极、所述第三下拉晶体管N3的漏极以及所述写入电路302连接；所述第三下拉晶体管N3的源极以及所述第四下拉晶体管N4的源极均接地。即所述第三上拉晶体管P3、所述第四上拉晶体管P4、所述第三下拉晶体管N3和所述第四下拉晶体管N4构成两个交叉耦合的反相器。
进一步地，所述第三上拉晶体管P3和所述第四上拉晶体管P4为P沟道场效应管；所述第三下拉晶体管N3和所述第四下拉晶体管N4为N沟道场效应管。通常情况下，所述第三上拉晶体管P3和所述第四上拉晶体管P4采用PMOS管，所述第三下拉晶体管N3和所述第四下拉晶体管N4采用NMOS管。
一个可能的实施方式中，当所述存储电路301具有如图5所示的结构时，所述写入电路302包括第一写传输晶体管TW1和第二写传输晶体管TW2，如图6所示。其中。所述第一写传输晶体管TW1的源极与第一写位线WBL连接，所述第一写传输晶体管TW1的栅极与写字线WL连接，所述第一写传输晶体管TW1的漏极分别与所述第三上拉晶体管P3的漏极以及所述第四上拉晶体管P4的栅极连接；所述第二写传输晶体管TW2的源极分别与所述第四上拉晶体管N4的漏极以及所述第三上拉晶体管P3的栅极连接，所述第二写 传输晶体管TW2的漏极与第二写位线WBLB连接，所述第二写传输晶体管TW2的栅极与所述写字线WL连接，所述第二写传输晶体管TW2的漏极分别与所述第四上拉晶体管N4的源极以及所述第三上拉晶体管P3的栅极连接；所述写位线包括所述第一写位线以及所述第二写位线；当所述写入电路302向所述存储电路301写入数据时，所述第一写传输晶体管TW1以及所述第二写传输晶体管TW2均处于导通状态，所述第一写位线与所述第二写位线反相。
进一步地，所述TW1第一写传输晶体管和所述第二写传输晶体管TW2均为N沟道场效应管。通常情况下，所述TW1第一写传输晶体管和所述第二写传输晶体管TW2均采用NMOS管。
一个可能的实施方式中，所述SRAM单元300可以通过第五上拉晶体管P5、第五下拉晶体管N5、第一二选一开关Q1和第二二选一开关Q2，实现对所述读位线RBL的充电和放电。如图7a所示，所述第五上拉晶体管P5的源极与电源连接，所述第五上拉晶体管P5的栅极与所述第一二选一开关Q1的输出端连接，所述第五上拉晶体管P5的漏极与所述SRAM存储阵列中所述读控制电路804连接的一列SRAM单元对应的读位线的一端连接，所述第一二选一开关Q1的第一输入端与电源VCC连接，所述第一二选一开关Q1的第二输入端用于输入所述预充电信号的反相信号
Figure PCTCN2019099132-appb-000012
所述第一二选一开关的控制端用于输入所述第一读控制信号MODE1或所述第二读控制信号MODE2；所述第五下拉晶体管N5的漏极与所述读位线RBL连接，所述第五下拉晶体管N5的栅极与所述第二二选一开关Q2的输出端连接，所述第五下拉晶体管N5的源极接地，所述第二二选一开关Q2的第一输入端用于输入所述预充电信号PRECHARGE，所述第二二选一开关Q2的第二输入端接地，所述第二二选一开关Q2的控制端用于输入所述第一读控制信号MODE1或所述第二读控制信号MODE2。
其中，当所述第一二选一开关Q1的控制端以及所述第二二选一开关Q2的控制端输入所述第一读控制信号MODE1，且所述预充电信号的反相信号
Figure PCTCN2019099132-appb-000013
有效时，所述第一二选一开关Q1的输出端与所述第一二选一开关Q1的第一输入端连通，所述第五上拉晶体管P5处于导通状态，所述第二二选一开关Q2的输出端与所述第二二选一开关Q2的第二输入端连通，所述第五下拉晶体管N5处于关断状态；当所述第一二选一开关Q1的控制端以及所述第二二选一开关Q2的控制端输入所述第二读控制信号MODE2，且所述预充电信号PRECHARGE有效时，所述第一二选一开关Q1的输出端与所述第一二选一开关Q1的第二输入端连通，所述第五上拉晶体管P5处于关断状态，所述第二二选一开关Q2的输出端与所述第二二选一开关Q2的第一输入端连通，所述第五下拉晶体管N5处于导通状态。
进一步地，所述第五上拉晶体管为P沟道场效应管，所述第五下拉晶体管为N沟道场效应管，此时所述预充电信号PRECHARGE高电平有效。当所述第一二选一开关Q1的控制端以及所述第二二选一开关Q2的控制端输入所述第一读控制信号MODE1，所述预充电信号PRECHARGE的反相信号
Figure PCTCN2019099132-appb-000014
有效之后、所述读使能信号有效之前，所述预充电信号PRECHARGE信号为高电平，所述预充电信号PRECHARGE信号的反相信号
Figure PCTCN2019099132-appb-000015
为低电平，所述预充电信号PRECHARGE信号的反相信号
Figure PCTCN2019099132-appb-000016
以及所述第一读控制信号MODE1使得所述第五上拉晶体管P5导通，所述预充电信号PRECHARGE信号以及所述第一读控制信号MODE1使得所述第五下拉晶体管N5关断，将所述读位线RBL充电到高电平，所述读位线RBL充电结束后，所述预充电信号 PRECHARGE信号从高电平变为低电平，使得所述第五上拉晶体管P5关断。当所述第一二选一开关Q1的控制端以及所述第二二选一开关Q2的控制端输入所述第二读控制信号MODE2，所述预充电信号PRECHARGE有效之后、所述读使能信号有效之前，所述预充电信号PRECHARGE信号为高电平，所述预充电信号PRECHARGE信号的反相信号
Figure PCTCN2019099132-appb-000017
为低电平，所述预充电信号PRECHARGE信号的反信号
Figure PCTCN2019099132-appb-000018
以及所述第二读控制信号MODE2使得所述第五上拉晶体管P5关断，所述第五下拉晶体管N5导通，将所述读位线RBL到低电平，当所述读位线RBL放电结束后，所述预充电信号PRECHARGE信号从高电平变为低电平，使得所述第五下拉晶体管N5关断。
下面通过所述读出电路303具有如图4a所示的结构，所述存储单元301具有如图5所示的结构，所述写入电路302具有如图6所示的结构时，所述读位线RBL的预充放电通过上述图7a中的所述第五上拉晶体管P5、所述第五下拉晶体管N5、所述第一二选一开关Q1和所述第二二选一开关Q2实现时，即所述SRAM单元300具有如图7b所示的结构时，对所述SRAM单元300的工作原理进行详细说明。
当所述SRAM存储阵列中所述SRAM单元300所在的列中存储所述第一数据的SRAM单元的个数大于存储所述第二数据的SRAM单元的个数时，所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极输入所述第一读控制信号MODE1，用高电平表示，即MODE1＝1时，所述SRAM单元300被配置在预充电模式，所述第二上拉晶体管P2处于关断状态，所述第二下拉晶体管N2处于导通状态，在所述与充电信号PRECHARGE有效之后，所述第一读使能信号RE以及所述第二读使能信号
Figure PCTCN2019099132-appb-000019
有效之前，所述第五上拉晶体管P5处于导通状态，所述第五下拉晶体管N4处于关断状态，所述读位线RBL被充电到高电平。在所述第一读使能信号RE以及所述第二读使能信号
Figure PCTCN2019099132-appb-000020
有效时，即对所述SRAM单元300进行读操作时，所述第一读使能信号RE为高电平以及所述第二读使能信号
Figure PCTCN2019099132-appb-000021
所述第一读传输晶体管TR1和所述第二读传输晶体管TR2导通。若所述存储电路301中的节点Q存储的数据为Q＝0，节点QB存储的数据为QB＝1，则所述第一下拉晶体管N1导通，所述读位线RBL放电至低电平，表示读出“0”，使得所述读出电路303下次读取所述存储电路301中存储的数据时，对所述读位线RBL进行充电需要消耗能量；若所述存储电路301中存储的数据为Q＝1，QB＝0，则所述第一下拉晶体管N1关断，所述读位线RBL保持高电平，表示读出“1”，使得所述读出电路303下次读取所述存储电路301中存储的数据时，对所述读位线RBL进行充电不需要消耗能量。
当所述SRAM存储阵列中所述SRAM单元300所在的列中存储所述第一数据的SRAM单元的个数小于存储所述第二数据的SRAM单元的个数时，所述第二上拉晶体管P2的栅极以及所述第二下拉晶体管N2的栅极输入所述第二读控制信号MODE2，用低电平表示，即MODE2＝0时，所述SRAM单元300被配置在预放电模式，所述第二上拉晶体管P2处于导通状态，所述第二下拉晶体管N2处于关断状态，在所述与充电信号PRECHARGE有效之后，所述第一读使能信号RE以及所述第二读使能信号
Figure PCTCN2019099132-appb-000022
有效之前，所述第五上拉晶体管P5处于关断状态，所述第五下拉晶体管N4处于导通状态，所述读位线RBL被放电到低电平。在所述第一读使能信号RE以及所述第二读使能信号
Figure PCTCN2019099132-appb-000023
有效时，即对所述SRAM单元300进行读操作时，所述第一读使能信号RE为高电平，所述第二读使能信号为低电平，所述第一读传输晶体管TR1和所述第二读传输晶体管TR2导通。若所述存储电路301中存储的数据为Q＝0，QB＝1，则所述第一上拉晶体管P1关断，所述读位线RBL 保持低电平，表示读出“0”，此过程不消耗能量；若所述存储电路301中存储的数据为Q＝1，QB＝0，则所述第一上拉晶体管P1导通，所述读位线RBL被充电到高电平，表示读出“1”，此过程需要消耗能量。
由上可知，当所述SRAM单元300所在的列中存储所述第一数据的SRAM单元的个数大于存储所述第二数据的SRAM单元的个数时，从所述SRAM单元300中读取“0”时需要消耗能量，从所述SRAM单元300中读取“1”时不需要消耗能量；当所述SRAM单元300所在的列中存储所述第一数据的SRAM单元的个数小于存储所述第二数据的SRAM单元的个数时，从所述SRAM单元300中读取“0”时不需要消耗能量，从所述SRAM单元300中读取“1”时需要消耗能量。
当所述SRAM单元300先写入第二数据“0”，然后读出第二数据“0”，再写入第一数据“1”，再读出第一数据“1”时，该SRAM单元300的工作时序图如7c所示，其中，Q表示所述SRAM单元300中存储的数据，MODE表示读控制信号，其中，MODE为高电平时表示所述第一读控制信号MODE1，MODE为低电平时表示所述第二读控制信号MODE2。由图12可知，当MODE＝1，即所述第一读控制信号MODE1＝1时，该SRAM单元300读取自身存储的第一数据“1”时，该SRAM单元对应的读位线RBL的电平没有发生翻转，不需要消耗能量，当MODE＝0，即所述第二读控制信号MODE2＝0时，该SRAM单元300读取自身存储的第一数据“0”时，该SRAM单元对应的读位线RBL的电平不发生翻转，不需要消耗能量。
综上所述，采用上述方案，当所述SRAM单元300所在的列中存储所述第一数据的SRAM单元的个数大于存储所述第二数据的SRAM单元的个数时，所述SRAM单元300连接的读位线在所述读出电路303读取所述存储电路301中存储的数据之前，被预先充电到高电平，使得所述读出电路301下次读出所述第一数据时，对所述读位线RBL充电不消耗能量；当所述SRAM单元300所在的列中存储所述第一数据的SRAM单元的个数小于存储所述第二数据的SRAM单元的个数时，所述读位线在所述读出电路303读取所述存储电路301中存储的数据之前，被预先放电到低电平，使得所述读出电路301下次读出所述第二数据时不消耗能量。即所述SRAM单元300所在的SRAM存储器能够根据所述SRAM存储阵列中一列SRAM单元中存储的第一数据的个数以及第二数据的个数，调整所述SRAM存储器的工作结构，以尽量避免对所述SRAM单元300进行读操作时，对所述SRAM单元300连接的读位线进行充电消耗的能量，进而降低所述SRAM存储器的功耗，尤其在对SRAM存储器的读操作较多的场景下，如神经网络场景中，能够显著降低所述SRAM存储器的功耗。
基于上述实施例，本申请还提供了一种SRAM存储器，所述SRAM存储器800包括多个所述SRAM单元300，如图8所示。其中，所述多个SRAM单元300通过多条写字线、多条写位线以及多条读位线连接，组成SRAM存储阵列。
一个可能的实施方式中，所述多个SRAM单元300组成的SRAM存储阵列中的每一列SRAM单元可以共用所述第二上拉晶体管P2以及所述第二下拉晶体管N2。
一个可能的实施方式中，所述SRAM存储器800还包括N个数据统计电路801、M×N个读控制信号存储电路802以及N个多路选择器803，其中，N等于所述SRAM存储器800的数据位宽，所述N个数据统计电路801与所述多路选择器803一一对应，所述SRAM存储阵列包括M×N列所述SRAM单元300；所述N个数据统计电路801中的每 个数据统计电路801通过对应的多路选择器803与M个所述读控制信号存储电路802连接，M×N个所述读控制信号存储电路802中的每个读控制信号存储电路802与所述SRAM存储阵列中的一列SRAM单元连接，如图9所示。
所述数据统计电路801，用于统计需要写入目标SRAM单元的数据中第一数据的个数以及第二数据的个数，所述目标SRAM单元为所述SRAM存储阵列中所述数据统计电路801连接的一列所述SRAM单元300；当所述第一数据的个数大于所述第二数据的个数时，产生用于控制所述读位线充电到高电平的所述第一读控制信号MODE1，当所述第一数据的个数小于所述第二数据的个数时，产生用于控制所述读位线放电到低电平的所述第二读控制信号MODE2。
所述目标SRAM单元连接的读控制信号存储电路802，用于存储所述第一读控制信号MODE1或者所述第二读控制信号MODE2；其中，所述第一读控制信号为高电平，所述第二读控制信号为低电平。
另一个可能的实施方式中，所述SRAM存储器800还包括：M×N个数据统计电路801以及M×N个读控制信号存储电路802，其中，所述N等于数据位宽，所述数据位宽对应的数据中每个比特对应SRAM存储阵列中的M列，所述SRAM存储阵列包括M×N列所述SRAM单元300，所述M×N个数据统计电路801与所述M×N列所述SRAM单元300一一对应，每个所述数据统计电路801通过一个所述读控制信号存储电路802与一列所述SRAM单元相连。
所述数据统计电路801，用于统计需要写入目标SRAM单元的数据中所述第一数据的个数以及所述第二数据的个数，所述目标SRAM单元为所述SRAM存储阵列中所述数据统计电路连接的一列所述SRAM单元；当所述第一数据的个数大于所述第二数据的个数时，产生用于控制所述读位线充电到高电平的第一读控制信号MODE1，当所述第一数据的个数小于所述第二数据的个数时，产生用于控制所述读位线放电到低电平的第二读控制信号MODE2；
所述目标SRAM单元连接的读控制信号存储电路802，用于存储所述第一读控制信号MODE1或者所述第二读控制信号MODE2；其中，所述第一读控制信号为高电平，所述第二读控制信号为低电平。
其中，所述数据统计电路801还用于：当所述第一个数等于所述第二个数时，产生所述第一读控制信号MODE1或者所述第二读控制信号MODE2。
具体地，所述N个数据统计电路801可以根据所述SRAM存储阵列的列地址，选通所述多路选择器803中所述SRAM存储阵列中所述列地址对应的一列，统计需要写入该列中SRAM单元的数据中第一数据与第二数据的个数。
一个具体的实施方式中，所述数据统计电路801包括计数电路以及比较电路，所述计数电路用于统计需要写入目标SRAM单元的数据中所述第一数据的第一个数以及所述第二数据的第二个数，所述比较电路用于对所述第一个数以及所述第二个数进行比较，当所述第一个数大于所述第二个数时输出所述第一读控制信号MODE1，当所述第一个数小于所述第二个数时输出所述第二读控制信号MODE2。
或者，所述计数电路用于统计需要写入目标SRAM单元的数据中所述第一数据的第一个数，根据所述第一个数以及确需要写入目标SRAM单元的数据中定所述第二数据的第二个数，所述比较电路用于对所述第一个数以及
Figure PCTCN2019099132-appb-000024
进行比较，L为需要写入目标SRAM单元 的数据的总个数(当所述SRAM的数据位宽以及包括的所述SRAM单元的个数一定时，需要写入所述目标SRAM单元的数据总数是已知的)，当所述第一个数大于
Figure PCTCN2019099132-appb-000025
时，输出所述第一读控制信号MODE1，当所述第一个数小于
Figure PCTCN2019099132-appb-000026
时，输出所述第二读控制信号MODE2。
或者，所述计数电路用于统计需要写入目标SRAM单元的数据中所述第二数据的第二个数，所述比较电路用于对所述第二个数以及所述
Figure PCTCN2019099132-appb-000027
进行比较，当所述第二个数小于所述
Figure PCTCN2019099132-appb-000028
时，输出所述第一读控制信号MODE1，当所述第二个数大于所述
Figure PCTCN2019099132-appb-000029
时，输出所述第二读控制信号MODE2。
一个可能的实施方式中，所述SRAM 800还包括M×N个读控制电路804，所述M×N个读控制电路804中的每个分别通过对应的读位线与所述SRAM存储阵列中的一列所述SRAM单元300连接，如图10所示。其中，
所述读控制电路804，用于在所述SRAM存储器800收到读命令之后、在所述读控制电路804连接的一列SRAM单元的所述读使能信号有效之前，在所述第一读控制信号MODE1以及预充电信号的反相信号
Figure PCTCN2019099132-appb-000030
的控制下，将所述读控制电路连接的一列SRAM单元对应的读位线充电到高电平；或者，
所述读控制电路804，用于在所述SRAM存储器收到读命令之后、在所述读控制电路804连接的一列SRAM单元的所述读使能信号有效之前，在所述第二读控制信号MODE2以及预充电信号PRECHARGE的控制下，将所述读控制电路连接的一列SRAM单元对应的读位线放电到低电平。
一个可能的实施方式中，所述读控制电路804包括图7b中所示的第五上拉晶体管P5、第五下拉晶体管N5、第一二选一开关Q1和第二二选一开关Q2。其中，所述第五上拉晶体管P5的源极与电源连接，所述第五上拉晶体管P5的栅极与所述第一二选一开关Q1的输出端连接，所述第五上拉晶体管P5的漏极与所述SRAM存储阵列中所述读控制电路804连接的一列SRAM单元对应的读位线的一端连接，所述第一二选一开关Q1的第一输入端与电源VCC连接，所述第一二选一开关Q1的第二输入端用于输入所述预充电信号的反信号
Figure PCTCN2019099132-appb-000031
所述第一二选一开关的控制端用于输入所述第一读控制信号MODE1或所述第二读控制信号MODE2；所述第五下拉晶体管N5的漏极与所述SRAM存储阵列中所述读控制电路804连接的一列SRAM单元对应的读位线连接，所述第五下拉晶体管N5的栅极与所述第二二选一开关Q2的输出端连接，所述第五下拉晶体管N5的源极接地，所述第二二选一开关Q2的第一输入端用于输入所述预充电信号PRECHARGE，所述第二二选一开关Q2的第二输入端接地，所述第二二选一开关Q2的控制端用于输入所述第一读控制信号MODE1或所述第二读控制信号MODE2。
具体地，当所述SRAM存储器800具有如图9所示的数据统计电路801、读控制信号存储电路802以及N个多路选择器803，以及如图10所示的读控制电路804时，结构如图11所示，所述读控制电路804通过对应的读控制信号存储电路802获取所述第一读控制信号MODE1或获取所述第二读控制信号MODE2。
下面以本申请实施提供的SRAM存储器800在Spectre仿真环境下，用SMIC 65nm工艺对电路进行仿真，并以典型的卷积神经网络为例，针对初始图像与神经元存取特点，对所述SRAM存储器800进行平均读取功耗评估。实验结果表明，对于原始图像的读取，本 申请实施例提供的SRAM单元300相对于现有的6T-SRAM单元平均节省64％的能量，相对8T-SRAM单元节省46％的能量。尤其在MNIST数据集下，节省的比例可以分别达到87％与86％；对于神经元数据的读取，所述相对于6T-SRAM单元平均节省67％的能量，相比8T-SRAM单元平均节省53％的能量。尤其在所述SRAM单元300处理AlexNet神经网络时，相对于6T-SRAM单元可以节省73％的能量，如表1所示，相比8T-SRAM单元可以节省67％的能量，如表2所示。
表1原始图像读取平均功耗
Figure PCTCN2019099132-appb-000032
表2神经元数据读取平均功耗
Figure PCTCN2019099132-appb-000033
应当理解的是，本申请实施例提供的SRAM存储器800为一个完整的SRAM存储器，也具备已知的SRAM具有的结构，如行地址译码器、列地址译码器、灵敏放大器以及缓冲/驱动电路等，在此仅对所述SRAM 800中涉及降低SRAM功耗的部件进行说明，对于其他部件不予赘述。
采用上述方案，所述SRAM存储器800能够根据SRAM存储器800的一列SRAM单元中存储的第一数据的个数以及第二数据的个数，调整所述SRAM存储器800的工作结构，以尽量减少对所述SRAM存储器800中的SRAM单元进行读操作时，对所述SRAM单元连接的读位线进行充电消耗的能量，进而降低所述SRAM存储器800的功耗。
需要说明的是，上述实施例中所述第二上拉晶体管P2的源极连接的电源、所述第三上拉晶体管P3的源极连接的电源、所述第四上拉晶体管P4的源极连接的电源、所述第五上拉晶体管P5的源极连接的电源以及所述第一二选一开关Q1的第一输入端连接的电源可以是同一个电源，也可以是不同的电源。
基于以上实施例，本申请还提供了一种处理电路芯片，所述处理电路芯片1200包括所述SRAM 800以及一个或多个处理电路1201，其中，所述SRAM存储器800用于存储所述一个或多个处理电路1201运行时所需的数据，如图12所示。
其中，所述处理电路1201可以是内核(core)(如ARM核)，也可以是基于专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合等实现的硬件电路。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。例如，所述处理电路芯片1200可以是通信设备(如手机、平板电脑以及个人计算机等)中的应用处理器 (application processor，AP)，也可以是神经网络中的加速器。
应当理解的是，本申请实施例提供的处理电路芯片1200还可以也具备已知的处理器具有的其他结构，如输入/输出接口等。
采用上述方案，所述处理电路芯片1200中的SRAM800能够根据所述SRAM存储器800中每一列SRAM单元中存储的第一数据的个数以及第二数据的个数，调整所述SRAM存储器800中每一列SRAM单元的工作结构，以尽量避免对所述SRAM单元进行读操作时，对所述SRAM单元连接的读位线进行充电消耗的能量，以降低所述SRAM存储器的功耗，进而能够提高所述处理电路芯片1200的性能(如处理速度)。
另外，本申请还提供了一种电子设备，所述电子设备包括电源以及所述处理电路芯片1200，其中，所述电源用于给所述处理电路芯片1200供电。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种静态随机存储器SRAM单元，其特征在于，位于SRAM存储器中，所述SRAM存储器包括由多个所述SRAM单元构成的SRAM存储阵列，所述SRAM单元包括：存储电路、写入电路以及读出电路；
    所述存储电路，分别与所述写入电路以及所述读出电路连接，用于存储数据；其中，所述数据为第一数据或第二数据，所述第一数据用高电平表示，所述第二数据用低电平表示；
    所述写入电路，还与写字线以及写位线连接，用于向所述存储电路中写入数据；
    所述读出电路，还与读使能信号端以及读位线连接，其中，当所述SRAM存储阵列中所述SRAM单元所在的列中存储所述第一数据的SRAM单元的第一个数大于存储所述第二数据的SRAM单元的第二个数时，所述读位线在所述SRAM存储器收到读命令之后、在所述读使能信号端上的读使能信号有效之前，被充电到高电平；当所述第一个数小于所述第二个数时，所述读位线在所述SRAM存储器收到读命令之后、在所述读使能信号有效之前，被放电到低电平；
    所述读出电路，用于在所述读使能信号有效后使得所述读位线上的数据为所述存储电路中存储的数据。
  2. 如权利要求1所述的SRAM单元，其特征在于，所述读出电路包括第一上拉晶体管、第一下拉晶体管、第一读传输晶体管和第二读传输晶体管；
    所述第一上拉晶体管的栅极分别与所述第一下拉晶体管的栅极以及所述存储电路连接，所述第一上拉晶体管的源极与第二上拉晶体管的漏极连接，所述第一上拉晶体管的漏极分别与所述第一下拉晶体管的漏极、所述第一读传输晶体管的源极以及所述第二读传输晶体管的漏极连接，所述第一下拉晶体管的源极与第二下拉晶体管的漏极连接，所述第二下拉晶体管的源极接地，所述第二上拉晶体管的源极与电源连接，所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极用于接收所述第一读控制信号或所述第二读控制信号；
    当所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极接收到所述第一读控制信号时，所述第二上拉晶体管处于关断状态，所述第二下拉晶体管处于导通状态；当所述第二上拉晶体管的栅极以及所述第二下拉晶体管的栅极接收到所述第二读控制信号时，所述第二上拉晶体管处于导通状态，所述第二下拉晶体管处于关断状态；
    所述第一读传输晶体管的漏极分别与所述第二读传输晶体管的源极以及所述读位线连接，所述第一读传输晶体管的栅极与第一读使能信号端连接，所述第二读传输晶体管的栅极与第二读使能信号端连接；当所述第一读使能信号端上的第一读使能信号有效，且所述第二读使能信号端上的第二读使能信号有效时，所述第一读传输晶体管以及所述第二读传输晶体管均处于导通状态；
    其中，所述读使能信号端包括所述第一读使能信号端以及所述第二读使能信号端，所述读使能信号包括所述第一读使能信号以及所述第二读使能信号，所述第二读使能信号是所述第一读使能信号的反相信号。
  3. 如权利要求2所述的SRAM单元，其特征在于，所述第一上拉晶体管、所述第二上拉晶体管以及所述第一读传输晶体管为P沟道场效应管；所述第一下拉晶体管、所述第 二下拉晶体管和所述第二读传输晶体管为N沟道场效应管。
  4. 如权利要求1-3任意一项所述的SRAM单元，其特征在于，所述存储电路包括第三上拉晶体管、第四上拉晶体管、第三下拉晶体管和第四下拉晶体管；
    所述第三上拉晶体管以及所述第四上拉晶体管的源极均与电源连接；所述第三上拉晶体管的栅极分别与所述第三下拉晶体管的栅极、所述第四上拉晶体管的漏极、所述第四下拉晶体管的漏极、所述读出电路以及所述写入电路连接；所述第四上拉晶体管的栅极分别与所述第四下拉晶体管的栅极、所述第三上拉晶体管的漏极、所述第三下拉晶体管的漏极以及所述写入电路连接；所述第三下拉晶体管的源极以及所述第四下拉晶体管的源极均接地。
  5. 如权利要求4所述的SRAM单元，其特征在于，所述第三上拉晶体管和所述第四上拉晶体管为P沟道场效应管；所述第三下拉晶体管和所述第四下拉晶体管为N沟道场效应管。
  6. 如权利要求4或5所述的SRAM单元，其特征在于，所述写入电路包括第一写传输晶体管和第二写传输晶体管；
    所述第一写传输晶体管的源极与第一写位线连接，所述第一写传输晶体管的栅极与所述写字线连接，所述第一写传输晶体管的漏极分别与所述第三上拉晶体管的漏极以及所述第四上拉晶体管的栅极连接；所述第二写传输晶体管的源极分别与所述第四上拉晶体管的漏极以及所述第三上拉晶体管的栅极连接，所述第二写传输晶体管的源极与第二写位线连接，所述第二写传输晶体管的栅极与所述写字线连接；
    所述写位线包括所述第一写位线以及所述第二写位线；当所述写入电路向所述存储电路写入数据时，所述第一写传输晶体管以及所述第二写传输晶体管均处于导通状态；所述第一写位线与所述第二写位线反相。
  7. 如权利要求6所述的SRAM单元，其特征在于，所述第一写传输晶体管和所述第二写传输晶体管均为N沟道场效应管。
  8. 一种静态随机存储器SRAM存储器，其特征在于，包括多个如权利要求1-7任意一项所述的SRAM单元。
  9. 如权利要求8所述的SRAM存储器，其特征在于，所述SRAM存储器还包括N个数据统计电路、N个多路选择器以及M×N个读控制信号存储电路，其中，所述N等于数据位宽，所述数据位宽对应的数据中每个比特对应SRAM存储阵列中的M列，所述N个数据统计电路与所述N个多路选择器一一对应，所述SRAM存储阵列包括M×N列所述SRAM单元；
    其中，所述N个数据统计电路中的每个通过对应的多路选择器与M个所述读控制信号存储电路连接，M×N个所述读控制信号存储电路中的每个与所述SRAM存储阵列中的一列SRAM单元连接；
    所述数据统计电路，用于统计需要写入目标SRAM单元的数据中所述第一数据的个数以及所述第二数据的个数，所述目标SRAM单元为所述SRAM存储阵列中所述数据统计电路连接的一列所述SRAM单元；当所述第一数据的个数大于所述第二数据的个数时，产生用于控制所述读位线充电到高电平的第一读控制信号，当所述第一数据的个数小于所述第二数据的个数时，产生用于控制所述读位线放电到低电平的第二读控制信号；
    所述目标SRAM单元连接的读控制信号存储电路，用于存储所述第一读控制信号或者 所述第二读控制信号；其中，所述第一读控制信号为高电平，所述第二读控制信号为低电平。
  10. 如权利要求8所述的SRAM存储器，其特征在于，还包括：M×N个数据统计电路、以及M×N个读控制信号存储电路，其中，所述N等于数据位宽，所述数据位宽对应的数据中每个比特对应SRAM存储阵列中的M列，所述SRAM存储阵列包括M×N列所述SRAM单元，所述M×N个数据统计电路与所述M×N列所述SRAM单元一一对应，每个所述数据统计电路通过一个所述读控制信号存储电路与一列所述SRAM单元相连；
    所述数据统计电路，用于统计需要写入目标SRAM单元的数据中所述第一数据的个数以及所述第二数据的个数，所述目标SRAM单元为所述SRAM存储阵列中所述数据统计电路连接的一列所述SRAM单元；当所述第一数据的个数大于所述第二数据的个数时，产生用于控制所述读位线充电到高电平的第一读控制信号，当所述第一数据的个数小于所述第二数据的个数时，产生用于控制所述读位线放电到低电平的第二读控制信号；
    所述目标SRAM单元连接的读控制信号存储电路，用于存储所述第一读控制信号或者所述第二读控制信号；其中，所述第一读控制信号为高电平，所述第二读控制信号为低电平。
  11. 如权利要求8-10任一所述的SRAM存储器，其特征在于，所述读控制信号存储电路为锁存器。
  12. 如权利要求8-11任意一项所述的SRAM存储器，其特征在于，还包括M×N个读控制电路，所述N等于数据位宽，所述M×N个读控制电路中的每个分别通过对应的读位线与所述SRAM存储阵列中的一列所述SRAM单元连接；
    所述读控制电路，用于在所述SRAM存储器收到读命令之后、在所述读控制电路连接的一列SRAM单元的所述读使能信号有效之前，在所述第一读控制信号以及预充电信号的反相信号的控制下，将所述读控制电路连接的一列SRAM单元对应的读位线充电到高电平；或者，
    所述读控制电路，用于在所述SRAM存储器收到读命令之后、在所述读控制电路连接的一列SRAM单元的所述读使能信号有效之前，在所述第二读控制信号以及预充电信号的控制下，将所述读控制电路连接的一列SRAM单元对应的读位线放电到低电平。
  13. 如权利要求12所述的SRAM存储器，其特征在于，所述读控制电路包括第五上拉晶体管、第五下拉晶体管、第一二选一开关和第二二选一开关；
    所述第五上拉晶体管的源极与电源连接，所述第五上拉晶体管的栅极与所述第一二选一开关的输出端连接，所述第五上拉晶体管的漏极与所述SRAM存储阵列中所述读控制电路连接的一列SRAM单元对应的读位线连接，所述第一二选一开关的第一输入端与电源连接，所述第一二选一开关的第二输入端用于输入预充电信号的反相信号，所述第一二选一开关的控制端用于输入所述第一读控制信号或所述第二读控制信号；
    所述第五下拉晶体管的漏极与所述SRAM存储阵列中所述读控制电路连接的一列SRAM单元对应的读位线连接，所述第五下拉晶体管的栅极与所述第二二选一开关的输出端连接，所述第五下拉晶体管的源极接地，所述第二二选一开关的第一输入端用于输入所述预充电信号，所述第二二选一开关的第二输入端接地，所述第二二选一开关的控制端用于输入所述第一读控制信号或所述第二读控制信号；
    其中，当所述第一二选一开关的控制端以及所述第二二选一开关的控制端输入所述第 一读控制信号，且所述预充电信号的反相信号有效时，所述第一二选一开关的输出端与所述第一二选一开关的第二输入端连通，所述第五上拉晶体管处于导通状态，所述第二二选一开关的输出端与所述第二二选一开关的第二输入端连通，所述第五下拉晶体管处于关断状态；当所述第一二选一开关的控制端以及所述第二二选一开关的控制端输入所述第二读控制信号，且所述预充电信号有效时，所述第一二选一开关的输出端与所述第一二选一开关的第一输入端连通，所述第五上拉晶体管处于关断状态，所述第二二选一开关的输出端与所述第二二选一开关的第一输入端连通，所述第五下拉晶体管处于导通状态。
  14. 如权利要求13所述的SRAM存储器，其特征在于，所述第五上拉晶体管为P沟道场效应管，所述第五下拉晶体管为N沟道场效应管。
  15. 一种处理电路芯片，其特征在于，包括如权利要求8-14任意一项所述的SRAM存储器以及一个或多个处理电路，所述SRAM存储器用于存储所述一个或多个处理电路运行时所需的数据。
  16. 一种电子设备，其特征在于，包括电源以及如权利要求14所述的处理电路芯片，其中，所述电源用于给所述处理电路芯片供电。
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