WO2020042288A1 - 有机发光二极管显示面板及其制造方法 - Google Patents

有机发光二极管显示面板及其制造方法 Download PDF

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Publication number
WO2020042288A1
WO2020042288A1 PCT/CN2018/109994 CN2018109994W WO2020042288A1 WO 2020042288 A1 WO2020042288 A1 WO 2020042288A1 CN 2018109994 W CN2018109994 W CN 2018109994W WO 2020042288 A1 WO2020042288 A1 WO 2020042288A1
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WIPO (PCT)
Prior art keywords
retaining wall
insulating layer
array substrate
display area
thin film
Prior art date
Application number
PCT/CN2018/109994
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English (en)
French (fr)
Inventor
曹君
徐湘伦
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/308,612 priority Critical patent/US10692950B2/en
Publication of WO2020042288A1 publication Critical patent/WO2020042288A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present application relates to a display technology, and particularly to an organic light emitting diode (OLED) display panel and a manufacturing method thereof.
  • OLED organic light emitting diode
  • OLED display can realize flexible display.
  • OLED devices are particularly sensitive to water and oxygen.
  • the traditional process will mold the OLED device with a thin film packaging structure.
  • the thin film packaging structure is composed of overlapping organic and inorganic layers.
  • the organic layer in the thin film packaging structure has a certain fluidity. In order to limit it to a certain area, a circle or Multi-turn retaining wall (dam).
  • FIG. 1 shows a schematic diagram of a conventional OLED display panel 100. As shown in FIG. 1, the display panel 100 is divided into a non-display area D and a display area E. The retaining wall 110 is disposed in the non-display area D. The retaining wall 110 defines a boundary of an organic layer in the thin film packaging structure.
  • FIG. 2 shows a schematic diagram of a conventional shaped screen 200. Please refer to FIG. 1 and FIG. 2 together.
  • the retaining wall 100 is a closed ring structure having a straight side area (straight line region) SR and a corner region region) CR.
  • the retaining wall shown in FIG. 1 has four corner regions CR, and the number and shape of the corner regions CR in the special-shaped screen 200 shown in FIG. 2 are more complicated.
  • the shape of the corner region CR is relatively more complicated than the shape of the straight side region SR, there is a problem in the prior art that the organic layer of the thin-film encapsulation structure overflows from the corner region CR, resulting in water and oxygen invasion. OLED display life. Due to the large number of CRs in the corner region of the special-shaped screen 200, the problem of the organic layer overflow of the thin film packaging structure is more serious.
  • the object of the present application is to provide an organic light emitting diode display panel and a manufacturing method thereof, so as to reduce the risk of overflowing the organic layer of the thin film packaging structure.
  • an aspect of the present application is to provide an organic light emitting diode display panel including a display area and a non-display area, the display area is used for displaying an image, the non-display area surrounds the display area, and the
  • the display panel includes: a thin film transistor array substrate including an insulating stacked structure on the non-display area, the insulating stacked structure including a plurality of stacked insulating layers; and a plurality of organic light emitting units disposed on the thin film transistor array.
  • a first retaining wall is disposed on the thin film transistor array substrate, the first retaining wall is located in the non-display area and surrounds the display area;
  • a second retaining wall Is disposed on the thin film transistor array substrate, the second retaining wall is located in the non-display area and surrounds the first retaining wall, and the first retaining wall and the second retaining wall are at a distance from each other, so
  • the first retaining wall includes a first closed-loop structure
  • the second retaining wall includes a second closed-loop structure
  • the first closed-loop structure is disposed on the second closed-loop structure.
  • the first retaining wall and the second retaining wall constitute an annular structure, and a straight edge area and a corner area are defined on the annular structure; a groove is provided in the straight edge area of the annular structure,
  • the trench is disposed between the first closed-loop structure and the second closed-loop structure, and the trench is disposed in the insulating stacked structure of the thin film transistor array substrate and has an exposed opening.
  • the thin film transistor array substrate A height in the straight edge region is lower than a height in the corner region; and a thin film encapsulation structure having one or more organic layers and one or more inorganic layers that overlap, and the thin film encapsulation structure covers the thin film A transistor array substrate, the plurality of organic light emitting units, the first retaining wall, the second retaining wall, and the opening exposed by the trench provided in the straight edge region of the annular structure.
  • several insulating layers included in the insulating stacked structure of the thin film transistor array substrate include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer in order.
  • the second interlayer insulating layer is an outermost insulating layer in the insulating laminated structure.
  • the depth of the trench is the thickness of the second interlayer insulating layer.
  • the depth of the trench is the total thickness of the first interlayer insulating layer and the second interlayer insulating layer.
  • the depth of the trench is a total thickness of the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.
  • an organic light emitting diode display panel including a display area and a non-display area, the display area is used for displaying an image, the non-display area surrounds the display area, and the display panel includes: A thin film transistor array substrate comprising an insulating stacked structure on the non-display area, the insulating stacked structure includes a plurality of stacked insulating layers; a plurality of organic light emitting units are disposed on the thin film transistor array substrate and are located at In the display area, a first retaining wall is provided on the thin film transistor array substrate, the first retaining wall is located in the non-display area and surrounds the display area, and a second retaining wall is provided in the On the thin film transistor array substrate, the second retaining wall is located in the non-display area and surrounds the first retaining wall.
  • the first retaining wall and the second retaining wall are spaced apart from each other.
  • the wall and the second retaining wall form an annular structure, and a straight edge area and a corner area are defined on the annular structure; a groove is provided in the annular structure.
  • a side region is located between the first retaining wall and the second retaining wall, the groove is provided in the insulating stack structure of the thin film transistor array substrate, and has an exposed opening; and a thin film packaging structure Having one or more organic layers and one or more inorganic layers overlapping, the thin film encapsulation structure covers the thin film transistor array substrate, the plurality of organic light emitting units, the first retaining wall, the first Two retaining walls and the openings exposed in the grooves of the straight edge region of the annular structure.
  • the first retaining wall includes a first closed-loop structure
  • the second retaining wall includes a second closed-loop structure
  • the first closed-loop structure is disposed in the second closed-loop structure.
  • a trench is disposed between the first closed-loop structure and the second closed-loop structure.
  • a height of the thin film transistor array substrate in the straight edge region is lower than a height in the corner region.
  • the trench has a sidewall and a bottom wall, and the sidewall and the bottom wall of the trench are adjacent to at least one of the insulation layers of the insulation stack structure. Insulation.
  • the trench has a side wall and a bottom wall, and the side wall of the trench is adjacent to one of the insulating layers in the insulating laminated structure.
  • the bottom wall of the trench is adjacent to another insulation layer of the plurality of insulation layers of the insulation stack.
  • several insulating layers included in the insulating stacked structure of the thin film transistor array substrate include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer in order.
  • the second interlayer insulating layer is an outermost insulating layer in the insulating laminated structure.
  • the depth of the trench is the thickness of the second interlayer insulating layer.
  • the depth of the trench is the total thickness of the first interlayer insulating layer and the second interlayer insulating layer.
  • the depth of the trench is a total thickness of the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.
  • the display panel includes a display area and a non-display area.
  • the display area is used to display an image.
  • the non-display area surrounds the display area.
  • the method includes forming a thin film transistor array substrate, the thin film transistor array substrate including an insulating stacked structure on the non-display area, the insulating stacked structure including a plurality of stacked insulating layers; and in the display area
  • a plurality of organic light emitting units are provided; in the non-display region, at least one of the plurality of insulating layers included in the insulating stacked structure of the thin film transistor array substrate is insulated.
  • a first barrier wall and a second barrier wall are provided on the thin film transistor array substrate in the non-display area, and the first barrier wall
  • the retaining wall and the second retaining wall constitute an annular structure, and a straight edge area and a corner area are defined on the annular structure, and the groove is provided In the straight edge region of the annular structure and located between the first retaining wall and the second retaining wall; forming a thin film having one or more organic layers and one or more inorganic layers overlapping A packaging structure to cover the thin film transistor array substrate, the plurality of organic light emitting units, the first retaining wall, the second retaining wall, and the trench provided in the straight edge region of the annular structure The opening is exposed.
  • the first retaining wall includes a first closed-loop structure
  • the second retaining wall includes a second closed-loop structure
  • the first closed-loop structure is disposed in the second closed-loop structure.
  • a trench is disposed between the first closed-loop structure and the second closed-loop structure.
  • a height of the thin film transistor array substrate in the straight edge region is lower than a height in the corner region.
  • several insulating layers included in the insulating stacked structure of the thin film transistor array substrate include a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer in order.
  • the second interlayer insulating layer is an outermost insulating layer in the insulating laminated structure.
  • the depth of the trench is the thickness of the second interlayer insulating layer.
  • the depth of the trench is the total thickness of the first interlayer insulating layer and the second interlayer insulating layer.
  • a groove is provided in the TFT array substrate corresponding to two retaining walls and the straight edge region between the gaps, which makes the height of the TFT array substrate in the straight edge region lower than the height in the corner region. That is, the TFT array substrate forms a height difference between the straight edge area and the corner area.
  • the overflowed portion can flow to the lower straight edge area by means of the height difference. . Therefore, the present application can effectively reduce the risk of the organic layer of the thin film packaging structure overflowing in the corner region.
  • FIG. 1 shows a schematic diagram of a conventional OLED display panel.
  • FIG. 2 shows a schematic diagram of a conventional shaped screen.
  • FIG. 3 is a schematic diagram of an organic light emitting diode display panel according to the present application.
  • FIG. 4 is a cross-sectional view taken along the line I-I in FIG. 3.
  • FIG. 5 is a cross-sectional view taken along the line II-II in FIG. 3.
  • FIG. 6 is a cross-sectional view taken along the dashed line III-III in FIG. 3.
  • FIG. 7 is a schematic diagram of an organic light emitting diode display panel according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram illustrating a cross section along a gap between two retaining walls according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an organic light emitting diode display panel according to another embodiment of the present application.
  • FIG. 10 is a schematic diagram illustrating a cross section along a gap between two retaining walls according to another embodiment of the present application.
  • FIG. 11 is a schematic diagram of an organic light emitting diode display panel according to another embodiment of the present application.
  • FIG. 12 is a schematic diagram illustrating a cross section along a gap between two retaining walls according to another embodiment of the present application.
  • FIG. 13 shows a flowchart of a method for manufacturing an organic light emitting diode display panel according to the present application.
  • FIG. 3 shows an organic light emitting diode according to the present application.
  • FIG. 4 is a cross-sectional view taken along the line I-I in FIG. 3.
  • FIG. 5 is a cross-sectional view taken along the line II-II in FIG. 3.
  • FIG. 6 is a cross-sectional view taken along the dashed line III-III in FIG. 3.
  • the OLED display panel 300 includes a non-display area D and a display area E.
  • the display area E is an effective display area.
  • the display area E has a plurality of pixels (not shown) formed by interlacing a plurality of scanning lines (not shown) and a plurality of data lines (not shown) for displaying an image.
  • the non-display area D surrounds the display area E.
  • the non-display area D is used to set, for example, a display chip (not shown) and a peripheral routing area (not shown).
  • the OLED display panel 300 includes a thin-film transistor. transistor (TFT) array substrate 310, a plurality of organic light emitting units 320 provided in the display area E, a first retaining wall 331 and a second retaining wall 332 provided in the non-display area D, and a thin film packaging structure 340.
  • TFT transistor
  • the TFT array substrate 310 includes a plurality of thin film transistors (not shown) on the display area E to drive the organic light emitting unit 320.
  • Each thin film transistor includes a gate, a source, and a drain.
  • Several organic light emitting units 320 are disposed on the TFT array substrate 310 (only one organic light emitting unit 320 is shown in FIGS. 5 and 6).
  • Each organic light emitting unit 320 includes an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.
  • the gate of the thin film transistor is connected to the scan line
  • the source is connected to the data line
  • the drain is connected to the anode of the organic light emitting unit 320
  • the organic light emitting unit 320 is driven in an active manner.
  • the TFT array substrate 310 has an insulating laminated structure on the non-display area D, which includes a plurality of laminated insulating layers (see FIGS. 7, 9 and 11).
  • the first barrier wall 331 and the second barrier wall 332 are disposed on the TFT array substrate 310 and are located in the non-display area D. That is, the first barrier wall 331 and the second barrier wall 332 are disposed on the topmost insulating layer of the TFT array substrate 310 in the non-display area D.
  • the first retaining wall 331 surrounds the display area E
  • the second retaining wall 332 surrounds the first retaining wall 331
  • the first retaining wall 331 and the second retaining wall 332 are spaced apart from each other.
  • the first retaining wall 331 and the second retaining wall 332 are convex structures, and a gap is formed between the two.
  • the thin film encapsulation structure 340 has one or more organic layers and one or more inorganic layers that overlap.
  • the organic layer is mainly used to provide flexibility of the OLED display panel 300, and the inorganic layer is mainly used to prevent water and oxygen from penetrating into the OLED display panel 300.
  • the number of organic layers and inorganic layers of the thin-film encapsulation structure 340 can be adjusted as needed.
  • the thin-film encapsulation structure 340 includes a first inorganic layer 341, an organic layer 342, and a second inorganic layer 343.
  • the organic layer 342 covers the organic light emitting unit 320 in the display area E, and the first inorganic layer 341 and the second inorganic layer 343 extend to the non-display area D, covering the first retaining wall 331 and the second retaining wall 332.
  • the first retaining wall 331 is mainly used to define a boundary of the organic layer 342.
  • the organic layer 342 is formed by using a flash evaporation method to cure the monomer by exposing it to ultraviolet light after the monomer is deposited.
  • the second retaining wall 332 is mainly used to prevent the monomer from being deposited in an area where the deposition is not desired when the organic layer 342 is formed. Causes problems of reduced adhesion and water and oxygen penetration.
  • the first retaining wall 331 and the second retaining wall 332 can be made by a general manufacturing process.
  • the materials of the first retaining wall 331 and the second retaining wall 332 may be the same or different from each other.
  • the materials of the first retaining wall 331 and the second retaining wall 332 may include a photoresist, an organic material of a polyacrylic resin, a polyimide resin, and an acrylic resin, or an inorganic material of a silicon compound.
  • the thin film encapsulation structure 340 can be made by a general manufacturing process.
  • Materials of the first inorganic layer 341 and the second inorganic layer 343 may be the same or different from each other.
  • Materials of the first inorganic layer 341 and the second inorganic layer 343 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide , Cerium oxide and silicon oxynitride.
  • the material of the organic layer 342 may include acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, perylene resin, and other polymer materials.
  • the first retaining wall 331 and the second retaining wall 332 form an annular structure, such as a closed annular structure.
  • the first retaining wall 331 includes a first closed-loop structure
  • the second retaining wall 332 includes a second closed-loop structure
  • the first closed-loop structure is disposed in the second closed-loop structure. That is, the area surrounded by the second closed-loop structure is larger than the area surrounded by the first closed-loop structure.
  • the aforementioned gap is located between the first closed-loop structure and the second closed-loop structure.
  • the annular structure formed by the first retaining wall 331 and the second retaining wall 332 defines a straight line region SR and a corner region CR, as shown in FIG. 3.
  • the straight edge area SR corresponds to the straight edge of the display area E, and the corner area CR should display the corner of the area E.
  • the corner region CR corresponds to a polygonal line or an arc line at a certain angle, or a combination of the two.
  • a trench 311 is provided between the first retaining wall 331 and the second retaining wall 332 in the straight edge region SR of the annular structure. That is, the trench 311 is disposed between the first closed-loop structure and the second closed-loop structure of the straight edge region SR.
  • the trench 311 is formed by hollowing out the TFT array substrate 310 of the straight edge region SR at a position corresponding to the gap between the two retaining walls 331 and 332. After digging the hole, the trench 311 has an exposed opening.
  • the trench 311 is an uppermost layer or an uppermost layer of an insulating layered structure of the TFT array substrate 310 corresponding to the straight edge region SR by applying processes such as photoresist, exposure, development, and etching. Formed by removal. That is, at least one insulating layer is removed to form the trench 311.
  • the TFT array substrate 310 can be made by a general manufacturing process.
  • the material of the insulating layer in the insulating stacked structure of the TFT array substrate 310 may include organic materials such as photoresist, acrylic polymer, polyimide polymer, polyamide polymer, siloxane polymer, and photosensitive Acrylic carboxyl polymer, phenolic resin or alkali soluble resin.
  • the material of the insulating layer in the insulating stacked structure of the TFT array substrate 310 may also include silicon compounds, inorganic materials of metal or metal oxides, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), Silicon Carbon Oxide (SiOxCy), Silicon Carbon Nitride (SiCxNy), Aluminum (A1), Magnesium (Mg), Zinc (Zn), Hafnium (Hf), Zirconium (Zr), Titanium (Ti), Tantalum (Ta), Alumina (A10x), titanium oxide (TiOx), tantalum oxide (TaOx), magnesium oxide ((MgOx), zinc oxide (ZnOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), and titanium oxide (TiOx).
  • silicon oxide SiOx
  • the trench 311 includes a sidewall 312 and a bottom wall 313.
  • a part of the uppermost insulating layer corresponding to the straight edge region SR in the insulating stack of the TFT array substrate 310 may be removed, so that the sidewall 312 and the bottom wall 313 of the trench 311 are adjacent to the uppermost layer.
  • the insulating layer that is, the insulating layer adjacent to the side wall 312 and the bottom wall 313 is the same insulating layer.
  • the uppermost insulating layer or the uppermost insulating layers corresponding to the straight edge region SR in the insulating stacked structure of the TFT array substrate 310 may be completely removed, so that the sidewall 312 of the trench 311 is adjacent to several insulating layers.
  • One of the insulating layers, the bottom wall 313 of the trench 311 is adjacent to another insulating layer of the plurality of insulating layers, that is, the insulating layer adjacent to the side wall 312 and the bottom wall 313 is a different insulating layer.
  • the lowermost insulating layer of the uppermost insulating layers may be partially removed.
  • the thin film encapsulation structure 340 covers the exposed openings of the TFT array substrate 310, the organic light emitting unit 320, the first retaining wall 331, the second retaining wall 332, and the trench 311 provided in the straight edge region SR of the ring structure.
  • the TFT array substrate 310 corresponding to the straight edge region SR is provided with a groove 311 (the area surrounded by the dotted line in FIG. 6), and the TFT array substrate 310 corresponding to the corner region CR. No grooves are provided. Since the TFT array substrate 310 corresponding to the straight edge region SR is hollowed out, and the TFT array substrate 310 of the corner region CR is not hollowed out, the height H1 of the TFT array substrate 310 in the straight edge region SR is lower than the height H2 of the corner region CR.
  • the TFT array substrate 310 of both the straight edge region SR and the corner region CR may be hollowed out, as long as the height of the TFT array substrate 310 in the straight edge region SR is lower than the height of the corner region CR.
  • the corner region CR has a complicated shape.
  • the adhesion of the thin film packaging structure 340 in the corner region CR is lower than that of the straight edge region SR.
  • the thin film packaging structure 340 is liable to fall off, so that the organic layer 342 in the thin film packaging structure 340 is liable to overflow in the corner region CR.
  • the large number of CRs in the corner area of the special-shaped screen makes this situation easier to happen.
  • a groove 311 is provided in the TFT array substrate 310 corresponding to the straight edge region SR of the gap between the two retaining walls 331 and 332, which makes the height H1 of the TFT array substrate 310 in the straight edge region SR lower than in the corner region CR. Height H2.
  • the TFT array substrate 310 forms a height difference between the straight edge region SR and the corner region CR.
  • the overflowed portion can be aided by Highly differential flow to the lower straight edge region SR. Therefore, the present application can effectively reduce the risk of the organic layer 342 of the thin film packaging structure 340 overflowing in the corner region CR.
  • FIG. 7 is a schematic diagram of an organic light emitting diode display panel according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram illustrating a cross section along a gap between two retaining walls 331 and 332 according to an embodiment of the present application.
  • several insulating layers included in the insulating stacked structure of the TFT array substrate 310 include a substrate 701, a buffer layer 702, a gate insulating layer 703, and a first interlayer insulation in order from bottom to top.
  • the material of the substrate 701 is glass or plastic.
  • the buffer layer 702 is an optional structure.
  • the second interlayer insulating layer 705 is an outermost insulating layer in the insulating laminated structure.
  • the second interlayer insulating layer 705 is dug in the straight edge region SR of the gap between the two retaining walls 331 and 332 by applying photoresist, exposure, development, and etching processes.
  • the trench is formed vacantly, so that the structure shown in FIG. 8 is formed at the gap. That is, the groove 311 is formed by digging a hole in the second interlayer insulating layer 705. In this embodiment, the depth of the trench 311 is the thickness of the second interlayer insulating layer 705.
  • an organic light emitting unit 320, two retaining walls 331 and 332, and a thin film packaging structure 340 are deposited.
  • FIG. 9 is a schematic diagram of an organic light emitting diode display panel according to another embodiment of the present application.
  • FIG. 10 is a schematic diagram illustrating a cross section along a gap between two retaining walls 331 and 332 according to another embodiment of the present application.
  • photoresist, exposure, Development, etching, and other processes hollow out the second interlayer insulating layer 705 and the first interlayer insulating layer 704 to form a trench 311, so that a structure as shown in FIG. 10 is formed at the gap.
  • the groove 311 is formed by boring the second interlayer insulating layer 705 and the first interlayer insulating layer 704.
  • the depth of the trench 311 is the total thickness of the first interlayer insulating layer 704 and the second interlayer insulating layer 705.
  • FIG. 11 is a schematic diagram of an organic light emitting diode display panel according to another embodiment of the present application.
  • FIG. 12 is a schematic diagram illustrating a cross section along a gap between two retaining walls 331 and 332 according to another embodiment of the present application.
  • photoresist, exposure, Development, etching, and other processes hollow out the second interlayer insulating layer 705, the first interlayer insulating layer 704, and the gate insulating layer 703 to form a trench 311, so that the structure shown in FIG. 12 is formed at the gap.
  • the groove 311 is formed by digging holes in the second interlayer insulating layer 705, the first interlayer insulating layer 704, and the gate insulating layer 703.
  • the depth of the trench 311 is the total thickness of the gate insulating layer 703, the first interlayer insulating layer 704, and the second interlayer insulating layer 705.
  • FIG. 13 shows a flowchart of a method for manufacturing an organic light emitting diode display panel according to the present application.
  • the display panel 300 includes a display area E and a non-display area D.
  • the display area E is used for displaying images, and the non-display area D surrounds the display area E. Please refer to FIG. 3 to FIG. 12 and FIG. 13 together.
  • the manufacturing method of the OLED display panel of the present application includes the following steps:
  • Step S1 forming a TFT array substrate.
  • a TFT array substrate 310 is formed.
  • the TFT array substrate 310 includes an insulating stacked structure on the non-display area D.
  • the insulating stacked structure includes several stacked insulating layers, such as a buffer layer 702, a gate insulating layer 703, a first An interlayer insulating layer 704 and a second interlayer insulating layer 705.
  • the TFT array substrate 310 can be formed using a general manufacturing process.
  • a plurality of organic light emitting units are disposed on the TFT array substrate on the display area.
  • a plurality of organic light emitting units 320 are disposed on the TFT array substrate 310 in the display area E.
  • the organic light emitting unit 320 may include an anode, an organic light emitting layer, and a cathode from top to bottom.
  • Step S3 removing the insulating layer in the TFT array substrate on the non-display area to form a trench.
  • the non-display area D at least one of the insulating layers included in the insulating stacked structure of the TFT array substrate 310 is removed to form a trench 311, and the trench 311 has an exposed opening.
  • the trench 311 is formed by applying photoresist, exposure, development, and etching processes to remove the uppermost layer or the uppermost layers of the insulating stack structure of the TFT array substrate 310 corresponding to the straight edge region SR. .
  • the trench 311 is formed by removing the second interlayer insulation layer 705, the trench 311 is formed by removing the second interlayer insulation layer 705 and the first interlayer insulation layer 704, and the trench 311 is formed by removing the second interlayer insulation
  • the layer 705, the first interlayer insulating layer 704, and the gate insulating layer 703 are formed.
  • the order of steps S2 and S3 can be reversed.
  • a first retaining wall and a second retaining wall are provided on the non-display area.
  • the first retaining wall and the second retaining wall form a ring structure, and the groove is located in the straight edge region of the ring structure.
  • a first blocking wall 331 and a second blocking wall 332 are disposed on the TFT array substrate 310 in the non-display area D.
  • the first retaining wall 331 and the second retaining wall 332 can be made by a general manufacturing process.
  • the first retaining wall 331 and the second retaining wall 332 constitute an annular structure.
  • a straight edge region SR and a corner region CR are defined on the annular structure.
  • the groove 311 is provided in the straight edge region SR of the annular structure and is located in the first retaining wall 331.
  • the second retaining wall 332 is provided on the non-display area.
  • Step S5 forming a thin film packaging structure.
  • a thin film encapsulation structure 340 having one or more organic layers and one or more inorganic layers is formed to cover the TFT array substrate 310, the organic light emitting unit 320, the first retaining wall 331, and the second retaining wall. 332 and the exposed opening of the trench 311 provided in the straight edge region SR of the annular structure.
  • the thin-film encapsulation structure can be made by a general manufacturing process.
  • the height H1 of the TFT array substrate 310 in the straight edge region SR is lower than the height H2 of the corner region CR.
  • the overflowed portion can be flowed to the lower straight edge region SR with a height difference, thereby reducing the risk of the organic layer 342 directly overflowing.

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Abstract

一种OLED显示面板及其制造方法，所述OLED显示面板包括一TFT阵列基板、若干个有机发光单元、一第一挡墙、一第二挡墙、一沟槽及一薄膜封装结构。有机发光单元设于显示区域中，第一挡墙和第二挡墙设于非显示区域中。沟槽形成于对应第一挡墙和第二挡墙间的空隙的位置，设置于TFT阵列基板之绝缘层层叠构中且具有一暴露的开口。薄膜封装结构覆盖上述元件。特别地，沟槽设置于直边区，因而TFT阵列基板在直边区和拐角区形成高度差。本申请能够有效降低薄膜封装结构的有机层在拐角区溢出的风险。

Description

有机发光二极管显示面板及其制造方法 技术领域
本申请涉及一种显示技术，特别涉及一种有机发光二极管（organic light emitting diode）显示面板及其制造方法。
 背景技术
有机发光二极管显示器和液晶显示器（liquid crystal display, LCD）相比，最大的优势在于OLED显示器可实现柔性显示。然而，OLED器件对水氧特别敏感，为了防止水氧入侵，同时达到柔性显示的效果，传统工艺会以一薄膜封装结构模封OLED器件。
一般来说，薄膜封装结构由交叠的有机层和无机层构成，薄膜封装结构中的有机层具有一定的流动性，为将其限定在一定区域内，通常会在显示区域外围形成一圈或多圈挡墙（dam）。
图1显示一种现有的OLED显示面板100的示意图。如图1所示，显示面板100分成非显示区域D和显示区域E，挡墙110设置在非显示区域D中，挡墙110定义了薄膜封装结构中有机层的边界。
图2显示一种现有的异形屏200的示意图。请一并参阅图1和图2，挡墙100为封闭的环形结构，其具有一直边区（straight line region）SR和一拐角区（corner region）CR。图1所示的挡墙有四个拐角区CR，图2所示的异形屏200中拐角区CR的数量和形貌则更加复杂。
由于拐角区CR的形状较直边区SR的形状相对复杂，现有技术中存在薄膜封装结构的有机层从拐角区CR溢出的问题，导致水氧入侵，OLED器件无法获得良好的水氧防护，降低OLED显示器的寿命。因异形屏200的拐角区CR数量多，薄膜封装结构的有机层溢出的问题更为严重。
 技术问题
本申请的目的在于提供一种有机发光二极管显示面板及其制造方法，以降低薄膜封装结构的有机层溢出的风险。
 技术解决方案
为实现上述目的，本申请一方面提供一种有机发光二极管显示面板，包括一显示区域和一非显示区域，所述显示区域用于显示影像，所述非显示区域围绕所述显示区域，所述显示面板包括：一薄膜晶体管阵列基板，其在所述非显示区域上包括一绝缘层叠构，所述绝缘层叠构包括若干个层叠的绝缘层；若干个有机发光单元，设置于所述薄膜晶体管阵列基板上，位于所述显示区域中；一第一挡墙，设置于所述薄膜晶体管阵列基板上，所述第一挡墙位于所述非显示区域且围绕所述显示区域；一第二挡墙，设置于所述薄膜晶体管阵列基板上，所述第二挡墙位于所述非显示区域且围绕所述第一挡墙，所述第一挡墙和所述第二挡墙相距一段距离，所述第一挡墙包括一第一闭环结构，所述第二挡墙包括一第二闭环结构，所述第一闭环结构设置于所述第二闭环结构内，所述第一挡墙和所述第二挡墙构成一环形结构，在所述环形结构上定义有一直边区和一拐角区；一沟槽，设置于所述环形结构的所述直边区，设置于所述第一闭环结构和所述第二闭环结构之间，所述沟槽设置于所述薄膜晶体管阵列基板之所述绝缘层叠构中，具有一暴露之开口，所述薄膜晶体管阵列基板在所述直边区的高度低于在所述拐角区的高度；以及一薄膜封装结构，具有交叠的一或多个有机层和一或多个无机层，所述薄膜封装结构覆盖所述薄膜晶体管阵列基板、所述若干个有机发光单元、所述第一挡墙、所述第二挡墙及设置于所述环形结构之所述直边区的所述沟槽暴露之所述开口。
本申请实施例中，所述薄膜晶体管阵列基板的所述绝缘层叠构所包括的若干个绝缘层依序包括一栅极绝缘层、一第一层间绝缘层及一第二层间绝缘层，所述第二层间绝缘层为所述绝缘层叠构中最外侧的绝缘层。
本申请实施例中，所述沟槽的深度为所述第二层间绝缘层的厚度。
本申请实施例中，所述沟槽的深度为所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
本申请实施例中，所述沟槽的深度为所述栅极绝缘层、所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
本申请另一方面提供一种有机发光二极管显示面板，包括一显示区域和一非显示区域，所述显示区域用于显示影像，所述非显示区域围绕所述显示区域，所述显示面板包括：一薄膜晶体管阵列基板，其在所述非显示区域上包括一绝缘层叠构，所述绝缘层叠构包括若干个层叠的绝缘层；若干个有机发光单元，设置于所述薄膜晶体管阵列基板上，位于所述显示区域中；一第一挡墙，设置于所述薄膜晶体管阵列基板上，所述第一挡墙位于所述非显示区域且围绕所述显示区域；一第二挡墙，设置于所述薄膜晶体管阵列基板上，所述第二挡墙位于所述非显示区域且围绕所述第一挡墙，所述第一挡墙和所述第二挡墙相距一段距离，所述第一挡墙和所述第二挡墙构成一环形结构，在所述环形结构上定义有一直边区和一拐角区；一沟槽，设置于所述环形结构的所述直边区，位于所述第一挡墙和所述第二挡墙之间，所述沟槽设置于所述薄膜晶体管阵列基板之所述绝缘层叠构中，具有一暴露之开口；以及一薄膜封装结构，具有交叠的一或多个有机层和一或多个无机层，所述薄膜封装结构覆盖所述薄膜晶体管阵列基板、所述若干个有机发光单元、所述第一挡墙、所述第二挡墙及设置于所述环形结构之所述直边区的所述沟槽暴露之所述开口。
本申请实施例中，所述第一挡墙包括一第一闭环结构，所述第二挡墙包括一第二闭环结构，所述第一闭环结构设置于所述第二闭环结构内，所述沟槽设置于所述第一闭环结构和所述第二闭环结构之间。
本申请实施例中，所述薄膜晶体管阵列基板在所述直边区的高度低于在所述拐角区的高度。
本申请实施例中，所述沟槽具有一侧壁及一底壁，所述沟槽的所述侧壁及所述底壁邻接所述绝缘层叠构的所述若干个绝缘层中的至少一绝缘层。
本申请实施例中，所述沟槽具有一侧壁及一底壁，所述沟槽的所述侧壁邻接所述绝缘层叠构的所述若干个绝缘层中的其中一绝缘层，所述沟槽的所述底壁邻接所述绝缘层叠构的所述若干个绝缘层中的另一绝缘层。
本申请实施例中，所述薄膜晶体管阵列基板的所述绝缘层叠构所包括的若干个绝缘层依序包括一栅极绝缘层、一第一层间绝缘层及一第二层间绝缘层，所述第二层间绝缘层为所述绝缘层叠构中最外侧的绝缘层。
本申请实施例中，所述沟槽的深度为所述第二层间绝缘层的厚度。
本申请实施例中，所述沟槽的深度为所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
本申请实施例中，所述沟槽的深度为所述栅极绝缘层、所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
本申请再一方面提供一种有机发光二极管显示面板的制造方法，所述显示面板包括一显示区域和一非显示区域，所述显示区域用于显示影像，所述非显示区域围绕所述显示区域，所述方法包括：形成一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板在所述非显示区域上包括一绝缘层叠构，所述绝缘层叠构包括若干个层叠的绝缘层；于所述显示区域中、所述薄膜晶体管阵列基板上设置若干个有机发光单元；去除所述非显示区域中、所述薄膜晶体管阵列基板之所述绝缘层叠构所包括的所述若干个绝缘层中的至少一绝缘层，以形成一沟槽，所述沟槽具有一暴露之开口；于所述非显示区域中、所述薄膜晶体管阵列基板上设置一第一挡墙和一第二挡墙，所述第一挡墙和所述第二挡墙构成一环形结构，在所述环形结构上定义有一直边区和一拐角区，所述沟槽设置于所述环形结构的所述直边区，且位于所述第一挡墙和所述第二挡墙之间；形成具有交叠的一或多个有机层和一或多个无机层的一薄膜封装结构，以覆盖所述薄膜晶体管阵列基板、所述若干个有机发光单元、所述第一挡墙、所述第二挡墙及设置于所述环形结构之所述直边区的所述沟槽暴露之所述开口。
本申请实施例中，所述第一挡墙包括一第一闭环结构，所述第二挡墙包括一第二闭环结构，所述第一闭环结构设置于所述第二闭环结构内，所述沟槽设置于所述第一闭环结构和所述第二闭环结构之间。
本申请实施例中，所述薄膜晶体管阵列基板在所述直边区的高度低于在所述拐角区的高度。
本申请实施例中，所述薄膜晶体管阵列基板的所述绝缘层叠构所包括的若干个绝缘层依序包括一栅极绝缘层、一第一层间绝缘层及一第二层间绝缘层，所述第二层间绝缘层为所述绝缘层叠构中最外侧的绝缘层。
本申请实施例中，所述沟槽的深度为所述第二层间绝缘层的厚度。
本申请实施例中，所述沟槽的深度为所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
 有益效果
本申请中，对应两道挡墙和之间空隙的直边区的TFT阵列基板设置有一道沟槽，这使得TFT阵列基板在直边区的高度低于在拐角区的高度。也就是，TFT阵列基板在直边区和拐角区形成高度差，当薄膜封装结构中有机层从拐角区外溢到两道挡墙之间时，溢出的部分可以借助高度差分流到较低的直边区。因此，本申请能够有效降低薄膜封装结构的有机层在拐角区溢出的风险。
 附图说明
为让本申请的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
图1显示一种现有的OLED显示面板的示意图。
图2显示一种现有的异形屏的示意图。
图3显示根据本申请的一种有机发光二极管显示面板的示意图。
图4显示图3中沿I-I虚线的剖面图。
图5显示图3中沿II-II虚线的剖面图。
图6显示图3中沿III-III虚线的剖面图。
图7显示根据本申请一实施例的有机发光二极管显示面板的示意图。
图8显示根据本申请一实施例的沿两挡墙间的空隙的剖面的示意图。
图9显示根据本申请另一实施例的有机发光二极管显示面板的示意图。
图10显示根据本申请另一实施例的沿两挡墙间的空隙的剖面的示意图。
图11显示根据本申请又一实施例的有机发光二极管显示面板的示意图。
图12显示根据本申请又一实施例的沿两挡墙间的空隙的剖面的示意图。
图13显示根据本申请的一种有机发光二极管显示面板的制造方法的流程图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，本申请说明书所使用的词语“实施例”意指用作实例、示例或例证，并不用于限定本申请。
图3显示根据本申请的一种有机发光二极管（organic light emitting diode, OLED）显示面板300的示意图。图4显示图3中沿I-I虚线的剖面图。图5显示图3中沿II-II虚线的剖面图。图6显示图3中沿III-III虚线的剖面图。
OLED显示面板300包括一非显示区域D和一显示区域E。显示区域E为一有效显示区域。显示区域E具有由若干条扫描线（未图示）和若干条数据线（未图示）交错而成的若干个像素（未图示），用于显示影像。非显示区域D围绕显示区域E，非显示区域D用于设置例如一显示芯片（未图示）及一外围走线区（未图示）。
OLED显示面板300包括一薄膜晶体管（thin-film transistor, TFT）阵列基板310、设置于显示区域E的若干个有机发光单元320、设置于非显示区域D的一第一挡墙331和一第二挡墙332、以及一薄膜封装结构340。
TFT阵列基板310在显示区域E上包括若干个薄膜晶体管（未图示），用以驱动有机发光单元320。每个薄膜晶体管包括一栅极、一源极和一汲极。若干个有机发光单元320设置在TFT阵列基板310上（图5及图6仅示出一个有机发光单元320）。每个有机发光单元320包括一阳极、一阴极及设置在阳极和阴极间的有机发光层。在一些实施例中，薄膜晶体管的栅极连接扫描线，源极连接数据线，汲极连接有机发光单元320的阳极，以有源方式驱动有机发光单元320。
TFT阵列基板310在非显示区域D上具有一绝缘层叠构，其包括若干个层叠的绝缘层（见图7、9及11）。第一挡墙331和第二挡墙332设置在TFT阵列基板310上，位于非显示区域D。也就是，第一挡墙331和第二挡墙332设置在非显示区域D中的TFT阵列基板310之最上一层的绝缘层上。第一挡墙331围绕显示区域E，第二挡墙332围绕第一挡墙331，第一挡墙331和第二挡墙332彼此相距一段距离。第一挡墙331和第二挡墙332为凸起结构，两者之间形成一空隙。
薄膜封装结构340具有交叠的一或多个有机层和一或多个无机层，有机层主要用于提供OLED显示面板300柔性，无机层主要用于防止水氧渗透到OLED显示面板300。薄膜封装结构340的有机层和无机层的数量可视需要调整。于一实施例中，薄膜封装结构340包括一第一无机层341、一有机层342及一第二无机层343。有机层342覆盖显示区域E中的有机发光单元320，第一无机层341和第二无机层343则延伸到非显示区域D，覆盖第一挡墙331和第二挡墙332。
第一挡墙331主要用于界定有机层342的边界。有机层342使用闪蒸法在沉积单体后暴露于紫外光来固化单体而形成，第二挡墙332主要用于避免在形成有机层342时，单体沉积在于不期望沉积的区域，而造成黏合性降低，水氧渗透的问题。
第一挡墙331和第二挡墙332可采用一般的制程工艺制成。第一挡墙331和第二挡墙332的材料可以彼此相同或不同。第一挡墙331和第二挡墙332的材料可以包括光致抗蚀剂、聚丙烯酸类树脂、聚酰亚胺类树脂和丙烯酸类树脂的有机材料，或者硅化合物的无机材料。
薄膜封装结构340可采用一般的制程工艺制成。第一无机层341和第二无机层343的材料可以彼此相同或不同。第一无机层341和第二无机层343的材料可以包括氮化硅、氮化铝、氮化锆、氮化钛、氮化铪、氮化钽、氧化硅、氧化铝、氧化钛、氧化锡、氧化铈和氮氧化硅。有机层342的材料可以包括丙烯酸树脂、甲基丙烯酸树脂、聚异戊二烯、乙烯树脂、环氧树脂、聚氨酯树脂、纤维素树脂、二萘嵌苯树脂和其它聚合物材料。
第一挡墙331和第二挡墙332构成一环形结构，例如一封闭的环形结构。具体来说，第一挡墙331包括一第一闭环结构，第二挡墙332包括一第二闭环结构，第一闭环结构设置于所述第二闭环结构内。也就是，第二闭环结构所围绕的面积大于第一闭环结构围绕的面积。上述之空隙位于第一闭环结构和第二闭环结构之间。
第一挡墙331和第二挡墙332构成的环形结构上定义有一直边区（straight line region）SR和一拐角区（corner region）CR，如第3图所示。直边区SR对应显示区域E的直边，拐角区CR都应显示区域E的角落。拐角区CR对应呈一定角度的折线或者弧线，或者两者的组合。
在第一挡墙331和第二挡墙332之间，于环形结构的直边区SR设置有一沟槽311。也就是，沟槽311设置于直边区SR的第一闭环结构和第二闭环结构之间。沟槽311是通过在对应两道挡墙331和332间的空隙的位置，将直边区SR的TFT阵列基板310挖空而形成的。在挖孔后，沟槽311具有一暴露之开口。
具体来说，沟槽311是通过涂布光阻、曝光、显影、刻蚀等流程，将对应直边区SR之TFT阵列基板310的绝缘层叠构中的最上面一层或最上面几层绝缘层去除而形成的。也就是，至少一绝缘层被去除以形成沟槽311。
TFT阵列基板310可采用一般的制程工艺制成。TFT阵列基板310之绝缘层叠构中的绝缘层的材料可以包括有机材料，例如光致抗蚀剂、丙烯酸聚合物、聚酰亚胺聚合物、聚酰胺聚合物、硅氧烷聚合物、含有光敏丙烯酸羧基的聚合物、酚醛树脂或碱溶性树脂。TFT阵列基板310之绝缘层叠构中的绝缘层的材料也可以包括硅化合物、金属或金属氧化物的无机材料，例如氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅 (SiOxNy)、碳氧化硅(SiOxCy)、碳氮化硅(SiCxNy)、铝(A1)、镁(Mg)、锌（Zn)、铪(Hf)、锆 (Zr)、钛(Ti)、钽(Ta)、氧化铝(A10x)、氧化钛(TiOx)、氧化钽(TaOx)、氧化镁（(MgOx)、氧化锌(ZnOx)、氧化铪(HfOx)、氧化锆(ZrOx)和氧化钛(TiOx)。
具体来说，沟槽311包括一侧壁312和一底壁313。于一实施例中，可将TFT阵列基板310的绝缘层叠构中对应直边区SR的最上面一层绝缘层的一部分去除，使得沟槽311的侧壁312及底壁313都邻接最上面一层绝缘层，也就是侧壁312和底壁313邻接的绝缘层是相同的绝缘层。于另一实施例中，可将TFT阵列基板310的绝缘层叠构中对应直边区SR最上面一层绝缘层或最上面几层绝缘层全部去除，使得沟槽311的侧壁312邻接若干个绝缘层中的其中一绝缘层，311沟槽的底壁313邻接若干个绝缘层中的另一绝缘层，也就是，侧壁312和底壁313邻接的绝缘层是不同的绝缘层。于再一实施例中，最上面几层绝缘层中最下面的绝缘层也可被部分地去除。
薄膜封装结构340覆盖TFT阵列基板310、有机发光单元320、第一挡墙331、第二挡墙332及设置于环形结构之直边区SR的沟槽311暴露之开口。
如图4、图5和图6所示，特别是图6，对应直边区SR的TFT阵列基板310设置了凹槽311（图6虚线围绕之区域），而对应拐角区CR的TFT阵列基板310没有设置任何凹槽。由于对应直边区SR的TFT阵列基板310进行了挖空，而拐角区CR的TFT阵列基板310没有挖空，因此TFT阵列基板310在直边区SR的高度H1低于在拐角区CR的高度H2。在一些实施例中，也可对直边区SR和拐角区CR的TFT阵列基板310都进行挖空，只要TFT阵列基板310在直边区SR的高度低于在拐角区CR的高度即可。
拐角区CR形状复杂，薄膜封装结构340在拐角区CR的黏合性较直边区SR不佳，薄膜封装结构340容易脱落，使得薄膜封装结构340中的有机层342容易在拐角区CR溢出。异形屏的拐角区CR数量多，使得这种情况更容易发生。本申请中，对应两道挡墙331和332之间空隙的直边区SR的TFT阵列基板310设置有一道沟槽311，这使得TFT阵列基板310在直边区SR的高度H1低于在拐角区CR的高度H2。也就是，TFT阵列基板310在直边区SR和拐角区CR形成高度差，当薄膜封装结构340中有机层342从拐角区CR外溢到两道挡墙331和332之间时，溢出的部分可以借助高度差分流到较低的直边区SR。因此，本申请能够有效降低薄膜封装结构340的有机层342在拐角区CR溢出的风险。
图7显示根据本申请一实施例的有机发光二极管显示面板的示意图。图8显示根据本申请一实施例的沿两挡墙331和332间的空隙的剖面的示意图。于非显示区域D，TFT阵列基板310的绝缘层叠构所包括的若干个绝缘层由下而上依序包括一基底701、一缓冲层702、一栅极绝缘层703、一第一层间绝缘层704及一第二层间绝缘层705。基底701的材料为玻璃或塑料。缓冲层702为一可选的结构。第二层间绝缘层705为绝缘层叠构中最外侧的绝缘层。
当第二层间绝缘层705沉积完成后，在两道挡墙331和332空隙的直边区SR，通过涂布光阻、曝光、显影、刻蚀等流程将第二层间绝缘层705进行挖空，形成沟槽311，这样在空隙处就形成如图8的结构。也就是，凹槽311是对第二层间绝缘层705挖孔而形成。本实施例中，沟槽311的深度为第二层间绝缘层705的厚度。形成沟槽311后，再沉积有机发光单元320、两道挡墙331和332以及薄膜封装结构340。
图9显示根据本申请另一实施例的有机发光二极管显示面板的示意图。图10显示根据本申请另一实施例的沿两挡墙331和332间的空隙的剖面的示意图。相对于图7和图8的实施例，本实施例中，当第二层间绝缘层705沉积完成后，在两道挡墙331和332空隙的直边区SR，通过涂布光阻、曝光、显影、刻蚀等流程将第二层间绝缘层705和第一层间绝缘层704进行挖空，形成沟槽311，这样在空隙处就形成如图10的结构。也就是，凹槽311是对第二层间绝缘层705和第一层间绝缘层704挖孔而形成。本实施例中，沟槽311的深度为第一层间绝缘层704和第二层间绝缘层705的总厚度。
图11显示根据本申请又一实施例的有机发光二极管显示面板的示意图。图12显示根据本申请又一实施例的沿两挡墙331和332间的空隙的剖面的示意图。相对于图7和图8的实施例，本实施例中，当第二层间绝缘层705沉积完成后，在两道挡墙331和332空隙的直边区SR，通过涂布光阻、曝光、显影、刻蚀等流程将第二层间绝缘层705、第一层间绝缘层704和栅极绝缘层703进行挖空，形成沟槽311，这样在空隙处就形成如图12的结构。也就是，凹槽311是对第二层间绝缘层705、第一层间绝缘层704和栅极绝缘层703挖孔而形成。本实施例中，沟槽311的深度为栅极绝缘层703、第一层间绝缘层704和第二层间绝缘层705的总厚度。
图13显示根据本申请的一种有机发光二极管显示面板的制造方法的流程图。如上所述，显示面板300包括一显示区域E和一非显示区域D，显示区域E用于显示影像，非显示区域D围绕显示区域E。请配合图3至图12，一并参阅图13，本申请的OLED显示面板的制造方法包括如下步骤：
步骤S1，形成一TFT阵列基板。具体地，形成一TFT阵列基板310，TFT阵列基板310在非显示区域D上包括一绝缘层叠构，绝缘层叠构包括若干个层叠的绝缘层，如缓冲层702、栅极绝缘层703、第一层间绝缘层704和第二层间绝缘层705。TFT阵列基板310可采用一般的制成工艺形成。
步骤S2，于显示区域上，在TFT阵列基板上设置若干个有机发光单元。具体地，于显示区域E中、TFT阵列基板310上设置若干个有机发光单元320。有机发光单元320由上而下可包括一阳极、一有机发光层及一阴极。
步骤S3，于非显示区域上，去除TFT阵列基板中的绝缘层，以形成一沟槽。具体地，去除非显示区域D中、TFT阵列基板310之绝缘层叠构所包括的若干个绝缘层中的至少一绝缘层，以形成一沟槽311，沟槽311具有一暴露之开口。沟槽311是通过涂布光阻、曝光、显影、刻蚀等流程，将对应直边区SR之TFT阵列基板310的绝缘层叠构中的最上面一层或最上面几层绝缘层去除而形成的。例如，沟槽311通过去除第二层间绝缘层705而形成，沟槽311通过去除第二层间绝缘层705和第一层间绝缘层704而形成，沟槽311通过去除第二层间绝缘层705、第一层间绝缘层704和栅极绝缘层703而形成。步骤S2和S3的顺序可以调换。
步骤S4，于非显示区域上，设置一第一挡墙和一第二挡墙，第一挡墙和第二挡墙构成一环形结构，沟槽位于环形结构的直边区。具体地，于非显示区域D中、TFT阵列基板310上设置一第一挡墙331和一第二挡墙332。第一挡墙331和第二挡墙332可采用一般的制程工艺制成。第一挡墙331和第二挡墙332构成一环形结构，在环形结构上定义有一直边区SR和一拐角区CR，沟槽311设置于环形结构的直边区SR，且位于第一挡墙331和第二挡墙332之间。
步骤S5，形成一薄膜封装结构。具体地，形成具有交叠的一或多个有机层和一或多个无机层的一薄膜封装结构340，以覆盖TFT阵列基板310、有机发光单元320、第一挡墙331、第二挡墙332及设置于环形结构之直边区SR的沟槽311暴露之开口。薄膜封装结构可采用一般的制程工艺制成。
本申请的OLED显示面板的制造方法中，TFT阵列基板310在直边区SR的高度H1低于在拐角区CR的高度H2。当薄膜封装结构340中有机层342从拐角区CR外溢到两道挡墙331和332之间时，溢出的部分可以借助高度差分流到较低的直边区SR，降低有机层342直接溢出的风险。
本申请的OLED显示面板的制造方法的其他技术细节可参照上文对OLED显示面板的描述，在此不再赘述。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种有机发光二极管显示面板，包括一显示区域和一非显示区域，所述显示区域用于显示影像，所述非显示区域围绕所述显示区域，所述显示面板包括：
    一薄膜晶体管阵列基板，其在所述非显示区域上包括一绝缘层叠构，所述绝缘层叠构包括若干个层叠的绝缘层；
    若干个有机发光单元，设置于所述薄膜晶体管阵列基板上，位于所述显示区域中；
    一第一挡墙，设置于所述薄膜晶体管阵列基板上，所述第一挡墙位于所述非显示区域且围绕所述显示区域；
    一第二挡墙，设置于所述薄膜晶体管阵列基板上，所述第二挡墙位于所述非显示区域且围绕所述第一挡墙，所述第一挡墙和所述第二挡墙相距一段距离，所述第一挡墙包括一第一闭环结构，所述第二挡墙包括一第二闭环结构，所述第一闭环结构设置于所述第二闭环结构内，所述第一挡墙和所述第二挡墙构成一环形结构，在所述环形结构上定义有一直边区和一拐角区；
    一沟槽，设置于所述环形结构的所述直边区，设置于所述第一闭环结构和所述第二闭环结构之间，所述沟槽设置于所述薄膜晶体管阵列基板之所述绝缘层叠构中，具有一暴露之开口，所述薄膜晶体管阵列基板在所述直边区的高度低于在所述拐角区的高度；以及
    一薄膜封装结构，具有交叠的一或多个有机层和一或多个无机层，所述薄膜封装结构覆盖所述薄膜晶体管阵列基板、所述若干个有机发光单元、所述第一挡墙、所述第二挡墙及设置于所述环形结构之所述直边区的所述沟槽暴露之所述开口。
  2. 根据权利要求1所述的显示面板，其中所述薄膜晶体管阵列基板的所述绝缘层叠构所包括的若干个绝缘层依序包括一栅极绝缘层、一第一层间绝缘层及一第二层间绝缘层，所述第二层间绝缘层为所述绝缘层叠构中最外侧的绝缘层。
  3. 根据权利要求2所述的显示面板，其中所述沟槽的深度为所述第二层间绝缘层的厚度。
  4. 根据权利要求2所述的显示面板，其中所述沟槽的深度为所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
  5. 根据权利要求2所述的显示面板，其中所述沟槽的深度为所述栅极绝缘层、所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
  6. 一种有机发光二极管显示面板，包括一显示区域和一非显示区域，所述显示区域用于显示影像，所述非显示区域围绕所述显示区域，所述显示面板包括：
    一薄膜晶体管阵列基板，其在所述非显示区域上包括一绝缘层叠构，所述绝缘层叠构包括若干个层叠的绝缘层；
    若干个有机发光单元，设置于所述薄膜晶体管阵列基板上，位于所述显示区域中；
    一第一挡墙，设置于所述薄膜晶体管阵列基板上，所述第一挡墙位于所述非显示区域且围绕所述显示区域；
    一第二挡墙，设置于所述薄膜晶体管阵列基板上，所述第二挡墙位于所述非显示区域且围绕所述第一挡墙，所述第一挡墙和所述第二挡墙相距一段距离，所述第一挡墙和所述第二挡墙构成一环形结构，在所述环形结构上定义有一直边区和一拐角区；
    一沟槽，设置于所述环形结构的所述直边区，位于所述第一挡墙和所述第二挡墙之间，所述沟槽设置于所述薄膜晶体管阵列基板之所述绝缘层叠构中，具有一暴露之开口；以及
    一薄膜封装结构，具有交叠的一或多个有机层和一或多个无机层，所述薄膜封装结构覆盖所述薄膜晶体管阵列基板、所述若干个有机发光单元、所述第一挡墙、所述第二挡墙及设置于所述环形结构之所述直边区的所述沟槽暴露之所述开口。
  7. 根据权利要求6所述的显示面板，其中所述第一挡墙包括一第一闭环结构，所述第二挡墙包括一第二闭环结构，所述第一闭环结构设置于所述第二闭环结构内，所述沟槽设置于所述第一闭环结构和所述第二闭环结构之间。
  8. 根据权利要求6所述的显示面板，其中所述薄膜晶体管阵列基板在所述直边区的高度低于在所述拐角区的高度。
  9. 根据权利要求6所述的显示面板，其中所述沟槽具有一侧壁及一底壁，所述沟槽的所述侧壁及所述底壁邻接所述绝缘层叠构的所述若干个绝缘层中的至少一绝缘层。
  10. 根据权利要求6所述的显示面板，其中所述沟槽具有一侧壁及一底壁，所述沟槽的所述侧壁邻接所述绝缘层叠构的所述若干个绝缘层中的其中一绝缘层，所述沟槽的所述底壁邻接所述绝缘层叠构的所述若干个绝缘层中的另一绝缘层。
  11. 根据权利要求6所述的显示面板，其中所述薄膜晶体管阵列基板的所述绝缘层叠构所包括的若干个绝缘层依序包括一栅极绝缘层、一第一层间绝缘层及一第二层间绝缘层，所述第二层间绝缘层为所述绝缘层叠构中最外侧的绝缘层。
  12. 根据权利要求11所述的显示面板，其中所述沟槽的深度为所述第二层间绝缘层的厚度。
  13. 根据权利要求11所述的显示面板，其中所述沟槽的深度为所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
  14. 根据权利要求11所述的显示面板，其中所述沟槽的深度为所述栅极绝缘层、所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
  15. 一种有机发光二极管显示面板的制造方法，所述显示面板包括一显示区域和一非显示区域，所述显示区域用于显示影像，所述非显示区域围绕所述显示区域，所述方法包括：
    形成一薄膜晶体管阵列基板，所述薄膜晶体管阵列基板在所述非显示区域上包括一绝缘层叠构，所述绝缘层叠构包括若干个层叠的绝缘层；
    于所述显示区域中、所述薄膜晶体管阵列基板上设置若干个有机发光单元；
    去除所述非显示区域中、所述薄膜晶体管阵列基板之所述绝缘层叠构所包括的所述若干个绝缘层中的至少一绝缘层，以形成一沟槽，所述沟槽具有一暴露之开口；
    于所述非显示区域中、所述薄膜晶体管阵列基板上设置一第一挡墙和一第二挡墙，所述第一挡墙和所述第二挡墙构成一环形结构，在所述环形结构上定义有一直边区和一拐角区，所述沟槽设置于所述环形结构的所述直边区，且位于所述第一挡墙和所述第二挡墙之间；
    形成具有交叠的一或多个有机层和一或多个无机层的一薄膜封装结构，以覆盖所述薄膜晶体管阵列基板、所述若干个有机发光单元、所述第一挡墙、所述第二挡墙及设置于所述环形结构之所述直边区的所述沟槽暴露之所述开口。
  16. 根据权利要求15所述的制造方法，其中所述第一挡墙包括一第一闭环结构，所述第二挡墙包括一第二闭环结构，所述第一闭环结构设置于所述第二闭环结构内，所述沟槽设置于所述第一闭环结构和所述第二闭环结构之间。
  17. 根据权利要求15所述的制造方法，其中所述薄膜晶体管阵列基板在所述直边区的高度低于在所述拐角区的高度。
  18. 根据权利要求15所述的制造方法，其中所述薄膜晶体管阵列基板的所述绝缘层叠构所包括的若干个绝缘层依序包括一栅极绝缘层、一第一层间绝缘层及一第二层间绝缘层，所述第二层间绝缘层为所述绝缘层叠构中最外侧的绝缘层。
  19. 根据权利要求18所述的制造方法，其中所述沟槽的深度为所述第二层间绝缘层的厚度。
  20. 根据权利要求18所述的制造方法，其中所述沟槽的深度为所述第一层间绝缘层和所述第二层间绝缘层的总厚度。
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