WO2020034631A1 - 一种基于机器学习的电路路径延时波动预测方法 - Google Patents

一种基于机器学习的电路路径延时波动预测方法 Download PDF

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WO2020034631A1
WO2020034631A1 PCT/CN2019/077798 CN2019077798W WO2020034631A1 WO 2020034631 A1 WO2020034631 A1 WO 2020034631A1 CN 2019077798 W CN2019077798 W CN 2019077798W WO 2020034631 A1 WO2020034631 A1 WO 2020034631A1
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path
delay
path delay
circuit
predicting
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曹鹏
徐冰倩
郭静静
李梦潇
杨军
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东南大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2882—Testing timing characteristics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • G06F18/20—Analysing
    • G06F18/24—Classification techniques
    • G06F18/243—Classification techniques relating to the number of classes
    • G06F18/24323—Tree-organised classifiers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/01—Probabilistic graphical models, e.g. probabilistic networks

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  • the invention relates to the field of integrated circuits, and in particular, to a method for predicting the delay of a circuit path.
  • near-threshold circuits have significant energy efficiency advantages, which has aroused great interest in industry and academia.
  • near-threshold PVT deviations cause path delay deviations to multiply, making the circuit performance serious Deterioration greatly offsets the energy efficiency dividend brought by the near-threshold circuit.
  • the path delay is calculated by establishing a feature library for each combinational logic unit in the path, but this method has drawbacks.
  • the delay deviation of the unit under a near threshold is non-Gaussian. It is difficult to calculate the path delay by the linear accumulation method.
  • the path delay is too pessimistic due to the failure to consider the correlation of the unit delay time.
  • the object of the present invention is to provide a method for predicting the delay of a circuit path fluctuation based on machine learning with high accuracy and low running time.
  • the method for predicting a delay of a circuit path based on machine learning based on the present invention includes the following steps:
  • S2 Generate a random path by enumerating the values of the randomization parameters, obtain the maximum path delay by performing Monte Carlo simulation on the random path, select a reliable path through the 3 ⁇ standard, and use the sample feature quantity and path delay of the reliable path as the sample set ;
  • the sample characteristic amount in step S1 includes the number of circuit path stages, the type of each stage unit, the size of each stage unit, the polarity of each stage unit, the load capacitance of each stage, and the path intrinsic delay.
  • step S3 is established by the following steps:
  • the path delay prediction model is established by clustering the data of n trees to predict the new path delay.
  • the average value of the clustering result is the path delay output by the path delay prediction model.
  • step S3 includes: continuously increasing the number of decision trees and the number of variables at each node, and selecting a parameter value optimization model when the error is the smallest.
  • step S4 includes the following processes: verifying the accuracy of the path delay prediction model by calculating the average error of the training set, the average error of the test set, and the maximum absolute error; observing the change of the average error of the test set by changing the number of samples in the test set To verify the stability of the path delay prediction model.
  • generating a random path in the step S2 includes the following process: selecting and randomizing the circuit structure parameters and parasitic parameters of the set path to generate a SPICE netlist file corresponding to the random path; the circuit structure parameters include the number of circuit path stages, each stage Unit type, unit size of each stage, path input signal polarity, parasitic parameters include load capacitance of each stage.
  • the present invention discloses a method for predicting a circuit path delay fluctuation based on machine learning, establishes a path delay prediction model, and obtains timing analysis results. It has the advantages of high accuracy and low running time, and accuracy and efficiency in timing analysis. Significant advantages. Taking a 5-level path at 0.6V, 25 ° C process angle as an example, the average error of the training set and test set is less than 5%, and the lowest can reach 1.27% and 2.83%, respectively.
  • FIG. 1 is a flowchart of a method in a specific embodiment of the present invention
  • FIG. 2 is a flowchart of establishing a path delay prediction model in a specific embodiment of the present invention
  • FIG. 3 (a) shows the influence of adjusting the number of decision trees under different voltages on model accuracy in a specific embodiment of the present invention
  • FIG. 3 (b) shows the influence of adjusting the number of decision trees at different temperatures on model accuracy in a specific embodiment of the present invention
  • FIG. 3 (c) shows the influence of adjusting the number of decision trees on the accuracy of the model under different path levels in a specific embodiment of the present invention
  • FIG. 4 (a) shows the effect of adjusting the number of variables at each node on the accuracy of the model in different embodiments of the present invention
  • Figure 4 (b) shows the effect of adjusting the number of variables at each node on the accuracy of the model in different embodiments of the present invention
  • FIG. 4 (c) shows the effect of the 5-level circuit adjusting the number of variables at each node on the accuracy of the model in a specific embodiment of the present invention
  • FIG. 4 (d) shows the influence of the number of variables at each node on the accuracy of the model in a 10-level circuit in a specific embodiment of the present invention
  • FIG. 4 (e) shows the influence of the number of variables at each node on the accuracy of the model in a 20-level circuit in a specific embodiment of the present invention.
  • This specific embodiment discloses a method for predicting a circuit path delay fluctuation based on machine learning. As shown in FIG. 1, the method includes the following steps:
  • S1 Select the appropriate sample feature by analyzing the relationship between the circuit characteristics and the path delay; the sample feature includes the cell type, cell size, cell polarity, load capacitance, and path intrinsic delay.
  • Generating a random path includes the following processes: selecting and randomizing circuit configuration parameters and parasitic parameters of the path, and generating a SPICE netlist file corresponding to the random path.
  • the randomly structured circuit structure parameters include the number of circuit path stages, the types, sizes, and polarities of the various units in the path, and the randomly set circuit parasitic parameters include the load capacitance values of the units in each stage.
  • the unit type is used to characterize the types of logic units such as inverters and NAND gates. It is represented by the type number, and this parameter obeys uniform distribution.
  • the unit size is used to represent the driving capability of the corresponding unit, which is expressed by the normalized driving multiple. This parameter obeys a uniform distribution; the unit polarity is used to characterize the rising or falling state of the output waveform of the unit. This parameter of each unit is determined according to the polarity of the previous unit and the type of the unit at this stage. Capacitance, obey uniform distribution.
  • the relevant process parameters are set to a random quantity that obeys the Gaussian distribution.
  • the delay values obtained by Monte Carlo simulation of each random path are arranged in ascending order. The delay value of 99.87% quantile is selected as the random path. 3 ⁇ delay value.
  • S3 Establish a path delay prediction model and adjust the model parameters.
  • the process of adjusting the model parameters includes: increasing the number of decision trees and the number of variables at each node, and selecting the parameter value optimization model when the error is the smallest.
  • the specific process is: first fix the value of the number of variables at each node, change the number of decision trees, use the SPICE simulation results as label values, calculate the error, and continuously increase the value of the number of decision trees.
  • the number of decision trees corresponding to the smallest error is used as the model
  • the number of decision trees, then the value of the number of decision trees is fixed, the number of variables per node is changed, the SPICE simulation result is used as the label value, the error is calculated, and the value of the number of variables per node is continuously increased.
  • Each node corresponding to the minimum error The number of variables is the number of variables per node of the model.
  • the path delay prediction model in step S3 is established by the following steps:
  • the new path delay is predicted by clustering the data of n trees, and the average value of the clustering result is the predicted path delay.
  • Step S4 includes the following processes: verifying the accuracy of the path delay prediction model by calculating the average error of the training set, the average error of the test set, and the maximum absolute error; verifying the path delay by changing the number of samples in the test set and observing the average error of the test set Predict the stability of the model.
  • FIG. 3 shows the influence of adjusting the number of decision trees on the accuracy of the model according to a specific embodiment of the present invention, keeping the number of variables at each node unchanged, changing the number of decision trees, and re-establishing a prediction model. Changes in the training set change to obtain a new prediction model, and the average error of the test set is calculated to obtain Figure 3. Among them, Fig.
  • FIG. 3 (a) shows the effect of the number of decision trees under different voltages on the model when the path is 5 levels, the number of samples in the training set is 800, the number of samples in the test set is 200, and the temperature is 25 ° C; Level 5, the number of samples in the training set is 800, the number of samples in the test set is 200, and the effect of the number of decision trees at different temperatures on the model when the voltage is 0.6V;
  • Figure 3 (c) shows the voltage is 0.6V and the temperature is 25 ° C When the number of samples in the training set is 800 and the number of samples in the test set is 200, the impact of the number of decision trees under different stages of the circuit on the model.
  • FIG. 4 shows the effect of adjusting the number of variables at each node on the accuracy of the model, keeping the number of variables at each node unchanged, changing the number of variables at each node, and re-establishing the prediction model.
  • the training set is changed according to the change of the path series, temperature, and voltage to obtain a new prediction model.
  • the average error of the test set is calculated, and FIG. 4 is obtained.
  • Figure 4 (a) shows the influence of the number of variables at each node on the model at different voltages when the path is level 5, the number of samples in the training set is 800, the number of samples in the test set is 200, and the temperature is 25 ° C; b) The path is 5 levels, the number of samples in the training set is 800, the number of samples in the test set is 200, and the voltage at 0.6V affects the model at each node at different temperatures;
  • Figure 4 (c) shows the voltage When the temperature is 0.6V, the temperature is 25 ° C, the number of samples in the training set is 800, and the number of samples in the test set is 200, the effect of the number of variables at each node on the 5-level circuit on the model;
  • Figure 4 (d) shows the voltage of 0.6V , The temperature is 25 °C, the number of samples in the training set is 800, and the number of samples in the test set is 200.
  • Figure 4 (e) shows the voltage of 0.6V and the temperature of At 25 ° C, the number of samples in the training set is 800, and the number of samples in the test set is 200.

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Abstract

一种基于机器学习的电路路径延时波动预测方法，包括以下步骤：S1：通过分析电路特征与路径延时的关系选择合适的样本特征量；S2：通过枚举随机化参数的值生成随机路径，通过对随机路径进行蒙特卡洛仿真获得路径最大延时，通过3σ标准选取可靠路径，将可靠路径的样本特征量以及路径延时作为样本集(D)；S3：建立路径延时预测模型，调整模型参数；S4：验证路径延时预测模型的精度和稳定性；S5：得到路径延时。基于机器学习的电路路径延时波动预测方法具有高精度和低运行时间的优点，在时序分析准确性和效率方面优势显著。

Description

一种基于机器学习的电路路径延时波动预测方法 技术领域
本发明涉及集成电路领域，特别是涉及电路路径延时波动预测方法。
背景技术
随着物联网、可穿戴等智能设备的兴起，而极低电压关键技术是其重要使能技术，其设计方法学已经成为工业界和学术界研究的热点。相比于常规电压和亚阈值电压，近阈值电路具有显著的能效优势，引起了工业界和学术界的极大兴趣，但是近阈值下PVT偏差导致路径延时偏差成倍增加，使得电路性能严重恶化，极大抵消了近阈值电路带来的能效红利。
在传统的基于路径的静态时序分析方法中，通过对路径中各组合逻辑单元建立特征库的手段计算路径延时，但这种方法存在缺陷，一方面由于近阈值下单元延迟偏差呈非高斯分布，难以通过线性累加的方法计算路径延时，另一方面由于未能考虑单元延时间的相关性，导致路径延时过于悲观。
发明内容
发明目的：本发明的目的是提供一种高精度、低运行时间的基于机器学习的电路路径延时波动预测方法。
技术方案：为达到此目的，本发明采用以下技术方案：
本发明所述的基于机器学习的电路路径延时波动预测方法，包括以下步骤：
S1：通过分析电路特征与路径延时的关系选择合适的样本特征量；
S2：通过枚举随机化参数的值生成随机路径，通过对随机路径进行蒙特卡洛仿真获得路径最大延时，通过3σ标准选取可靠路径，将可靠路径的样本特征量以及路径延时作为样本集；
S3：建立路径延时预测模型，调整模型参数；
S4：验证路径延时预测模型的精度和稳定性；
S5：得到路径延时。
进一步，所述步骤S1中的样本特征量包括电路路径级数、每级单元类型、每级单元尺寸、每级单元极性、每级负载电容和路径本征延时。
进一步，所述步骤S3中的路径延时预测模型通过以下步骤建立：
S3.1：从训练集数据中随机、有放回地选取n个样本，作为生成回归树的训练集；
S3.2：对于每个自举样本，生成未修剪的回归树，并且进行修改，在每个节点处随机抽样预测变量，并从这些预测变量中选择最佳分割点；
S3.3：通过聚类n棵树的数据来建立路径延时预测模型预测新的路径延时，聚类结果的平均值就是路径延时预测模型输出的路径延时。
进一步，所述步骤S3中调整模型参数的过程包括：不断增加决策树的数量和每个节点处的变量数，选择误差最小时的参数值优化模型。
进一步，所述步骤S4包括以下过程：通过计算训练集的平均误差、测试集的平均误差和最大绝对误差来验证路径延时预测模型的精度；通过改变测试集样本数，观察测试集平均误差变化来验证路径延时预测模型的稳定性。
进一步，所述步骤S2中的生成随机路径包括以下过程：选取并随机化设置路径的电路结构参数和寄生参数，生成随机路径对应的SPICE网表文件；电路结构参数包括电路路径级数、每级单元类型、每级单元尺寸、路径输入信号极性，寄生参数包括每级负载电容。
有益效果：本发明公开了一种基于机器学习的电路路径延时波动预测方法，建立路径延时预测模型，得到时序分析结果，具有高精度和低运行时间的优点，在时序分析准确性和效率方面优势显著。以0.6V，25℃工艺角下的5级路径为例，训练集和测试集的平均误差均低于5％，最低可分别达到1.27％和2.83％。
附图说明
图1为本发明具体实施方式中方法的流程图；
图2为本发明具体实施方式中路径延时预测模型的建立流程图；
图3(a)为本发明具体实施方式中不同电压下调整决策树数量对模型精度的影响；
图3(b)为本发明具体实施方式中不同温度下调整决策树数量对模型精度的影响；
图3(c)为本发明具体实施方式中不同路径级数下调整决策树数量对模型精度的影响；
图4(a)为本发明具体实施方式中不同电压下调整每个节点处的变量数对模型精度的影响；
图4(b)为本发明具体实施方式中不同温度下调整每个节点处的变量数对模型精度的影响；
图4(c)为本发明具体实施方式中5级电路调整每个节点处的变量数对模型精度的影响；
图4(d)为本发明具体实施方式中10级电路调整每个节点处的变量数对模型精度的影响；
图4(e)为本发明具体实施方式中20级电路调整每个节点处的变量数对模型精度的影响。
具体实施方式
本具体实施方式公开了一种基于机器学习的电路路径延时波动预测方法，如图1所示， 包括以下步骤：
S1：通过分析电路特征与路径延时的关系选择合适的样本特征量；样本特征量包括单元类型、单元尺寸、单元极性、负载电容和路径本征延时。
S2：通过枚举随机化参数的值生成随机路径，通过对随机路径进行蒙特卡洛仿真获得路径最大延时，通过3σ标准选取可靠路径，将可靠路径的样本特征量以及路径延时作为样本集。生成随机路径包括以下过程：选取并随机化设置路径的电路结构参数和寄生参数，生成随机路径对应的SPICE网表文件。随机化设置的电路结构参数包括电路路径级数、路径中各级单元的类型、尺寸和极性，随机化设置的电路寄生参数包括各级单元的负载电容值。其中，单元类型用于表征反相器、与非门等逻辑单元的类型，以类型编号表示，该参数服从均匀分布；单元尺寸用于表征对应单元的驱动能力，以归一化驱动倍数表示，该参数服从均匀分布；单元极性用于表征单元输出波形上升或下降状态，每级单元的该参数根据上一级单元极性和本级单元类型确定；负载电容表征路径中各级单元的负载电容，服从均匀分布。蒙特卡洛仿真过程中将相关工艺参数设置为服从高斯分布的随机量，每条随机路径蒙特卡洛仿真得到的延时值升序排列，选取99.87％分位点的延时值作为该条随机路径的3σ延时值。
S3：建立路径延时预测模型，调整模型参数；调整模型参数的过程包括：不断增加决策树的数量和每个节点处的变量数，选择误差最小时的参数值优化模型。具体过程为：先固定每个节点处变量数的值，改变决策树数量，将SPICE仿真结果作为标签值，计算误差，不断增加决策树数量的值，误差最小时对应的决策树数量作为模型的决策树数量，后固定决策树数量的值，改变每个节点数变量数，将SPICE仿真结果作为标签值，计算误差，不断增加每个节点数变量数的值，误差最小时对应的每个节点数变量数作为模型的每个节点数变量数。
S4：验证路径延时预测模型的精度和稳定性。
S5：得到路径延时。
如图2所示，步骤S3中的路径延时预测模型通过以下步骤建立：
S3.1：从训练集数据中随机、有放回地选取n个样本，作为生成回归树的训练集；
S3.2：对于每个自举样本，生成未修剪的回归树，并且进行修改，在每个节点处随机抽样预测变量，并从这些预测变量中选择最佳分割点；
S3.3：通过聚类n棵树的数据来预测新的路径延时，聚类结果的平均值就是预测的路径延时。
步骤S4包括以下过程：通过计算训练集的平均误差、测试集的平均误差和最大绝对误差来验证路径延时预测模型的精度；通过改变测试集样本数，观察测试集平均误差变化来验证路径延时预测模型的稳定性。
图3为本发明具体实施方式的调整决策树数量对模型精度的影响，保持每个节点处的变量数不变，改变决策树数量，重新建立预测模型，同时，根据路径级数、温度、电压的变化改变训练集，得到新的预测模型，计算测试集平均误差，得到图3。其中图3(a)为路径为5级，训练集样本数为800，测试集样本数为200，温度为25℃时，不同电压下决策树数量对模型的影响；图3(b)为路径为5级，训练集样本数为800，测试集样本数为200，电压为0.6V时，不同温度下决策树数量对模型的影响；图3(c)为电压为0.6V，温度为25℃，训练集样本数为800，测试集样本数为200时，不同级数电路下决策树数量对模型的影响。
图4为本发明具体实施方式的调整每个节点处的变量数对模型精度的影响，保持每个节点处的变量数不变，改变每个节点处的变量数，重新建立预测模型，同时，根据路径级数、温度、电压的变化改变训练集，得到新的预测模型，计算测试集平均误差，得到图4。其中图4(a)为路径为5级，训练集样本数为800，测试集样本数为200，温度为25℃时，不同电压下每个节点处的变量数对模型的影响；图4(b)为路径为5级，训练集样本数为800，测试集样本数为200，电压为0.6V时，不同温度下每个节点处的变量数对模型的影响；图4(c)为电压为0.6V，温度为25℃，训练集样本数为800，测试集样本数为200时，5级电路下每个节点处的变量数对模型的影响；图4(d)为电压为0.6V，温度为25℃，训练集样本数为800，测试集样本数为200时，10级电路下每个节点处的变量数对模型的影响；图4(e)为电压为0.6V，温度为25℃，训练集样本数为800，测试集样本数为200时，20级电路下每个节点处的变量数对模型的影响。

Claims (6)

  1. 一种基于机器学习的电路路径延时波动预测方法，其特征在于：包括以下步骤：
    S1：通过分析电路特征与路径延时的关系选择合适的样本特征量；
    S2：通过枚举随机化参数的值生成随机路径，通过对随机路径进行蒙特卡洛仿真获得路径最大延时，通过3σ标准选取可靠路径，将可靠路径的样本特征量以及路径延时作为样本集；
    S3：建立路径延时预测模型，调整模型参数；
    S4：验证路径延时预测模型的精度和稳定性；
    S5：得到路径延时。
  2. 根据权利要求1所述的基于机器学习的电路路径延时波动预测方法，其特征在于：所述步骤S1中的样本特征量包括电路路径级数、每级单元类型、每级单元尺寸、每级单元极性、每级负载电容和路径本征延时。
  3. 根据权利要求1所述的基于机器学习的电路路径延时波动预测方法，其特征在于：所述步骤S3中的路径延时预测模型通过以下步骤建立：
    S3.1：从训练集数据中随机、有放回地选取n个样本，作为生成回归树的训练集；
    S3.2：对于每个自举样本，生成未修剪的回归树，并且进行修改，在每个节点处随机抽样预测变量，并从这些预测变量中选择最佳分割点；
    S3.3：通过聚类n棵树的数据来建立路径延时预测模型预测新的路径延时，聚类结果的平均值就是路径延时预测模型输出的路径延时。
  4. 根据权利要求1所述的基于机器学习的电路路径延时波动预测方法，其特征在于：所述步骤S3中调整模型参数的过程包括：不断增加决策树的数量和每个节点处的变量数，选择误差最小时的参数值优化模型。
  5. 根据权利要求1所述的基于机器学习的电路路径延时波动预测方法，其特征在于：所述步骤S4包括以下过程：通过计算训练集的平均误差、测试集的平均误差和最大绝对误差来验证路径延时预测模型的精度；通过改变测试集样本数，观察测试集平均误差变化来验证路径延时预测模型的稳定性。
  6. 根据权利要求1所述的基于机器学习的电路路径延时波动预测方法，其特征在于：所述步骤S2中的生成随机路径包括以下过程：选取并随机化设置路径的电路结构参数和寄生参数，生成随机路径对应的SPICE网表文件；电路结构参数包括电路路径级数、每级单元类型、每级单元尺寸、路径输入信号极性，寄生参数包括每级负载电容。
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