WO2020024533A1 - 显示装置及显示面板的制造方法 - Google Patents

显示装置及显示面板的制造方法 Download PDF

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Publication number
WO2020024533A1
WO2020024533A1 PCT/CN2018/122791 CN2018122791W WO2020024533A1 WO 2020024533 A1 WO2020024533 A1 WO 2020024533A1 CN 2018122791 W CN2018122791 W CN 2018122791W WO 2020024533 A1 WO2020024533 A1 WO 2020024533A1
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Prior art keywords
layer
dielectric material
passivation layer
metal
display panel
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PCT/CN2018/122791
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English (en)
French (fr)
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林佩欣
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/315,208 priority Critical patent/US10833105B2/en
Publication of WO2020024533A1 publication Critical patent/WO2020024533A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display technology, and in particular, to a display device and a method for manufacturing a display panel.
  • each pixel includes a thin-film transistor (TFT), where the gate of the thin-film transistor is connected to a horizontal scanning line and the source is connected to The vertical data line, and the drain is connected to the pixel electrode.
  • TFT thin-film transistor
  • the gate driving circuit of the thin film transistor gate for driving each pixel uses a shift register circuit (Shift Register) to generate a continuous driving signal to the scanning line to control the thin film transistor of each pixel in the display to be turned on. And off.
  • the current technology is to directly manufacture a shift register circuit on an array substrate instead of a driving chip made of an external silicon chip. This technology is also called a gate driver circuit board technology (GOA). .
  • GOA gate driver circuit board technology
  • the display panel's process architecture is divided into gate-driven designs, which can be divided into SOC (System On Chip) and GOA. From the perspective of product demand, a small frame is also expected by everyone, so compared to SOC version design, GOA has a smaller border.
  • GOA is an important technology in panel design. The main advantage is that it can eliminate the gate drive integrated circuit and reduce product costs. Therefore, GOA products are bound to be the mainstream trend in the future. Therefore, how to solve the problem of excessive circuit load is currently on the market. A major challenge for GOA products.
  • An object of the present application is to provide a method for manufacturing a display panel, including but not limited to solving a technical problem of excessive circuit load.
  • the technical solution adopted in the embodiments of the present application is to provide a method for manufacturing a display panel, including:
  • the material of the passivation layer includes a low dielectric material.
  • the low dielectric material is a pure inorganic material, a pure organic material, or an inorganic-organic mixed material.
  • the low dielectric material is a ceramic material or a silica-based material.
  • the thickness of the passivation layer ranges from 2300 ⁇ m to 20,000 ⁇ m.
  • the active layer is an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.
  • the passivation layer is provided by a yellow light process.
  • the specific steps of setting the passivation layer by using a yellow light process are: setting a low dielectric material layer on the second metal layer and the active layer, and setting the low dielectric material layer on the A photoresist is coated thereon, and a photomask is used to expose and develop the photoresist to obtain a photoresist layer.
  • the photoresist layer is used as a barrier layer, and the low dielectric material layer is etched to obtain The passivation layer.
  • the low dielectric material layer described in the physical vapor deposition method, the chemical meteorological deposition method, the coating method or the evaporation method is used.
  • the organic material layer is etched by a dry etching method or a wet etching method to obtain the passivation layer.
  • Another object of the present application is to provide a method for manufacturing a display panel, including:
  • the material of the passivation layer includes a low dielectric material
  • the low dielectric material is a ceramic material or a silica-based material
  • the thickness of the passivation layer ranges from 2300 ⁇ m to 20,000 ⁇ m
  • the active layer is non-conductive.
  • a crystalline silicon layer, a polysilicon layer, or a metal oxide semiconductor layer; the passivation layer is set by a yellow light process, and the specific steps are: using a physical vapor deposition method, a chemical meteorological deposition method, a coating method, or an evaporation method in the first step;
  • a low dielectric material layer is disposed on the two metal layers and the active layer, a photoresist is coated on the low dielectric material layer, and a photomask is used to expose and develop the photoresist to obtain a photoresist layer,
  • the photoresist layer is used as a barrier layer, and the low-dielectric material layer is etched by using a dry etching method or a wet etching method to obtain the passivation layer.
  • Another object of the present application is to provide a display device, including:
  • a first metal layer is disposed on the substrate
  • An insulating layer is disposed on the first metal layer and covers the substrate;
  • An active layer is disposed on the insulating layer
  • a second metal layer is disposed on the active layer
  • a passivation layer is disposed on the second metal layer and covers the active layer
  • the material of the passivation layer includes a low dielectric material.
  • the low dielectric material is a ceramic material or a silica-based material.
  • the active layer is an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.
  • the passivation layer is manufactured by a yellow light process, and the specific steps are as follows: a low dielectric material layer is provided on the second metal layer and the active layer, and the low dielectric material layer is disposed on the low metal material layer. A photoresist is coated thereon, and a photomask is used to expose and develop the photoresist to obtain a photoresist layer. The photoresist layer is used as a barrier layer, and the low dielectric material layer is etched to obtain The passivation layer.
  • the low-dielectric material layer is provided by a physical vapor deposition method, a chemical meteorological deposition method, a coating method, or an evaporation method.
  • the organic material layer is etched by a dry etching method or a wet etching method to obtain the passivation layer.
  • the thickness of the passivation layer ranges from 2300 ⁇ m to 20,000 ⁇ m.
  • This application adopts a low-dielectric material to set a passivation layer. Since the low-dielectric material has a low dielectric coefficient, the capacitance value of the overall GOA circuit can be reduced, thereby reducing the load of the gate driving circuit and making the display panel produced more highly Energy efficiency level.
  • FIG. 1 is a schematic diagram of an exemplary display panel
  • FIG. 2 is a schematic diagram of a display device according to an embodiment of the present application.
  • 3a is a schematic diagram of a display panel according to an embodiment of the present application.
  • 3b is a schematic diagram of a display panel according to another embodiment of the present application.
  • 3c is a schematic diagram of a display device according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a capacitor structure with two parallel metal plates according to an embodiment of the present application.
  • FIG. 5 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of an exemplary display panel. Please refer to FIG. 1, an exemplary display panel 10 includes an array substrate 100 and a driving chip 105 for driving a circuit.
  • FIG. 2 is a schematic diagram of a display device according to an embodiment of the present application.
  • a display panel 11 with gate array driving includes an array substrate 100, a driving chip 105, and a gate array driving circuit 110, which are used to connect the gate driving circuit 110. Fabricated on the array substrate 100.
  • the so-called GOA is to configure a gate driving circuit on an array substrate to replace a driving chip made of an external silicon chip. Because GOA technology can be directly arranged around the panel, it simplifies the production process, improves the integration of the display panel, and makes the panel thinner. With the development of science and technology, the display panel industry has developed a GOA circuit with dual driving mode. This technology is to configure two sets of GOA circuits on each side of the panel.
  • FIG. 3a is a schematic diagram of a display panel 301 according to an embodiment of the present application. Please refer to FIG. 3a and FIG. 5.
  • a method for manufacturing a display panel includes:
  • the passivation layer 360 is provided by using a low dielectric material.
  • the low dielectric material refers to a material having a dielectric constant (K) less than or equal to that of silicon dioxide. It is generally impossible to reduce the dielectric constant of the material.
  • the design permittivity requirements for the interlayer metal insulator are: for 65nm
  • the dielectric constant must be less than 2.1; for a 45nm process node, the dielectric constant must be less than 1.9; for a 32nm process node, the dielectric constant must be less than 1.7; for a 22nm process
  • the dielectric constant should be less than 1.6. Because the dielectric constant of the low-dielectric material is low, the capacitance value of the overall GOA circuit can be reduced, thereby effectively reducing the load of the gate drive circuit, so that the display panel produced has a higher Energy efficiency level.
  • the low dielectric material may be a pure inorganic material, a pure organic material, or an inorganic-organic mixed material.
  • the low-dielectric material may be a ceramic material or a silica-based material.
  • the low-dielectric material may be other materials.
  • the passivation layer 360 may be doped with other materials, so as to reduce the manufacturing cost.
  • the passivation layer 360 is further doped with a silicon nitride material.
  • the composition material of the passivation layer 360 of the present application includes a low-dielectric material, which can make the dielectric constant of the passivation layer 360 lower, and therefore can effectively reduce the load of the gate driving circuit.
  • the passivation layer 360 The constituent materials also include lower cost silicon nitride materials, which can reduce manufacturing costs.
  • the manufacturing method of the display panel of the present application uses a parallel capacitance formula as follows:
  • ⁇ 0 is the dielectric coefficient in vacuum
  • ⁇ r is the dielectric coefficient of the material
  • A is the area of the metal layer
  • the thickness of the passivation layer 360 is d.
  • the dielectric coefficient of the silicon oxide material is about 4
  • the dielectric coefficient of the silicon nitride material is about 7, and by reducing the dielectric coefficient of the passivation layer 360, the capacitance value of the overall GOA circuit is reduced, and the load of the gate driving circuit is effectively reduced, so that the produced display panel has a higher Energy efficiency level.
  • the thickness of the passivation layer 360 ranges from 2300 ⁇ m to 20,000 ⁇ m.
  • the active layer 340 is an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.
  • the specific process of the active layer 340 is: depositing an amorphous silicon layer on the insulating layer 330, crystallizing the amorphous silicon layer to obtain a polysilicon layer, and The layer is ion-doped, and finally patterned by an etching process using a photomask to obtain an active layer 340.
  • the first metal layer 320 and the second metal layer 350 may be disposed by a physical vapor deposition method.
  • a material of the first metal layer 320 and the second metal layer 350 includes one or more of molybdenum, titanium, aluminum, and copper.
  • the second metal layer 350 includes a source electrode and a drain electrode.
  • FIG. 3b is a schematic diagram of a display panel 302 according to another embodiment of the present application. Please refer to FIG. 3b and FIG. 5.
  • a method for manufacturing a display panel includes:
  • the passivation layer 361 is made of a low dielectric material.
  • the low dielectric material refers to a material having a dielectric constant (K) less than or equal to that of silicon dioxide. It is generally impossible to reduce the dielectric constant of the material. Without reducing the mechanical properties of the material (elastic modulus, hardness, toughness), and according to the 2001 International Technology Roadmap for Semiconductor (ITRS) interconnect wiring map (roadmap), the design permittivity requirements for the interlayer metal insulator are: for 65nm For a process node, the dielectric constant must be less than 2.1; for a 45nm process node, the dielectric constant must be less than 1.9; for a 32nm process node, the dielectric constant must be less than 1.7; for a 22nm process For the node, the dielectric constant should be less than 1.6. Because the dielectric constant of the low-dielectric material is low, the capacitance value of the overall GOA circuit can be reduced, thereby effectively reducing the load of the
  • the passivation layer 361 is set by using a yellow light process.
  • the pattern of the passivation layer 361 is highly accurate, which can effectively improve the product yield.
  • the specific steps for setting the passivation layer 361 by using a yellow light process are: setting a low dielectric material layer on the second metal layer 350 and the active layer 340, and coating light on the low dielectric material layer.
  • the photoresist layer is subjected to photoresist exposure and development using a photomask to obtain a photoresist layer.
  • the photoresist layer is used as a barrier layer to etch a low dielectric material layer to obtain a passivation layer 361.
  • the low-dielectric material layer is provided by physical vapor deposition method, chemical meteorological deposition method, or coating method.
  • the low-dielectric material layer can also be provided by other methods, such as evaporation method; dry etching method or wet method is used.
  • the organic material layer is etched by a method such that a passivation layer 361 is obtained.
  • the photomask has a light-transmitting area, a non-light-transmitting area, and a semi-light-transmitting area, and the light-transmitting area, the non-light-transmitting area, and the semi-light-transmitting area form a pattern of the passivation layer 361.
  • the low dielectric material may be a pure inorganic material, a pure organic material, or an inorganic-organic mixed material.
  • the low-dielectric material may be a ceramic material or a silica-based material.
  • the low-dielectric material may be other materials.
  • the passivation layer 361 may be doped with other materials to reduce manufacturing costs.
  • the passivation layer 361 is further doped with a silicon nitride material.
  • the composition material of the passivation layer 361 of the present application includes both a low dielectric material and a low dielectric constant of the passivation layer 361, which can effectively reduce the load of the gate driving circuit.
  • the composition of the passivation layer 361 Materials also include lower cost silicon nitride materials, which can reduce manufacturing costs.
  • the manufacturing method of the display panel of the present application uses a parallel capacitance formula as follows:
  • ⁇ 0 is the dielectric coefficient in vacuum
  • ⁇ r is the dielectric coefficient of the material
  • A is the area of the metal layer
  • the thickness of the passivation layer 361 is d.
  • the dielectric coefficient of the silicon oxide material is about 4
  • the dielectric coefficient of the silicon nitride material is about 7.
  • the thickness of the passivation layer 361 ranges from 2300 ⁇ m to 20,000 ⁇ m.
  • the active layer 340 is an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.
  • the specific process of the active layer 340 is: depositing an amorphous silicon layer on the insulating layer 330, crystallizing the amorphous silicon layer to obtain a polysilicon layer, and The layer is ion-doped, and finally patterned by an etching process using a photomask to obtain an active layer 340.
  • the first metal layer 320 and the second metal layer 350 may be disposed by a physical vapor deposition method.
  • a material of the first metal layer 320 and the second metal layer 350 includes one or more of molybdenum, titanium, aluminum, and copper.
  • the second metal layer 350 includes a source electrode and a drain electrode.
  • FIG. 3c is a schematic diagram of a display device 303 according to an embodiment of the present application. Please refer to FIG. 3c, a display device including:
  • the first metal layer 320 is disposed on the substrate 310;
  • the insulating layer 330 is disposed on the first metal layer 320 and covers the substrate 310.
  • the active layer 340 is disposed on the insulating layer 330;
  • the second metal layer 350 is disposed on the active layer 340;
  • a passivation layer 362 is disposed on the second metal layer 350 and covers the active layer 340;
  • the passivation layer 362 is provided with a low dielectric material.
  • the low dielectric material refers to a material having a dielectric constant (K) less than or equal to that of silicon dioxide. It is generally impossible to reduce the dielectric constant of the material.
  • the design dielectric constant requirement for the interlayer metal insulator is: for 65nm
  • the dielectric constant must be less than 2.1; for a 45nm process node, the dielectric constant must be less than 1.9; for a 32nm process node, the dielectric constant must be less than 1.7; for a 22nm process
  • the dielectric constant should be less than 1.6. Due to the low dielectric constant of the low-dielectric material, the capacitance value of the overall GOA circuit can be reduced, thereby effectively reducing the load of the gate drive circuit, which makes the display panel produced with a higher Energy efficiency level.
  • the passivation layer 362 is set by using a yellow light process.
  • the pattern of the passivation layer 362 is highly accurate, which can effectively improve the product yield.
  • the specific steps of setting the passivation layer 362 by using a yellow light process are: setting a low dielectric material layer on the second metal layer 350 and the active layer 340, and coating light on the low dielectric material layer.
  • the photoresist layer is subjected to photoresist exposure and development using a photomask to obtain a photoresist layer.
  • the photoresist layer is used as a barrier layer to etch a low dielectric material layer to obtain a passivation layer 362.
  • the low-dielectric material layer is provided by physical vapor deposition method, chemical meteorological deposition method, or coating method.
  • the low-dielectric material layer can also be provided by other methods, such as evaporation method; dry etching method or wet method is used.
  • the organic material layer is etched by a method of etching to obtain a passivation layer 362.
  • the photomask has a light-transmitting area, a non-light-transmitting area, and a semi-light-transmitting area.
  • the light-transmitting area, the non-light-transmitting area, and the semi-light-transmitting area form a pattern of the passivation layer 362.
  • the low dielectric material may be a pure inorganic material, a pure organic material, or an inorganic-organic mixed material.
  • the low dielectric material may be a ceramic material or a silica-based material.
  • the passivation layer 362 may be doped with other materials to reduce manufacturing costs.
  • the passivation layer 362 is further doped with a silicon nitride material.
  • the composition material of the passivation layer 362 of the present application includes both a low-dielectric material and a lower dielectric constant of the passivation layer 362, which can effectively reduce the gate driving circuit load.
  • the composition of the passivation layer 362 Materials also include lower cost silicon nitride materials, which can reduce manufacturing costs.
  • the manufacturing method of the display panel of the present application uses a parallel capacitance formula as follows:
  • ⁇ 0 is the dielectric coefficient in vacuum
  • ⁇ r is the dielectric coefficient of the material
  • A is the area of the metal layer
  • the thickness of the passivation layer 362 is d.
  • the dielectric coefficient of the silicon oxide material is about 4
  • the dielectric coefficient of the silicon nitride material is about 7.
  • the thickness of the passivation layer 362 ranges from 2300 ⁇ m to 20,000 ⁇ m.
  • the active layer 340 is an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.
  • the specific process of the active layer 340 is: depositing an amorphous silicon layer on the insulating layer 330, crystallizing the amorphous silicon layer to obtain a polysilicon layer, and The layer is ion-doped, and finally patterned by an etching process using a photomask to obtain an active layer 340.
  • the first metal layer 320 and the second metal layer 350 may be disposed by a physical vapor deposition method.
  • a material of the first metal layer 320 and the second metal layer 350 includes one or more of molybdenum, titanium, aluminum, and copper.
  • the second metal layer 350 includes a source electrode and a drain electrode.
  • FIG. 4 is a schematic diagram of a capacitor structure with two parallel metal plates according to an embodiment of the present application.
  • a flat metal plate capacitor architecture 400 includes: a first metal plate 410, a second metal plate 420, and a distance d between the first metal plate 410 and the second metal plate 420 to generate a capacitor 430.
  • the parallel capacitance formula is used to learn Among them, ⁇ 0 is the dielectric coefficient in vacuum, ⁇ r is the dielectric coefficient of the material, A is the area of the metal layer, and the thickness of the passivation layer is d.
  • the passivation layer of a low dielectric material is used for the process. The low dielectric material enables the dielectric material ⁇ r of the passivation layer to be reduced, so the capacitance value of the overall GOA circuit can be effectively reduced.
  • the display panel may include an LCD (Liquid Crystal Display) panel, where the LCD panel includes: a thin film transistor (TFT) substrate, and a color filter (CF ) A substrate and a liquid crystal layer disposed between the two substrates, the display panel may also be an OLED (Organic Light-Emitting Diode) panel, or a QLED (Quantum Dots Light-Emitting Diode) panel.
  • LCD Liquid Crystal Display
  • TFT thin film transistor
  • CF color filter
  • This application adopts a low-dielectric material to set a passivation layer. Since the low-dielectric material has a low dielectric coefficient, the capacitance value of the overall GOA circuit can be reduced, thereby reducing the load of the gate driving circuit and the power of the tablet, so that the display of the production The panel has a higher level of energy efficiency.

Abstract

一种显示装置及显示面板的制造方法，将第一金属层设置于基板上，将绝缘层设置于所述第一金属层上，并且所述绝缘层覆盖所述基板，将有源层设置于所述绝缘层上，将第二金属层设置于所述有源层上，将钝化层设置于所述第二金属层上，并且所述钝化层覆盖所述有源层；其中，所述钝化层的材料包括低介材质，使得所形成的钝化层的介电系数较低。

Description

显示装置及显示面板的制造方法
本申请要求于2018年08月03日提交中国专利局，申请号为2018108790463，发明名称为“显示装置及显示面板的制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示装置及显示面板的制造方法。
背景技术
在主动式矩阵液晶显示器(Active Matrix Liquid Crystal Display)中，每个像素包含一个薄膜晶体管(Thin-Film Transistor，TFT)，其中，薄膜晶体管的闸极连接至水平方向的扫描线，源极连接至垂直方向的数据线，而漏极则连接至像素电极。若在水平方向的某一条扫描线提供足够的正电压，会使得在该条扫描线所有的薄膜晶体管打开，而在该条扫描线的像素电极会与垂直方向的数据线导通，从而将数据线的讯号电压写入对应该条扫描线的每一个像素电容中，控制不同像素的液晶层的透光度进而达到控制色彩的效果。
用以驱动每个像素的薄膜晶体管闸极的闸极驱动电路是使用移位寄存器电路(Shift Register，SR)来产生连续的驱动讯号到扫描线，以控制显示器中每个像素的薄膜晶体管的开启和关闭。目前的技术是将移位寄存器电路直接制作在阵列(Array)基板上，来代替由外接硅芯片制作的驱动芯片，这样的技术又称作闸极驱动电路基板技术(Gate Driver on Array，GOA)。进一步来说，将移位寄存器电路直接制作在显示面板的边框(Border)上，可减少制作程序，并且降低产品成本，进而提高主动式矩阵面板的高集成度，使面板能更薄型化。
显示面板的工艺架构，以闸极驱动设计来分，可以分为SOC(System on chip，系统芯片)和GOA两种，就产品需求的角度来看，边框小也是大家所期望 的，所以相较SOC版设计，GOA有较小的边框(Border)。GOA在面板设计上是一项重要技术，主要优点是可以免去闸极驱动集成电路，降低产品成本，所以GOA产品势必是未来的主流趋势，所以如何解决电路负载过大问题，是目前市场上GOA产品面临的一个重大挑战。
申请内容
本申请一目的在于提供一种显示面板的制造方法，包括但不限于解决电路负载过大的技术问题。
本申请实施例采用的技术方案是：提供一种显示面板的制造方法，包括：
基板；
将第一金属层设置于所述基板上；
将绝缘层设置于所述第一金属层上，并覆盖所述基板；
将有源层设置于所述绝缘层上；
将第二金属层设置于所述有源层上；以及
将钝化层设置于所述第二金属层上，并覆盖所述有源层；
其中，所述钝化层的材料包括低介材质。
在本申请一实施例中，所述低介材质为纯无机材料、纯有机材料或无机-有机混合材料。
在本申请一实施例中，所述低介材质为陶瓷材料或者二氧化硅基材料。
在本申请一实施例中，所述钝化层的厚度的范围为2300μm～20000μm。
在本申请一实施例中，所述有源层为非晶硅层、多晶硅层或者金属氧化物半导体层。
在本申请一实施例中，采用黄光制程设置所述钝化层。
在本申请一实施例中，采用黄光制程设置所述钝化层的具体步骤为：在所述第二金属层与所述有源层上设置低介材质层，在所述低介材质层上涂覆光刻胶，采用光罩对所述光刻胶进行曝光与显影处理得到光刻胶层，以所述光刻胶层为阻挡层，对所述低介材质层进行蚀刻，从而得到所述钝化层。
在本申请一实施例中，采用物理气相沉积法、化学气象沉积法、涂布法或蒸镀法所述低介材质层。
在本申请一实施例中，采用干法蚀刻的方式或者湿法蚀刻的方式对所述有机材质层进行蚀刻，从而得到所述钝化层。
本申请的另一目的在于提供一种显示面板的制造方法，包括：
基板；
将第一金属层设置于所述基板上；
将绝缘层设置于所述第一金属层上，并覆盖所述基板；
将有源层设置于所述绝缘层上；
将第二金属层设置于所述有源层上；以及
将钝化层设置于所述第二金属层上，并覆盖所述有源层；
其中，所述钝化层的材料包括低介材质，所述低介材质为陶瓷材料或者二氧化硅基材料，所述钝化层的厚度的范围为2300μm～20000μm，所述有源层为非晶硅层、多晶硅层或者金属氧化物半导体层；所述钝化层采用黄光制程设置，具体步骤为：采用物理气相沉积法、化学气象沉积法、涂布法或蒸镀法在所述第二金属层与所述有源层上设置低介材质层，在所述低介材质层上涂覆光刻胶，采用光罩对所述光刻胶进行曝光与显影处理得到光刻胶层，以所述光刻胶层为阻挡层，采用干法蚀刻的方式或者湿法蚀刻的方式对所述低介材质层进行蚀刻，从而得到所述钝化层。
本申请的再一目的在于提供一种显示装置，包括：
基板；
第一金属层设置于所述基板上；
绝缘层设置于所述第一金属层上，并覆盖所述基板；
有源层设置于所述绝缘层上；
第二金属层设置于所述有源层上；以及
钝化层设置于所述第二金属层上，并覆盖所述有源层；
其中，所述钝化层的材料包括低介材质。
在本申请一实施例中，所述低介材质为陶瓷材料或二氧化硅基材料。
在本申请一实施例中，所述有源层为非晶硅层、多晶硅层或者金属氧化物半导体层。
在本申请一实施例中，所述钝化层采用黄光制程制作，具体步骤为：在所述第二金属层与所述有源层上设置低介材质层，在所述低介材质层上涂覆光刻胶，采用光罩对所述光刻胶进行曝光与显影处理得到光刻胶层，以所述光刻胶层为阻挡层，对所述低介材质层进行蚀刻，从而得到所述钝化层。
在本申请一实施例中，采用物理气相沉积法、化学气象沉积法、涂布法或蒸镀法设置所述低介材质层。
在本申请一实施例中，采用干法蚀刻的方式或者湿法蚀刻的方式对所述有机材质层进行蚀刻，从而得到所述钝化层。
在本申请一实施例中，所述钝化层的厚度的范围为2300μm～20000μm。
本申请通过采用低介材质设置钝化层，由于低介材质的介电系数较低，因此能降低整体GOA电路的电容值，从而可以降低闸极驱动电路负载，使得生产的显示面板具有更高的能效水平。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为范例性的显示面板的示意图；
图2为本申请一实施例的显示装置的示意图；
图3a为本申请一实施例的显示面板的示意图；
图3b为本申请另一实施例的显示面板的示意图；
图3c为本申请一实施例的显示装置的示意图；
图4为本申请一实施例的具有两平行金属板电容架构的示意图；
图5为本申请一实施例的显示面板的制造方法的流程图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
图1为范例性的显示面板示意图。请参考图1，一种范例性显示面板10，包括阵列基板100及驱动芯片105，用以驱动电路。
图2为本申请一实施例的显示装置示意图。请参考图2，在本申请的一实施例中，一种具有闸极阵列驱动的显示面板11，包括阵列基板100、驱动芯片105及闸极阵列驱动电路110，用以将闸极驱动电路110制作在阵列基板100上。而所谓GOA是将闸极驱动电路配置于阵列基板上，以取替由外接硅芯片制作之驱动芯片。由于GOA技术可直接配置在面板周围，因而简化制作程序，提高显示面板的整合度，使得面板更加薄型化。而随着科技的进展，显示面板产业更研发出双驱动模式的GOA电路，此技术是将两组GOA电路分别配置于面板之两侧。
图3a为本申请一实施例的显示面板301示意图。请参考图3a与图5，一种显示面板的制造方法，包括：
基板310；
将第一金属层320设置于基板310上；
将绝缘层330设置于第一金属层320上，并覆盖基板310；
将有源层340设置于绝缘层330上；
将第二金属层350设置于有源层340上；以及
将钝化层360设置于第二金属层350上，并覆盖有源层340；
其中，钝化层360是采用低介材质设置的，低介材质指的是一种介电常数(K)小于等于二氧化硅的介电常数的材料，一般不可能减小材料的介电常数而不降低材料的力学性能(弹性模量、硬度、韧性)，且根据2001International Technology roadmap for Semiconductor(ITRS)互连布线图(roadmap)，对于层间金属绝缘体的设计介电常数要求为：对于65nm的工艺节点(node)来说，介电常数要小于2.1；对于45nm的工艺节点来说，介电常数要小于1.9；对于32nm的工艺节点来说，介电常数要小于1.7；对于22nm的工艺节点来说，介电常数要小于1.6，由于低介材质的介电系数较低，因此能降低整体GOA电路的电容值，从而有效降低闸极驱动电路负载，使得生产的显示面板具有更高的能效水平。
在本申请的一实施例中，低介材质可为纯无机材料、纯有机材料或无机-有机混合材料。
可选的，低介材质可为陶瓷材料或二氧化硅基材料，当然，根据实际情况的使用，低介材质也可为其它材料。
在本申请的一实施例中，钝化层360中还可以掺杂其它材料，以便于降低制作成本，如钝化层360中还掺杂氮化硅材料，相比于现有显示面板的钝化层来说，本申请的钝化层360的组成材料既包括低介材质，能够使得钝化层360的介电系数较低，因此能有效降低闸极驱动电路负载，此外，钝化层360的组 成材料还包括成本较低的氮化硅材料，可以降低制作成本。
在本申请的一实施例中，本申请的显示面板的制造方法利用平行电容公式为：
Figure PCTCN2018122791-appb-000001
其中，ε 0为真空中的介电系数，ε r为材料的介电系数，A为金属层面积，钝化层360的厚度为d，其中以氧化硅材料的介电系数约为4，以氮化硅材料的介电系数约为7，通过降低钝化层360的介电系数，从而降低了整体GOA电路的电容值，进而有效降低闸极驱动电路负载，使得生产的显示面板具有更高的能效水平。
在本申请的一实施例中，钝化层360的厚度的范围为2300μm～20000μm。
在本申请的一实施例中，有源层340为非晶硅层、多晶硅层或者金属氧化物半导体层。
可选的，当有源层340为多晶硅层时，有源层340的具体制程为：在绝缘层330上沉积非晶硅层，对非晶硅层进行晶化处理得到多晶硅层，对该多晶硅层进行离子掺杂，最后使用光罩通过蚀刻工艺进行图案化处理，得到有源层340。
在本申请的一实施例中，第一金属层320与第二金属层350可以通过物理气相沉积方法设置。
在本申请的一实施例中，第一金属层320与第二金属层350的材料包括钼、钛、铝、铜中的一种或多种。
在本申请的一实施例中，第二金属层350包括源极和漏极。
图3b为本申请另一实施例的显示面板302示意图。请参考图3b与图5，一种显示面板的制造方法，包括：
基板310；
将第一金属层320设置于基板310上；
将绝缘层330设置于第一金属层320上，并覆盖基板310；
将有源层340设置于绝缘层330上；
将第二金属层350设置于有源层340上；以及
将钝化层361设置于第二金属层350上，并覆盖有源层340；
其中，钝化层361是采用低介材质设置的，低介材质指的是一种介电常数(K)小于等于二氧化硅的介电常数的材料，一般不可能减小材料的介电常数而不降低材料的力学性能(弹性模量、硬度、韧性)，且根据2001International Technology roadmap for Semiconductor(ITRS)互连布线图(roadmap)，对于层间金属绝缘体的设计介电常数要求为：对于65nm的工艺节点(node)来说，介电常数要小于2.1；对于45nm的工艺节点来说，介电常数要小于1.9；对于32nm的工艺节点来说，介电常数要小于1.7；对于22nm的工艺节点来说，介电常数要小于1.6，由于低介材质的介电系数较低，因此能降低整体GOA电路的电容值，从而有效降低闸极驱动电路负载，使得生产的显示面板具有更高的能效水平。
在本申请的一实施例中，采用黄光制程设置钝化层361，所制得的钝化层361的图案的精准度较高，能够有效提高产品良率。
在本申请的一实施例中，采用黄光制程设置钝化层361的具体步骤为：在第二金属层350与有源层340上设置低介材质层，在低介材质层上涂覆光刻胶，采用光罩对光刻胶进行曝光与显影处理得到光刻胶层，以该光刻胶层为阻挡层，对低介材质层进行蚀刻，从而得到钝化层361。
可选地，采用物理气相沉积法、化学气象沉积法或涂布法设置低介材质层，当然也可以采用其它方式设置低介材质层，如蒸镀法等；采用干法蚀刻的方式或者湿法蚀刻的方式对有机材质层进行蚀刻，从而得到钝化层361。
在本申请的一实施例中，光罩具有透光区、非透光区以及半透光区，上述透光区、非透光区以及半透光区组成钝化层361的图案。
在本申请的一实施例中，低介材质可为纯无机材料、纯有机材料或无机-有机混合材料。
可选的，低介材质可为陶瓷材料或二氧化硅基材料，当然，根据实际情况的使用，低介材质也可为其它材料。
在本申请的一实施例中，钝化层361中还可以掺杂其它材料，以便于降低制作成本，如钝化层361中还掺杂氮化硅材料，相比于现有显示面板的钝化层来说，本申请的钝化层361的组成材料既包括低介材质，钝化层361的介电系数较低，因此能有效降低闸极驱动电路负载，此外，钝化层361的组成材料还包括成本较低的氮化硅材料，可以降低制作成本。
在本申请的一实施例中，本申请的显示面板的制造方法利用平行电容公式为：
Figure PCTCN2018122791-appb-000002
其中，ε 0为真空中的介电系数，ε r为材料的介电系数，A为金属层面积，钝化层361的厚度为d，其中以氧化硅材料的介电系数约为4，以氮化硅材料的介电系数约为7，通过降低钝化层361的介电系数，从而降低了整体GOA电路的电容值，进而有效降低闸极驱动电路负载，使得生产的显示面板具有更高的能效水平。
在本申请的一实施例中，钝化层361的厚度的范围为2300μm～20000μm。
在本申请的一实施例中，有源层340为非晶硅层、多晶硅层或者金属氧化物半导体层。
可选的，当有源层340为多晶硅层时，有源层340的具体制程为：在绝缘层330上沉积非晶硅层，对非晶硅层进行晶化处理得到多晶硅层，对该多晶硅层进行离子掺杂，最后使用光罩通过蚀刻工艺进行图案化处理，得到有源层340。
在本申请的一实施例中，第一金属层320与第二金属层350可以通过物理气相沉积方法设置。
在本申请的一实施例中，第一金属层320与第二金属层350的材料包括钼、钛、铝、铜中的一种或多种。
在本申请的一实施例中，第二金属层350包括源极和漏极。
图3c为本申请一实施例的显示装置303示意图。请参考图3c，一种显示装置，包括：
基板310；
第一金属层320，设置于基板310上；
绝缘层330，设置于第一金属层320上，并覆盖基板310；
有源层340，设置于绝缘层330上；
第二金属层350，设置于有源层340上；以及
钝化层362，设置于第二金属层350上，并覆盖有源层340；
其中，钝化层362是采用低介材质设置的，低介材质指的是一种介电常数(K)小于等于二氧化硅的介电常数的材料，一般不可能减小材料的介电常数而不降低材料的力学性能(弹性模量、硬度、韧性)，且根据2001International Technology roadmap for Semiconductor(ITRS)互连布线图(roadmap)，对于层间金属绝缘体的设计介电常数要求为：对于65nm的工艺节点(node)来说，介电常数要小于2.1；对于45nm的工艺节点来说，介电常数要小于1.9；对于32nm的工艺节点来说，介电常数要小于1.7；对于22nm的工艺节点来说，介电常数要小于1.6，由于低介材质的介电系数较低，因此能降低整体GOA电路的电容值，从而有效降低闸极驱动电路负载，使得生产的显示面板具有更高的能效水平。
在本申请的一实施例中，采用黄光制程设置钝化层362，所制得的钝化层362的图案的精准度较高，能够有效提高产品良率。
在本申请的一实施例中，采用黄光制程设置钝化层362的具体步骤为：在第二金属层350与有源层340上设置低介材质层，在低介材质层上涂覆光刻胶，采用光罩对光刻胶进行曝光与显影处理得到光刻胶层，以该光刻胶层为阻挡层，对低介材质层进行蚀刻，从而得到钝化层362。
可选地，采用物理气相沉积法、化学气象沉积法或涂布法设置低介材质层， 当然也可以采用其它方式设置低介材质层，如蒸镀法等；采用干法蚀刻的方式或者湿法蚀刻的方式对有机材质层进行蚀刻，从而得到钝化层362。
在本申请的一实施例中，光罩具有透光区、非透光区以及半透光区，上述透光区、非透光区以及半透光区组成钝化层362的图案。
在本申请的一实施例中，低介材质可为纯无机材料、纯有机材料或无机-有机混合材料。
可选的，低介材质可为陶瓷材料或二氧化硅基材料。
在本申请的一实施例中，钝化层362中还可以掺杂其它材料，以便于降低制作成本，如钝化层362中还掺杂氮化硅材料，相比于现有显示面板的钝化层来说，本申请的钝化层362的组成材料既包括低介材质，钝化层362的介电系数较低，因此能有效降低闸极驱动电路负载，此外，钝化层362的组成材料还包括成本较低的氮化硅材料，可以降低制作成本。
在本申请的一实施例中，本申请的显示面板的制造方法利用平行电容公式为：
Figure PCTCN2018122791-appb-000003
其中，ε 0为真空中的介电系数，ε r为材料的介电系数，A为金属层面积，钝化层362的厚度为d，其中以氧化硅材料的介电系数约为4，以氮化硅材料的介电系数约为7，通过降低钝化层362的介电系数，从而降低了整体GOA电路的电容值，进而有效降低闸极驱动电路负载，使得生产的显示面板具有更高的能效水平。
在本申请的一实施例中，钝化层362的厚度的范围为2300μm～20000μm。
在本申请的一实施例中，有源层340为非晶硅层、多晶硅层或者金属氧化物半导体层。
可选的，当有源层340为多晶硅层时，有源层340的具体制程为：在绝缘层330上沉积非晶硅层，对非晶硅层进行晶化处理得到多晶硅层，对该多晶硅层进行离子掺杂，最后使用光罩通过蚀刻工艺进行图案化处理，得到有源层 340。
在本申请的一实施例中，第一金属层320与第二金属层350可以通过物理气相沉积方法设置。
在本申请的一实施例中，第一金属层320与第二金属层350的材料包括钼、钛、铝、铜中的一种或多种。
在本申请的一实施例中，第二金属层350包括源极和漏极。
图4为本申请一实施例的具有两平行金属板电容架构示意图。请参考图4，一种平形金属板电容架构400，包括：第一金属板410、第二金属板420，第一金属板410及第二金属板420之间具有距离d，产生电容430。
在本申请的一实施例中，利用平行电容公式得知
Figure PCTCN2018122791-appb-000004
其中，ε 0为真空中的介电系数，ε r为材料的介电系数，A为金属层面积，钝化层的厚度即为d。在此利用低介材质的钝化层来制程，低介材质使钝化层的介电材料ε r可以降低，因此可以有效降低整体GOA电路的电容值。
在本申请的某些实施例中，显示面板可包括LCD(Liquid Crystal Display，液晶显示)面板，其中LCD面板包括：开关阵列(thin film transistor，TFT)基板、彩色滤光层(color filter，CF)基板与设置于两基板之间的液晶层，显示面板也可以为OLED(Organic Light-Emitting Diode，有机发光二极管)面板，或QLED(Quantum Dots Light-Emitting Diode，量子点发光二极管)面板。
本申请通过采用低介材质设置钝化层，由于低介材质的介电系数较低，因此能降低整体GOA电路的电容值，从而可以降低闸极驱动电路负载及降低平板功率，使得生产的显示面板具有更高的能效水平。
以上仅为本申请的可选实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (17)

  1. 一种显示面板的制造方法，包括：
    基板；
    将第一金属层设置于所述基板上；
    将绝缘层设置于所述第一金属层上，并覆盖所述基板；
    将有源层设置于所述绝缘层上；
    将第二金属层设置于所述有源层上；以及
    将钝化层设置于所述第二金属层上，并覆盖所述有源层；
    其中，所述钝化层的材料包括低介材质。
  2. 如权利要求1所述的显示面板的制造方法，所述低介材质为纯无机材料、纯有机材料或无机-有机混合材料。
  3. 如权利要求2所述的显示面板的制造方法，所述低介材质为陶瓷材料或者二氧化硅基材料。
  4. 如权利要求1所述的显示面板的制造方法，所述钝化层的厚度的范围为2300μm～20000μm。
  5. 如权利要求1所述的显示面板的制造方法，所述有源层为非晶硅层、多晶硅层或者金属氧化物半导体层。
  6. 如权利要求1所述的显示面板的制造方法，采用黄光制程设置所述钝化层。
  7. 如权利要求6所述的显示面板的制造方法，采用黄光制程设置所述钝化层的具体步骤为：在所述第二金属层与所述有源层上设置低介材质层，在所述低介材质层上涂覆光刻胶，采用光罩对所述光刻胶进行曝光与显影处理得到光刻胶层，以所述光刻胶层为阻挡层，对所述低介材质层进行蚀刻，从而得到所述钝化层。
  8. 如权利要求7所述的显示面板的制造方法，采用物理气相沉积法、化学 气象沉积法、涂布法或蒸镀法设置所述低介材质层。
  9. 如权利要求7所述的显示面板的制造方法，采用干法蚀刻的方式或者湿法蚀刻的方式对所述有机材质层进行蚀刻，从而得到所述钝化层。
  10. 一种显示面板的制造方法，包括：
    基板；
    将第一金属层设置于所述基板上；
    将绝缘层设置于所述第一金属层上，并覆盖所述基板；
    将有源层设置于所述绝缘层上；
    将第二金属层设置于所述有源层上；以及
    将钝化层设置于所述第二金属层上，并覆盖所述有源层；
    其中，所述钝化层的材料包括低介材质，所述低介材质为陶瓷材料或者二氧化硅基材料，所述钝化层的厚度的范围为2300μm～20000μm，所述有源层为非晶硅层、多晶硅层或者金属氧化物半导体层；所述钝化层采用黄光制程设置，具体步骤为：采用物理气相沉积法、化学气象沉积法、涂布法或蒸镀法在所述第二金属层与所述有源层上设置低介材质层，在所述低介材质层上涂覆光刻胶，采用光罩对所述光刻胶进行曝光与显影处理得到光刻胶层，以所述光刻胶层为阻挡层，采用干法蚀刻的方式或者湿法蚀刻的方式对所述低介材质层进行蚀刻，从而得到所述钝化层。
  11. 一种显示装置，包括：
    基板；
    第一金属层，设置于所述基板上；
    绝缘层，设置于所述第一金属层上，并覆盖所述基板；
    有源层，设置于所述绝缘层上；
    第二金属层，设置于所述有源层上；以及
    钝化层，设置于所述第二金属层上，并覆盖所述有源层；
    其中，所述钝化层的材料包括低介材质。
  12. 如权利要求11所述的显示装置，所述低介材质为纯无机材料、纯有机材料或无机-有机混合材料。
  13. 如权利要求12所述的显示装置，所述低介材质为陶瓷材料或二氧化硅基材料。
  14. 如权利要求11所述的显示装置，所述钝化层采用黄光制程制作，具体步骤为：在所述第二金属层与所述有源层上设置低介材质层，在所述低介材质层上涂覆光刻胶，采用光罩对所述光刻胶进行曝光与显影处理得到光刻胶层，以所述光刻胶层为阻挡层，对所述低介材质层进行蚀刻，从而得到所述钝化层。
  15. 如权利要求14所述的显示装置，采用物理气相沉积法、化学气象沉积法、涂布法或蒸镀法设置所述低介材质层。
  16. 如权利要求14所述的显示装置，采用干法蚀刻的方式或者湿法蚀刻的方式对所述有机材质层进行蚀刻，从而得到所述钝化层。
  17. 如权利要求14所述的显示装置，所述钝化层的厚度的范围为2300μm～20000μm。
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