WO2020024292A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2020024292A1
WO2020024292A1 PCT/CN2018/098669 CN2018098669W WO2020024292A1 WO 2020024292 A1 WO2020024292 A1 WO 2020024292A1 CN 2018098669 W CN2018098669 W CN 2018098669W WO 2020024292 A1 WO2020024292 A1 WO 2020024292A1
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Prior art keywords
layer
light
substrate
blocking layer
array substrate
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PCT/CN2018/098669
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English (en)
French (fr)
Inventor
贾纬华
张祖强
邱昌明
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深圳市柔宇科技有限公司
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Priority to CN201880094119.6A priority Critical patent/CN112639600A/zh
Priority to PCT/CN2018/098669 priority patent/WO2020024292A1/zh
Publication of WO2020024292A1 publication Critical patent/WO2020024292A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate and a display device.
  • the oxide TFT has poor light stability. When the oxide TFT is exposed to external light, the leakage current of the oxide active layer is likely to increase, which reduces the reliability of the oxide TFT and affects the display quality.
  • an embodiment of the present invention discloses an array substrate and a display device with improved reliability.
  • An array substrate includes a substrate, a thin film transistor provided on the substrate, and a first light blocking layer, the first light blocking layer is located on a side of the thin film transistor away from the substrate, and the thin film
  • the orthographic projection of the oxide active layer of the transistor on the substrate is located within the orthographic projection of the first light blocking layer on the substrate.
  • the array substrate further includes a second light blocking layer, and the second light blocking layer is disposed between the substrate and the oxide active layer.
  • the array substrate further includes a first passivation layer, and the first passivation layer is disposed between the substrate and the second light blocking layer.
  • the array substrate further includes a second passivation layer, and the second passivation layer is located between the oxide active layer and the second light blocking layer.
  • the thin film transistor further includes a gate and a gate insulating layer, the gate is disposed on the substrate, and the second light blocking layer is disposed on the gate and covers the gate.
  • the gate insulating layer is disposed between the oxide active layer and the second light blocking layer.
  • the orthographic projection of the second light blocking layer on the substrate is located within the orthographic projection of the first light blocking layer on the substrate, and the second light blocking layer is on the substrate.
  • the orthographic area on the substrate is smaller than the orthographic area of the first light blocking layer on the substrate.
  • the thin film transistor further includes a gate and a gate insulating layer, the gate is provided on the substrate, and the gate insulating layer is provided between the oxide active layer and the gate. Meanwhile, the second light blocking layer is disposed on the gate insulating layer.
  • the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, the gate, the first gate insulating layer, the second light blocking layer, and the second A gate insulating layer is sequentially stacked on the substrate.
  • the thin film transistor further includes a gate and a gate insulating layer
  • the array substrate further includes a passivation layer, the second light blocking layer, the passivation layer, the oxide active layer, and The gate insulating layer and the gate are sequentially stacked on the substrate, and the second light blocking layer is disposed adjacent to the substrate.
  • the second light blocking layer is made of a passivation layer material doped with a light absorbing material.
  • the second light-blocking layer includes a light-shielding layer and a light-absorbing layer which are arranged in a stack.
  • the first light-blocking layer includes a light-shielding layer and a light-absorbing layer which are arranged in a stack.
  • the array substrate further includes a third passivation layer, the third passivation layer covers the thin film transistor, and the first light blocking layer is disposed on the third passivation layer away from the substrate. One side.
  • the array substrate further includes a fourth passivation layer, and the fourth passivation layer covers a side of the first light blocking layer away from the oxide active layer.
  • the first light blocking layer is formed by doping a light absorbing material with a passivation layer material.
  • a display device includes the array substrate as described above.
  • a first light blocking layer is provided on an oxide active layer side away from the substrate, and an orthographic projection of the oxide active layer on the substrate is located in the first A light-blocking layer is in the orthographic projection on the substrate, which can effectively prevent light from damaging the oxide active layer, and improves the reliability of the array substrate.
  • the array substrate is provided with a second light blocking layer on the side of the oxide active layer adjacent to the substrate, so that the oxide active layer is double protected, further improving the reliability of the array substrate.
  • FIG. 1 is a cross-sectional view of an array substrate according to a first embodiment of the present invention.
  • FIG. 1a is a cross-sectional view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of an array substrate according to a second embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of the array substrate shown in FIG. 2 and a color filter substrate provided on the array substrate.
  • FIG. 4 is a cross-sectional view of an array substrate according to a third embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of an array substrate according to a fourth embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of an array substrate according to a fifth embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of an array substrate according to a sixth embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of an array substrate according to a seventh embodiment of the present invention.
  • FIG. 9 is a cross-sectional view of an array substrate according to an eighth embodiment of the present invention.
  • FIG. 10 is a top view of a display device provided by the present invention.
  • a first embodiment of the present invention provides an array substrate 10.
  • the array substrate 10 includes a substrate 11, a thin film transistor 13 and a first light blocking layer 15.
  • the thin film transistor 13 is disposed on the substrate 11.
  • the first light blocking layer 15 is located on the side of the thin film transistor 13 away from the substrate 10, and is used to prevent light from irradiating the oxide active layer 133 of the thin film transistor 13 to cause damage.
  • the orthographic projection of the oxide active layer 133 on the substrate 11 is located within the orthographic projection of the first light blocking layer 15 on the substrate 11.
  • the orthographic projection of the oxide active layer 133 on the substrate 11 overlaps the orthographic projection of the first light blocking layer 15 on the substrate 11, and the orthographic active layer 133 is on the orthographic projection on the substrate 11.
  • the projection area is smaller than or equal to the orthographic projection area of the first light-blocking layer 15 on the substrate 11.
  • the light is side leakage light from other processes (for example, exposure, development), or reflected light from exposure, or ambient light, or light emitted from a backlight.
  • the thin film transistor 13 has a bottom-gate structure.
  • the thin film transistor 13 includes a gate electrode 131, a gate insulating layer 135, a source electrode 137, and a drain electrode 139.
  • the array substrate 10 further includes a second light blocking layer 17 and a passivation layer 19.
  • the gate electrode 131 is attached to the substrate 11.
  • the second light blocking layer 17 covers a side of the gate electrode 131 away from the substrate 11, and is used to prevent the gate active layer 133 from being damaged by reflected light from the gate.
  • the gate insulating layer 135 is disposed between the oxide active layer 133 and the second light blocking layer 17.
  • the source electrode 137 and the drain electrode 139 are disposed on the oxide active layer 133 away from the substrate 11.
  • the passivation layer 19 is provided on the source electrode 137 and the drain electrode 139 and the oxide active layer 133.
  • the first light blocking layer 15 is disposed on the passivation layer 19.
  • the orthographic projection of the second light-blocking layer 17 on the substrate 11 is located within the orthographic projection of the first light-blocking layer 15 on the substrate 11, the orthographic projection area of the second light-blocking layer 17 on the substrate 11, the first resistance
  • the orthographic projection area of the optical layer 15 on the substrate 11 and the orthographic projection area of the gate electrode 131 on the substrate 11 are substantially the same.
  • the array substrate 10 can be realized through chemical vapor deposition, physical vapor deposition, exposure, development, and etching process steps.
  • the first light-blocking layer 15 and the second light-blocking layer 17 are located on both sides of the oxide active layer 133, respectively, so that the oxide active layer 133 is double-protected and can effectively avoid side light, backlight, ambient light, and gate
  • the destruction of the oxide active layer 133 by polarized light or the like improves the reliability of the array substrate 10.
  • the orthographic projection of the oxide active layer 133 on the substrate 11 is located within the orthographic projection of the first light blocking layer 15 on the substrate 11, it is avoided that the oxide active layer 133 is not blocked by the source 137 and the drain 139. The covered part is damaged by the irradiation of light.
  • the material for the first light blocking layer 15 is made of a light absorbing material, which can absorb the energy of incident light and reduce the destruction of the oxide active layer 133 by the incident light entering the array substrate 10.
  • the light-absorbing material includes one or a combination of a carbon black composition, an organic macromolecule having a hole structure, a carbon nanotube mixture, a resin composite, and the like.
  • the light-absorbing effect of the light-absorbing material reaches 99 In order to avoid damaging the active oxide layer 133 by light, most of the energy of the incident light entering the array substrate 10 can be absorbed.
  • the second light blocking layer 17 is made of an insulating opaque material to avoid affecting the performance of the gate electrode 131.
  • the components of the carbon black composition include: 5% to 20% of a photosensitive resin, 0.1% to 5% of a photoinitiator, 10% to 50% of a carbon black dispersion solution, 30% to 50% of a solvent, and 0.1% to an additive. 1%.
  • the carbon black-containing composition may further include monomers to polymerize small and large molecules; the solvents and additives include various organic solvents and additives that make the surface of the composition containing carbon black flat, for example, the organic solvent may be Ethylene glycol methyl ether, ethylene glycol ether, propylene glycol ether, propylene glycol methyl ether acetate, propylene glycol ether acetate, tetrahydrofuran, cyclohexanone, ethyl cellosolve acetate, butyl cellosolve acetate, 1-methoxy One or two or more of -2-propyl acetate, diethylene glycol dimethyl ether, ethylbenzene, xylene, methanol, or isoacetone.
  • the additive includes one or two or more of a defoaming agent, a wetting agent, and a leveling agent.
  • the particle size of the carbon black in the carbon black composition is greater than or equal to 20 Angstroms and less than or equal to 1000 Angstroms. Preferably, the particle size of the carbon black in the carbon black composition is greater than or equal to 20 Angstroms and less than or equal to 500 Angstroms.
  • the first light blocking layer 15 is made of a light-shielding material, such as a metal material.
  • the materials used to make the first light-blocking layer 15 and the second light-blocking layer 17 are not limited, and the ability to prevent part of the incident light from entering the array substrate 10 to irradiate the oxide active layer 133, such as the first light-blocking layer A side facing away from the substrate 11 is coated with a reflective material as a reflecting surface.
  • the light-blocking effect of the first light-blocking layer 15 is adjusted by adjusting the vertical distance between the first light-blocking layer 15 and the oxide active layer 133;
  • the vertical distance between the object active layers 133 is used to adjust the light blocking effect of the second light blocking layer 17.
  • the first light-blocking layer 15 includes a light-shielding layer 151 and a light-absorbing layer 153 that are stacked.
  • the second light-blocking layer 17 includes a light-shielding layer 171 and a light-absorbing layer 173 and a light-shielding layer.
  • 151 and 171 are made of an opaque material, and the materials made of the light absorbing layers 153 and 173 include a light absorbing material.
  • the light-shielding layer 151 of the first light-shielding layer 15 is disposed on a side of the first light-shielding layer 15 away from the substrate 10, and the light-shielding layer 171 of the second light-shielding layer 17 is disposed on a side of the second light-shielding layer 17 away from the substrate 10. side.
  • the light-shielding layer 151 of the first light-blocking layer 15 may be provided on the side of the first light-blocking layer 15 adjacent to the substrate 10; the light-shielding layer 171 of the second light-blocking layer 17 may be provided on the second light-blocking layer.
  • the first light blocking layer 15 includes at least one of a light blocking layer 151 and a light absorbing layer 153
  • the second light blocking layer 17 includes at least one of a light blocking layer 171 and a light absorbing layer 173.
  • a second embodiment of the present invention provides an array substrate 20.
  • the structure of the array substrate 20 is substantially the same as that of the array substrate 10 provided in the first embodiment, except that the orthographic area of the second light-blocking layer 27 on the substrate 21 is smaller than that of the first light-blocking layer 25 on the substrate 21. Positive projection area.
  • the color filter substrate 201 includes a plurality of light emitting sources 203.
  • a side surface of the gate 231 adjacent to the substrate 21 includes a first end point 2311 and a second end point 2313 which are oppositely disposed.
  • the side surface of the oxide active layer 233 adjacent to the substrate 21 includes a first end point 2331 and a second end point 2333 opposite to each other.
  • the side of the first light blocking layer 25 adjacent to the oxide active layer 233 includes a first boundary 251 and a second boundary 253 opposite to each other.
  • the first end point 2311 of the gate electrode 231 and the first end point 2331 of the oxide active layer 233 correspond to the first boundary 251 of the first light blocking layer 25.
  • the second terminal 2313 of the gate 231 and the second terminal 2333 of the oxide active layer 233 correspond to the second boundary 253 of the first light blocking layer 25.
  • Each light source 203 includes a first boundary 2031 and a second boundary 2033 that are oppositely disposed. Two light emitting sources 203 are selected from the plurality of light emitting sources 203, and the two light emitting sources 203 are a first light emitting source 2035 and a second light emitting source 2037, respectively.
  • the first light emitted from the first light source 2035 from the first boundary 2031 can be irradiated to the first end point 2311 of the gate 231, and the second light emitted from the second light source 2035 from the second boundary 2033 can be irradiated to the oxide source.
  • the first light emitting source 2035 is a light emitting source 203 that can affect the first terminal 2311 of the gate 231 of the thin film transistor 23 and the first terminal 2331 of the oxide active layer 233.
  • the distance from the first boundary 2031 is
  • the first end point 2331 of the oxide active layer 233 is the largest light emitting source to further reduce the probability that the oxide active layer 233 is irradiated with light.
  • the intersection of the first light and the second light is the position of the first boundary 251.
  • the third light emitted from the second light source 2037 from the first boundary 2033 can be irradiated to the second endpoint 2313 of the gate 231, and the fourth light emitted from the second light source 2037 from the second boundary 2033 can be irradiated to the oxide active layer.
  • the second endpoint 233 is 2333.
  • the second light emitting source 2037 is the light emitting source 203 that can affect the second terminal 2313 of the gate 231 of the thin film transistor 23 and the second terminal 2333 of the oxide active layer 233.
  • the second boundary 2033 is away from the oxide.
  • the largest light emitting source 203 at the second end point 2333 of the active layer 233 further reduces the probability that the oxide active layer 233 is irradiated with light.
  • the intersection of the third light and the fourth light is the position of the second boundary 253.
  • the length, the width, and the distance from the oxide active layer 233 of the first light blocking layer 25 are adjusted according to needs.
  • a third embodiment of the present invention provides an array substrate 40.
  • the array substrate 40 has substantially the same structure as the array substrate 10 provided in the first embodiment, except that the gate insulating layer 435 includes a first gate insulating layer 4351 and a second gate insulating layer 4353, and the gate 431 and the first gate
  • the electrode insulating layer 4351, the second light blocking layer 47, the second gate insulating layer 4353, the oxide active layer 433, and the source electrode 437 are sequentially stacked on the substrate 41, and the gate electrode 431 is disposed adjacent to the substrate 41.
  • the second light blocking layer 47 is disposed between the first gate insulating layer 4351 and the second gate insulating layer 4353, in this embodiment, the second light blocking layer 47 is made of a metal material that does not transmit light. In one embodiment, a material of the second light blocking layer 47 includes a light absorbing material. It can be understood that the second light blocking layer 47 is completely covered by the gate insulating layer 435, that is, each side of the second light blocking layer 47 is covered by the gate insulating layer 435.
  • a fourth embodiment of the present invention provides an array substrate 50.
  • the structure of the array substrate 50 is substantially the same as that of the array substrate 10 provided in the first embodiment.
  • the array substrate 50 includes a substrate 51, a thin film transistor 53, a first light blocking layer 55, a second light blocking layer 57 and a passivation layer 58.
  • the thin film transistor 53 has a top gate structure, and the first The arrangement of the light blocking layer 55 and the second light blocking layer 57.
  • the first light blocking layer 55 and the second light blocking layer 57 are both disposed on the passivation layer 58.
  • the passivation layer 58 includes a first passivation layer 581, a second passivation layer 583, a third passivation layer 585, and a fourth passivation layer 587.
  • the first passivation layer 581, the second light-blocking layer 57, the second passivation layer 583, the thin film transistor 53, the third passivation layer 585, the first light-blocking layer 55, and the fourth passivation layer 587 are sequentially stacked on the substrate.
  • the first passivation layer 581 is disposed adjacent to the substrate 51.
  • the oxide active layer 533 of the thin film transistor 53 is located between the first light blocking layer 55 and the second light blocking layer 57.
  • the first light blocking layer 55 is located between the third passivation layer 585 and the fourth passivation layer 587, and the second light blocking layer 57 is located between the first passivation layer 581 and the second passivation layer 583.
  • the thin film transistor 53 further includes a gate electrode 531, a gate insulating layer 535, a source electrode 537, and a drain electrode 539.
  • the oxide active layer 533, the gate insulating layer 535, and the gate electrode 531 are sequentially stacked on the second passivation layer 583 away from On one side of the first passivation layer 581, the oxide active layer 533 is disposed adjacent to the second passivation layer 583.
  • the source electrode 537, the gate insulating layer 535, and the drain electrode 539 are spaced apart from each other on the oxide active layer 533.
  • the gate insulating layer 535 is located between the source electrode 537 and the drain electrode 539, and the third passivation layer 585 covers the gate electrode 531, the source electrode 537, the drain electrode 539, and the oxide active layer 533.
  • a first light-blocking layer 55 is formed on the side of the oxide active layer 533 away from the substrate 51 to prevent the portion of the oxide active layer 533 that is not covered by the gate insulating layer 535, the source 537, and the drain 539 from being exposed to light. Damaged by irradiation.
  • a second light blocking layer 57 is formed on the side of the oxide active layer 533 adjacent to the substrate 51 to prevent the oxide active layer 533 from being affected by a backlight, reflected light, and the like.
  • a material of the second light blocking layer 57 includes a light absorbing material.
  • the light absorbing material is coated on the first passivation layer 583, and the light absorbing material is exposed, developed, and post-baked to form a second light blocking layer 57, which can prevent the light Destruction of the oxide active layer 533 by light leakage, backlight, and the like.
  • a fifth embodiment of the present invention provides an array substrate 60.
  • the structure of the array substrate 60 is substantially the same as that of the array substrate 50 provided in the fourth embodiment, except that the arrangement of the first light blocking layer 65 and the second light blocking layer 67 is different.
  • the passivation layer 68 includes a first passivation layer 681 and a second passivation layer 683.
  • the second light blocking layer 67, the first passivation layer 681, the thin film transistor 63, the second passivation layer 683, and the first light blocking layer 65 are sequentially disposed on the substrate 61, and the second light blocking layer 67 is attached to the substrate. 61 on.
  • a second light-blocking layer 67 is provided on the bottom of the first passivation layer 681 under the oxide active layer 633, and a first light-blocking layer 65 is provided on top of the second passivation layer 683 above the oxide active layer 633. Difficult process and simplified process.
  • a sixth embodiment of the present invention provides an array substrate 70.
  • the structure of the array substrate 70 is substantially the same as that of the array substrate 60 provided in the fifth embodiment, except that the second light blocking layer 77 is located between the oxide active layer 733 and the substrate 71, and the first light blocking layer 77
  • the side surface is attached together with the oxide active layer 733, the second side surface of the second light blocking layer 77 is attached together with the substrate 71, and the second light blocking layer 77 is formed by doping a light absorbing material with a passivation layer material to
  • the second light blocking layer 77 is provided with both the function of a passivation layer and the light blocking function.
  • the passivation layer material includes at least one of silicon oxide and silicon nitride.
  • a first light-blocking layer 75 is provided above the oxide active layer 733, and a light-absorbing material is doped in the passivation layer below the oxide active layer 733 to form a second light-blocking layer 77 to achieve shielding of light.
  • a seventh embodiment of the present invention provides an array substrate 80.
  • the structure of the array substrate 80 is substantially the same as that of the array substrate 60 provided in the fifth embodiment, except that the first light blocking layer 85 covers the thin film transistor 83, and the first light blocking layer 85 is formed by doping a passivation layer material with a light absorbing material.
  • the passivation layer material includes at least one of silicon oxide and silicon nitride.
  • a light-absorbing material is doped in the passivation layer on the oxide active layer 833 to form a first light-blocking layer 85, and a second light-blocking layer 87 is provided outside the first passivation layer 883 under the oxide active layer 833 to realize The shielding of light improves the performance and reliability of the array substrate 80.
  • an eighth embodiment of the present invention provides an array substrate 90.
  • the structure of the array substrate 90 is substantially the same as that of the array substrate 60 provided in the fifth embodiment, except that the first light blocking layer 95 of the array substrate 90 covers the thin film transistor 93, and the second light blocking layer 97 of the array substrate 90 is provided on the thin film transistor.
  • the second light blocking layer 97 and the first light blocking layer 97 are both formed by doping the passivation layer material with a light absorbing material, so as to have both the function of the passivation layer and Double function of blocking light.
  • the present invention further provides a display device 100 including an array substrate according to any one of the above embodiments.
  • Display panels electronic paper, Organic Light-Emitting Diode (OLED) panels, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators and any other products or components with display functions.
  • OLED Organic Light-Emitting Diode
  • the array substrate and the display device provided by the present invention because the first light blocking layer is provided on the oxide active layer side away from the substrate, can effectively avoid damage to the oxide active layer caused by light, and improves the array substrate. Reliability.
  • the array substrate is provided with a second light blocking layer on the side adjacent to the oxide active layer and the substrate, so that the oxide active layer is double-protected, which further improves the reliability of the array substrate.

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Abstract

一种阵列基板(10)，包括衬底(11)、设于衬底(11)上的薄膜晶体管(13)及第一阻光层(15)，第一阻光层(15)位于薄膜晶体管(13)远离衬底(11)的一侧，薄膜晶体管(13)的氧化物有源层(133)于衬底(11)上的正投影位于第一阻光层(15)于衬底(11)上的正投影内。还提供一种显示装置。

Description

阵列基板及显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及显示装置。
背景技术
目前，平板显示器已经占据了显示器市场的主导地位，并且朝着大尺寸，高分辨率的方向发展。为了满足大尺寸，高分辨率的要求，需要提高显示器中薄膜晶体管TFT的迁移率以提高显示效果，但是现有技术中非晶硅(a-Si)薄膜晶体管(Thin Film Transistor，TFT)的迁移率较低，已经成为提高显示效果的制约因素，氧化物TFT由于其比a-Si TFT高的迁移率，应用前途越来越广。
但是，氧化物TFT的光照稳定性不强，氧化物TFT在受到外界光照射时容易造成氧化物有源层的漏电流增加，使得氧化物TFT的信赖性降低，影响显示质量。
发明内容
为解决上述问题，本发明实施例公开一种提高信赖性的阵列基板及显示装置。
一种阵列基板，包括衬底、设于所述衬底上的薄膜晶体管及第一阻光层，所述第一阻光层位于所述薄膜晶体管远离所述衬底的一侧，所述薄膜晶体管的氧化物有源层于所述衬底上的正投影位于所述第一阻光层于所述衬底上的正投影内。
进一步地，所述阵列基板还包括第二阻光层，所述第二阻光层设于所述衬底与所述氧化物有源层之间。
进一步地，所述阵列基板还包括第一钝化层，所述第一钝化层设于所述衬底与所述第二阻光层之间。
进一步地，所述阵列基板还包括第二钝化层，所述第二钝化层位于所述氧化物有源层与所述第二阻光层之间。
进一步地，所述薄膜晶体管还包括栅极及栅极绝缘层，所述栅极设于所述 衬底上，所述第二阻光层设于所述栅极上并覆盖所述栅极，所述栅极绝缘层设于所述氧化物有源层与所述第二阻光层之间。
进一步地，所述第二阻光层于所述衬底上的正投影位于所述第一阻光层于所述衬底上的正投影内，所述第二阻光层于所述衬底上的正投影面积小于所述第一阻光层于所述衬底上的正投影面积。
进一步地，所述薄膜晶体管还包括栅极及栅极绝缘层，所述栅极设于所述衬底上，所述栅极绝缘层设于所述氧化物有源层与所述栅极之间，所述第二阻光层设于所述栅极绝缘层。
进一步地，所述栅极绝缘层包括第一栅极绝缘层及第二栅极绝缘层，所述栅极、所述第一栅极绝缘层、所述第二阻光层及所述第二栅极绝缘层依次层叠设于所述衬底。
进一步地，所述薄膜晶体管还包括栅极及栅极绝缘层，所述阵列基板还包括钝化层，所述第二阻光层、所述钝化层、所述氧化物有源层、所述栅极绝缘层及所述栅极依次层叠设置于所述衬底上，所述第二阻光层与所述衬底相邻设置。
进一步地，所述第二阻光层通过钝化层材料掺杂吸光材料制成。
进一步地，所述第二阻光层包括层叠设置的遮光层与吸光层。
进一步地，所述第一阻光层包括层叠设置的遮光层与吸光层。
进一步地，所述阵列基板还包括第三钝化层，所述第三钝化层覆盖所述薄膜晶体管，所述第一阻光层设于所述第三钝化层远离所述衬底的一侧。
进一步地，所述阵列基板还包括第四钝化层，所述第四钝化层覆盖所述第一阻光层远离所述氧化物有源层的一侧。
进一步地，所述第一阻光层通过钝化层材料掺杂吸光材料形成。
一种显示装置，包括如上所述的阵列基板。
本发明提供的阵列基板及显示装置，由于在氧化物有源层远离衬底一侧设第一阻光层，且所述氧化物有源层于所述衬底上的正投影位于所述第一阻光层于所述衬底上的正投影内，从而能够有效避免光对氧化物有源层的照射造成破坏，提高了阵列基板的信赖性。此外，阵列基板在氧化物有源层与衬底相邻一侧设第二阻光层，从而使氧化物有源层受到双重保护，进一步提高了阵列基板 的信赖性。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一实施方式提供的阵列基板的剖视图。
图1a为本发明一实施方式提供的阵列基板的剖视图。
图2为本发明第二实施方式提供的阵列基板的剖视图。
图3为图2所示阵列基板与设于阵列基板上的彩膜基板的剖视图。
图4为本发明第三实施方式提供的阵列基板的剖视图。
图5为本发明第四实施方式提供的阵列基板的剖视图。
图6为本发明第五实施方式提供的阵列基板的剖视图。
图7为本发明第六实施方式提供的阵列基板的剖视图。
图8为本发明第七实施方式提供的阵列基板的剖视图。
图9为本发明第八实施方式提供的阵列基板的剖视图。
图10为本发明提供的显示装置的俯视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明第一实施方式提供一种阵列基板10。阵列基板10包括衬底11、薄膜晶体管13及第一阻光层15，薄膜晶体管13设于衬底11上。第一阻光层15位于薄膜晶体管13远离衬底10一侧，用于避免光照射薄膜晶 体管13的氧化物有源层133造成破坏。氧化物有源层133于衬底11上的正投影位于第一阻光层15于衬底11上的正投影内。
换而言之，氧化物有源层133位于衬底11上的正投影，重叠于第一阻光层15于衬底11上的正投影，氧化物有源层133位于衬底11上的正投影面积小于或等于第一阻光层15于衬底11上的正投影面积，如此，有效避免光照射至氧化物有源层133对氧化物有源层133进行破坏，从而提高了阵列基板10的信赖性。所述光为其他工艺(例如曝光、显影)的侧漏光，或曝光反射光，或环境光，或背光源的出射光等。
本实施方式中，薄膜晶体管13为底栅结构。薄膜晶体管13包括栅极131、栅极绝缘层135、源极137及漏极139。阵列基板10还包括第二阻光层17及钝化层19。栅极131贴附于衬底11上。第二阻光层17覆盖栅极131远离衬底11的一侧，用于避免栅极反射光等对氧化物有源层133的破坏。栅极绝缘层135设于氧化物有源层133与第二阻光层17之间。源极137及漏极139间隔设于氧化物有源层133远离衬底11一侧。钝化层19设于源极137及漏极139以及氧化物有源层133上。第一阻光层15设于钝化层19上。第二阻光层17于衬底11上的正投影位于第一阻光层15于衬底11上的正投影内，第二阻光层17于衬底11上的正投影面积、第一阻光层15于衬底11上的正投影面积及栅极131于衬底11上的正投影面积大致相同。阵列基板10能够通过化学气相沉积法、物理气相沉积法、曝光、显影、刻蚀等工艺步骤实现。
第一阻光层15与第二阻光层17分别位于氧化物有源层133的两侧，使得氧化物有源层133受到双重保护，能够有效避免侧向光、背光源、环境光、栅极反射光等对氧化物有源层133的破坏，提高了阵列基板10的信赖性。另外，由于氧化物有源层133于衬底11上的正投影位于第一阻光层15于衬底11上的正投影内，避免氧化物有源层133未被源极137及漏极139覆盖的部分受到光的照射而被破坏。
本实施方式中，第一阻光层15的制成材料由吸光材料组成，所述吸光材料能够吸收入射光的能量，减少进入至阵列基板10内的入射光对氧化物有源层133的破坏。所述吸光材料包括炭黑的组合物、存在空穴结构的有机大分子、碳纳米管混合物、树脂复合物等中的一种或几种组合，优选的，所述吸光材料 的吸光效果达到99％以上，以能够吸收进入阵列基板10的入射光的大部分能量，避免光对氧化物有源层133造成破坏。第二阻光层17由绝缘的不透光材料制成，避免影响栅极131的性能。
所述炭黑的组合物的组成成分包括：感光树脂5％～20％、光引发剂0.1％～5％、炭黑分散溶液10％～50％、溶剂30％～50％、添加剂0.1％～1％。其中，包含炭黑的组合物中还可以包含单体，以聚合小分子和大分子；溶剂和添加剂包括多种使得包含炭黑的组合物表面平整的有机溶剂和添加剂，例如：有机溶剂可以是乙二醇甲醚、乙二醇乙醚、丙二醇乙醚、丙二醇甲醚醋酸酯、丙二醇乙醚醋酸酯、四氢呋喃、环已酮、乙基溶纤剂醋酸酯、丁基溶纤剂醋酸酯、1-甲氧基-2-丙基乙酸酯、二乙二醇二甲基醚、乙苯、二甲苯、甲醇或异丙酮等中的一种或两种以上。添加剂包含消泡剂、润湿剂和流平剂中的一种或两种以上。
在一种实施方式中，所述炭黑的组合物中炭黑的粒径大于或等于20埃米，且小于或等于1000埃米。优选的，炭黑的组合物中炭黑的粒径大于或等于20埃米，且小于或等于500埃米。
在一实施方式中，第一阻光层15由不透光的遮光材料制成，例如金属材料。
可以理解，第一阻光层15与第二阻光层17的制成材料不限定，具备阻止部分入射光进入阵列基板10照射氧化物有源层133的能力即可，例如第一阻光层15远离衬底11的侧面涂覆反射材料作为反射面。
在一实施方式中，通过调节第一阻光层15与氧化物有源层133之间的垂直距离，来调节第一阻光层15的阻光效果；通过调节第二阻光层17与氧化物有源层133之间的垂直距离，来调节第二阻光层17的阻光效果。
在一实施方式中，请参阅图1a，第一阻光层15包括层叠设置的遮光层151与吸光层153，第二阻光层17均包括层叠设置的遮光层171与吸光层173，遮光层151、171由不透光材料制成，吸光层153、173的制成材料包括吸光材料。第一阻光层15的遮光层151设于第一阻光层15远离衬底10的一侧，第二阻光层17的遮光层171设于第二阻光层17远离衬底10的一侧。可以理解，第一阻光层15的遮光层151可以设于第一阻光层15与衬底10相邻的一侧；第 二阻光层17的遮光层171可以设于第二阻光层17与衬底10相邻的一侧，第一阻光层15包括遮光层151与吸光层153中的至少一个，第二阻光层17包括遮光层171与吸光层173中的至少一个。
请参阅图2，本发明第二实施方式提供一种阵列基板20。阵列基板20与第一实施方式提供的阵列基板10的结构大致相同，不同在于，第二阻光层27于衬底21上的正投影面积，小于第一阻光层25于衬底21上的正投影面积。
请参阅图3，以位于阵列基板20上方的彩膜基板201的发光源203为例，对如何确定第一阻光层25的边界位置进行简单说明，彩膜基板201与第一阻光层25相邻设置。彩膜基板201包括多个发光源203。
栅极231与衬底21相邻一侧的侧面包括相对设置的第一端点2311及第二端点2313。氧化物有源层233与衬底21相邻一侧的侧面包括相对设置的第一端点2331与第二端点2333。第一阻光层25与氧化物有源层233相邻一侧面包括相对设置的第一边界251及第二边界253。栅极231的第一端点2311、氧化物有源层233的第一端点2331对应于第一阻光层25的第一边界251。栅极231的第二端点2313、氧化物有源层233的第二端点2333对应于第一阻光层25的第二边界253。
每个发光源203包括相对设置的第一边界2031及第二边界2033。选取多个发光源203中的两个发光源203，所述两个发光源203分别为第一发光源2035及第二发光源2037。
第一发光源2035从第一边界2031出射的第一光线能够照射至栅极231的第一端点2311，第一发光源2035从第二边界2033出射的第二光线能够照射至氧化物有源层233的第一端点2331。本实施方式中，第一发光源2035为能够影响薄膜晶体管23的栅极231的第一端点2311及氧化物有源层233的第一端点2331的发光源203中，第一边界2031距离氧化物有源层233的第一端点2331最大的发光源，以进一步降低氧化物有源层233被光照射到的几率。所述第一光线与所述第二光线的交叉点为第一边界251的所在位置。
第二发光源2037从第一边界2033出射的第三光线能够照射至栅极231的第二端点2313，第二发光源2037从第二边界2033出射的第四光线能够照射至氧化物有源层233的第二端点2333。本实施方式中，第二发光源2037为能 够影响薄膜晶体管23的栅极231的第二端点2313及氧化物有源层233的第二端点2333的发光源203中，第二边界2033距离氧化物有源层233的第二端点2333最大的发光源203，以进一步降低氧化物有源层233被光照射到的几率。所述第三光线与所述第四光线的交叉点为第二边界253的所在位置。
可以理解，依据需要对第一阻光层25的长度、宽度以及距离氧化物有源层233进行调节。
请参阅图4，本发明第三实施方式提供一种阵列基板40。阵列基板40与第一实施方式提供的阵列基板10的结构大致相同，不同在于，栅极绝缘层435包括第一栅极绝缘层4351及第二栅极绝缘层4353，栅极431、第一栅极绝缘层4351、第二阻光层47、第二栅极绝缘层4353、氧化物有源层433、源极437依次层叠设于衬底41，栅极431与衬底41相邻设置。
由于第二阻光层47设于第一栅极绝缘层4351与第二栅极绝缘层4353之间，本实施方式中，第二阻光层47由不透光的金属材料制成。在一实施例方式中，第二阻光层47的制成材料包括吸光材料。可以理解，第二阻光层47完全被栅极绝缘层435包覆，即第二阻光层47的各个侧面均被栅极绝缘层435包覆。
请参阅图5，本发明第四实施方式提供一种阵列基板50。阵列基板50与第一实施方式提供的阵列基板10的结构大致相同。阵列基板50包括衬底51、薄膜晶体管53、第一阻光层55、第二阻光层57及钝化层58，不同在于，本实施方式中，薄膜晶体管53为顶栅结构，以及第一阻光层55及第二阻光层57的设置方式。
第一阻光层55与第二阻光层57均设于钝化层58。具体的，钝化层58包括第一钝化层581、第二钝化层583、第三钝化层585及第四钝化层587。第一钝化层581、第二阻光层57、第二钝化层583、薄膜晶体管53、第三钝化层585、第一阻光层55及第四钝化层587依次层叠设置于衬底51上。第一钝化层581与衬底51相邻设置。薄膜晶体管53的氧化物有源层533位于第一阻光层55及第二阻光层57之间。第一阻光层55位于第三钝化层585及第四钝化层587之间，第二阻光层57位于第一钝化层581与第二钝化层583之间。
薄膜晶体管53还包括栅极531、栅极绝缘层535、源极537及漏极539， 氧化物有源层533、栅极绝缘层535及栅极531依次层叠设于第二钝化层583远离第一钝化层581的一侧，氧化物有源层533与第二钝化层583相邻设置，源极537、栅极绝缘层535及漏极539间隔设于氧化物有源层533上，栅极绝缘层535位于源极537与漏极539之间，第三钝化层585覆盖栅极531、源极537、漏极539以及氧化物有源层533。
在氧化物有源层533远离衬底51的一侧形成第一阻光层55，避免氧化物有源层533未被栅极绝缘层535、源极537及漏极539覆盖的部分受到光的照射而被破坏。在氧化物有源层533与衬底51相邻的一侧形成第二阻光层57，避免氧化物有源层533受到背光源、反射光等的影响。
本实施方式中，第二阻光层57的制成材料包括吸光材料。制备阵列基板50时，在所述第一钝化层583上涂布所述吸光材料，对所述吸光材料进行曝光、显影、后烘工艺，形成第二阻光层57，可起到防止侧漏光、背光源等对氧化物有源层533的破坏。
请参阅图6，本发明第五实施方式提供一种阵列基板60。阵列基板60与第四实施方式提供的阵列基板50的结构大致相同，不同在于，第一阻光层65与第二阻光层67的设置方式。
钝化层68包括第一钝化层681及第二钝化层683。第二阻光层67、第一钝化层681、薄膜晶体管63、第二钝化层683及第一阻光层65依次设置于衬底61上，第二阻光层67贴附于衬底61上。
在氧化物有源层633下方的第一钝化层681底部设置第二阻光层67，在氧化物有源层633上方的第二钝化层683顶部设置第一阻光层65，降低制作工艺难度，简化制程。
请参阅图7，本发明第六实施方式提供一种阵列基板70。阵列基板70与第五实施方式提供的阵列基板60的结构大致相同，不同在于，第二阻光层77位于氧化物有源层733与衬底71之间，第二阻光层77的第一侧面与氧化物有源层733贴附于一起，第二阻光层77的第二侧面与衬底71贴附于一起，第二阻光层77通过钝化层材料掺杂吸光材料形成，以使第二阻光层77同时具备钝化层的功能及阻光的双重作用。本实施方式中，所述钝化层材料包括氧化硅、氮化硅中的至少一种。
在氧化物有源层733上方设置第一阻光层75，在氧化物有源层733下方的钝化层中掺杂吸光材料形成第二阻光层77，实现对光的屏蔽。
请参阅图8，本发明第七实施方式提供一种阵列基板80。阵列基板80与第五实施方式提供的阵列基板60的结构大致相同，不同在于，第一阻光层85覆盖薄膜晶体管83，第一阻光层85通过将钝化层材料掺杂吸光材料形成，以同时具备钝化层的功能及阻光的双重作用。本实施方式中，所述钝化层材料包括氧化硅、氮化硅中的至少一种。
在氧化物有源层833上的钝化层中掺杂吸光材料形成第一阻光层85，在氧化物有源层833下方的第一钝化层883外设置第二阻光层87，实现对光的屏蔽，提高阵列基板80的性能及信赖性。
请参阅图9，本发明第八实施方式提供一种阵列基板90。阵列基板90与第五实施方式提供的阵列基板60的结构大致相同，不同在于，阵列基板90的第一阻光层95覆盖薄膜晶体管93，阵列基板90的第二阻光层97设于薄膜晶体管93的氧化物有源层933与衬底91之间，第二阻光层97及第一阻光层97均通过将钝化层材料掺杂吸光材料形成，以同时具备钝化层的功能及阻光的双重作用。
请参阅图10，本发明还提供一种显示装置100，包括如上任意一实施方式所述的阵列基板。显示面板、电子纸、有机发光二极管(Organic Light-Emitting Diode，OLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明提供的阵列基板及显示装置，由于在氧化物有源层远离衬底一侧设第一阻光层，从而能够有效避免光对氧化物有源层的照射造成破坏，提高了阵列基板的信赖性。此外，阵列基板在氧化物有源层与衬底相邻一侧设第二阻光层，从而使氧化物有源层受到双重保护，进一步提高了阵列基板的信赖性。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (16)

  1. 一种阵列基板，其特征在于，包括衬底、设于所述衬底上的薄膜晶体管及第一阻光层，所述第一阻光层位于所述薄膜晶体管远离所述衬底的一侧，所述薄膜晶体管的氧化物有源层于所述衬底上的正投影位于所述第一阻光层于所述衬底上的正投影内。
  2. 如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括第二阻光层，所述第二阻光层设于所述衬底与所述氧化物有源层之间。
  3. 如权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括第一钝化层，所述第一钝化层设于所述衬底与所述第二阻光层之间。
  4. 如权利要求3所述的阵列基板，其特征在于，所述阵列基板还包括第二钝化层，所述第二钝化层位于所述氧化物有源层与所述第二阻光层之间。
  5. 如权利要求2所述的阵列基板，其特征在于，所述薄膜晶体管还包括栅极及栅极绝缘层，所述栅极设于所述衬底上，所述第二阻光层设于所述栅极上并覆盖所述栅极，所述栅极绝缘层设于所述氧化物有源层与所述第二阻光层之间。
  6. 如权利要求5所述的阵列基板，其特征在于，所述第二阻光层于所述衬底上的正投影位于所述第一阻光层于所述衬底上的正投影内，所述第二阻光层于所述衬底上的正投影面积小于所述第一阻光层于所述衬底上的正投影面积。
  7. 如权利要求2所述的阵列基板，其特征在于，所述薄膜晶体管还包括栅极及栅极绝缘层，所述栅极设于所述衬底上，所述栅极绝缘层设于所述氧化物有源层与所述栅极之间，所述第二阻光层设于所述栅极绝缘层。
  8. 如权利要求7所述的阵列基板，其特征在于，所述栅极绝缘层包括第一栅极绝缘层及第二栅极绝缘层，所述栅极、所述第一栅极绝缘层、所述第二阻光层及所述第二栅极绝缘层依次层叠设于所述衬底。
  9. 如权利要求2所述的阵列基板，其特征在于，所述薄膜晶体管还包括栅极及栅极绝缘层，所述阵列基板还包括钝化层，所述第二阻光层、所述钝化层、所述氧化物有源层、所述栅极绝缘层及所述栅极依次层叠设置于所述衬底 上，所述第二阻光层与所述衬底相邻设置。
  10. 如权利要求2所述的阵列基板，其特征在于，所述第二阻光层通过钝化层材料掺杂吸光材料制成。
  11. 如权利要求2所述的阵列基板，其特征在于，所述第二阻光层包括层叠设置的遮光层与吸光层。
  12. 如权利要求1所述的阵列基板，其特征在于，所述第一阻光层包括层叠设置的遮光层与吸光层。
  13. 如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括第三钝化层，所述第三钝化层覆盖所述薄膜晶体管，所述第一阻光层设于所述第三钝化层远离所述衬底的一侧。
  14. 如权利要求13所述的阵列基板，其特征在于，所述阵列基板还包括第四钝化层，所述第四钝化层覆盖所述第一阻光层远离所述氧化物有源层的一侧。
  15. 如权利要求1所述的阵列基板，其特征在于，所述第一阻光层通过钝化层材料掺杂吸光材料形成。
  16. 一种显示装置，其特征在于，所述显示装置包括如权利要求1-15项中任意一项所述的阵列基板。
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