WO2020021652A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2020021652A1
WO2020021652A1 PCT/JP2018/027881 JP2018027881W WO2020021652A1 WO 2020021652 A1 WO2020021652 A1 WO 2020021652A1 JP 2018027881 W JP2018027881 W JP 2018027881W WO 2020021652 A1 WO2020021652 A1 WO 2020021652A1
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WO
WIPO (PCT)
Prior art keywords
region
semiconductor
buried
conductivity type
semiconductor device
Prior art date
Application number
PCT/JP2018/027881
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English (en)
Japanese (ja)
Inventor
藤田　直人
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サンケン電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by サンケン電気株式会社 filed Critical サンケン電気株式会社
Priority to PCT/JP2018/027881 priority Critical patent/WO2020021652A1/fr
Publication of WO2020021652A1 publication Critical patent/WO2020021652A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device in which a current path of a main current is parallel to a main surface.
  • a structure is disclosed in which a field plate is arranged between a gate electrode and a drain region of a MOSFET (metal oxide semiconductor field effect transistor) (see Patent Document 1).
  • MOSFET metal oxide semiconductor field effect transistor
  • the breakdown voltage of the semiconductor device is improved by arranging the field plate on the thermal oxide film formed between the gate electrode and the drain region.
  • An object of the present invention is to provide a lateral semiconductor device capable of improving withstand voltage.
  • a semiconductor substrate of a first conductivity type a buried region of a second conductivity type buried in a part of the upper surface of the semiconductor substrate, and a buried region selectively covering the buried region on the upper surface of the semiconductor substrate.
  • a second conductive type first semiconductor region having a lower impurity concentration than the buried region, and a first conductive region disposed on the upper surface of the semiconductor substrate in a remaining region of the region where the first semiconductor region is disposed.
  • a gate electrode disposed above the second semiconductor region between the drain region and the source region.
  • the position of the opposite end of the buried region facing the second semiconductor region in plan view is the drain of the gate electrode.
  • the edge near the region and the gate voltage of the drain region The semiconductor device is provided which is between the near side of the end portion.
  • FIG. 2 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.
  • 6 is a graph showing the relationship between the position of the opposite end of the buried region and the breakdown voltage of the semiconductor device.
  • FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 1).
  • FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 2).
  • FIG. 7 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 3).
  • FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 4).
  • FIG. 9 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to another embodiment of the present invention.
  • the semiconductor device includes a buried region 20 of a second conductivity type buried in a part of the upper surface of a semiconductor substrate 10 of a first conductivity type, and covers the buried region 20. And a first semiconductor region 30 of the second conductivity type selectively disposed on the upper surface of the semiconductor substrate 10.
  • the buried region 20 is in contact with the semiconductor substrate 10, and the first semiconductor region 30 is in contact with the semiconductor substrate 10 in a region where the buried region 20 is not arranged.
  • the impurity concentration of the first semiconductor region 30 is set lower than the impurity concentration of the buried region 20.
  • the semiconductor device shown in FIG. 1 further includes a second semiconductor region 40 of the first conductivity type disposed on the upper surface of the semiconductor substrate 10 in the remaining region where the first semiconductor region 30 is disposed.
  • the second conductivity type drain region 50 is disposed on a part of the upper surface of the first semiconductor region 30, and the second conductivity type source region 60 is formed on a part of the upper surface of the second semiconductor region 40.
  • a gate electrode 80 is disposed above the second semiconductor region 40 via a gate insulating film 70.
  • the end of the buried region 20 facing the second semiconductor region 40 (hereinafter referred to as “opposite end”) in plan view is positioned closer to the drain region 50 of the gate electrode 80. Between the end and the end of the drain region 50 on the side closer to the gate electrode 80.
  • the first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is p-type, the second conductivity type is n-type, and if the first conductivity type is n-type, the second conductivity type is p-type.
  • the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.
  • the semiconductor device shown in FIG. 1 is a lateral transistor in which a main current flows between the source region 60 and the drain region 50 in parallel with the main surface of the semiconductor substrate 10 in the ON operation.
  • a basic operation of the semiconductor device illustrated in FIG. 1 will be described.
  • the semiconductor device is turned on by controlling the potential of the gate electrode 80 in a state where a positive potential is applied to the drain region 50 with reference to the potential of the source region 60. That is, by setting the voltage between the gate electrode 80 and the source region 60 to a predetermined threshold voltage or more, a channel is formed in the second semiconductor region 40 below the gate electrode 80. Thereby, a main current flows between the source region 60 and the drain region 50.
  • the voltage between the gate electrode 80 and the source region 60 is set lower than a predetermined threshold voltage. As a result, the channel disappears and the main current is cut off.
  • the opposite end of the buried region 20 has an end on the side closer to the drain region 50 in a region where a channel is formed below the gate electrode 80 in the ON operation (hereinafter, referred to as a “channel forming region”), and It is located between the region 50.
  • the depletion layer spreads from the pn junction at the interface between the semiconductor substrate 10 and the second semiconductor region 40 of the first conductivity type and the first semiconductor region 30 and the buried region 20 of the second conductivity type. Since the buried region 20 has a higher impurity concentration than the first semiconductor region 30, the depletion layer is formed at the interface between the buried region 20 and the semiconductor substrate 10 rather than at the interface between the first semiconductor region 30 and the semiconductor substrate 10. Stretch long to the side. Therefore, the breakdown voltage of the semiconductor device shown in FIG. 1 can be improved as compared with the semiconductor device having no buried region 20. By making the area where the semiconductor substrate 10 contacts the buried region 20 larger than the area where the semiconductor substrate 10 contacts the first semiconductor region 30, the breakdown voltage of the semiconductor device can be further improved.
  • FIG. 2 shows the results of the investigation.
  • the vertical axis in FIG. 2 is the breakdown voltage of the semiconductor device.
  • the horizontal axis in FIG. 2 indicates the distance La from the end of the drain region 50 closer to the drain region 50 to the distance La to the end of the buried region 20 closer to the drain region 50 when the end is closer to the gate electrode 80. This is the value of the ratio of the distance Lb to the opposing end (hereinafter, referred to as “Lb / La ratio”).
  • the distance La and the distance Lb are distances in plan view.
  • the breakdown voltage of the semiconductor device shown in FIG. 1 is shown by a solid line, and the breakdown voltage of the semiconductor device having no buried region 20 is shown by a broken line for reference.
  • the withstand voltage of the semiconductor device decreases as shown in FIG. This is because if the buried region 20 is extended too much toward the gate electrode 80, the lateral expansion of a depletion layer formed between the first semiconductor region 30 and the second semiconductor region 40 is suppressed. . That is, before the depletion layer spreads sufficiently, breakdown voltage breakdown occurs between the first semiconductor region 30 and the second semiconductor region 40, and the breakdown voltage of the semiconductor device decreases.
  • the breakdown withstand voltage first occurs at the interface between the buried region 20 and the semiconductor substrate 10. Occurs.
  • the position of the opposing end of the buried region 20 is moved closer to the second semiconductor region 40 beyond the maximum breakdown voltage position, breakdown breakdown occurs first at the interface between the first semiconductor region 30 and the second semiconductor region 40. .
  • the breakdown voltage increases at the interface between the buried region 20 and the semiconductor substrate 10. Greatly decreases.
  • the opposite end of the buried region 20 is connected to the end of the gate electrode 80 closer to the drain region 50 and closer to the gate electrode 80 of the drain region 50. Between the side ends. Thereby, the breakdown voltage of the semiconductor device can be improved. In particular, setting the Lb / La ratio to 80.5% improves the breakdown voltage of the semiconductor device.
  • FIG. 1 a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the drawings.
  • the method of manufacturing a semiconductor device described below is an example, and can be realized by various other manufacturing methods including this modification.
  • a semiconductor substrate 10 of the first conductivity type is prepared.
  • a p-type silicon substrate is used as the semiconductor substrate 10.
  • the impurity concentration of the semiconductor substrate 10 is about 5.0 ⁇ 10 13 to 4.5 ⁇ 10 14 cm ⁇ 3 .
  • a substrate other than a silicon substrate may be used as the semiconductor substrate 10.
  • a buried region 20 is formed so as to be buried in a part of the upper surface of the semiconductor substrate 10.
  • an n-type impurity is selectively ion-implanted into a part of the upper surface of the semiconductor substrate 10 using a mask material formed by a photolithography technique to form the buried region 20 at a predetermined position.
  • the n-type impurity is, for example, arsenic or phosphorus.
  • the thickness of the buried region 20 is about 15 to 25 ⁇ m, and the impurity concentration is about 1.1 ⁇ 10 15 to 1.5 ⁇ 10 15 cm ⁇ 3 .
  • a first semiconductor region 30 is formed on the entire upper surface of the semiconductor substrate 10 so as to cover the buried region 20.
  • the first semiconductor region 30 is formed by using an epitaxial growth method.
  • the thickness of the first semiconductor region 30 is about 5 to 10 ⁇ m, and the impurity concentration is about 8.0 ⁇ 10 14 to 1.0 ⁇ 10 15 cm ⁇ 3 .
  • a p-type impurity is selectively ion-implanted into a part of the first semiconductor region 30 to form a second semiconductor region 40.
  • the second semiconductor region 40 is formed so as to reach the upper surface of the semiconductor substrate 10.
  • the p-type impurity is, for example, boron.
  • the thickness of the second semiconductor region 40 is about 10 to 15 ⁇ m, and the impurity concentration is about 5.0 ⁇ 10 15 to 1.0 ⁇ 10 18 cm ⁇ 3 .
  • a drain region 50 and a source region 60 are formed.
  • an n-type impurity is selectively implanted into a part of the upper portion of the first semiconductor region 30 by an ion implantation method using a mask material patterned using a photolithography technique as a mask to form the drain region 50.
  • the source region 60 is formed by selectively implanting an n-type impurity into a part of the upper portion of the second semiconductor region 40.
  • the gate insulating film 70 and the gate electrode 80 are formed at predetermined positions, and the semiconductor device shown in FIG. 1 is completed.
  • the impurities in the buried region 20 diffuse around due to the influence of heat treatment in the manufacturing process after the buried region 20 is formed. Therefore, the upper part of the buried region 20 extends upward, and the interface between the buried region 20 and the first semiconductor region 30 is located higher than the interface between the semiconductor substrate 10 and the first semiconductor region 30.
  • the breakdown voltage is reduced by disposing the buried region 20. It has been found that the effect of improving is remarkable.
  • a field insulating film 90 is formed on the upper surface of the first semiconductor region 30 between the drain region 50 and the gate electrode 80, and the field plate 100 is disposed on the upper surface of the field insulating film 90. Is also good. By setting the field plate 100 to a predetermined potential, the electric field concentration at the end of the gate electrode 80 near the drain region 50 is reduced, and the withstand voltage of the semiconductor device can be further improved.
  • a back gate region 110 of the first conductivity type is arranged on a part of the upper surface of the second semiconductor region 40.
  • the first conductive type connection region 120 is buried in the upper portion of the semiconductor substrate 10 in contact with the lower surface of the second semiconductor region 40.
  • the back gate region 110 and the semiconductor substrate 10 are electrically connected via the second semiconductor region 40 and the connection region 120.
  • the semiconductor device is a MOSFET
  • the semiconductor device may be a transistor having another structure.
  • the present invention is applicable even when the semiconductor device is a JFET.
  • the semiconductor device of the present invention can be used in the electronic equipment industry including the manufacturing industry for manufacturing horizontal semiconductor devices.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur comprenant : une région enfouie de second type de conductivité (20) enfouie dans la surface supérieure d'un substrat semi-conducteur de premier type de conductivité (10) ; une première région semi-conductrice de second type de conductivité (30) qui est disposée sur la surface supérieure du substrat semi-conducteur (10) de façon à recouvrir la région enfouie (20) et a une concentration d'impuretés inférieure à celle de la région enfouie (20) ; une seconde région semi-conductrice de premier type de conductivité (40) disposée sur la surface supérieure du substrat semi-conducteur (10) dans une région restante de la région où la première région semi-conductrice (30) est disposée ; une région de drain de second type de conductivité (50) disposée sur la surface supérieure de la première région semi-conductrice (30) ; une région de source de second type de conductivité (60) disposée sur la surface supérieure de la seconde région semi-conductrice (40) ; et une électrode de grille (80) disposée au-dessus de la seconde région semi-conductrice (40) entre la région de drain (50) et la région de source (60), la position, en vue en plan, de l'extrémité opposée de la région enfouie (20) faisant face à la seconde région semi-conductrice (40) étant entre l'extrémité de l'électrode de grille (80) sur le côté plus proche de la région de drain (50) et la région de drain (50).
PCT/JP2018/027881 2018-07-25 2018-07-25 Dispositif à semi-conducteur WO2020021652A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/027881 WO2020021652A1 (fr) 2018-07-25 2018-07-25 Dispositif à semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/027881 WO2020021652A1 (fr) 2018-07-25 2018-07-25 Dispositif à semi-conducteur

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WO2020021652A1 true WO2020021652A1 (fr) 2020-01-30

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236142A (ja) * 2004-02-20 2005-09-02 Shindengen Electric Mfg Co Ltd 横型短チャネルｄｍｏｓ及びその製造方法並びに半導体装置
JP2006344817A (ja) * 2005-06-09 2006-12-21 Toyota Motor Corp 半導体装置
JP2011023734A (ja) * 2010-09-08 2011-02-03 Mitsubishi Electric Corp 半導体装置
JP2013122948A (ja) * 2011-12-09 2013-06-20 Seiko Instruments Inc 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236142A (ja) * 2004-02-20 2005-09-02 Shindengen Electric Mfg Co Ltd 横型短チャネルｄｍｏｓ及びその製造方法並びに半導体装置
JP2006344817A (ja) * 2005-06-09 2006-12-21 Toyota Motor Corp 半導体装置
JP2011023734A (ja) * 2010-09-08 2011-02-03 Mitsubishi Electric Corp 半導体装置
JP2013122948A (ja) * 2011-12-09 2013-06-20 Seiko Instruments Inc 半導体装置およびその製造方法

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