WO2020021652A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2020021652A1
WO2020021652A1 PCT/JP2018/027881 JP2018027881W WO2020021652A1 WO 2020021652 A1 WO2020021652 A1 WO 2020021652A1 JP 2018027881 W JP2018027881 W JP 2018027881W WO 2020021652 A1 WO2020021652 A1 WO 2020021652A1
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region
semiconductor
buried
conductivity type
semiconductor device
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PCT/JP2018/027881
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French (fr)
Japanese (ja)
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藤田　直人
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サンケン電気株式会社
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Priority to PCT/JP2018/027881 priority Critical patent/WO2020021652A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device in which a current path of a main current is parallel to a main surface.
  • a structure is disclosed in which a field plate is arranged between a gate electrode and a drain region of a MOSFET (metal oxide semiconductor field effect transistor) (see Patent Document 1).
  • MOSFET metal oxide semiconductor field effect transistor
  • the breakdown voltage of the semiconductor device is improved by arranging the field plate on the thermal oxide film formed between the gate electrode and the drain region.
  • An object of the present invention is to provide a lateral semiconductor device capable of improving withstand voltage.
  • a semiconductor substrate of a first conductivity type a buried region of a second conductivity type buried in a part of the upper surface of the semiconductor substrate, and a buried region selectively covering the buried region on the upper surface of the semiconductor substrate.
  • a second conductive type first semiconductor region having a lower impurity concentration than the buried region, and a first conductive region disposed on the upper surface of the semiconductor substrate in a remaining region of the region where the first semiconductor region is disposed.
  • a gate electrode disposed above the second semiconductor region between the drain region and the source region.
  • the position of the opposite end of the buried region facing the second semiconductor region in plan view is the drain of the gate electrode.
  • the edge near the region and the gate voltage of the drain region The semiconductor device is provided which is between the near side of the end portion.
  • FIG. 2 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.
  • 6 is a graph showing the relationship between the position of the opposite end of the buried region and the breakdown voltage of the semiconductor device.
  • FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 1).
  • FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 2).
  • FIG. 7 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 3).
  • FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 4).
  • FIG. 9 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to another embodiment of the present invention.
  • the semiconductor device includes a buried region 20 of a second conductivity type buried in a part of the upper surface of a semiconductor substrate 10 of a first conductivity type, and covers the buried region 20. And a first semiconductor region 30 of the second conductivity type selectively disposed on the upper surface of the semiconductor substrate 10.
  • the buried region 20 is in contact with the semiconductor substrate 10, and the first semiconductor region 30 is in contact with the semiconductor substrate 10 in a region where the buried region 20 is not arranged.
  • the impurity concentration of the first semiconductor region 30 is set lower than the impurity concentration of the buried region 20.
  • the semiconductor device shown in FIG. 1 further includes a second semiconductor region 40 of the first conductivity type disposed on the upper surface of the semiconductor substrate 10 in the remaining region where the first semiconductor region 30 is disposed.
  • the second conductivity type drain region 50 is disposed on a part of the upper surface of the first semiconductor region 30, and the second conductivity type source region 60 is formed on a part of the upper surface of the second semiconductor region 40.
  • a gate electrode 80 is disposed above the second semiconductor region 40 via a gate insulating film 70.
  • the end of the buried region 20 facing the second semiconductor region 40 (hereinafter referred to as “opposite end”) in plan view is positioned closer to the drain region 50 of the gate electrode 80. Between the end and the end of the drain region 50 on the side closer to the gate electrode 80.
  • the first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is p-type, the second conductivity type is n-type, and if the first conductivity type is n-type, the second conductivity type is p-type.
  • the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.
  • the semiconductor device shown in FIG. 1 is a lateral transistor in which a main current flows between the source region 60 and the drain region 50 in parallel with the main surface of the semiconductor substrate 10 in the ON operation.
  • a basic operation of the semiconductor device illustrated in FIG. 1 will be described.
  • the semiconductor device is turned on by controlling the potential of the gate electrode 80 in a state where a positive potential is applied to the drain region 50 with reference to the potential of the source region 60. That is, by setting the voltage between the gate electrode 80 and the source region 60 to a predetermined threshold voltage or more, a channel is formed in the second semiconductor region 40 below the gate electrode 80. Thereby, a main current flows between the source region 60 and the drain region 50.
  • the voltage between the gate electrode 80 and the source region 60 is set lower than a predetermined threshold voltage. As a result, the channel disappears and the main current is cut off.
  • the opposite end of the buried region 20 has an end on the side closer to the drain region 50 in a region where a channel is formed below the gate electrode 80 in the ON operation (hereinafter, referred to as a “channel forming region”), and It is located between the region 50.
  • the depletion layer spreads from the pn junction at the interface between the semiconductor substrate 10 and the second semiconductor region 40 of the first conductivity type and the first semiconductor region 30 and the buried region 20 of the second conductivity type. Since the buried region 20 has a higher impurity concentration than the first semiconductor region 30, the depletion layer is formed at the interface between the buried region 20 and the semiconductor substrate 10 rather than at the interface between the first semiconductor region 30 and the semiconductor substrate 10. Stretch long to the side. Therefore, the breakdown voltage of the semiconductor device shown in FIG. 1 can be improved as compared with the semiconductor device having no buried region 20. By making the area where the semiconductor substrate 10 contacts the buried region 20 larger than the area where the semiconductor substrate 10 contacts the first semiconductor region 30, the breakdown voltage of the semiconductor device can be further improved.
  • FIG. 2 shows the results of the investigation.
  • the vertical axis in FIG. 2 is the breakdown voltage of the semiconductor device.
  • the horizontal axis in FIG. 2 indicates the distance La from the end of the drain region 50 closer to the drain region 50 to the distance La to the end of the buried region 20 closer to the drain region 50 when the end is closer to the gate electrode 80. This is the value of the ratio of the distance Lb to the opposing end (hereinafter, referred to as “Lb / La ratio”).
  • the distance La and the distance Lb are distances in plan view.
  • the breakdown voltage of the semiconductor device shown in FIG. 1 is shown by a solid line, and the breakdown voltage of the semiconductor device having no buried region 20 is shown by a broken line for reference.
  • the withstand voltage of the semiconductor device decreases as shown in FIG. This is because if the buried region 20 is extended too much toward the gate electrode 80, the lateral expansion of a depletion layer formed between the first semiconductor region 30 and the second semiconductor region 40 is suppressed. . That is, before the depletion layer spreads sufficiently, breakdown voltage breakdown occurs between the first semiconductor region 30 and the second semiconductor region 40, and the breakdown voltage of the semiconductor device decreases.
  • the breakdown withstand voltage first occurs at the interface between the buried region 20 and the semiconductor substrate 10. Occurs.
  • the position of the opposing end of the buried region 20 is moved closer to the second semiconductor region 40 beyond the maximum breakdown voltage position, breakdown breakdown occurs first at the interface between the first semiconductor region 30 and the second semiconductor region 40. .
  • the breakdown voltage increases at the interface between the buried region 20 and the semiconductor substrate 10. Greatly decreases.
  • the opposite end of the buried region 20 is connected to the end of the gate electrode 80 closer to the drain region 50 and closer to the gate electrode 80 of the drain region 50. Between the side ends. Thereby, the breakdown voltage of the semiconductor device can be improved. In particular, setting the Lb / La ratio to 80.5% improves the breakdown voltage of the semiconductor device.
  • FIG. 1 a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the drawings.
  • the method of manufacturing a semiconductor device described below is an example, and can be realized by various other manufacturing methods including this modification.
  • a semiconductor substrate 10 of the first conductivity type is prepared.
  • a p-type silicon substrate is used as the semiconductor substrate 10.
  • the impurity concentration of the semiconductor substrate 10 is about 5.0 ⁇ 10 13 to 4.5 ⁇ 10 14 cm ⁇ 3 .
  • a substrate other than a silicon substrate may be used as the semiconductor substrate 10.
  • a buried region 20 is formed so as to be buried in a part of the upper surface of the semiconductor substrate 10.
  • an n-type impurity is selectively ion-implanted into a part of the upper surface of the semiconductor substrate 10 using a mask material formed by a photolithography technique to form the buried region 20 at a predetermined position.
  • the n-type impurity is, for example, arsenic or phosphorus.
  • the thickness of the buried region 20 is about 15 to 25 ⁇ m, and the impurity concentration is about 1.1 ⁇ 10 15 to 1.5 ⁇ 10 15 cm ⁇ 3 .
  • a first semiconductor region 30 is formed on the entire upper surface of the semiconductor substrate 10 so as to cover the buried region 20.
  • the first semiconductor region 30 is formed by using an epitaxial growth method.
  • the thickness of the first semiconductor region 30 is about 5 to 10 ⁇ m, and the impurity concentration is about 8.0 ⁇ 10 14 to 1.0 ⁇ 10 15 cm ⁇ 3 .
  • a p-type impurity is selectively ion-implanted into a part of the first semiconductor region 30 to form a second semiconductor region 40.
  • the second semiconductor region 40 is formed so as to reach the upper surface of the semiconductor substrate 10.
  • the p-type impurity is, for example, boron.
  • the thickness of the second semiconductor region 40 is about 10 to 15 ⁇ m, and the impurity concentration is about 5.0 ⁇ 10 15 to 1.0 ⁇ 10 18 cm ⁇ 3 .
  • a drain region 50 and a source region 60 are formed.
  • an n-type impurity is selectively implanted into a part of the upper portion of the first semiconductor region 30 by an ion implantation method using a mask material patterned using a photolithography technique as a mask to form the drain region 50.
  • the source region 60 is formed by selectively implanting an n-type impurity into a part of the upper portion of the second semiconductor region 40.
  • the gate insulating film 70 and the gate electrode 80 are formed at predetermined positions, and the semiconductor device shown in FIG. 1 is completed.
  • the impurities in the buried region 20 diffuse around due to the influence of heat treatment in the manufacturing process after the buried region 20 is formed. Therefore, the upper part of the buried region 20 extends upward, and the interface between the buried region 20 and the first semiconductor region 30 is located higher than the interface between the semiconductor substrate 10 and the first semiconductor region 30.
  • the breakdown voltage is reduced by disposing the buried region 20. It has been found that the effect of improving is remarkable.
  • a field insulating film 90 is formed on the upper surface of the first semiconductor region 30 between the drain region 50 and the gate electrode 80, and the field plate 100 is disposed on the upper surface of the field insulating film 90. Is also good. By setting the field plate 100 to a predetermined potential, the electric field concentration at the end of the gate electrode 80 near the drain region 50 is reduced, and the withstand voltage of the semiconductor device can be further improved.
  • a back gate region 110 of the first conductivity type is arranged on a part of the upper surface of the second semiconductor region 40.
  • the first conductive type connection region 120 is buried in the upper portion of the semiconductor substrate 10 in contact with the lower surface of the second semiconductor region 40.
  • the back gate region 110 and the semiconductor substrate 10 are electrically connected via the second semiconductor region 40 and the connection region 120.
  • the semiconductor device is a MOSFET
  • the semiconductor device may be a transistor having another structure.
  • the present invention is applicable even when the semiconductor device is a JFET.
  • the semiconductor device of the present invention can be used in the electronic equipment industry including the manufacturing industry for manufacturing horizontal semiconductor devices.

Abstract

A semiconductor device comprises: a second conductivity type buried region (20) buried in the upper surface of a first conductivity type semiconductor substrate (10); a second conductivity type first semiconductor region (30) that is disposed on the upper surface of the semiconductor substrate (10) so as to cover the buried region (20) and has a lower impurity concentration than the buried region (20); a first conductivity type second semiconductor region (40) disposed on the upper surface of the semiconductor substrate (10) in a remaining region of the region where the first semiconductor region (30) is disposed; a second conductivity type drain region (50) disposed on the upper surface of the first semiconductor region (30); a second conductivity type source region (60) disposed on the upper surface of the second semiconductor region (40); and a gate electrode (80) disposed above the second semiconductor region (40) between the drain region (50) and the source region (60), wherein the position, in plan view, of the opposite end of the buried region (20) facing the second semiconductor region (40) is between the end of the gate electrode (80) on the side closer to the drain region (50) and the drain region (50).

Description

半導体装置Semiconductor device
　 本発明は、主電流の電流経路が主面と平行である半導体装置に関する。 << The present invention relates to a semiconductor device in which a current path of a main current is parallel to a main surface.
　半導体装置の耐圧を向上させるために、種々の対策が検討されている。例えば、ＭＯＳＦＥＴ（metal oxide semiconductor field effect transistor）のゲート電極とドレイン領域との間にフィールドプレートを配置する構造が開示されている（特許文献１参照。）。特許文献１に記載の発明では、ゲート電極とドレイン領域の間に形成された熱酸化膜の上にフィールドプレートを配置することによって、半導体装置の耐圧を向上させている。 種 々 Various countermeasures are being studied to improve the breakdown voltage of semiconductor devices. For example, a structure is disclosed in which a field plate is arranged between a gate electrode and a drain region of a MOSFET (metal oxide semiconductor field effect transistor) (see Patent Document 1). In the invention described in Patent Document 1, the breakdown voltage of the semiconductor device is improved by arranging the field plate on the thermal oxide film formed between the gate electrode and the drain region.
特開２００１－７３２７号公報JP 2001-7327 A
　近年、半導体装置の耐圧に対する要求は高まっている。これに対し、オン動作で流れる主電流が半導体基板の主面と平行である半導体装置（以下、「横型の半導体装置」という。）について十分な耐圧を実現することが困難になっている。本発明は、耐圧を向上できる横型の半導体装置を提供することを目的とする。 In recent years, demands on the breakdown voltage of semiconductor devices have been increasing. On the other hand, it is difficult to realize a sufficient withstand voltage for a semiconductor device in which a main current flowing in the ON operation is parallel to the main surface of the semiconductor substrate (hereinafter, referred to as a “horizontal semiconductor device”). SUMMARY OF THE INVENTION An object of the present invention is to provide a lateral semiconductor device capable of improving withstand voltage.
　本発明の一態様によれば、第１導電型の半導体基板と、半導体基板の上面の一部に埋め込まれた第２導電型の埋設領域と、埋設領域を覆って半導体基板の上面に選択的に配置された、埋設領域よりも不純物濃度の低い第２導電型の第１半導体領域と、第１半導体領域の配置された領域の残余の領域で、半導体基板の上面に配置された第１導電型の第２半導体領域と、第１半導体領域の上面の一部に配置された第２導電型のドレイン領域と、第２半導体領域の上面の一部に配置された第２導電型のソース領域と、ドレイン領域とソース領域との間で第２半導体領域の上方に配置されたゲート電極とを備え、埋設領域の第２半導体領域に対向する対向端の平面視の位置が、ゲート電極のドレイン領域に近い側の端部と、ドレイン領域のゲート電極に近い側の端部との間である半導体装置が提供される。 According to one embodiment of the present invention, a semiconductor substrate of a first conductivity type, a buried region of a second conductivity type buried in a part of the upper surface of the semiconductor substrate, and a buried region selectively covering the buried region on the upper surface of the semiconductor substrate. And a second conductive type first semiconductor region having a lower impurity concentration than the buried region, and a first conductive region disposed on the upper surface of the semiconductor substrate in a remaining region of the region where the first semiconductor region is disposed. Second semiconductor region, a second conductivity type drain region disposed on a portion of the upper surface of the first semiconductor region, and a second conductivity type source region disposed on a portion of the upper surface of the second semiconductor region. And a gate electrode disposed above the second semiconductor region between the drain region and the source region. The position of the opposite end of the buried region facing the second semiconductor region in plan view is the drain of the gate electrode. The edge near the region and the gate voltage of the drain region The semiconductor device is provided which is between the near side of the end portion.
　本発明によれば、耐圧を向上できる横型の半導体装置を提供できる。 According to the present invention, it is possible to provide a lateral semiconductor device capable of improving the breakdown voltage.
本発明の実施形態に係る半導体装置の構造を示す模式的な断面図である。FIG. 2 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention. 埋設領域の対向端の位置と半導体装置の耐圧の関係を示すグラフである。6 is a graph showing the relationship between the position of the opposite end of the buried region and the breakdown voltage of the semiconductor device. 本発明の実施形態に係る半導体装置の製造方法を説明するための模式的な断面図である（その１）。FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 1). 本発明の実施形態に係る半導体装置の製造方法を説明するための模式的な断面図である（その２）。FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 2). 本発明の実施形態に係る半導体装置の製造方法を説明するための模式的な断面図である（その３）。FIG. 7 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 3). 本発明の実施形態に係る半導体装置の製造方法を説明するための模式的な断面図である（その４）。FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention (part 4). 本発明のその他の実施形態に係る半導体装置の構造を示す模式的な断面図である。FIG. 9 is a schematic cross-sectional view illustrating a structure of a semiconductor device according to another embodiment of the present invention.
　次に、図面を参照して、本発明の実施形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、各層の厚みの比率などは現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。 Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of thickness of each layer are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.
　また、以下に示す実施形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の実施形態は、構成部品の材質、形状、構造、配置などを下記のものに特定するものでない。この発明の実施形態は、請求の範囲において、種々の変更を加えることができる。 Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention are based on the materials, shapes, structures, arrangements and the like of the components. Is not specified as: Various changes can be made to the embodiments of the present invention within the scope of the claims.
　本発明の実施形態に係る半導体装置は、図１に示すように、第１導電型の半導体基板１０の上面の一部に埋め込まれた第２導電型の埋設領域２０と、埋設領域２０を覆って半導体基板１０の上面に選択的に配置された第２導電型の第１半導体領域３０を備える。埋設領域２０は半導体基板１０と接しており、埋設領域２０の配置されていない領域で、第１半導体領域３０が半導体基板１０と接している。第１半導体領域３０の不純物濃度は、埋設領域２０の不純物濃度よりも低く設定されている。 As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention includes a buried region 20 of a second conductivity type buried in a part of the upper surface of a semiconductor substrate 10 of a first conductivity type, and covers the buried region 20. And a first semiconductor region 30 of the second conductivity type selectively disposed on the upper surface of the semiconductor substrate 10. The buried region 20 is in contact with the semiconductor substrate 10, and the first semiconductor region 30 is in contact with the semiconductor substrate 10 in a region where the buried region 20 is not arranged. The impurity concentration of the first semiconductor region 30 is set lower than the impurity concentration of the buried region 20.
　図１に示した半導体装置は、第１半導体領域３０の配置された領域の残余の領域で、半導体基板１０の上面に配置された第１導電型の第２半導体領域４０を更に備える。図１に示すように、第２導電型のドレイン領域５０が第１半導体領域３０の上面の一部に配置され、第２導電型のソース領域６０が第２半導体領域４０の上面の一部に配置されている。更に、ドレイン領域５０とソース領域６０との間で、ゲート絶縁膜７０を介してゲート電極８０が第２半導体領域４０の上方に配置されている。 1 The semiconductor device shown in FIG. 1 further includes a second semiconductor region 40 of the first conductivity type disposed on the upper surface of the semiconductor substrate 10 in the remaining region where the first semiconductor region 30 is disposed. As shown in FIG. 1, the second conductivity type drain region 50 is disposed on a part of the upper surface of the first semiconductor region 30, and the second conductivity type source region 60 is formed on a part of the upper surface of the second semiconductor region 40. Are located. Further, between the drain region 50 and the source region 60, a gate electrode 80 is disposed above the second semiconductor region 40 via a gate insulating film 70.
　図１に示す半導体装置において、埋設領域２０の第２半導体領域４０に対向する端部（以下において「対向端」という。）の平面視の位置は、ゲート電極８０のドレイン領域５０に近い側の端部と、ドレイン領域５０のゲート電極８０に近い側の端部との間である。 In the semiconductor device shown in FIG. 1, the end of the buried region 20 facing the second semiconductor region 40 (hereinafter referred to as “opposite end”) in plan view is positioned closer to the drain region 50 of the gate electrode 80. Between the end and the end of the drain region 50 on the side closer to the gate electrode 80.
　なお、第１導電型と第２導電型とは互いに反対導電型である。すなわち、第１導電型がｐ型であれば、第２導電型はｎ型であり、第１導電型がｎ型であれば、第２導電型はｐ型である。以下では、第１導電型がｐ型であり、第２導電型がｎ型である場合について例示的に説明する。 The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is p-type, the second conductivity type is n-type, and if the first conductivity type is n-type, the second conductivity type is p-type. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.
　図１に示した半導体装置は、オン動作においてソース領域６０とドレイン領域５０の間に半導体基板１０の主面と平行に主電流の流れる横型トランジスタである。以下に、図１に示した半導体装置の基本的な動作について説明する。 The semiconductor device shown in FIG. 1 is a lateral transistor in which a main current flows between the source region 60 and the drain region 50 in parallel with the main surface of the semiconductor substrate 10 in the ON operation. Hereinafter, a basic operation of the semiconductor device illustrated in FIG. 1 will be described.
　ソース領域６０の電位を基準として、ドレイン領域５０に正の電位を印加した状態でゲート電極８０の電位を制御することにより、半導体装置がオン動作する。即ち、ゲート電極８０とソース領域６０間の電圧を所定の閾値電圧以上にすることにより、ゲート電極８０の下方で第２半導体領域４０にチャネルが形成される。これにより、ソース領域６０とドレイン領域５０間に主電流が流れる。 (4) The semiconductor device is turned on by controlling the potential of the gate electrode 80 in a state where a positive potential is applied to the drain region 50 with reference to the potential of the source region 60. That is, by setting the voltage between the gate electrode 80 and the source region 60 to a predetermined threshold voltage or more, a channel is formed in the second semiconductor region 40 below the gate electrode 80. Thereby, a main current flows between the source region 60 and the drain region 50.
　一方、オフ動作では、ゲート電極８０とソース領域６０間の電圧を所定の閾値電圧よりも低くする。これにより、チャネルが消滅し、主電流が遮断される。 {On the other hand, in the off operation, the voltage between the gate electrode 80 and the source region 60 is set lower than a predetermined threshold voltage. As a result, the channel disappears and the main current is cut off.
　したがって、埋設領域２０の対向端は、オン動作においてチャネルがゲート電極８０の下方で形成される領域（以下において、「チャネル形成領域」という。）のドレイン領域５０に近い側の端部と、ドレイン領域５０との間に位置する。 Therefore, the opposite end of the buried region 20 has an end on the side closer to the drain region 50 in a region where a channel is formed below the gate electrode 80 in the ON operation (hereinafter, referred to as a “channel forming region”), and It is located between the region 50.
　オフ動作では、第１導電型である半導体基板１０及び第２半導体領域４０と、第２導電型である第１半導体領域３０及び埋設領域２０との界面のｐｎ接合から空乏層が広がる。第１半導体領域３０よりも埋設領域２０の不純物濃度の高いため、第１半導体領域３０と半導体基板１０との界面よりも、埋設領域２０と半導体基板１０との界面において、空乏層が半導体基板１０側に長く延伸する。したがって、埋設領域２０を有さない半導体装置と比べて、図１に示した半導体装置では耐圧を向上させることができる。半導体基板１０と埋設領域２０の接触する面積を、半導体基板１０と第１半導体領域３０の接触する面積よりも広くすることにより、半導体装置の耐圧をより向上できる。 In the off operation, the depletion layer spreads from the pn junction at the interface between the semiconductor substrate 10 and the second semiconductor region 40 of the first conductivity type and the first semiconductor region 30 and the buried region 20 of the second conductivity type. Since the buried region 20 has a higher impurity concentration than the first semiconductor region 30, the depletion layer is formed at the interface between the buried region 20 and the semiconductor substrate 10 rather than at the interface between the first semiconductor region 30 and the semiconductor substrate 10. Stretch long to the side. Therefore, the breakdown voltage of the semiconductor device shown in FIG. 1 can be improved as compared with the semiconductor device having no buried region 20. By making the area where the semiconductor substrate 10 contacts the buried region 20 larger than the area where the semiconductor substrate 10 contacts the first semiconductor region 30, the breakdown voltage of the semiconductor device can be further improved.
　更に、本発明者らは、埋設領域２０の対向端の位置と半導体装置の逆バイアス時の耐圧との関係を調査した。調査結果を図２に示す。図２の縦軸は半導体装置の耐圧である。図２の横軸は、ドレイン領域５０のゲート電極８０に近い側の端部を基点とした場合の、ゲート電極８０のドレイン領域５０に近い側の端部までの距離Ｌａに対する、埋設領域２０の対向端までの距離Ｌｂの比（以下、「Ｌｂ／Ｌａ比」という。）の値である。距離Ｌａ及び距離Ｌｂは、平面視の距離である。なお、図１に示した半導体装置の耐圧を実線で示しており、参考として埋設領域２０を有さない半導体装置の耐圧を破線で示した。 {Circle around (4)} The present inventors further investigated the relationship between the position of the opposite end of the buried region 20 and the breakdown voltage of the semiconductor device at the time of reverse bias. FIG. 2 shows the results of the investigation. The vertical axis in FIG. 2 is the breakdown voltage of the semiconductor device. The horizontal axis in FIG. 2 indicates the distance La from the end of the drain region 50 closer to the drain region 50 to the distance La to the end of the buried region 20 closer to the drain region 50 when the end is closer to the gate electrode 80. This is the value of the ratio of the distance Lb to the opposing end (hereinafter, referred to as “Lb / La ratio”). The distance La and the distance Lb are distances in plan view. The breakdown voltage of the semiconductor device shown in FIG. 1 is shown by a solid line, and the breakdown voltage of the semiconductor device having no buried region 20 is shown by a broken line for reference.
　図２において最大の耐圧を示すのは、Ｌｂ／Ｌａ比が８０．５％の場合である。半導体装置の耐圧が最大となる埋設領域２０の対向端の位置を、以下において「最大耐圧位置」という。また、図２に示すように、Ｌｂ／Ｌａ比が０％より大きく、８０．５％以下である場合には、埋設領域２０を配置することにより耐圧が向上する。 (2) The maximum breakdown voltage is shown in FIG. 2 when the Lb / La ratio is 80.5%. The position of the opposite end of the buried region 20 where the withstand voltage of the semiconductor device becomes maximum is hereinafter referred to as “maximum withstand voltage position”. Further, as shown in FIG. 2, when the Lb / La ratio is larger than 0% and 80.5% or less, the breakdown voltage is improved by arranging the buried region 20.
　埋設領域２０の対向端が第２半導体領域４０に近いほど、第１半導体領域３０と半導体基板１０との界面の距離に対して、埋設領域２０と半導体基板１０との界面の距離の比が長い。このため、半導体装置の耐圧が向上する。 The closer the opposing end of the buried region 20 is to the second semiconductor region 40, the longer the ratio of the distance of the interface between the buried region 20 and the semiconductor substrate 10 to the distance of the interface between the first semiconductor region 30 and the semiconductor substrate 10 is. . Therefore, the breakdown voltage of the semiconductor device is improved.
　しかし、埋設領域２０の対向端が最大耐圧位置を越えて第２半導体領域４０に近づいた場合には、図２に示すように半導体装置の耐圧が低下する。これは、埋設領域２０をゲート電極８０の側に延伸させすぎると、第１半導体領域３０と第２半導体領域４０の間に形成される空乏層の横方向の広がりが抑制されてしまうためである。つまり、空乏層が十分に広がる前に、第１半導体領域３０と第２半導体領域４０の間で耐圧破壊が生じ、半導体装置の耐圧が低下する。 However, when the opposing end of the buried region 20 approaches the second semiconductor region 40 beyond the maximum withstand voltage position, the withstand voltage of the semiconductor device decreases as shown in FIG. This is because if the buried region 20 is extended too much toward the gate electrode 80, the lateral expansion of a depletion layer formed between the first semiconductor region 30 and the second semiconductor region 40 is suppressed. . That is, before the depletion layer spreads sufficiently, breakdown voltage breakdown occurs between the first semiconductor region 30 and the second semiconductor region 40, and the breakdown voltage of the semiconductor device decreases.
　本発明者らの調査によれば、埋設領域２０の対向端の位置が最大耐圧位置とドレイン領域５０との間にある場合には、埋設領域２０と半導体基板１０との界面で最初に耐圧破壊が生じる。一方、最大耐圧位置を越えて埋設領域２０の対向端の位置を第２半導体領域４０に近づけた場合には、第１半導体領域３０と第２半導体領域４０との界面で最初に耐圧破壊が生じる。図２に示すように、第１半導体領域３０と第２半導体領域４０との界面で耐圧破壊が生じる場合には、埋設領域２０と半導体基板１０との界面で耐圧破壊が生じる場合よりも、耐圧が大きく低下する。 According to the investigation by the present inventors, when the position of the opposing end of the buried region 20 is between the maximum withstand voltage position and the drain region 50, the breakdown withstand voltage first occurs at the interface between the buried region 20 and the semiconductor substrate 10. Occurs. On the other hand, when the position of the opposing end of the buried region 20 is moved closer to the second semiconductor region 40 beyond the maximum breakdown voltage position, breakdown breakdown occurs first at the interface between the first semiconductor region 30 and the second semiconductor region 40. . As shown in FIG. 2, when the breakdown voltage occurs at the interface between the first semiconductor region 30 and the second semiconductor region 40, the breakdown voltage increases at the interface between the buried region 20 and the semiconductor substrate 10. Greatly decreases.
　以上に説明したように、本発明の実施形態に係る半導体装置では、埋設領域２０の対向端を、ゲート電極８０のドレイン領域５０に近い側の端部と、ドレイン領域５０のゲート電極８０に近い側の端部との間に配置する。これにより、半導体装置の耐圧を向上させることができる。特に、Ｌｂ／Ｌａ比を８０．５％とすることにより、半導体装置の耐圧が向上する。 As described above, in the semiconductor device according to the embodiment of the present invention, the opposite end of the buried region 20 is connected to the end of the gate electrode 80 closer to the drain region 50 and closer to the gate electrode 80 of the drain region 50. Between the side ends. Thereby, the breakdown voltage of the semiconductor device can be improved. In particular, setting the Lb / La ratio to 80.5% improves the breakdown voltage of the semiconductor device.
　以下に、図面を参照して図１に示した半導体装置の製造方法を説明する。なお、以下に述べる半導体装置の製造方法は一例であり、この変形例を含めて、これ以外の種々の製造方法により実現可能である。 Hereinafter, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the drawings. The method of manufacturing a semiconductor device described below is an example, and can be realized by various other manufacturing methods including this modification.
　まず、第１導電型の半導体基板１０を用意する。例えば、半導体基板１０にｐ型のシリコン基板を用いる。半導体基板１０の不純物濃度は、５．０×１０13～４．５×１０14ｃｍ-3程度である。なお、半導体基板１０にシリコン基板以外の基板を使用してもよい。 First, a semiconductor substrate 10 of the first conductivity type is prepared. For example, a p-type silicon substrate is used as the semiconductor substrate 10. The impurity concentration of the semiconductor substrate 10 is about 5.0 × 10 13 to 4.5 × 10 14 cm −3 . Note that a substrate other than a silicon substrate may be used as the semiconductor substrate 10.
　そして、図３に示すように、半導体基板１０の上面の一部に埋め込むようにして埋設領域２０を形成する。例えば、フォトリソグラフィ技術により形成したマスク材を用いて、ｎ型不純物を半導体基板１０の上面の一部に選択的にイオン注入し、埋設領域２０を所定の位置に形成する。ｎ型不純物は、例えば砒素やリンなどである。埋設領域２０の膜厚は１５～２５μｍ程度であり、不純物濃度は、１．１×１０15～１．５×１０15ｃｍ-3程度である。 Then, as shown in FIG. 3, a buried region 20 is formed so as to be buried in a part of the upper surface of the semiconductor substrate 10. For example, an n-type impurity is selectively ion-implanted into a part of the upper surface of the semiconductor substrate 10 using a mask material formed by a photolithography technique to form the buried region 20 at a predetermined position. The n-type impurity is, for example, arsenic or phosphorus. The thickness of the buried region 20 is about 15 to 25 μm, and the impurity concentration is about 1.1 × 10 15 to 1.5 × 10 15 cm −3 .
　次いで、図４に示すように、埋設領域２０を覆うように、半導体基板１０の上面の全面に第１半導体領域３０を形成する。例えば、エピタキシャル成長法を用いて、第１半導体領域３０を形成する。第１半導体領域３０の膜厚は５～１０μｍ程度であり、不純物濃度は８．０×１０14～１．０×１０15ｃｍ-3程度である。 Next, as shown in FIG. 4, a first semiconductor region 30 is formed on the entire upper surface of the semiconductor substrate 10 so as to cover the buried region 20. For example, the first semiconductor region 30 is formed by using an epitaxial growth method. The thickness of the first semiconductor region 30 is about 5 to 10 μm, and the impurity concentration is about 8.0 × 10 14 to 1.0 × 10 15 cm −3 .
　次に、図５に示すように、第１半導体領域３０の一部に選択的にｐ型不純物をイオン注入して、第２半導体領域４０を形成する。このとき、半導体基板１０の上面に達するように第２半導体領域４０が形成される。ｐ型不純物は、例えばボロンなどである。第２半導体領域４０の膜厚は１０～１５μｍ程度であり、不純物濃度は、５．０×１０15～１．０×１０18ｃｍ-3程度である。 Next, as shown in FIG. 5, a p-type impurity is selectively ion-implanted into a part of the first semiconductor region 30 to form a second semiconductor region 40. At this time, the second semiconductor region 40 is formed so as to reach the upper surface of the semiconductor substrate 10. The p-type impurity is, for example, boron. The thickness of the second semiconductor region 40 is about 10 to 15 μm, and the impurity concentration is about 5.0 × 10 15 to 1.0 × 10 18 cm −3 .
　その後、図６に示すように、ドレイン領域５０及びソース領域６０を形成する。例えばフォトリソグラフィ技術を用いてパターニングしたマスク材をマスクにしたイオン注入法により、ｎ型不純物を第１半導体領域３０の上部の一部に選択的に注入してドレイン領域５０を形成する。同様に、ｎ型不純物を第２半導体領域４０の上部の一部に選択的に注入してソース領域６０を形成する。更に、ゲート絶縁膜７０及びゲート電極８０を所定の位置に形成して、図１に示す半導体装置が完成する。 (4) Thereafter, as shown in FIG. 6, a drain region 50 and a source region 60 are formed. For example, an n-type impurity is selectively implanted into a part of the upper portion of the first semiconductor region 30 by an ion implantation method using a mask material patterned using a photolithography technique as a mask to form the drain region 50. Similarly, the source region 60 is formed by selectively implanting an n-type impurity into a part of the upper portion of the second semiconductor region 40. Further, the gate insulating film 70 and the gate electrode 80 are formed at predetermined positions, and the semiconductor device shown in FIG. 1 is completed.
　なお、埋設領域２０を形成した後の製造工程での熱処理の影響などにより、埋設領域２０の不純物が周囲に拡散する。このため、埋設領域２０の上部が上方に延伸し、半導体基板１０と第１半導体領域３０の界面よりも埋設領域２０と第１半導体領域３０の界面が上方に位置している。 (4) The impurities in the buried region 20 diffuse around due to the influence of heat treatment in the manufacturing process after the buried region 20 is formed. Therefore, the upper part of the buried region 20 extends upward, and the interface between the buried region 20 and the first semiconductor region 30 is located higher than the interface between the semiconductor substrate 10 and the first semiconductor region 30.
　本発明者らが検討を重ねた結果、半導体基板１０、第１半導体領域３０及び第２半導体領域４０の不純物濃度の比率が一定の範囲にある場合に、埋設領域２０を配置することによって耐圧を向上させる効果が顕著であることを見出した。 As a result of repeated studies by the present inventors, when the ratio of the impurity concentration of the semiconductor substrate 10, the first semiconductor region 30, and the second semiconductor region 40 is within a certain range, the breakdown voltage is reduced by disposing the buried region 20. It has been found that the effect of improving is remarkable.
　（その他の実施形態）
　上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。 (Other embodiments)
As described above, the present invention has been described by the embodiments. However, it should not be understood that the description and drawings forming part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.
　例えば、図７に示すように、ドレイン領域５０とゲート電極８０との間で第１半導体領域３０の上面にフィールド絶縁膜９０を形成し、フィールド絶縁膜９０の上面にフィールドプレート１００を配置してもよい。フィールドプレート１００を所定の電位に設定することにより、ゲート電極８０のドレイン領域５０に近い側の端部における電界集中が緩和され、半導体装置の耐圧を更に向上させることができる。 For example, as shown in FIG. 7, a field insulating film 90 is formed on the upper surface of the first semiconductor region 30 between the drain region 50 and the gate electrode 80, and the field plate 100 is disposed on the upper surface of the field insulating film 90. Is also good. By setting the field plate 100 to a predetermined potential, the electric field concentration at the end of the gate electrode 80 near the drain region 50 is reduced, and the withstand voltage of the semiconductor device can be further improved.
　なお、図７に示した半導体装置では、第２半導体領域４０の上面の一部に、第１導電型のバックゲート領域１１０が配置されている。そして、第２半導体領域４０の下面に接して、第１導電型の接続領域１２０が半導体基板１０の上部に埋め込まれている。これにより、第２半導体領域４０と接続領域１２０を介して、バックゲート領域１１０と半導体基板１０が電気的に接続されている。 In the semiconductor device shown in FIG. 7, a back gate region 110 of the first conductivity type is arranged on a part of the upper surface of the second semiconductor region 40. The first conductive type connection region 120 is buried in the upper portion of the semiconductor substrate 10 in contact with the lower surface of the second semiconductor region 40. Thus, the back gate region 110 and the semiconductor substrate 10 are electrically connected via the second semiconductor region 40 and the connection region 120.
　上記では半導体装置がＭＯＳＦＥＴである場合を説明した。しかし、半導体装置が他の構造のトランジスタであってもよい。例えば、半導体装置がＪＦＥＴの場合にも、本発明は適用可能である。 (4) The case where the semiconductor device is a MOSFET has been described above. However, the semiconductor device may be a transistor having another structure. For example, the present invention is applicable even when the semiconductor device is a JFET.
　このように、本発明はここでは記載していない様々な実施形態等を含むことはもちろんである。 As described above, the present invention naturally includes various embodiments and the like not described herein.
　本発明の半導体装置は、横型の半導体装置を製造する製造業を含む電子機器産業に利用可能である。 The semiconductor device of the present invention can be used in the electronic equipment industry including the manufacturing industry for manufacturing horizontal semiconductor devices.
　１０…半導体基板
　２０…埋設領域
　３０…第１半導体領域
　４０…第２半導体領域
　５０…ドレイン領域
　６０…ソース領域
　７０…ゲート絶縁膜
　８０…ゲート電極 Reference Signs List 10 semiconductor substrate 20 buried region 30 first semiconductor region 40 second semiconductor region 50 drain region 60 source region 70 gate insulating film 80 gate electrode

Claims (3)

  1. 　第１導電型の半導体基板と、
    　前記半導体基板の上面の一部に埋め込まれた第２導電型の埋設領域と、
    　前記埋設領域を覆って前記半導体基板の上面に選択的に配置された、前記埋設領域よりも不純物濃度の低い第２導電型の第１半導体領域と、
    　前記第１半導体領域の配置された領域の残余の領域で、前記半導体基板の上面に配置された第１導電型の第２半導体領域と、
    　前記第１半導体領域の上面の一部に配置された第２導電型のドレイン領域と、
    　前記第２半導体領域の上面の一部に配置された第２導電型のソース領域と、
    　前記ドレイン領域と前記ソース領域との間で前記第２半導体領域の上方に配置されたゲート電極と
    　を備え、
    　前記埋設領域の前記第２半導体領域に対向する対向端の平面視の位置が、前記ゲート電極の前記ドレイン領域に近い側の端部と、前記ドレイン領域の前記ゲート電極に近い側の端部との間であることを特徴とする半導体装置。     A first conductivity type semiconductor substrate;
    A buried region of the second conductivity type buried in a part of the upper surface of the semiconductor substrate;
    A first semiconductor region of a second conductivity type having a lower impurity concentration than the buried region, selectively disposed on the upper surface of the semiconductor substrate so as to cover the buried region;
    A second semiconductor region of a first conductivity type disposed on an upper surface of the semiconductor substrate in a remaining region of the region where the first semiconductor region is disposed;
    A second conductivity type drain region disposed on a part of an upper surface of the first semiconductor region;
    A second conductivity type source region disposed on a part of an upper surface of the second semiconductor region;
    A gate electrode disposed above the second semiconductor region between the drain region and the source region;
    The position of the opposite end of the buried region facing the second semiconductor region in plan view is the end of the gate electrode closer to the drain region, and the end of the drain region closer to the gate electrode. Semiconductor device.
  2. 　前記ドレイン領域の前記ゲート電極に近い側の端部を基点とする前記ゲート電極の前記ドレイン領域に近い側の端部までの距離に対する、前記基点から前記埋設領域の前記対向端までの距離の比が、８０．５％以下であることを特徴とする請求項１に記載の半導体装置。 The ratio of the distance from the base point to the opposite end of the buried region, relative to the distance from the end of the drain region closer to the gate electrode to the end of the gate electrode closer to the drain region. The semiconductor device according to claim 1, wherein is less than or equal to 80.5%.
  3. 　前記半導体基板と前記埋設領域の接触する面積が、前記半導体基板と前記第１半導体領域の接触する面積よりも広いことを特徴とする請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein an area where the semiconductor substrate contacts the buried region is larger than an area where the semiconductor substrate contacts the first semiconductor region.
PCT/JP2018/027881 2018-07-25 2018-07-25 Semiconductor device WO2020021652A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236142A (en) * 2004-02-20 2005-09-02 Shindengen Electric Mfg Co Ltd Horizontal short channel dmos and its manufacturing method and semiconductor device
JP2006344817A (en) * 2005-06-09 2006-12-21 Toyota Motor Corp Semiconductor device
JP2011023734A (en) * 2010-09-08 2011-02-03 Mitsubishi Electric Corp Semiconductor device
JP2013122948A (en) * 2011-12-09 2013-06-20 Seiko Instruments Inc Semiconductor device and manufacturing method of the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236142A (en) * 2004-02-20 2005-09-02 Shindengen Electric Mfg Co Ltd Horizontal short channel dmos and its manufacturing method and semiconductor device
JP2006344817A (en) * 2005-06-09 2006-12-21 Toyota Motor Corp Semiconductor device
JP2011023734A (en) * 2010-09-08 2011-02-03 Mitsubishi Electric Corp Semiconductor device
JP2013122948A (en) * 2011-12-09 2013-06-20 Seiko Instruments Inc Semiconductor device and manufacturing method of the same

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