WO2020020118A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020020118A1
WO2020020118A1 PCT/CN2019/097200 CN2019097200W WO2020020118A1 WO 2020020118 A1 WO2020020118 A1 WO 2020020118A1 CN 2019097200 W CN2019097200 W CN 2019097200W WO 2020020118 A1 WO2020020118 A1 WO 2020020118A1
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Prior art keywords
transistor
electrically connected
electrode
terminal
circuit
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PCT/CN2019/097200
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English (en)
French (fr)
Inventor
施蓉蓉
杨盛际
刘伟
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京东方科技集团股份有限公司
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Priority to US16/643,093 priority Critical patent/US11217183B2/en
Publication of WO2020020118A1 publication Critical patent/WO2020020118A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Definitions

  • the present invention relates to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • a pixel circuit in one aspect, includes: a driving signal generating sub-circuit configured to generate and output an initial driving signal; a boosting sub-circuit electrically connected to the driving signal generating sub-circuit, configured to receive the initial driving signal, and The initial driving signal is amplified to generate a target driving signal, and the target driving signal is output; a light-emitting sub-circuit electrically connected to the boosting sub-circuit is configured to receive the target driving signal, Driven by light.
  • the booster sub-circuit includes: a transistor having a base, a collector, and an emitter; a first resistor electrically connected to the driving signal generating sub-circuit and a base of the transistor Between; a second resistor electrically connected between the first voltage terminal and the collector of the transistor; a third resistor electrically connected between the second voltage terminal and the emitter of the transistor; the crystal The emitter of the transistor is also electrically connected to the light-emitting sub-circuit.
  • the crystal transistor includes a silicon crystal transistor.
  • the driving signal generating sub-circuit includes: a first transistor, a second transistor, a third transistor, and a first storage capacitor; a control electrode of the first transistor is electrically connected to a first scanning signal terminal, The first electrode is electrically connected to the data voltage terminal, and the second electrode is electrically connected to the first terminal of the first storage capacitor; the control electrode of the second transistor is connected to the second electrode of the first transistor and the first electrode.
  • a first end of the storage capacitor is electrically connected, a first pole is electrically connected to a second pole of the third transistor, and a second pole is electrically connected to the booster sub-circuit; a control pole of the third transistor is connected to the operating electrode.
  • the energy signal terminal is electrically connected, the first pole is electrically connected to the third voltage terminal, and the second terminal of the first storage capacitor is electrically connected to the fourth voltage terminal.
  • the driving signal generating sub-circuit further includes: a fourth transistor; a control electrode of the fourth transistor is electrically connected to a second scanning signal terminal, a first electrode is electrically connected to the data voltage terminal, The second pole is electrically connected to the first terminal of the first storage capacitor.
  • one of the first transistor and the fourth transistor is an N-type transistor, and the other is a P-type transistor.
  • the driving signal generating sub-circuit further includes: a fifth transistor; the control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode is electrically connected to the fifth voltage terminal, and the second A pole is electrically connected to the second pole of the second transistor and the booster sub-circuit.
  • the third voltage terminal when the boost sub-circuit is electrically connected to a first voltage terminal, the third voltage terminal is configured to output a voltage signal that is the same as a voltage signal output by the first voltage terminal .
  • the driving signal generating sub-circuit includes: a sixth transistor, a seventh transistor, and a second storage capacitor; a control electrode of the sixth transistor is electrically connected to a third scanning signal terminal, and the first electrode is in communication with the third scanning signal terminal.
  • the data voltage terminal is electrically connected, and the second electrode is electrically connected to the first terminal of the second storage capacitor; the control electrode of the seventh transistor is connected to the second electrode of the sixth transistor and the first electrode of the second storage capacitor.
  • One terminal is electrically connected, the first electrode is electrically connected to the second terminal and the sixth voltage terminal of the second storage capacitor, and the second electrode is electrically connected to the booster sub-circuit.
  • the driving signal generating sub-circuit further includes: an eighth transistor; a control electrode of the eighth transistor is electrically connected to a fourth scanning signal terminal, a first electrode is electrically connected to the data voltage terminal, and the first The second electrode is electrically connected to the control electrode of the seventh transistor and the first terminal of the second storage capacitor.
  • one of the sixth transistor and the eighth transistor is an N-type transistor, and the other is a P-type transistor.
  • the driving signal generating sub-circuit further includes: a ninth transistor; a control electrode of the ninth transistor is electrically connected to a second reset signal terminal, a first electrode is electrically connected to a seventh voltage terminal, and a second A pole is electrically connected to the second pole of the seventh transistor and the booster sub-circuit.
  • the sixth voltage terminal when the booster sub-circuit is electrically connected to the first voltage terminal, the sixth voltage terminal is configured to output the same voltage signal as the voltage signal output from the first voltage terminal. Voltage signal.
  • the light-emitting sub-circuit includes a self-light-emitting device, an anode of the self-light-emitting device is electrically connected to the booster sub-circuit, and a cathode is electrically connected to an eighth voltage terminal.
  • the light-emitting sub-circuit further includes: a fourth resistor; the fourth resistor is electrically connected between the anode of the self-light-emitting device and the boost sub-circuit.
  • the driving signal generating sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first storage capacitor.
  • the control electrode of the first transistor is electrically connected to the first scanning signal terminal, the first electrode is electrically connected to the data voltage terminal, and the second electrode is electrically connected to the first terminal of the first storage capacitor; the first storage capacitor The second terminal is electrically connected to the fourth voltage terminal.
  • the control electrode of the second transistor is electrically connected to the second electrode of the first transistor and the first terminal of the first storage capacitor.
  • the first electrode is electrically connected to the second electrode of the third transistor.
  • a pole is electrically connected to the booster sub-circuit.
  • the control electrode of the third transistor is electrically connected to the enable signal terminal, and the first electrode is electrically connected to the third voltage terminal.
  • a control electrode of the fourth transistor is electrically connected to a second scanning signal terminal, a first electrode is electrically connected to the data voltage terminal, a second electrode is connected to a control electrode of the second transistor, and a first electrode of the first storage capacitor is connected. One end is electrically connected.
  • the control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode is electrically connected to the fifth voltage terminal, and the second electrode is electrically connected to the second electrode of the second transistor and the booster circuit. .
  • One of the first transistor and the fourth transistor is an N-type transistor, and the other is a P-type transistor; and when the booster sub-circuit is electrically connected to a first voltage terminal, the third transistor The voltage terminal is configured to output the same voltage signal as the voltage signal output from the first voltage terminal.
  • the driving signal generating sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a second storage capacitor.
  • the control electrode of the sixth transistor is electrically connected to the third scanning signal terminal, the first electrode is electrically connected to the data voltage terminal, and the second electrode is electrically connected to the first terminal of the second storage capacitor.
  • the control electrode of the sixth transistor is electrically connected to the third scanning signal terminal, the first electrode is electrically connected to the data voltage terminal, and the second electrode is electrically connected to the first terminal of the second storage capacitor.
  • the control electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor and the first terminal of the second storage capacitor, and the first electrode is connected to the second terminal of the second storage capacitor and the sixth voltage.
  • the terminal is electrically connected, and the second pole is electrically connected to the booster sub-circuit.
  • the control electrode of the eighth transistor is electrically connected to the fourth scanning signal terminal, the first electrode is electrically connected to the data voltage terminal, the second electrode is connected to the control electrode of the seventh transistor, and the first electrode of the second storage capacitor is electrically connected to the fourth electrode. One end is electrically connected.
  • the control electrode of the ninth transistor is electrically connected to the second reset signal terminal, the first electrode is electrically connected to the seventh voltage terminal, and the second electrode is electrically connected to the second electrode of the seventh transistor and the booster circuit. .
  • One of the sixth transistor and the eighth transistor is an N-type transistor, and the other is a P-type transistor; and in a case where the booster sub-circuit is electrically connected to the first voltage terminal, the The sixth voltage terminal is configured to output the same voltage signal as the voltage signal output from the first voltage terminal.
  • a display device is provided. Including the pixel circuit according to any one of the above embodiments.
  • a method for driving a pixel circuit includes: a driving signal generating sub-circuit generating an initial driving signal and outputting the initial driving signal; a boosting sub-circuit receiving the initial driving signal, amplifying the initial driving signal, generating a target driving signal, and Outputting the target driving signal; a light-emitting sub-circuit receives the target driving signal, and a self-emitting device in the light-emitting sub-circuit emits light under the driving of the target driving signal.
  • the driving signal generating sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first storage capacitor.
  • the driving signal generating sub-circuit generates an initial driving signal, including: the first transistor is turned on under the control of a first scanning signal output through a first scanning signal terminal, and the fourth transistor is output through a second scanning signal terminal It is turned on under the control of the second scanning signal; the data voltage signal output through the data voltage terminal is transmitted through the first transistor and the fourth transistor and stored in the first storage capacitor, and simultaneously transmitted to the second transistor.
  • the third transistor is turned on under the control of an enable signal output via an enable signal terminal, and the third voltage signal output via the third voltage terminal is transmitted to the second transistor via the third transistor, The second electrode of the second transistor is output as the initial driving signal.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided in the related art
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic structural diagram of each sub-circuit in the pixel circuit shown in FIG. 2 according to some embodiments of the present disclosure
  • FIG. 4 is a schematic structural diagram of various sub-circuits in the pixel circuit shown in FIG. 2 according to some embodiments of the present disclosure
  • FIG. 5 is a schematic structural diagram of sub-circuits in the pixel circuit shown in FIG. 2 according to still another embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of various sub-circuits in the pixel circuit shown in FIG. 2 according to some embodiments of the present disclosure
  • FIG. 7 is a timing diagram for driving the pixel circuit shown in FIG. 4 according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of sub-circuits in the pixel circuit shown in FIG. 2 according to another embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of various sub-circuits in the pixel circuit shown in FIG. 2 according to some embodiments of the present disclosure.
  • FIG. 10 is a timing diagram for driving the pixel circuit shown in FIG. 9 according to some embodiments of the present disclosure.
  • FIG. 11 is a simulation effect diagram of the pixel circuit shown in FIG. 1 provided by some embodiments of the present disclosure.
  • FIG. 12 is a simulation effect diagram of the pixel circuit shown in FIG. 4 provided by some embodiments of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a display device provided by some embodiments of the present disclosure.
  • FIG. 14 is a schematic flowchart of a driving method of a pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 15 is a schematic flowchart of a driving signal generating sub-circuit generating an initial driving signal provided by some embodiments of the present disclosure.
  • An OLED (Organic Light-Emitting Diode) display device includes a plurality of sub-pixels, and each sub-pixel is correspondingly provided with a pixel circuit.
  • an AMOLED (Active-Matrix Organic Light-Emitting Diode) pixel circuit includes two thin-film transistors (a switching transistor T C and a driving transistor T d ), and a capacitor C. , And an OLED light emitting device.
  • the switching transistor T C is turned on, the data voltage at the data voltage terminal Data is written into the storage capacitor C, and the driving transistor T d is controlled to operate in a saturation region to input the voltage at the voltage terminal V b to the driving transistor T d and convert It is a constant current, and then drives the OLED light emitting device to emit light within a frame time.
  • the OLED light-emitting device is a current-type element.
  • the current input to the OLED light-emitting device is controlled by the data voltage signal input at the data voltage terminal Data, and is also affected by the threshold voltage of the driving transistor T d .
  • Conventional OLED display device the lower data voltage signal Data input terminal of the data voltage with a voltage, and the voltage of the terminal voltage V a is limited, which results in the voltage across the OLED device can not meet the demand for high luminance.
  • the transistor parameters in the pixel circuit need to be changed, the circuit and other devices need to be redesigned, and the process is cumbersome; on the other hand, the driving transistor T d exists Body effect, that is, the threshold voltage drift of the driving transistor T d is large.
  • the data voltage signal has a high voltage
  • there is a large voltage loss at the driving transistor T d so that the data voltage signal is transmitted to the OLED.
  • the voltage drop of the light-emitting device is large, resulting in that only a low driving voltage can be input to the OLED light-emitting device.
  • the brightness of the OLED light-emitting device is still low and high-brightness display cannot be achieved, thereby reducing the applicable range of the OLED display device.
  • the pixel circuit 1 includes a driving signal generating sub-circuit 10, a booster sub-circuit 20 electrically connected to the driving signal generating sub-circuit 10, and a booster sub-circuit.
  • the light-emitting sub-circuit 30 is electrically connected to the circuit 20.
  • the driving signal generating sub-circuit 10 is configured to generate and output an initial driving signal. It should be noted that the structure of the driving signal generating sub-circuit 10 is not limited here, and the driving signal generating sub-circuit 10 can generate an initial driving signal. Therefore, all the circuits that can transmit the initial driving signal for the anode of the light-emitting sub-circuit 30 can be used as the driving signal generating sub-circuit 10 in the present disclosure.
  • the boosting sub-circuit 20 is configured to receive an initial driving signal output from the driving signal generating sub-circuit 10, amplify the initial driving signal to generate a target driving signal, and output the target driving signal.
  • the light emitting sub-circuit 30 is configured to receive a target driving signal output from the boosting sub-circuit 20, and emit light when driven by the target driving signal.
  • a booster sub-circuit 20 is added to the pixel circuit 1, and the booster sub-circuit 20 can amplify the initial driving signal generated by the driving signal generating sub-circuit 10 so that the target driving signal transmitted to the light-emitting sub-circuit 30 It is larger than the initial driving signal generated by the driving signal generating sub-circuit 10. In this way, the driving current of the light-emitting sub-circuit 30 can be increased, thereby achieving the effect of increasing the light-emitting brightness of the light-emitting sub-circuit 30.
  • the boosting sub-circuit 20 amplifies the initial driving signal output by the driving signal generating sub-circuit 10, so the voltage loss in the driving signal generating sub-circuit 10 due to the body effect of the driving transistor can be ignored. Effect of luminous brightness enhancement effect.
  • the boost sub-circuit 20 includes a first resistor R 1 , a second resistor R 2 , a third resistor R 3, and a transistor Q.
  • the transistor Q has a base a, a collector b, and an emitter c.
  • the first resistor R 1 is electrically connected between the driving signal generating sub-circuit 10 and the base a of the transistor Q.
  • the second resistor R 2 is electrically connected. Connected between the first voltage terminal V 1 and the collector b of the transistor Q.
  • the third resistor R 3 is electrically connected between the second voltage terminal V 2 and the emitter c of the transistor Q, and the emitter c of the transistor Q is also electrically connected to the light-emitting sub-circuit 30.
  • the working principle of the boosting sub-circuit 20 is: when the driving signal generating sub-circuit 10 generates a voltage initial driving signal V in and transmits it to the output terminal A (that is, the input terminal of the boosting sub-circuit 20) of the driving signal generating sub-circuit 10,
  • the transistor Q satisfies the amplification condition
  • the base a current of the transistor Q is I B
  • the current c of the emitter of the transistor Q is (1 + ⁇ ) ⁇ I B.
  • the target driving signal output from the output terminal B of the boost sub-circuit 20 that is, the input terminal of the light-emitting sub-circuit 30
  • the voltage of the driving signal is increased.
  • ⁇ is the magnification of the transistor Q, ⁇ is greater than 1; U be is the turning-on voltage of the base a and the emitter c of the transistor Q, R b is the resistance of the first resistor R 1 , and R e is the third resistor R 3 resistance.
  • the amplification conditions of the transistor are forward bias of the emitter junction and reverse bias of the collector junction. Therefore, the resistance of the first resistor R1, the second resistor R2, and the third resistor R3 should be selected to meet the initial driving voltage V in of the base. , The transmitting junction is forward biased and the collector junction is reverse biased. Exemplarily, the resistance of the first resistor R1 is 1K ⁇ , the resistance of the second resistor R2 is 2K ⁇ , the resistance of the third resistor R3 is 20 ⁇ , and ⁇ is 100. In this way, the transistor Q can be operated in a linear amplification region (the amplification condition is satisfied).
  • the output target drive signal V out is 6.6V, and the voltage will increase by 47%.
  • the transistor Q is a silicon transistor or a germanium transistor.
  • the transistor Q in the pixel circuit is a silicon transistor, the occupied space of the transistor Q can be reduced, thereby reducing the occupied space of the entire pixel circuit.
  • the driving signal generating sub-circuit 10 includes a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , and a first storage capacitor C 1 .
  • control electrode of the first transistor T 1 as a terminal connected to the first scan signal Gate1 electrically, and the first electrode is electrically connected to the data Data voltage terminal, a second electrode of the first storage capacitor C 1 is electrically connected to the first terminal.
  • the control electrode of the second transistor T 2 is electrically connected to the second electrode of the first transistor T 1 and the first terminal of the first storage capacitor C 1.
  • the first electrode is electrically connected to the second electrode of the third transistor T 3 .
  • the pole is electrically connected to the booster sub-circuit 20.
  • the control electrode of the third transistor T 3 is electrically connected to the enable signal terminal EM, and the first electrode is electrically connected to the third voltage terminal V 3 .
  • the second terminal of the first storage capacitor C 1 is electrically connected to the fourth voltage terminal V 4 .
  • the first transistor T 1 transmits the signal of the data voltage terminal Data to the first storage capacitor C 1 under the control of the first scan signal terminal Gate1.
  • the first storage capacitor C 1 is used to ensure the second transistor.
  • T 2 (used as a driving transistor) works in the saturation region.
  • the third transistor T 3 transmits the voltage at the third voltage terminal V 3 to the second transistor T 2 to make the second transistor T
  • the second pole of 2 can output an initial driving signal, so that the initial driving signal can be input into the booster sub-circuit 20.
  • the driving signal generating sub-circuit 10 further includes a plurality of switching transistors connected in parallel with the first transistor T 1, a plurality of switching transistors connected in parallel with the second transistor T 2 , and a third transistor T 3 Multiple switching transistors in parallel.
  • the driving signal generating sub-circuit 10 further includes: a fourth transistor T 4 , and a control electrode of the fourth transistor T 4 is electrically connected to the second scanning signal terminal Gate2.
  • the electrode is electrically connected to the data voltage terminal Data
  • the second electrode is electrically connected to the first terminal of the first storage capacitor C 1 .
  • the first transistor T 1 transmits the signal of the data voltage terminal Data to the first storage capacitor C 1 under the control of the first scanning signal terminal Gate1; the fourth transistor T 4 is controlled under the control of the second scanning signal terminal Gate2, The signal of the data voltage terminal Data is transmitted to the first storage capacitor C 1 .
  • FIG. 3 Exemplarily, as shown in FIG.
  • one of the first transistor T 1 and the fourth transistor T 4 is an N-type transistor, and the other is a P-type transistor.
  • the N-type transistor can effectively transmit a low voltage
  • the P-type transistor can effectively transmit a high voltage. Therefore, by using the first transistor T 1 and the fourth transistor T 4 to transmit the signal of the data voltage terminal Data together, it is possible to stably and reliably transfer data.
  • the signal of the data voltage terminal Data is transmitted to the first storage capacitor C 1 .
  • the low voltage and high voltage here only indicate the relative magnitude relationship between the voltages of the input signals.
  • the driving signal generating sub-circuit 10 further includes a plurality of switching transistors connected in parallel with the fourth transistor T 4 .
  • the drive signal generator 10 further includes a fifth sub-circuit transistor T 5, a fifth control transistor T 5 is connected to the first reset signal Reset1 electrical terminal, a first electrode and the second The five voltage terminal V 5 is electrically connected, and the second electrode is electrically connected to the second electrode of the second transistor T 2 and the booster sub-circuit 20.
  • the light-emitting sub-circuit 30 may be initialized first, thereby reducing the influence of the threshold voltage drift on the light-emitting effect.
  • the driving signal generating sub-circuit 10 further includes a plurality of switching transistors connected in parallel with the fifth transistor T 5 .
  • one end of the first resistor R 1 is connected to the second pole of the second transistor T 2 and the first pole of the fifth transistor T 5 , and the other end of the first resistor R 1 is connected to the transistor Q. Base.
  • the third voltage terminal V 3 is configured to output a voltage output from the first voltage terminal V 1 .
  • the driving signal generating sub-circuit 10 includes a sixth transistor T 6 , a seventh transistor T 7 , and a second storage capacitor C 2 .
  • the control electrode of the sixth transistor T 6 is electrically connected to the third scanning signal terminal Gate3, the first electrode is electrically connected to the data voltage terminal Data, and the second electrode is electrically connected to the first terminal of the second storage capacitor C 2 .
  • the control electrode of the seventh transistor T 7 is electrically connected to the second electrode of the sixth transistor T 6 and the first terminal of the second storage capacitor C 2.
  • the first electrode is connected to the second terminal of the second storage capacitor C 2 and the sixth voltage.
  • the terminal V 6 is electrically connected, and the second electrode is electrically connected to the booster sub-circuit 20.
  • the sixth transistor T 6 transmits the signal of the data voltage terminal Data to the second storage capacitor C 2 under the control of the third scanning signal terminal Gate3.
  • the second storage capacitor C 2 is used to ensure the seventh transistor.
  • T 7 (used as a driving transistor) works in the saturation region. At this time, the voltage at the sixth voltage terminal V 6 is transmitted to the seventh transistor T 7 , so that the second pole of the seventh transistor T 7 can output an initial driving signal, so that This initial driving signal is input to the booster sub-circuit 20.
  • the driving signal generating sub-circuit 10 further includes a plurality of switching transistors connected in parallel with the sixth transistor T 6 and a plurality of switching transistors connected in parallel with the seventh transistor T 7 .
  • the sub-drive signal generating circuit 10 further comprises: an eighth transistor T 8, the control electrode of the eighth transistor T 8 is connected to the fourth scanning signal terminal electrically Gate4, a first The electrode is electrically connected to the data voltage terminal Data, and the second electrode is electrically connected to the control electrode of the seventh transistor T 7 and the first terminal of the second storage capacitor C 2 .
  • the sixth transistor T 6 transmits the signal of the data voltage terminal Data to the second storage capacitor C 2 under the control of the third scanning signal terminal Gate3; the eighth transistor T 8 is under the control of the fourth scanning signal terminal Gate4, The signal of the data voltage terminal Data is transmitted to the second storage capacitor C 2 .
  • FIG. 1 Exemplarily, as shown in FIG.
  • one of the sixth transistor T 6 and the eighth transistor T 8 is an N-type transistor, and the other is a P-type transistor.
  • the N-type transistor can effectively transmit a low voltage
  • the P-type transistor can effectively transmit a high voltage. Therefore, by using the sixth transistor T 6 and the eighth transistor T 8 to transmit the signal of the data voltage terminal Data together, it is possible to stably and reliably transfer the data.
  • the signal of the data voltage terminal Data is transmitted to the first storage capacitor C 2 .
  • the low voltage and high voltage here only indicate the relative magnitude relationship between the voltages of the input signals.
  • the driving signal generating sub-circuit 10 further includes a plurality of switching transistors connected in parallel with the eighth transistor T 8 .
  • the driving signal generating sub-circuit 10 further includes: a ninth transistor T 9 , a control electrode of the ninth transistor T 9 is electrically connected to the second reset signal terminal Reset2, and the first electrode is connected to The seventh voltage terminal V 7 is electrically connected, and the second electrode is electrically connected to the second electrode of the seventh transistor T 7 and the booster sub-circuit 20.
  • the light-emitting sub-circuit 30 may be initialized first, thereby reducing the influence of the threshold voltage drift on the light-emitting effect.
  • the driving signal generating sub-circuit 10 further includes a plurality of switching transistors connected in parallel with the ninth transistor T 9 .
  • one end of the first resistor R 1 is connected to the second pole of the seventh transistor T 7 and the first pole of the ninth transistor T 9 , and the other end of the first resistor R 1 is connected to the transistor Q. Base.
  • the sixth voltage terminal V 6 is configured to output the same voltage signal as the voltage signal output from the first voltage terminal V 1 .
  • This design can use the same power source to output the same voltage signal to the first voltage terminal V 1 and the sixth voltage terminal V 6 , which simplifies the circuit structure, reduces the manufacturing difficulty, and improves stability and reliability.
  • the light-emitting sub-circuit 30 There are various structures of the light-emitting sub-circuit 30.
  • the anode of the self-emitting device L is connected to the emitter of the transistor Q), and the cathode is electrically connected to the eighth voltage terminal V 8 .
  • the target driving signal output from the booster sub-circuit 20 and the signal output from the eighth voltage terminal V 8 can be used to drive the light-emitting device L to emit light.
  • the luminous brightness of the self-emitting device is improved.
  • the self-emitting device L is an OLED device.
  • the light-emitting sub-circuit 30 further includes a fourth resistor R 4.
  • the fourth resistor R 4 is electrically connected between the anode of the self-light-emitting device L and the booster sub-circuit 20.
  • one end of the fourth resistor R 4 is connected to the emitter of the transistor Q, and the other end is connected to the anode of the light-emitting device L.
  • the fourth resistor R 4 in the pixel circuit can reduce the short-circuit current thereon, thereby preventing the surrounding The pixel circuit is also short-circuited.
  • the types of the transistors included in the pixel circuit in some embodiments of the present disclosure are not limited.
  • the first to ninth transistors T 1 to T 9 may be N-type transistors or P-type transistors.
  • the pixel circuit shown in FIG. 4 includes a third transistor T 3 and a fourth transistor T 4 which are P-type transistors, and each transistor except the third transistor T 3 and the fourth transistor T 4 . All are N-type transistors. The following uses the pixel circuit shown in FIG. 4 as an example for description.
  • control of the transistor is at the gate.
  • the transistor has a first electrode drain and a second electrode source; or a first electrode source and a second electrode drain. This disclosure does not limit this.
  • each of the transistors in the pixel circuit may be an enhancement transistor or a depletion transistor. This disclosure does not limit this.
  • the eighth voltage signal outputted through the eighth voltage terminal V 8 is a low-level signal
  • the fourth voltage signal outputted through the fourth voltage terminal V 4 is a low-level signal
  • a first voltage signal output from the high-level signal, a second voltage terminal V 2 illustrate an example of the ground.
  • the high level and low level only indicate the relative magnitude relationship between the voltages of the input signals.
  • the driving process of the pixel circuit shown in FIG. 4 includes three phases: an initial driving signal generation phase, a target driving signal generation phase, and a light emitting phase.
  • This phase includes a first period t 1 , a second period t 2 and a third period t 3 .
  • First period t 1 The initial signal terminal Reset1 inputs a high-level initial signal, controls the fifth transistor T 5 to be turned on, and transmits the signal at the fifth voltage terminal V 5 to the booster sub-circuit 20 and transmits the signal via the booster sub-circuit 20.
  • the anode of the self-light-emitting device L is initialized.
  • the signal transmitted by the fifth voltage terminal V 5 may be very small, or may be 0V.
  • the boosting sub-circuit 20 can amplify the signal at the fifth voltage terminal V 5 and transmit the signal to the light-emitting sub-circuit 30.
  • Second period t 2 The first scanning signal terminal Gate1 inputs a high-level first scanning signal, controls the first transistor T 1 to turn on, and transmits the data voltage signal outputted via the data voltage terminal Data to the first storage capacitors C 1 and The gate of the second transistor T 2 .
  • the second scan signal terminal Gate2 inputs a second low-level scan signal to control the fourth transistor T 4 to be turned on, and transmits the data voltage signal output through the data voltage terminal Data to the first storage capacitor C 1 and the second transistor T. 2 control pole.
  • Third period t 3 The signal input from the first scanning signal terminal Gate1 becomes a low-level signal, and the signal input from the second scanning signal terminal Gate2 becomes a high-level signal, and the first transistor T 1 and the fourth transistor T 4 are controlled. Off, the second transistor T 2 operates in a saturation region.
  • the enable signal terminal EM inputs a low-level enable signal to control the third transistor T 3 to be turned on, and transmits the third voltage signal output through the third voltage terminal V 3 to the second transistor T 2 so that the second transistor T 2 generates an initial driving signal and outputs it to the booster sub-circuit 20.
  • the data voltage terminal Data may continue to input the data voltage signal, and may also stop inputting the data voltage signal.
  • the third transistor T 3 in the pixel circuit 1 may be replaced by a P-type transistor with an N-type transistor.
  • the pixel circuit in FIG. 8 is compared with that in FIG. 3.
  • the pixel circuit of the third transistor T 3 type by replacing the P-type transistors are N-type transistors
  • the pixel circuit of FIG. 9 in FIG. 4 as compared to the pixel circuits
  • the type of the third transistor T 3 of the P-type The transistor was replaced with an N-type transistor.
  • the third stage t 3 of the above-mentioned initial signal generation stage will change. As shown in FIG.
  • the third stage t 3 requires the enable signal terminal EM to input a high level. To enable the third transistor T 3 to be turned on, so that the third voltage signal output through the third voltage terminal V 3 can be transmitted to the second transistor T 2 , so that the second transistor T 2 generates an initial driving signal and outputs it to Boost sub circuit 20.
  • the size of the initial driving signal can be adjusted by adjusting the duty cycle of the enable signal input from the enable signal end EM, so as to achieve the adjustment of the brightness and contrast of the self-emitting device L.
  • Target driving signal generation stage The boosting sub-circuit 20 amplifies the received initial driving signal to generate a target driving signal and outputs it to the light-emitting sub-circuit 30.
  • the amplified target driving signal is:
  • the self-light-emitting device L emits light under the driving of the target driving signal and the eighth voltage signal outputted through the eighth voltage terminal V 8 .
  • the third transistor T 3 transmits the voltage provided by the signal provided by the third voltage terminal V 3 to the second transistor T 2 under the control of the enable signal output from the enable signal terminal EM to the self-light-emitting device L.
  • the anode provides voltage.
  • the signal provided by the eighth voltage terminal V 8 provides a voltage to the cathode of the self-light emitting device L.
  • the driving voltage applied to the self-light-emitting device L can be adjusted by adjusting the signal at the eighth voltage terminal V 8 , so as to adjust the brightness and contrast of the self-light-emitting device L.
  • FIG. 11 is a light emitting current of the OLED light emitting device in the pixel circuit shown in FIG. 1 simulated by HSPICE (High Precision Circuit Simulation).
  • the voltage input to the anode of the light emitting device OLED is 4.5V
  • the current flowing through the OLED light emitting device is 1.90nA.
  • FIG. 12 is an HSPICE simulation of the light-emitting current of the self-light-emitting device L (ie, the OLED light-emitting device) in the pixel circuit shown in FIG. 4.
  • the sub-booster circuit 20 amplifies the voltage input to the anodes L self-luminous device is 6.6V
  • the voltage L by the end of the cathode voltage V 8 is input to the self-luminous device can be adjusted, when the input voltage terminal through to V 8 from When the voltage of the cathode of the light-emitting device L is -1V, as shown in FIG.
  • the current of the self-light-emitting device L is 7.70nA
  • the current is increased by 305%.
  • the brightness of the self-emitting device L is greatly improved.
  • the display device 2 includes a plurality of pixel circuits, and each pixel circuit is a pixel circuit provided by any one of the foregoing embodiments.
  • the display device 2 includes a plurality of pixel units 1, and the plurality of pixel units 1 are arranged in an array.
  • Each pixel unit 1 includes any one of the pixel circuits described above.
  • each pixel circuit 1 includes a driving signal generating sub-circuit 10, a boosting sub-circuit 20, and a light-emitting sub-circuit 30.
  • the light-emitting sub-circuit 30 includes a self-light-emitting device L.
  • the sub-circuit 20 and the boosting sub-circuit 20 may amplify the initial driving signal generated by the driving signal generating sub-circuit 10 so that the target driving signal transmitted to the light-emitting sub-circuit 30 is larger than the initial driving signal generated by the driving signal generating sub-circuit 10.
  • the driving current of the self-light-emitting device L in the light-emitting sub-circuit 30 can be increased, and the light-emitting brightness of the self-light-emitting device L can be increased, thereby achieving the effect of increasing the light-emitting brightness of the entire display device 2.
  • the display device is, by way of example, a product or component having any display function, such as an OLED display, a digital photo frame, a mobile phone, a tablet computer, and a navigator.
  • any display function such as an OLED display, a digital photo frame, a mobile phone, a tablet computer, and a navigator.
  • Some embodiments of the present disclosure also provide a driving method of the pixel circuit. As shown in FIG. 14, the driving method includes:
  • Step 10 The driving signal generating sub-circuit 10 generates an initial driving signal and outputs the initial driving signal.
  • the driving signal generating sub-circuit includes a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4, and a first storage capacitor C. 1 .
  • step 10 includes:
  • Step 101 The first transistor T 1 is turned on under the control of a first scan signal output through the first scan signal terminal Gate1, and the fourth transistor T 4 is turned on under the control of a second scan signal output through the second scan signal terminal Gate 2 .
  • Step 102 The data voltage signal output through the data voltage terminal Data is transmitted through the first transistor T 1 and the fourth transistor T 4 and stored in the first storage capacitor C 1 , and at the same time transmitted to the control electrode of the second transistor T 2 .
  • Step 103 The third transistor T 3 is turned on under the control of the enable signal outputted through the enable signal terminal EM, and the third voltage signal outputted through the third voltage terminal V 3 is transmitted to the second transistor through the third transistor T 3.
  • T 2 is output by the second pole of the second transistor T 2 as an initial driving signal.
  • Step 20 The boosting sub-circuit receives the initial driving signal, amplifies the initial driving signal, generates a target driving signal, and outputs the target driving signal.
  • the driving signal generating sub-circuit 10 transmits the initial driving signal to the boosting sub-circuit 20.
  • the boosting sub-circuit 20 is turned on, the initial driving signal is amplified, and the amplified target driving signal is
  • Step 30 The light-emitting sub-circuit 30 receives the target driving signal, and the self-light-emitting device in the light-emitting sub-circuit emits light under the driving of the target driving signal.
  • the driving method provided by some embodiments of the present disclosure may control the boosting sub-circuit 20 to amplify the initial driving signal generated by the driving signal generating sub-circuit 10 so that the target driving signal transmitted to the light-emitting sub-circuit 30 is larger than the driving signal generating sub-circuit 10 Generated initial drive signal.
  • the driving current of the self-light-emitting device in the light-emitting sub-circuit 30 can be increased, and the light-emitting brightness of the self-light-emitting device can be increased, thereby achieving the effect of increasing the light-emitting brightness of the entire display device.

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Abstract

一种像素电路，包括：驱动信号生成子电路，被配置为生成并输出初始驱动信号；与驱动信号生成子电路电连接的升压子电路，被配置为接收初始驱动信号，对初始驱动信号进行放大以生成目标驱动信号，并输出目标驱动信号；与升压子电路电连接的发光子电路，被配置为接收目标驱动信号，在目标驱动信号的驱动下发光。

Description

像素电路及其驱动方法、显示装置
本申请要求于2018年07月24日提交中国专利局、申请号为201810821748.6、申请名称为“一种像素电路及其驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
OLED(Organic Light-Emitting Diode，有机电致发光二极管)显示装置具有薄、轻、宽视角、主动发光、发光颜色连续可调、成本低、高色域、高对比度、响应速度快、耗能小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高、抗震性能好及可柔性显示等优点，因此被广泛应用于显示领域。
发明内容
一方面，提供一种像素电路。所述像素电路包括：驱动信号生成子电路，被配置为生成并输出初始驱动信号；与所述驱动信号生成子电路电连接的升压子电路，被配置为接收所述初始驱动信号，对所述初始驱动信号进行放大以生成目标驱动信号，并输出所述目标驱动信号；与所述升压子电路电连接的发光子电路，被配置为接收所述目标驱动信号，在所述目标驱动信号的驱动下发光。
在一些实施例中，所述升压子电路包括：晶体三极管，具有基极、集电极、及发射极；第一电阻，电连接于所述驱动信号生成子电路和所述晶体三极管的基极之间；第二电阻，电连接于第一电压端和所述晶体三极管的集电极之间；第三电阻，电连接于第二电压端和所述晶体三极管的发射极之间；所述晶体三极管的发射极还与所述发光子电路电连接。
在一些实施例中，所述晶体三极管包括硅晶体三极管。
在一些实施例中，所述驱动信号生成子电路包括：第一晶体管、第二晶体管、第三晶体管、及第一存储电容；所述第一晶体管的控制极与第一扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第 一存储电容的第一端电连接；所述第二晶体管的控制极与所述第一晶体管的第二极及所述第一存储电容的第一端电连接，第一极与所述第三晶体管的第二极电连接，第二极与所述升压子电路电连接；所述第三晶体管的控制极与所述使能信号端电连接，第一极与第三电压端电连接；所述第一存储电容的第二端与第四电压端电连接。
在一些实施例中，所述驱动信号生成子电路还包括：第四晶体管；所述第四晶体管的控制极与第二扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第一存储电容的第一端电连接。
在一些实施例中，所述第一晶体管和所述第四晶体管中的一个为N型晶体管，另一个为P型晶体管。
在一些实施例中，所述驱动信号生成子电路还包括：第五晶体管；所述第五晶体管的控制极与第一复位信号端电连接，第一极与第五电压端电连接，第二极与所述第二晶体管的第二极及所述升压子电路电连接。
在一些实施例中，在所述升压子电路与第一电压端电连接的情况下，所述第三电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
在一些实施例中，所述驱动信号生成子电路包括：第六晶体管、第七晶体管、及第二存储电容；所述第六晶体管的控制极与第三扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第二存储电容的第一端电连接；所述第七晶体管的控制极与所述第六晶体管的第二极及所述第二存储电容的第一端电连接，第一极与所述第二存储电容的第二端及第六电压端电连接，第二极与所述升压子电路电连接。
在一些实施例中，所述驱动信号生成子电路还包括：第八晶体管；所述第八晶体管的控制极与第四扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第七晶体管的控制极及所述第二存储电容的第一端电连接。
在一些实施例中，所述第六晶体管和所述第八晶体管中的一个为N型晶体管，另一个为P型晶体管。
在一些实施例中，所述驱动信号生成子电路还包括：第九晶体管；所述第九晶体管的控制极与第二复位信号端电连接，第一极与第七电压端电连接，第二极与所述第七晶体管的第二极及所述升压子电路电连接。
在一些实施例中，在所述升压子电路与所述第一电压端电连接的情 况下，所述第六电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
在一些实施例中，所述发光子电路包括：自发光器件，所述自发光器件的阳极与所述升压子电路电连接，阴极与第八电压端电连接。
在一些实施例中，所述发光子电路还包括：第四电阻；所述第四电阻电连接于所述自发光器件的阳极与所述升压子电路之间。
在一些实施例中，所述驱动信号生成子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、及第一存储电容。所述第一晶体管的控制极与第一扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第一存储电容的第一端电连接；所述第一存储电容的第二端与第四电压端电连接。所述第二晶体管的控制极与所述第一晶体管的第二极及所述第一存储电容的第一端电连接，第一极与所述第三晶体管的第二极电连接，第二极与所述升压子电路电连接。所述第三晶体管的控制极与所述使能信号端电连接，第一极与第三电压端电连接。所述第四晶体管的控制极与第二扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第二晶体管的控制极及所述第一存储电容的第一端电连接。所述第五晶体管的控制极与第一复位信号端电连接，第一极与第五电压端电连接，第二极与所述第二晶体管的第二极及所述升压子电路电连接。其中，所述第一晶体管和所述第四晶体管中的一个为N型晶体管，另一个为P型晶体管；在所述升压子电路与第一电压端电连接的情况下，所述第三电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
在一些实施例中，所述驱动信号生成子电路包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、及第二存储电容。所述第六晶体管的控制极与第三扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第二存储电容的第一端电连接。所述第六晶体管的控制极与第三扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第二存储电容的第一端电连接。所述第七晶体管的控制极与所述第六晶体管的第二极及所述第二存储电容的第一端电连接，第一极与所述第二存储电容的第二端及第六电压端电连接，第二极与所述升压子电路电连接。所述第八晶体管的控制极与第四扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第七晶体管的控制极及所述第二存储电容 的第一端电连接。所述第九晶体管的控制极与第二复位信号端电连接，第一极与第七电压端电连接，第二极与所述第七晶体管的第二极及所述升压子电路电连接。其中，所述第六晶体管和所述第八晶体管中的一个为N型晶体管，另一个为P型晶体管；在所述升压子电路与所述第一电压端电连接的情况下，所述第六电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
另一方面，提供一种显示装置。包括上述任一实施例所述的像素电路。
再一方面，提供一种如上述任一实施例所述的像素电路的驱动方法。所述驱动方法包括：驱动信号生成子电路生成初始驱动信号，并输出所述初始驱动信号；升压子电路接收所述初始驱动信号，对所述初始驱动信号进行放大，生成目标驱动信号，并输出所述目标驱动信号；发光子电路接收所述目标驱动信号，所述发光子电路中的自发光器件在所述目标驱动信号的驱动下发光。
在一些实施例中，驱动信号生成子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第一存储电容。所述驱动信号生成子电路生成初始驱动信号，包括：所述第一晶体管在经由第一扫描信号端输出的第一扫描信号的控制下开启，所述第四晶体管在经由第二扫描信号端输出的第二扫描信号的控制下开启；经由数据电压端输出的数据电压信号经所述第一晶体管和所述第四晶体管传输并存储至所述第一存储电容，同时传输至所述第二晶体管的控制极；所述第三晶体管在经由使能信号端输出的使能信号的控制下开启，经由第三电压端输出的第三电压信号经所述第三晶体管传输至所述第二晶体管，被所述第二晶体管的第二极作为所述初始驱动信号输出。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为相关技术中提供的一种像素电路的结构示意图；
图2为本公开一些实施例提供的像素电路的结构示意图；
图3为本公开一些实施例提供的一种图2所示的像素电路中各子电 路的结构示意图；
图4为本公开一些实施例提供的另一种图2所示的像素电路中各子电路的结构示意图；
图5为本公开一些实施例提供的再一种图2所示的像素电路中各子电路的结构示意图；
图6为本公开一些实施例提供的又一种图2所示的像素电路中各子电路的结构示意图；
图7为本公开一些实施例提供的一种用于驱动图4所示的像素电路的时序图；
图8为本公开一些实施例提供的又一种图2所示的像素电路中各子电路的结构示意图；
图9为本公开一些实施例提供的又一种图2所示的像素电路中各子电路的结构示意图；
图10为本公开一些实施例提供的一种用于驱动图9所示的像素电路的时序图；
图11为本公开一些实施例提供的图1所示的像素电路的仿真效果图；
图12为本公开一些实施例提供的图4所示的像素电路的仿真效果图；
图13为本公开一些实施例提供的显示装置的结构示意图；
图14为本公开一些实施例提供的一种像素电路的驱动方法的流程示意图；
图15为本公开一些实施例提供的一种驱动信号生成子电路生成初始驱动信号的流程示意图。
具体实施方式
下面将结合附图，对本公开的一些实施例进行描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
OLED(Organic Light-Emitting Diode,有机发光二极管)显示装置包括多个子像素，每个子像素对应设置一像素电路。相关技术中，如图1所示，AMOLED(Active-Matrix Organic Light-Emitting Diode，有源矩 阵有机发光二极管)像素电路包括两个薄膜晶体管(开关晶体管T C和驱动晶体管T d)、一个电容C、及一个OLED发光器件。驱动过程中，开关晶体管T C打开，数据电压端Data的数据电压写入存储电容C，控制驱动晶体管T d工作在饱和区，以将电压端V b的电压输入至驱动晶体管T d，并变换为恒定的电流，进而在一帧时间内驱动OLED发光器件发光。
其中，OLED发光器件为电流型元件，输入至OLED发光器件的电流受数据电压端Data输入的数据电压信号的控制，同时也受到驱动晶体管T d阈值电压的影响。现有的OLED显示装置中，数据电压端Data输入的数据电压信号具有的电压较低，且电压端V a的电压有限，这导致OLED器件两端电压无法满足高亮度需求。如果要通过更改数据电压信号具有的电压来提高OLED发光器件的亮度，一方面是像素电路中的晶体管参数需要变化，电路等器件均需要重新设计，过程繁琐；另一方面，驱动晶体管T d存在体效应(body effect)，即驱动晶体管T d存在较大的阈值电压漂移，当数据电压信号具有较高电压时，驱动晶体管T d处存在较大的电压损失，使得数据电压信号在传送至OLED发光器件时压降较大，导致只能向OLED发光器件输入较低的驱动电压，OLED发光器件亮度依然较低，无法实现高亮显示，从而减小了OLED显示装置的适用范围。
本公开一些实施例提供一种像素电路，如图2所示，该像素电路1包括驱动信号生成子电路10、与驱动信号生成子电路10电连接的升压子电路20、以及与升压子电路20电连接的发光子电路30。
其中，驱动信号生成子电路10被配置为生成并输出初始驱动信号。需要说明的是，此处不对驱动信号生成子电路10的结构进行限定，驱动信号生成子电路10能够生成初始驱动信号即可。因此，可以为发光子电路30的阳极传输初始驱动信号的电路均可以作为本公开中的驱动信号生成子电路10。
升压子电路20被配置为接收驱动信号生成子电路10输出的初始驱动信号，对该初始驱动信号进行放大以生成目标驱动信号，并输出所述目标驱动信号。
发光子电路30被配置为接收升压子电路20输出的目标驱动信号，在该目标驱动信号的驱动下发光。
在该实施例中，像素电路1中增加了升压子电路20，升压子电路20可以对驱动信号生成子电路10生成的初始驱动信号进行放大，使传输至发光子电路30的目标驱动信号大于驱动信号生成子电路10生成的初始驱动信号。这样能够提高发光子电路30的驱动电流，从而达到提高发光子电路30发光亮度的效果。
此外，升压子电路20是对驱动信号生成子电路10输出后的初始驱动信号进行放大，因此可以忽略驱动信号生成子电路10中的由于驱动晶体管的体效应造成的电压损失对发光子电路30发光亮度提升效果的影响。
在一些实施例中，如图3所示，升压子电路20包括：第一电阻R 1、第二电阻R 2、第三电阻R 3以及晶体三极管Q。
其中，晶体三极管Q具有基极a、集电极b、及发射极c，第一电阻R 1电连接于驱动信号生成子电路10和晶体三极管Q的基极a之间，第二电阻R 2电连接于第一电压端V 1和晶体三极管Q的集电极b之间。第三电阻R 3电连接于第二电压端V 2和晶体三极管Q的发射极c之间，晶体三极管Q的发射极c还与发光子电路30电连接。
升压子电路20的工作原理为：当驱动信号生成子电路10产生电压初始驱动信号V in传输至驱动信号生成子电路10的输出端A(也就是升压子电路20的输入端)处，且晶体三极管Q满足放大条件时，晶体三极管Q的基极a电流为I B，晶体三极管Q的发射极c电流为(1+β)×I B。此时升压子电路20的输出端B(也就是发光子电路30的输入端)输出的目标驱动信号为
Figure PCTCN2019097200-appb-000001
从而实现对驱动信号所具有的电压升压。
其中，β为晶体三极管Q的放大倍数，β大于1；U be为晶体三极管Q的基极a和发射极c开启电压，R b为第一电阻R 1的阻值，R e为第三电阻R 3的阻值。
晶体三极管的放大条件为发射结正偏、集电结反偏，因此，第一电阻R1、第二电阻R2、第三电阻R3的阻值的选取应满足在基极输入初始驱动电压V in后，发射结正偏及集电结反偏。示例性的，第一电阻R1的阻值为1KΩ，第二电阻R2的阻值为2KΩ，第三电阻R3的阻值为20Ω，β为100。这样，可以使晶体三极管Q工作在线性放大区(满足放大条 件)。此时，如果数据电压端Data写入的数据电压信号为5V，初始驱动信号V in为4.5V，通过升压子电路20后，输出的目标驱动信号V out为6.6V，电压将增长47％。
示例性的，晶体三极管Q为硅晶体三极管或锗晶体三极管。当像素电路中的晶体三极管Q为硅晶体三极管时，可以减小晶体三极管Q的占用空间，从而可以减小整个像素电路的占用空间。
上述驱动信号生成子电路10的结构有多种，包括但不限于如下示出的多个实施例。
在一些实施例中，如图3所示，驱动信号生成子电路10包括：第一晶体管T 1、第二晶体管T 2、第三晶体管T 3、及第一存储电容C 1。
其中，第一晶体管T 1的控制极与第一扫描信号端Gate1电连接，第一极与数据电压端Data电连接，第二极与第一存储电容C 1的第一端电连接。
第二晶体管T 2的控制极与第一晶体管T 1的第二极及第一存储电容C 1的第一端电连接，第一极与第三晶体管T 3的第二极电连接，第二极与升压子电路20电连接。
第三晶体管T 3的控制极与使能信号端EM电连接，第一极与第三电压端V 3电连接。
第一存储电容C 1的第二端与第四电压端V 4电连接。
在该实施例中，第一晶体管T 1在第一扫描信号端Gate1的控制下，将数据电压端Data的信号传输至第一存储电容C 1，第一存储电容C 1用于保证第二晶体管T 2(作为驱动晶体管使用)工作在饱和区，第三晶体管T 3在使能信号端EM的控制下，将第三电压端V 3的电压传输至第二晶体管T 2，使第二晶体管T 2的第二极可以输出初始驱动信号，从而可以将该初始驱动信号输入至升压子电路20中。
其中，示例性的，上述驱动信号生成子电路10中，还包括与第一晶体管T 1并联的多个开关晶体管、与第二晶体管T 2并联的多个开关晶体管、以及与第三晶体管T 3并联的多个开关晶体管。
基于此，在一些实施例中，如图3所示，驱动信号生成子电路10还包括：第四晶体管T 4，第四晶体管T 4的控制极与第二扫描信号端Gate2电连接，第一极与数据电压端Data电连接，第二极与第一存储电容C 1 的第一端电连接。这样，第一晶体管T 1在第一扫描信号端Gate1的控制下，将数据电压端Data的信号传输至第一存储电容C 1；第四晶体管T 4在第二扫描信号端Gate2的控制下，将数据电压端Data的信号传输至第一存储电容C 1。示例性的，如图3所示，第一晶体管T 1和第四晶体管T 4中的一个为N型晶体管，另一个为P型晶体管。其中，N型晶体管可以有效的传输低电压，P型晶体管可以有效的传输高电压，因此通过采用第一晶体管T 1和第四晶体管T 4共同传输数据电压端Data的信号，可以稳定可靠地将数据电压端Data的信号传输至第一存储电容C 1。需要说明的是，这里的低电压、高电压仅表示输入的信号所具有的电压之间的相对大小关系。
其中，示例性的，上述驱动信号生成子电路10还包括与第四晶体管T 4并联的多个开关晶体管。
在一些实施例中，如图4所示，上述驱动信号生成子电路10还包括第五晶体管T 5，第五晶体管T 5的控制极与第一复位信号端Reset1电连接，第一极与第五电压端V 5电连接，第二极与第二晶体管T 2的第二极及升压子电路电20连接。这样，在驱动发光子电路30发光之前，可以先对发光子电路30进行初始化，降低了阈值电压漂移对发光效果的影响。
其中，示例性的，上述驱动信号生成子电路10还包括与第五晶体管T 5并联的多个开关晶体管。
示例性的，如图4所示，第一电阻R 1的一端连接第二晶体管T 2的第二极和第五晶体管T 5的第一极，第一电阻R 1的另一端连接晶体三极管Q的基极。
示例性的，如图4所示，在升压子电路20与第一电压端V 1电连接的情况下，第三电压端V 3被配置为输出与第一电压端V 1所输出的电压信号相同的电压信号。这样设计，可以利用同一电源电压信号端向第一电压端V 1和第三电压端V 3输出电压信号，简化了电路结构，降低了像素电路的制作难度，提高了像素电路的稳定性和可靠性。
在另一些实施例中，如图5所示，驱动信号生成子电路10包括：第六晶体管T 6、第七晶体管T 7、及第二存储电容C 2。
其中，第六晶体管T 6的控制极与第三扫描信号端Gate3电连接，第一极与数据电压端Data电连接，第二极与第二存储电容C 2的第一端电 连接。
第七晶体管T 7的控制极与第六晶体管T 6的第二极及第二存储电容C 2的第一端电连接，第一极与第二存储电容C 2的第二端及第六电压端V 6电连接，第二极与升压子电路20电连接。
在该实施例中，第六晶体管T 6在第三扫描信号端Gate3的控制下，将数据电压端Data的信号传输至第二存储电容C 2，第二存储电容C 2用于保证第七晶体管T 7(作为驱动晶体管使用)工作在饱和区，此时，第六电压端V 6的电压传输至第七晶体管T 7，使第七晶体管T 7的第二极可以输出初始驱动信号，从而可以将该初始驱动信号输入至升压子电路20中。
其中，示例性的，上述驱动信号生成子电路10中，还包括与第六晶体管T 6并联的多个开关晶体管，以及与第七晶体管T 7并联的多个开关晶体管。
基于此，在一些实施例中，如图6所示，驱动信号生成子电路10还包括：第八晶体管T 8，第八晶体管T 8的控制极与第四扫描信号端Gate4电连接，第一极与数据电压端Data电连接，第二极与第七晶体管T 7的控制极及第二存储电容C 2的第一端电连接。这样，第六晶体管T 6在第三扫描信号端Gate3的控制下，将数据电压端Data的信号传输至第二存储电容C 2；第八晶体管T 8在第四扫描信号端Gate4的控制下，将数据电压端Data的信号传输至第二存储电容C 2。示例性的，如图6所示，第六晶体管T 6和第八晶体管T 8中的一个为N型晶体管，另一个为P型晶体管。其中，N型晶体管可以有效的传输低电压，P型晶体管可以有效的传输高电压，因此通过采用第六晶体管T 6和第八晶体管T 8共同传输数据电压端Data的信号，可以稳定可靠地将数据电压端Data的信号传输至第一存储电容C 2。需要说明的是，这里的低电压、高电压仅表示输入的信号所具有的电压之间的相对大小关系。
其中，示例性的，上述驱动信号生成子电路10还包括与第八晶体管T 8并联的多个开关晶体管。
在一些实施例中，如图6所示，上述驱动信号生成子电路10还包括：第九晶体管T 9，第九晶体管T 9的控制极与第二复位信号端Reset2电连接，第一极与第七电压端V 7电连接，第二极与第七晶体管T 7的第二极 及升压子电路20电连接。这样，在驱动发光子电路30发光之前，可以先对发光子电路30进行初始化，降低了阈值电压漂移对发光效果的影响。
其中，示例性的，上述驱动信号生成子电路10还包括与第九晶体管T 9并联的多个开关晶体管。
示例性的，如图6所示，第一电阻R 1的一端连接第七晶体管T 7的第二极和第九晶体管T 9的第一极，第一电阻R 1的另一端连接晶体三极管Q的基极。
示例性的，在升压子电路20与第一电压端V 1电连接的情况下，第六电压端V 6被配置为输出与第一电压端V 1所输出的电压信号相同的电压信号。这样设计，可以利用同一电源向第一电压端V 1和第六电压端V 6输出相同的电压信号，简化了电路结构，降低了制作难度，提高了稳定性和可靠性。
发光子电路30的结构有多种，在一些实施例中，如图3至图6所示，发光子电路30包括：自发光器件L，自发光器件L的阳极与升压子电路20电连接(例如，自发光器件L的阳极连接至晶体三极管Q的发射极)，阴极与第八电压端V 8电连接。这样设计，可以利用升压子电路20输出的目标驱动信号和第八电压端V 8输出的信号驱动自发光器件L发光，由于目标驱动信号大于驱动信号生成子电路10生成的初始驱动信号，因此提高了自发光器件的发光亮度。
其中，示例性的，自发光器件L为OLED器件。
在一些实施例中，如图4和图6所示，发光子电路30还包括：第四电阻R 4，第四电阻R 4电连接于自发光器件L的阳极与升压子电路20之间，例如，第四电阻R 4的一端连接晶体三极管Q的发射极，另一端连接自发光器件L的阳极。这样设计，在将多个像素电路应用于显示装置时，如果其中的一个像素电路发生短路，该像素电路中的第四电阻R 4可以减小其上的短路电流，从而可以防止引起其周围的像素电路也发生短路。
基于上述一些实施例对驱动信号生成子电路10、升压子电路20、及发光子电路30的描述，以下结合图4和图7对上述像素电路的驱动过程进行详细的说明。
需要说明的是，本公开一些实施例中像素电路包括的各晶体管的类型不做限定，上述第一晶体管T 1至第九晶体管T 9可以是N型晶体管， 也可以是P型晶体管。在一些实施例中，如图4所示的像素电路，其包含的第三晶体管T 3和第四晶体管T 4为P型晶体管，除第三晶体管T 3和第四晶体管T 4以外的各个晶体管均为N型晶体管。下面以图4所示的像素电路为例进行说明。
另外，在一些实施例中，晶体管的控制极为栅极。晶体管的第一极为漏极、第二极为源极；或者，第一极为源极、第二极为漏极。本公开对此不作限制。
根据晶体管导电方式的不同，可以将上述像素电路中的各个晶体管设置为增强型晶体管或耗尽型晶体管。本公开对此不作限制。
本公开一些实施例以经由第八电压端V 8输出的第八电压信号为低电平信号，经由第四电压端V 4输出的第四电压信号为低电平信号，经由第一电压端V 1输出的第一电压信号为高电平信号，第二电压端V 2接地为例进行的说明。此处，这里的高电平、低电平仅表示输入的信号所具有的电压之间的相对大小关系。
如图4所示的像素电路的驱动过程包括三个阶段：初始驱动信号生成阶段、目标驱动信号生成阶段、发光阶段。
初始信号生成阶段：
在此阶段中，各信号端的时序图如图7所示。此阶段包括第一时段t 1、第二时段t 2和第三时段t 3。
第一时段t 1：初始信号端Reset1输入高电平的初始信号，控制第五晶体管T 5开启，将第五电压端V 5的信号传输至升压子电路20，经升压子电路20传输至发光子电路30，对自发光器件L的阳极进行初始化。
其中，本领域技术人员应该明白，第五电压端V 5传输的信号可以很小很小，或者可以为0V。而且升压子电路20可以对第五电压端V 5的信号进行放大后再传输至发光子电路30。
第二时段t 2：第一扫描信号端Gate1输入高电平的第一扫描信号，控制第一晶体管T 1开启，将经由数据电压端Data输出的数据电压信号传输至第一存储电容C 1和第二晶体管T 2的控制极。
同时，第二扫描信号端Gate2输入低电平的第二扫描信号，控制第四晶体管T 4开启，将经由数据电压端Data输出的数据电压信号传输至第一存储电容C 1和第二晶体管T 2的控制极。
第三时段t 3：第一扫描信号端Gate1输入的信号变为低电平信号，第二扫描信号端Gate2输入的信号变为高电平信号，控制第一晶体管T 1和第四晶体管T 4截止，第二晶体管T 2工作在饱和区。使能信号端EM输入低电平的使能信号，控制第三晶体管T 3开启，将经由第三电压端V 3输出的第三电压信号传输至第二晶体管T 2，以使第二晶体管T 2生成初始驱动信号并输出至升压子电路20。
此时，数据电压端Data可持续输入数据电压信号，也可以停止输入数据电压信号。
在一些实施例中，如图8和图9所示，像素电路1中的第三晶体管T 3可以由P型晶体管替换为N型晶体管，例如图8中的像素电路相较于图3中的像素电路而言将第三晶体管T 3的类型由P型晶体管替换为N型晶体管，图9中的像素电路相较于图4中的像素电路而言将第三晶体管T 3的类型由P型晶体管替换为N型晶体管。此时，基于图9示出的像素电路1，上述初始信号生成阶段的第三阶段t 3将发生变化，如图10所示，,第三阶段t 3需要使能信号端EM输入高电平的使能信号来控制第三晶体管T 3开启，才能将经由第三电压端V 3输出的第三电压信号传输至第二晶体管T 2，以使第二晶体管T 2生成初始驱动信号并输出至升压子电路20。
在一些实施例中，可以通过调整使能信号端EM输入的使能信号的占空比来调整初始驱动信号的大小，从而实现对自发光器件L亮度和对比度的调节。
目标驱动信号生成阶段：升压子电路20对接收到的初始驱动信号进行放大生成目标驱动信号并输出至发光子电路30，放大后的目标驱动信号为：
Figure PCTCN2019097200-appb-000002
发光阶段：自发光器件L在目标驱动信号和经由第八电压端V 8输出的第八电压信号的驱动下发光。
其中，第三晶体管T 3在经由使能信号端EM输出的使能信号的控制下，将第三电压端V 3提供的信号具有的电压传输至第二晶体管T 2，以向自发光器件L的阳极提供电压。第八电压端V 8提供的信号为自发光器件L的阴极提供电压。可以通过调整第八电压端V 8的信号来调整施加到自发光器件L上的驱动电压，从而实现对自发光器件L亮度和对比度的调 节。
图11为HSPICE(高精度电路仿真)模拟的如图1所示的像素电路中OLED发光器件的发光电流。其中，输入至OLED发光器件阳极的电压为4.5V，经电压端V a输入至OLED发光器件阴极的电压可调节，当经电压端V a输入至OLED发光器件阴极的电压为-1V时，如图8所示，OLED发光器件两端的电压为4.5V-(-1V)＝5.5V，流经OLED发光器件的电流为1.90nA。
图12为HSPICE模拟的如图4所示的像素电路中自发光器件L(即OLED发光器件)的发光电流。其中，经升压子电路20放大后，输入至自发光器件L阳极的电压为6.6V，经电压端V 8输入至自发光器件L阴极的电压可调节，当经电压端V 8输入至自发光器件L阴极的电压为-1V时，如图12所示，自发光器件L两端的电压为6.6V-(-1V)＝7.6V，自发光器件L的电流为7.70nA，电流提高305％，自发光器件L的亮度大幅度提高。
本公开一些实施例还提供一种显示装置。如图13所示，所述显示装置2包括多个像素电路，每个像素电路为上述任一实施例提供的像素电路。其中，示例性的，如图13所示，所述显示装置2包括多个像素单元1，多个像素单元1阵列设置，每一个像素单元1包括上述的任意一个像素电路。
在该实施例中，每个像素电路1包括驱动信号生成子电路10、升压子电路20、及发光子电路30，发光子电路30包含自发光器件L，由于像素电路1中增加了升压子电路20，升压子电路20可以对驱动信号生成子电路10生成的初始驱动信号进行放大，使传输至发光子电路30的目标驱动信号大于驱动信号生成子电路10生成的初始驱动信号。这样能够提高发光子电路30中的自发光器件L的驱动电流，提高自发光器件L发光亮度，从而达到提高整个显示装置2的发光亮度的效果。
其中，示例性的，上述显示装置为OLED显示器、数码相框、手机、平板电脑、导航仪等具有任何显示功能的产品或者部件。
本公开一些实施例还提供一种上述像素电路的驱动方法，如图14所示，该驱动方法包括：
步骤10、驱动信号生成子电路10生成初始驱动信号，并输出初始驱动信号。
在一些实施例中，如图4所示，所述驱动信号生成子电路包括：第一晶体管T 1、第二晶体管T 2、第三晶体管T 3、第四晶体管T 4以及第一存储电容C 1。
在此基础上，如图15所示，步骤10包括：
步骤101、第一晶体管T 1在经由第一扫描信号端Gate1输出的第一扫描信号的控制下开启，第四晶体管T 4在经由第二扫描信号端Gate2输出的第二扫描信号的控制下开启。
步骤102、经由数据电压端Data输出的数据电压信号经第一晶体管T 1和第四晶体管T 4传输并存储至第一存储电容C 1，同时传输至第二晶体管T 2的控制极。
步骤103、第三晶体管T 3在经由使能信号端EM输出的使能信号的控制下开启，经由第三电压端V 3的输出的第三电压信号经第三晶体管T 3传输至第二晶体管T 2，被第二晶体管T 2的第二极作为生成初始驱动信号输出。
步骤20、升压子电路接收初始驱动信号，对初始驱动信号进行放大，生成目标驱动信号，并输出目标驱动信号。
在该步骤中，驱动信号生成子电路10将初始驱动信号传输至升压子电路20，升压子电路20开启时，将初始驱动信号放大，放大后的目标驱动信号为
Figure PCTCN2019097200-appb-000003
步骤30、发光子电路30接收所述目标驱动信号，发光子电路中的自发光器件在所述目标驱动信号的驱动下发光。
本公开一些实施例提供的驱动方法，可以控制升压子电路20对驱动信号生成子电路10生成的初始驱动信号进行放大，使传输至发光子电路30的目标驱动信号大于驱动信号生成子电路10生成的初始驱动信号。这样能够提高发光子电路30中的自发光器件的驱动电流，提高自发光器件发光亮度，从而达到提高整个显示装置的发光亮度的效果。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素电路，包括：
    驱动信号生成子电路，被配置为生成并输出初始驱动信号；
    与所述驱动信号生成子电路电连接的升压子电路，被配置为接收所述初始驱动信号，对所述初始驱动信号进行放大以生成目标驱动信号，并输出所述目标驱动信号；
    与所述升压子电路电连接的发光子电路，被配置为接收所述目标驱动信号，在所述目标驱动信号的驱动下发光。
  2. 根据权利要求1所述的像素电路，其中，所述升压子电路包括：
    晶体三极管，具有基极、集电极、及发射极；
    第一电阻，电连接于所述驱动信号生成子电路和所述晶体三极管的基极之间；
    第二电阻，电连接于第一电压端和所述晶体三极管的集电极之间；
    第三电阻，电连接于第二电压端和所述晶体三极管的发射极之间；
    所述晶体三极管的发射极还与所述发光子电路电连接。
  3. 根据权利要求2所述的像素电路，其中，所述晶体三极管包括硅晶体三极管。
  4. 根据权利要求1～3中任一项所述的像素电路，其中，所述驱动信号生成子电路包括：第一晶体管、第二晶体管、第三晶体管、及第一存储电容；
    所述第一晶体管的控制极与第一扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第一存储电容的第一端电连接；
    所述第二晶体管的控制极与所述第一晶体管的第二极及所述第一存储电容的第一端电连接，第一极与所述第三晶体管的第二极电连接，第二极与所述升压子电路电连接；
    所述第三晶体管的控制极与所述使能信号端电连接，第一极与第三电压端电连接；
    所述第一存储电容的第二端与第四电压端电连接。
  5. 根据权利要求4所述的像素电路，其中，所述驱动信号生成子电路还包括：第四晶体管；
    所述第四晶体管的控制极与第二扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第一存储电容的第一端电连接。
  6. 根据权利要求5所述的像素电路，其中，所述第一晶体管和所述第四晶体管中的一个为N型晶体管，另一个为P型晶体管。
  7. 根据权利要求4所述的像素电路，其中，所述驱动信号生成子电路还包括：第五晶体管；
    所述第五晶体管的控制极与第一复位信号端电连接，第一极与第五电压端电连接，第二极与所述第二晶体管的第二极及所述升压子电路电连接。
  8. 根据权利要求4所述的像素电路，其中，在所述升压子电路与第一电压端电连接的情况下，所述第三电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
  9. 根据权利要求1～3中任一项所述的像素电路，其中，所述驱动信号生成子电路包括：第六晶体管、第七晶体管、及第二存储电容；
    所述第六晶体管的控制极与第三扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第二存储电容的第一端电连接；
    所述第七晶体管的控制极与所述第六晶体管的第二极及所述第二存储电容的第一端电连接，第一极与所述第二存储电容的第二端及第六电压端电连接，第二极与所述升压子电路电连接。
  10. 根据权利要求9所述的像素电路，其中，所述驱动信号生成子电路还包括：第八晶体管；
    所述第八晶体管的控制极与第四扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第七晶体管的控制极及所述第二存储电容的第一端电连接。
  11. 根据权利要求10所述的像素电路，其中，所述第六晶体管和所述第八晶体管中的一个为N型晶体管，另一个为P型晶体管。
  12. 根据权利要求9所述的像素电路，其中，所述驱动信号生成子电路还包括：第九晶体管；
    所述第九晶体管的控制极与第二复位信号端电连接，第一极与第七电压端电连接，第二极与所述第七晶体管的第二极及所述升压子电路电连接。
  13. 根据权利要求9所述的像素电路，其中，在所述升压子电路与所述第一电压端电连接的情况下，所述第六电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
  14. 根据权利要求1所述的像素电路，其中，所述发光子电路包括：
    自发光器件，所述自发光器件的阳极与所述升压子电路电连接，阴极与第八电压端电连接。
  15. 根据权利要求14所述的像素电路，其中，所述发光子电路还包括：第四电阻；
    所述第四电阻电连接于所述自发光器件的阳极与所述升压子电路之间。
  16. 根据权利要求1所述的像素电路，其中，所述驱动信号生成子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、及第一存储电容；
    所述第一晶体管的控制极与第一扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第一存储电容的第一端电连接；所述第一存储电容的第二端与第四电压端电连接；
    所述第二晶体管的控制极与所述第一晶体管的第二极及所述第一存储电容的第一端电连接，第一极与所述第三晶体管的第二极电连接，第二极与所述升压子电路电连接；
    所述第三晶体管的控制极与所述使能信号端电连接，第一极与第三电压端电连接；
    所述第四晶体管的控制极与第二扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第二晶体管的控制极及所述第一存储电容的第一端电连接；
    所述第五晶体管的控制极与第一复位信号端电连接，第一极与第五电压端电连接，第二极与所述第二晶体管的第二极及所述升压子电路电连接；
    其中，所述第一晶体管和所述第四晶体管中的一个为N型晶体管，另一个为P型晶体管；在所述升压子电路与第一电压端电连接的情况下，所述第三电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
  17. 根据权利要求1所述的像素电路，其中，所述驱动信号生成子电路包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、及第二存储电容；
    所述第六晶体管的控制极与第三扫描信号端电连接，第一极与数据 电压端电连接，第二极与所述第二存储电容的第一端电连接；
    所述第六晶体管的控制极与第三扫描信号端电连接，第一极与数据电压端电连接，第二极与所述第二存储电容的第一端电连接；
    所述第七晶体管的控制极与所述第六晶体管的第二极及所述第二存储电容的第一端电连接，第一极与所述第二存储电容的第二端及第六电压端电连接，第二极与所述升压子电路电连接；
    所述第八晶体管的控制极与第四扫描信号端电连接，第一极与所述数据电压端电连接，第二极与所述第七晶体管的控制极及所述第二存储电容的第一端电连接；
    所述第九晶体管的控制极与第二复位信号端电连接，第一极与第七电压端电连接，第二极与所述第七晶体管的第二极及所述升压子电路电连接；
    其中，所述第六晶体管和所述第八晶体管中的一个为N型晶体管，另一个为P型晶体管；在所述升压子电路与所述第一电压端电连接的情况下，所述第六电压端被配置为输出与所述第一电压端所输出的电压信号相同的电压信号。
  18. 一种显示装置，包括权利要求1～17中任一项所述的像素电路。
  19. 一种如权利要求1～17中任一项所述的像素电路的驱动方法，包括：
    驱动信号生成子电路生成初始驱动信号，并输出所述初始驱动信号；
    升压子电路接收所述初始驱动信号，对所述初始驱动信号进行放大，生成目标驱动信号，并输出所述目标驱动信号；
    发光子电路接收所述目标驱动信号，所述发光子电路中的自发光器件在所述目标驱动信号的驱动下发光。
  20. 根据权利要求19所述的像素电路的驱动方法，其中，所述驱动信号生成子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第一存储电容；
    所述驱动信号生成子电路生成初始驱动信号，包括：
    所述第一晶体管在经由第一扫描信号端输出的第一扫描信号的控制下开启，所述第四晶体管在经由第二扫描信号端输出的第二扫描信号的控制下开启；
    经由数据电压端输出的数据电压信号经所述第一晶体管和所述第四 晶体管传输并存储至所述第一存储电容，同时传输至所述第二晶体管的控制极；
    所述第三晶体管在经由使能信号端输出的使能信号的控制下开启，经由第三电压端输出的第三电压信号经所述第三晶体管传输至所述第二晶体管，被所述第二晶体管的第二极作为所述初始驱动信号输出。
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