WO2020009763A1 - Micro light emitting diode array lithography - Google Patents

Micro light emitting diode array lithography Download PDF

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Publication number
WO2020009763A1
WO2020009763A1 PCT/US2019/035059 US2019035059W WO2020009763A1 WO 2020009763 A1 WO2020009763 A1 WO 2020009763A1 US 2019035059 W US2019035059 W US 2019035059W WO 2020009763 A1 WO2020009763 A1 WO 2020009763A1
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WIPO (PCT)
Prior art keywords
substrate
light emitting
array
logic
lithography apparatus
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Application number
PCT/US2019/035059
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English (en)
French (fr)
Inventor
David Markle
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Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to CN201980044364.0A priority Critical patent/CN112334837B/zh
Publication of WO2020009763A1 publication Critical patent/WO2020009763A1/en

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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20Exposure; Apparatus therefor
    • G03F7/2051Exposure without an original mask, e.g. using a programmed deflection of a point source, by scanning, by drawing with a light beam, using an addressed light or corpuscular source
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70383Direct write, i.e. pattern is written directly without the use of a mask by one or multiple beams
    • G03F7/70391Addressable array sources specially adapted to produce patterns, e.g. addressable LED arrays
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection

Definitions

  • aspects of the disclosure relate to maskless lithography systems. More specifically, aspects of the disclosure relate to systems and methods for micro light emitting diode array lithography.
  • LEDs light emitting diodes
  • the conventional techniques for mask-less lithography use a laser-illuminated, micro-mirror array, such as those available from Texas Instruments.
  • Use of this device has two inherent disadvantages in conjunction with lithography.
  • a first disadvantage is that the maximum frame rate is 20 kHz.
  • the second disadvantage is that the coherence of the illumination beam combined with the grating nature of the mirror array conflicts with the telecentricity requirements of the projection lens.
  • the limited frame rate results in either a very slow scan rate and/or a low overall throughput.
  • the limited frame rate may also result in very complex software that computes fifty (50) or more different patterns for every point on the substrate.
  • the lack of telecentricity compromises not only the depth-of-field performance but also the overlay performance.
  • a lithography apparatus comprising a substrate scanning system configured to scan a substrate, one or more arrays of micro light emitting diodes, which are imaged by an imaging system onto the substrate wherein hard wired logic is incorporated into the one or more arrays and are configured to shift a logic signal in one scan direction and configured to use the logic signal to turn an individual LED fully on or fully off.
  • a method to perform micro light emitting diode lithography comprising: placing a substrate on to a stage configured to hold the substrate, aligning the substrate on the stage with a reference; illuminating the substrate on the stage with at least one array of micro light emitting diodes and removing the substrate from the stage.
  • FIG. 1 is a graph showing how the location of a line edge can be moved by changing the relative exposure dose generated by the pixels at the line edge.
  • FIG. 2 is a graph showing the nearly linear relationship between the relative exposure dose generated by the row of diodes defining an edge vs. the line edge position.
  • FIG. 3 is a plan and cross-sectional view of an LED array covered by immersion lenses.
  • FIG. 4 is a schematic illustrating how flip-flop logic states progress through 5 clock cycles.
  • FIG. 5 is a schematic example illustrating how the internal and external logic contained in an LED column can be arranged to transfer an exposure pattern from one end of an LED array to the other in synchronism with the motion of the substrate.
  • FIG. 6 is a layout illustrating how two LED arrays can be positioned in a relay object plane so that the column spacing is preserved.
  • FIG. 7 is a lithography apparatus in one example aspect described.
  • FIG. 8 is an example method for performing a lithography service in one described aspect.
  • FIG. 9 is an example method for performing a lithography service in one described aspect.
  • the aspects presented herein provide an LED approach to lithography.
  • Such an LED approach to lithography can potentially provide frame diode modulation rates exceeding 1 MHz, if needed, significantly exceeding the 20 kHz maximum frame rates of conventional micro-mirror systems.
  • the LED approach to lithography, described herein can provide incoherent illumination at 405 nm, which does not produce interference that conflicts with projection system telecentricity requirements.
  • each LED output to the substrate and utilizes the output of every LED in a column to achieve the maximum exposure: thus maximizing the exposure dose delivered per diode.
  • this arrangement is capable of delivering a very finely gradiated gray scale to each sub-pixel on the substrate, each diode is operated either full-on or full-off. There is no need for complex control circuitry to provide continuously variable output power for every diode.
  • a lithography apparatus 101 having a stage 100 that holds a substrate 102.
  • a substrate scanning system 104 is configured to scan the substrate 102.
  • the substrate scanning system 104 is configured with arrays of micro light emitting diodes 106, wherein individual diodes are automatically sequenced on and off to transfer the exposure pattern from one end of the array to the other in synchronism with the motion of the substrate, while at the same time, the exposure dose delivered by each sub-pixel is finely controlled.
  • a pattern generator 110 is also provided and is connected to a computer 112.
  • a system clock 116 synchronized to the scan velocity drives the transfer of data through the array of flip-flops 114.
  • Each diode has an associated flip-flop logic circuit, the logic state of which determines whether an individual LED is full-on or full-off.
  • Each column of diodes is oriented in the scan direction. Each column has one diode that is operated individually, two diodes that are operated sequentially, four diodes that operated sequentially, 8 diodes that are operated sequentially, and so on to a total of 2 n -1 , where n could be an integer between 6 and 12.
  • Hard wiring determines the sequence length in each group of diodes in a column.
  • a column contains 255 LEDs arranged in groups containing 1 , 2, 4, 8, 16, 32, 64, and 128 diodes, with the diodes in each group wired to operate in sequence.
  • a logical 1 would have to transferred to the first unconnected flip-flop and after the first clock cycle a logical 1 would have be transferred to the first flip-flop in the group of 2 and after the next two clock cycles a logical 1 would have to be transferred to the group of 4 flip-flops and after the next 4 clock cycles a logical 1 would have to be transferred the group of 8 flip- flops and so on, until a logical 1 is transferred to the group of 128 flip-flops.
  • the substrate contains a pattern under the resist layer to which the next lithography pattern has to be accurately aligned.
  • the pattern is illuminated with a dark-field illuminator wrapped around the end of the objective just above the substrate.
  • Light diffracted from the feature edges on the substrate passes back through the objective to a beam-splitter located just in front of the LED array where it is intercepted by a camera.
  • Pattern recognition software is used to recognize and calculate the position of the alignment keys currently on the substrate as well as the position of targets projected from the LED array to the substrate and uses this data to align the substrate with the patterns to be laid down in the following exposure.
  • two different configurations are possible.
  • the optical column is held fixed and the substrate stage is designed to have sufficient degrees of freedom to provide substrate scanning, stepping and angular orientation about the normal to the plane of the substrate.
  • An alternate approach is to provide a single axis scan capability in the substrate stage along with a capability to rotate the substrate a small amount about an axis normal the plane of the substrate in order to align the preexisting patterns with the scan direction. If multiple columns are required, because of time constraints, then the best approach is to mount the optical columns on a bridge that can be accurately stepped orthogonal to the single scan axis of the substrate stage.
  • the required exposure from a single pixel can be determined by overlaying the pixel grid on the desired exposure pattern.
  • the required grey-level is determined by the percentage of the pixel that covers the desired exposure pattern.
  • FIG. 1 illustrates the movement of the line edge profile as the intensity of the line of pixels defining the edge is increased from zero to the full exposure dose. To a first approximation, values over the exposure threshold of a level of photoresist will be exposed.
  • the position of the line edge is provided by a first order linear relationship with the exposure dose provided by the pixels defining the line edge determining the edge position.
  • an exposure threshold was set to 50% of the maximum exposure dose (similar to the limit illustrated in FIG. 1). Such an exposure threshold is consistent with the chemically amplified resists available. Grey-scaling provides good control on the location of edges, but does not yield square corners, since these require spatial frequencies well beyond the diffraction limit.
  • An advantage of the proposed methods and arrangements over conventional lithography systems is that a correct exposure for a pixel in the pattern to be copied onto the substrate need only be computed once and hard wired logic moves this exposure pattern across the substrate in synchronism with the scanning system. The result is simplification of the underlying software and the elimination of any limits on the scan speed imposed by pattern complexity.
  • Each pixel for the system is a square emitter on a larger surround that also contains a logical flip-flop system and a power transistor that can turn the LED on or off depending on the flip-flop logic status.
  • This example allows a grey-scale covering an exposure range from 0 to 255 to be generated for every LED pixel on the object plane.
  • the gray-scale is stored as an 8 bit byte, the binary digits of which can be distributed to the appropriate flip-flop strings contained in the external logic connected to every column.
  • Micro-LEDs are Lambertian emitters that spread a light output over a 180 degree angle. As efficiency is important to the overall system, it is desired to capture as much of the 180 degree angle light as possible to be able to effectively expose the photoresist layers by the lithography system.
  • An immersion lens is placed on top of each LED, however, such a placement reduces the emission angle in both directions by the index of the immersion lens material and also increases the apparent size of the LED by an equivalent amount.
  • each LED is 6.25 microns square and separated from its nearest neighbor by 10 microns, the resultant output would appear to be a continuous array emitting over a 77 degree cone angle rather than a 180 degree cone angle.
  • the higher index of the immersion material is responsible for changing the emission angle.
  • the lenses on top of the array preserve the gains achieved by the higher index with the transition back to air.
  • the LED emission area only occupies 39% of the 10 by 10 micron area taken up by each LED. The remaining 61 % may be used for other purposes, such as adding flip-flop logic and drive circuitry.
  • the light output from adjacent LED pixels is incoherent (having no stable phase relationship); therefore there are no coherent interference effects between pixels and no grating effects.
  • FIG. 3 is a cross-section (bottom portion) through several LEDs and their respective immersion lenses. Although the diodes appear to be 10 microns square and densely packed when viewed from above, there is ample room on the substrate for placement of a driver and logic associated with each LED.
  • the logic contained with each row of the LED array and the associated external logic is, in one embodiment, based on a series of clocked flip-flop circuits, which are configured to remember either a 1 or a 0 value.
  • Each clock cycle causes the data stored in the flip-flop located to the left to be transferred to the flip-flop on the right, when there is a connection.
  • the first flip- flop in a chain receives its input from a computer data-base that holds the patterns required to generate the desired exposure patterns on the substrate.
  • the flow of logic states or bits along a single flip-flop chain with each successive clock cycle is illustrated in FIG. 4. Since the clock cycle time is constant, a new and possibly different state is provided to each flip-flop in the chain with each clock cycle.
  • Each of the internal flip-flops is associated with an individual LED, and the state determines whether or not the LED is on or off.
  • Defective LEDs may also be compensated for by adding an extra LED and associated flip-flop or two for compensation. However each additional isolated flip-flop and LED combination requires the addition of another bit in the word describing the grey-scale.
  • placing the short flip-flop chains near the beginning of the scan reduces the number of flip-flops in the external logic chip to about half of the number of LEDs in a row.
  • the direction the logic state travel is reversed and the connections both in the external and internal logic are changed. In this instance the previously described circuitry is disabled and a like set of circuitry is provided for scanning in the opposite direction.
  • FIG. 5 is a schematic example illustrating how the internal and external logic contained in an LED column can be arranged to transfer an exposure pattern from one end of an LED array to the other in synchronism with the motion of the substrate.
  • a maximum LED chip size is 26 by 33mm, which is the field size of a step and scan system.
  • the object field size may also be some multiple of 26 by 33 mm depending on how many LED array chips are included in the field.
  • An example of a field containing two 26 by 33 mm LED arrays is shown in FIG. 6.
  • the number of LED arrangements (chips) to be included in each object field may be specified by economics.
  • the cost of the optical system increases with the square or the cube of the field size, but there are savings in the number of focusing and alignment systems required and in the labor involved with testing and correcting each optical system.
  • a system is modeled containing 2 LED chips, each 26 by 33 mm and yielding a substrate field of about 6.6 mm wide. In the scan direction, the positions of the 2 chips are staggered so that the LED positions on each chip can be accurately butted together or even overlapped slightly after scanning.
  • the 26 mm dimension of the proposed chip could hold a column containing as many as 2,600 LEDs.
  • the immersion lens illustrated in FIG. 3 changes the apparent size of each LED by the index of the glass used to make the immersion lens.
  • a 6.26 micron square LED appears to be a 10 micron square LED assuming 1.6 as the refractive index of the glass array.
  • the net effect of the immersion lens is to reduce the total power required from the LED array and increase the proportion of that power, which is delivered to the pupil of the optical relay.
  • the apparent increase in the area of each LED from 6.25 pm square to 10 m square is exactly offset by the decrease in the solid angle over which the output radiation is dispersed.
  • the amount of radiation passed to the pupil from a single LED, P p is given by the formula:
  • the pixel size area on the substrate is 1/100 the size of a pixel on the LED array.
  • the total power at the substrate from a single LED array depends on the total number of pixels in the array (3,300 by 2,023) and is therefore 0.04719 Watts. At the substrate this power is spread over an area of 2.023 by 3.3 mm or 0.0668 cm 2 .
  • the exposure dose, Ed depends on the ratio of the length of the diode array in the scan direction, I, to the scan velocity, v, times the power density:
  • Each flat panel is 1.8 m by 1.5 m in area and the acceleration/deceleration time to reach a velocity of 447.7cm/s with an acceleration of 1 g and then decelerate to zero velocity at 1 g is:
  • the substrate needs to be oriented very accurately to the fixed scan direction or capabilities need to be incorporated into the scanning system to vary the scan direction over a limited range along with corresponding corrections in the orientation of the LED array, since each column in the array has to be accurately aligned with the direction of scan.
  • Another possible embodiment is to provide a capability for lateral offsets within each optical column by moving a lens or small group of lenses laterally or by moving the LED array laterally. Having a correction capability within each optical column provides a capability to correct for local errors in the position of the previous patterns applied to the substrate, including process-induced distortions in the substrate.
  • the LED Imaging System The LED Imaging System
  • FIG. 7 A layout of a possible imaging system which is capable of imaging 2 LED arrays, each 26 by 33 mm in extent, is shown in FIG. 7. This system has a magnification of -0.1 so that each of the 10pm square pixels in the LED array is imaged as a 1 pm square on the LED.
  • the 0.094 NA at the image plane was determined by 0.7l divided by the minimum feature size of 3.0 pm.
  • the“diffraction limit” is approximately 0.06A the optical correction in this system is well beyond the diffraction limit over the entire spectral range from 399 m to 650 nm.
  • the exposure spectrum, which extends from 399 to 407 nm is corrected to about 0.01 l RMS.
  • the actual performance is most likely to be limited by fabrication errors.
  • This optical system is doubly telecentric so that small changes in the positions of the object and image planes do not affect the magnification ratio. Distortion is perhaps the most demanding aberration in most lithography systems.
  • the distortion in the exposure part of the spectrum (399-407 nm) is essentially zero.
  • the distortion in the 500-650 nm spectral band, which is employed for alignment, is also zero out to about the half of the maximum field diameter.
  • an example method 200 for performing a lithography services is provided.
  • procedures may be accomplished of placing a substrate on a stage 202, the stage configured to move in at least one direction, positioning a lens in a projection system over the stage 204, and projecting an image onto the substrate exposing a layer of photoresist on the substrate, wherein the patterned light beam projected from the projection system is generated by an array of micro light emitting diodes 206 or arrays of micro light emitting diodes.
  • a lithography apparatus comprising a substrate scanning system configured to scan a substrate, one or more arrays of micro light emitting diodes, which are imaged by an imaging system onto the substrate wherein hard wired logic is incorporated into the one or more arrays and are configured to shift a logic signal in one scan direction and configured to use the logic signal to turn an individual LED fully on or fully off.
  • the lithography apparatus is configured wherein the hard wired logic connected into the one or more arrays is configured to delay an application of the logic signal related to a grey scale of a particular pattern element.
  • the lithography apparatus is further configured with an arrangement configured to switch the hard wired logic configured to delay the arrival of the logic signal to the hard wired logic incorporated into the one or more arrays wherein the logic can be used when scanning in either a first or a second direction.
  • the lithography apparatus is further configured with an arrangement configured to alter the hard wired logic incorporated into the one or more arrays configured to shift the logic signal in one scan direction so that the logic signal is shifted to an opposite direction.
  • the lithography apparatus is further configured with flip-flop circuitry configured to store and transfer logic states from one diode to another and to delay an arrival of a logic signal.
  • the lithography apparatus is further configured with a system clock connected to each flip-flop wherein a clock frequency is directly related to the scan velocity.
  • the lithography apparatus is further configured with an array of immersion lenses in optical contact with each array of light emitting diodes.
  • the lithography apparatus is further configured with an array of immersion lenses in optical contact with each array of light emitting diodes.
  • the lithography apparatus is configured wherein each array of light emitting diodes is rectilinear with a uniform spacing between diodes and is oriented with each column of diodes aligned parallel with a scan direction.
  • the lithography apparatus is configured wherein a number of diodes in the scan direction is given by a formula of m(2 n -1) where m and n are integers and 2 n is a number of different grey levels that can be generated by a column.
  • the lithography apparatus is configured wherein a number of interconnected light emitting diodes in each row is represented by inclusive integer powers of two.
  • the lithography apparatus is further configured with a detector array located in a substrate focal plane and configured wherein an exposure dose generated by each group of 2 n light emitting diodes in each column of diodes in each array can be measured.
  • the lithography apparatus is further configured with an imaging system that contains a beam-splitter and a camera that views a pattern on the substrate created in a previous lithography step along with an alignment pattern projected from the emitting diode array and reflected from the substrate and a pattern recognition system that identifies a specific pattern on the substrate and the projected alignment pattern from the light emitting diode array and which measures their relative positions.
  • an imaging system that contains a beam-splitter and a camera that views a pattern on the substrate created in a previous lithography step along with an alignment pattern projected from the emitting diode array and reflected from the substrate and a pattern recognition system that identifies a specific pattern on the substrate and the projected alignment pattern from the light emitting diode array and which measures their relative positions.
  • the lithography apparatus is further configured with a fixed optical column containing the imaging system, a stage which is accurately metered and free to move in a scan and cross-scan direction, a chuck mounted on the stage, which can be used to rotate the attached substrate through a small angular range and an alignment position correction system which moves the stage on which the substrate is mounted into a position where the projected pattern will be aligned with the previous pattern contained on the substrate during scanning.
  • the lithography apparatus is further configured with a stage which is configured to move in a scan direction, a chuck mounted on the stage, which can be used to rotate the attached substrate through a small angular range and an alignment position correction system which moves the stage on which the substrate is mounted and a bridge on which the imaging system is mounted into a position where a projected pattern will be aligned with a previous pattern contained on the substrate during scanning.
  • a method to perform micro light emitting diode lithography comprising placing a substrate on to a stage configured to hold the substrate; aligning the substrate on the stage with a reference; illuminating the substrate on the stage with at least one array of micro light emitting diodes and removing the substrate from the stage.
  • the method may be performed wherein the illuminating the substrate is through a hard wired logic that is incorporated into the at least one array wherein the logic is configured to shift a logic signal in one scan direction and configured to use the logic signal to turn an individual LED fully on or fully off.

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  • Engineering & Computer Science (AREA)
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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
PCT/US2019/035059 2018-07-03 2019-05-31 Micro light emitting diode array lithography WO2020009763A1 (en)

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US62/693,789 2018-07-03

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WO2021048746A1 (zh) * 2019-09-10 2021-03-18 默司科技股份有限公司 智慧光罩及其曝光设备、曝光方法和曝光图案形成方法

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US20050128559A1 (en) * 2003-12-15 2005-06-16 Nishimura Ken A. Spatial light modulator and method for performing dynamic photolithography
US20100279231A1 (en) * 2009-04-30 2010-11-04 Infineon Technologies Ag Method and device for marking objects
US20130314683A1 (en) * 2010-12-13 2013-11-28 Yoji Watanabe Spatial light modulator, method of driving same, and exposure method and apparatus
WO2017114658A1 (en) * 2015-12-30 2017-07-06 Asml Netherlands B.V. Method and apparatus for direct write maskless lithography
WO2018015113A1 (en) * 2016-07-19 2018-01-25 Asml Netherlands B.V. Apparatus for direct write maskless lithography

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Publication number Priority date Publication date Assignee Title
US20050128559A1 (en) * 2003-12-15 2005-06-16 Nishimura Ken A. Spatial light modulator and method for performing dynamic photolithography
US20100279231A1 (en) * 2009-04-30 2010-11-04 Infineon Technologies Ag Method and device for marking objects
US20130314683A1 (en) * 2010-12-13 2013-11-28 Yoji Watanabe Spatial light modulator, method of driving same, and exposure method and apparatus
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WO2018015113A1 (en) * 2016-07-19 2018-01-25 Asml Netherlands B.V. Apparatus for direct write maskless lithography

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Publication number Priority date Publication date Assignee Title
WO2021048746A1 (zh) * 2019-09-10 2021-03-18 默司科技股份有限公司 智慧光罩及其曝光设备、曝光方法和曝光图案形成方法

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