WO2020006945A1 - 背沟道蚀刻型tft基板的制作方法及背沟道蚀刻型tft基板 - Google Patents

背沟道蚀刻型tft基板的制作方法及背沟道蚀刻型tft基板 Download PDF

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WO2020006945A1
WO2020006945A1 PCT/CN2018/113263 CN2018113263W WO2020006945A1 WO 2020006945 A1 WO2020006945 A1 WO 2020006945A1 CN 2018113263 W CN2018113263 W CN 2018113263W WO 2020006945 A1 WO2020006945 A1 WO 2020006945A1
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layer
passivation layer
back channel
passivation
tft substrate
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葛世民
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technology, and in particular, to a method for manufacturing a back channel etching type TFT substrate and a back channel etching type TFT substrate.
  • each pixel is driven by a thin film transistor (TFT) integrated behind it, so that high-speed, high-brightness, high-contrast screen display effects can be achieved.
  • TFT thin film transistor
  • a common TFT is usually composed of a gate / source / drain (Gate / Source / Drain) three electrode, an insulating layer and a semiconductor layer.
  • the gate electrode controls the working region (depletion region or accumulation region) of the semiconductor layer, and thus controls the switching of the TFT.
  • a channel is provided on the semiconductor layer, and for back channel etching (Back For a TFT with a Channel Ethced (BCE) structure, the channel includes a front conductive channel next to the Gate electrode and a back channel exposed to the outside.
  • BCE Channel Ethced
  • the Gate electrode when the Gate electrode is forward biased Voltage, close to the front conductive channel of the Gate electrode (the front conductive channel and the gate electrode are separated by an insulating layer), accumulate electrons, and the TFT is turned on. When the source / drain electrode increases the bias voltage, a current flows through the TFT .
  • thin film transistors are mainly divided into amorphous silicon (a-Si) thin film transistors and low temperature polysilicon (Low Temperature Poly-silicon (LTPS) thin film transistor and oxide semiconductor (Oxide semiconductor) thin film transistor
  • oxide semiconductor thin film transistor Oxide TFT
  • a-Si amorphous silicon
  • LTPS Low Temperature Poly-silicon
  • Oxide semiconductor oxide semiconductor thin film transistor
  • oxide semiconductor thin film transistor Oxide TFT
  • the active layer of its channel position is not protected, which is easy to be processed during the process. The loss of semiconductor characteristics leads to failure of the switching characteristics of the oxide semiconductor thin film transistor.
  • the nature of the TFT back channel interface also has a crucial impact on the output electrical characteristics of the TFT.
  • the back channel is damaged during the process of opening the channel, and the damaged back channel is exposed to the air, which is more likely to cause water / oxygen adsorption. Defects are generated in the back channel, which causes degradation of the TFT characteristic curve during stability testing and improvement of leakage current, and reduces device stability.
  • ESL Etch Stop Layer
  • This structure can effectively reduce the influence of external environmental factors and etching damage of source and drain electrodes on the back channel.
  • the array fabrication method of the ESL structure requires more photomask times, and significantly increases the size and parasitic capacitance of the TFT device.
  • the back-channel etch-type TFT does not need an etching barrier layer, and the channel can be significantly reduced compared to the ESL structure, so it has lower production costs and technical advantages than the ESL structure.
  • a conventional BCE TFT substrate structure uses a silicon oxide (SIOx) inorganic insulating cover layer 200 to cover and protect the back channel of the active layer 100.
  • SIOx silicon oxide
  • a single layer of silicon oxide cannot provide water isolation.
  • the effect of oxygen on TFT devices is still poor.
  • FIG. 2 there is another BCE type TFT substrate structure.
  • the inorganic insulating cover layer 200 adopts a double-layer film structure of a silicon oxide layer and a silicon nitride (SiNx) layer stack.
  • SiNx silicon nitride
  • the purpose of the present invention is to provide a method for manufacturing a back channel etching type TFT substrate, which uses two silicon oxide layers to cover and protect the active layer back channel, which can improve the resistance of the back channel etching type oxide TFT to moisture. Improve the electrical properties of TFT, and at the same time achieve the purpose of simplifying the process.
  • the object of the present invention is also to provide a back channel etching type TFT substrate, which uses two silicon oxide layers to cover and protect the active layer back channel, which can increase the resistance of the back channel etching type oxide TFT to moisture and enhance the TFT. Electrical properties, and at the same time achieve the purpose of simplifying the process.
  • the present invention provides a method for manufacturing a back channel etching type TFT substrate, including the following steps:
  • Step S1 providing a base substrate, forming a gate on the base substrate, forming a gate insulating layer on the gate and the base substrate, and forming a gate insulating layer corresponding to the gate on the gate insulating layer.
  • An active layer above the electrode, a source and a drain are formed on the active layer and the gate insulating layer, and the source and the drain are in contact with two sides of the active layer respectively;
  • Step S2 depositing a first passivation layer on the source, drain, active layer, and gate insulating layer, and depositing a second passivation layer on the first passivation layer, wherein the The first passivation layer and the second passivation layer are both silicon oxide layers.
  • the deposition temperature of the first passivation layer is lower than that of the second passivation layer, and the oxygen content of the second passivation layer is greater than that of the second passivation layer.
  • the oxygen content of the first passivation layer wherein a thickness of the first passivation layer is greater than a thickness of the second passivation layer;
  • Step S3 The surface of the second passivation layer is treated by using a nitrogen-containing plasma, wherein a wetting angle on the surface of the second passivation layer is greater than 60 °.
  • the material of the active layer is a metal oxide semiconductor.
  • the material of the active layer is indium gallium zinc oxide.
  • the invention also provides a method for manufacturing a back channel etching type TFT substrate, which includes the following steps:
  • Step S1 providing a base substrate, forming a gate on the base substrate, forming a gate insulating layer on the gate and the base substrate, and forming a gate insulating layer corresponding to the gate on the gate insulating layer.
  • An active layer above the electrode, a source and a drain are formed on the active layer and the gate insulating layer, and the source and the drain are in contact with two sides of the active layer respectively;
  • Step S2 depositing a first passivation layer on the source, drain, active layer, and gate insulating layer, and depositing a second passivation layer on the first passivation layer, wherein the The first passivation layer and the second passivation layer are both silicon oxide layers.
  • the deposition temperature of the first passivation layer is lower than that of the second passivation layer, and the oxygen content of the second passivation layer is greater than that of the second passivation layer.
  • the oxygen content of the first passivation layer is
  • Step S3 The surface of the second passivation layer is processed by using a nitrogen-containing plasma.
  • the material of the active layer is a metal oxide semiconductor.
  • the material of the active layer is indium gallium zinc oxide.
  • the wetting angle on the surface of the second passivation layer is greater than 60 °.
  • the thickness of the first passivation layer is greater than the thickness of the second passivation layer.
  • the invention also provides a back channel etching type TFT substrate, which comprises a base substrate, a gate provided on the base substrate, a gate insulating layer provided on the gate and the base substrate, and The gate insulating layer corresponds to an active layer above the gate, and a source electrode provided on the active layer and the gate insulating layer and in contact with both sides of the active layer, respectively.
  • the first passivation layer and the second passivation layer are both silicon oxide layers formed by deposition, and the oxygen content of the second passivation layer is greater than the oxygen content of the first passivation layer;
  • the second passivation layer includes a nitrogen-containing substance.
  • the material of the active layer is a metal oxide semiconductor.
  • the material of the active layer is indium gallium zinc oxide.
  • the wetting angle on the surface of the second passivation layer is greater than 60 °.
  • the thickness of the first passivation layer is greater than the thickness of the second passivation layer.
  • a first passivation layer and a second passivation layer are respectively formed by depositing a silicon oxide layer twice, wherein The first passivation layer in contact with the channel uses a lower temperature deposition parameter, and the second passivation layer remote from the back channel uses a higher temperature deposition parameter, and the oxygen content in the second passivation layer is higher than that of the first passivation layer.
  • the surface of the second passivation layer is treated with a nitrogen-containing plasma, so that the wetting angle on the surface of the second passivation layer is 60 ° or more, compared with
  • the prior art scheme of using a single-layer silicon oxide layer to cover and protect the back channel can improve the resistance of the back-channel etching oxide TFT to water vapor and improve the electrical properties of the TFT.
  • Another prior art solution for the combination of silicon layers to cover and protect the back channel, without the use of a silicon nitride layer can avoid the problem of deposition machine switching of silicon oxide and silicon nitride and the problem of etching selection ratio, simplifying the production Craft.
  • the back-channel etching type TFT substrate provided by the present invention uses two silicon oxide layers to cover and protect the back layer of the active layer, which can improve the resistance of the back-channel etching type TFT to water vapor and improve the electrical properties of the TFT. To achieve the purpose of simplifying the process.
  • FIG. 1 is a schematic structural diagram of a conventional back channel etching type TFT substrate
  • FIG. 2 is a schematic structural diagram of another conventional back channel etching type TFT substrate
  • FIG. 3 is a schematic flowchart of a method for manufacturing a back channel etching type TFT substrate according to the present invention
  • step S1 is a schematic diagram of step S1 of a method for manufacturing a back channel etching type TFT substrate according to the present invention
  • FIG. 5 is a schematic diagram of step S2 of the method for manufacturing a back channel etching type TFT substrate according to the present invention.
  • step S3 is a schematic diagram of step S3 of a method for manufacturing a back channel etching type TFT substrate according to the present invention
  • FIG. 7 is a schematic structural diagram of a back channel etching type TFT substrate according to the present invention.
  • the present invention first provides a method for manufacturing a back channel etching type TFT substrate, which includes the following steps:
  • Step S1 as shown in FIG. 4, a base substrate 10 is provided, a gate electrode 11 is formed on the base substrate 10, a gate insulating layer 12 is formed on the gate electrode 11 and the base substrate 10, and An active layer 20 corresponding to the gate 11 is formed on the gate insulating layer 12, and a source 31 and a drain 32 are formed on the active layer 20 and the gate insulating layer 12.
  • the source 31 The drain electrode 32 is in contact with both sides of the active layer 20.
  • a material of the active layer 20 is a metal oxide semiconductor.
  • a material of the active layer 20 is indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO).
  • the active layer 20 includes source and drain contact regions at both ends and a channel region in the middle, and the source 31 and the drain 32 are respectively in contact with the source and drain contact regions of the active layer 20. Contact, the surface of the channel region is the back channel.
  • Step S2 as shown in FIG. 5, a first passivation layer 41 is deposited on the source 31, the drain 32, the active layer 20 and the gate insulating layer 12, and on the first passivation layer 41
  • a second passivation layer 42 is formed by deposition, wherein the first passivation layer 41 and the second passivation layer 42 are both silicon oxide layers, and the deposition temperature of the first passivation layer 41 is lower than that of the second passivation layer At a deposition temperature of 42, the oxygen content of the second passivation layer 42 is greater than the oxygen content of the first passivation layer 41.
  • the thickness of the first passivation layer 41 is greater than the thickness of the second passivation layer 42.
  • the thickness of the first passivation layer 41 is 100-250 nm.
  • the thickness of the second passivation layer 42 is 50-150 nm.
  • Step S3 As shown in FIG. 6, immediately after the second passivation layer 42 is formed by deposition, the surface of the second passivation layer 42 is treated with a nitrogen-containing plasma.
  • the wetting angle on the surface of the second passivation layer 42 is greater than 60 °.
  • the step S3 using ammonia (NH 3) and nitrogen (N 2) as the reaction gas is enhanced plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD ) a nitrogen-containing plasma is formed within the device pairs A surface of the second passivation layer 42 is processed,
  • NH 3 ammonia
  • N 2 nitrogen
  • PECVD enhanced plasma chemical vapor deposition
  • a first passivation layer 41 and a second passivation layer 42 are respectively formed by depositing a silicon oxide layer twice, wherein the first passivation layer in contact with the back channel of the active layer 20
  • the passivation layer 41 uses a lower temperature (LT) deposition parameter
  • the second passivation layer 42 farther from the back channel uses a higher temperature (HT) deposition parameter
  • the oxygen content in the second passivation layer 42 is higher than
  • the first passivation layer 41 is treated with a nitrogen-containing plasma immediately after the second passivation layer 42 is formed to form a second passivation layer 42 so that the wetting angle of the surface of the second passivation layer 42 is at Above 60 °, compared with the prior art schemes in which a single silicon oxide layer is used to cover and protect the back channel, the effect of the back channel etching type oxide TFT on resisting water vapor can be improved, and the electrical properties of the TFT can be improved.
  • Another prior art solution that uses a combination of a silicon oxide layer and a silicon nitride layer to cover and protect the back channel, without using a silicon nitride layer, can avoid the problem of deposition machine switching and etching selection of silicon oxide and silicon nitride This problem simplifies the manufacturing process.
  • the present invention also provides a back channel etching type TFT substrate, which includes a base substrate 10 and a gate provided on the base substrate 10.
  • the first passivation layer 41 and the second passivation layer 42 are both silicon oxide layers formed by deposition.
  • the deposition temperature of the first passivation layer 41 is lower than the deposition temperature of the second passivation layer 42.
  • the oxygen content of the second passivation layer 42 is greater than the oxygen content of the first passivation layer 41;
  • a surface of the second passivation layer 42 is treated with a nitrogen-containing plasma, and the second passivation layer 42 includes a nitrogen-containing substance.
  • the wetting angle on the surface of the second passivation layer 42 is greater than 60 °.
  • a material of the active layer 20 is a metal oxide semiconductor.
  • a material of the active layer 20 is indium gallium zinc oxide.
  • the active layer 20 includes source and drain contact regions at both ends and a channel region in the middle, and the source 31 and the drain 32 are respectively in contact with the source and drain contact regions of the active layer 20. Contact, the surface of the channel region is the back channel.
  • the thickness of the first passivation layer 41 is greater than the thickness of the second passivation layer 42.
  • the thickness of the first passivation layer 41 is 100-250 nm.
  • the thickness of the second passivation layer 42 is 50-150 nm.
  • the back channel etching type TFT substrate of the present invention two silicon oxide layers formed by deposition are used as the first passivation layer 41 and the second passivation layer 42 to cover the back channel of the active layer 20, wherein the first The deposition temperature of a passivation layer 41 is lower than the deposition temperature of the second passivation layer 42.
  • the oxygen content of the second passivation layer 42 is greater than the oxygen content of the first passivation layer 41.
  • the surface of the layer 42 is treated with a nitrogen-containing plasma, so that the wetting angle on the surface of the second passivation layer 42 is above 60 °, which can improve the resistance of the back channel etching oxide TFT to water vapor, and improve the electrical properties of the TFT. The purpose of simplifying the process.
  • a first passivation layer and a second passivation layer are respectively formed by depositing a silicon oxide layer twice, wherein the back passivation layer and the active layer are back trenched.
  • the first passivation layer in contact with the channel uses a lower temperature deposition parameter
  • the second passivation layer remote from the back channel uses a higher temperature deposition parameter
  • the oxygen content in the second passivation layer is higher than the first passivation layer.
  • the prior art solution of single-layer silicon oxide layer covering and protecting the back channel can improve the resistance of the back-channel etching type oxide TFT to resist moisture and improve the electrical properties of the TFT.
  • the combination of layers is another prior art solution for covering and protecting the back channel without using a silicon nitride layer, which can avoid the problem of deposition machine switching of silicon oxide and silicon nitride and the problem of etching selection ratio, and simplifies the manufacturing process.
  • the back-channel etching type TFT substrate provided by the present invention uses two silicon oxide layers to cover and protect the back layer of the active layer, which can improve the resistance of the back-channel etching type TFT to water vapor and improve the electrical properties of the TFT. To achieve the purpose of simplifying the process.

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Abstract

一种背沟道蚀刻型TFT基板的制作方法及背沟道蚀刻型TFT基板，该背沟道蚀刻型TFT基板的制作方法采用两层的氧化硅层对有源层（20）背沟道进行覆盖保护，先低温沉积形成氧化硅的第一钝化层（41），再高温沉积形成氧化硅的第二钝化层（42），然后采用含氮等离子体对第二钝化层（42）表面进行处理，使第二钝化层（42）表面的湿润角在60°以上，相比于采用单层氧化硅层对背沟道进行覆盖保护的现有技术方案，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，相比于采用氧化硅层与氮化硅层的组合对背沟道进行覆盖保护的另一现有技术方案，无需使用氮化硅层，可以避免氧化硅和氮化硅的沉积机台切换问题以及蚀刻选择比的问题，简化了制作工艺。

Description

背沟道蚀刻型TFT基板的制作方法及背沟道蚀刻型TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种背沟道蚀刻型TFT基板的制作方法及背沟道蚀刻型TFT基板。
 背景技术
在有源矩阵显示技术中，每一个像素点都由集成在其后的薄膜晶体管（Thin Film Transistor，TFT）进行驱动，从而可以实现高速度、高亮度、高对比度的屏幕显示效果。常见的TFT通常由栅极/源极/漏极（Gate/Source/Drain）三电极、绝缘层以及半导体层构成。Gate电极控制着半导体层的工作区域（耗尽区或积累区），从而控制着TFT的开关。所述半导体层上设有沟道，对于背沟道刻蚀（Back Channel Ethced，BCE）结构的TFT来说，所述沟道包括紧贴Gate电极的前导电沟道以及暴露于外界的背沟道，对于N型掺杂半导体层来说，当Gate电极加正偏压，紧贴Gate电极的前导电沟道（前导电沟道和栅电极被绝缘层隔开）产生电子的积累，TFT处于打开状态，当Source/Drain电极增加偏压时，TFT中有电流通过。
现有技术中薄膜晶体管根据有源层的材料主要分为非晶硅（a-Si）薄膜晶体管、低温多晶硅（Low Temperature Poly-silicon，LTPS）薄膜晶体管以及氧化物半导体（Oxide semiconductor）薄膜晶体管，氧化物半导体薄膜晶体管（Oxide TFT）由于具有较高的电子迁移率，而且相比低温多晶硅薄膜晶体管，氧化物半导体薄膜晶体管制程简单，与非晶硅薄膜晶体管制程相容性较高，而得到了广泛应用。低电阻接触条件下，氧化物半导体的高迁移率会被高接触电阻所掩蔽，另外，当氧化物薄膜晶体管采用BCE结构时，其沟道位置的有源层没有得到保护，容易在制程过程中失去半导体特性，进而导致氧化物半导体薄膜晶体管的开关特性失效。
虽然从空间位置上来说，TFT背沟道离前导电沟道的距离比较远，但是TFT背沟道界面的性质对TFT输出电性曲线也有至关重要的影响。对于背沟道刻蚀结构的TFT来说，在将沟道刻开的过程中会对背沟道造成损伤，并且，损伤的背沟道暴露于空气中，更容易引起由于水/氧的吸附而在背沟道中产生缺陷，造成TFT特性曲线在稳定性测试过程中的退化以及漏电的提升，器件稳定性降低。为了提高TFT的稳定性，刻蚀阻挡层（Etch Stop Layer，ESL）结构的TFT被广泛采用，该结构可有效降低外界环境因素与源漏电极的刻蚀损伤对背沟道的影响。然而，ESL结构的阵列制造方法需要更多的光罩次数，且显著增加了TFT 器件的尺寸和寄生电容。而背沟道蚀刻型结构的TFT无需蚀刻阻挡层，沟道较ESL结构可显著缩小，因而具有相对ESL结构更低的生产成本和技术优势。
如图1所示，现有一种BCE型TFT基板结构采用氧化硅（SIOx）的无机绝缘覆盖层200将有源层100的背沟道覆盖保护起来，然而单层的氧化硅无法起到隔绝水氧的作用，TFT器件特性仍较差。如图2所示，现有另一种BCE型TFT基板结构，无机绝缘覆盖层200采用氧化硅层和氮化硅（SiNx）层堆栈的双层膜结构，然而该种结构存在氧化硅和氮化硅沉积机台切换问题以及蚀刻选择比的问题。
 技术问题
本发明的目的在于提供一种背沟道蚀刻型TFT基板的制作方法，使用两层氧化硅层覆盖保护有源层背沟道，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，并同时达到简化工艺的目的。
本发明的目的还在于提供一种背沟道蚀刻型TFT基板，使用两层氧化硅层覆盖保护有源层背沟道，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，并同时达到简化工艺的目的。
 技术解决方案
为实现上述目的，本发明提供一种背沟道蚀刻型TFT基板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成栅极，在所述栅极与衬底基板上形成栅极绝缘层，在所述栅极绝缘层上形成对应于所述栅极上方的有源层，在所述有源层与栅极绝缘层上形成源极与漏极，所述源极与漏极分别与所述有源层的两侧相接触；
步骤S2、在所述源极、漏极、有源层及栅极绝缘层上沉积形成第一钝化层，在所述第一钝化层上沉积形成第二钝化层，其中，所述第一钝化层和第二钝化层均为氧化硅层，所述第一钝化层的沉积温度低于第二钝化层的沉积温度，所述第二钝化层的氧含量大于所述第一钝化层的氧含量，其中所述第一钝化层的厚度大于第二钝化层的厚度；以及；
步骤S3、采用含氮等离子体对所述第二钝化层表面进行处理，其中所述第二钝化层表面的湿润角大于60°。
所述有源层的材料为金属氧化物半导体。
所述有源层的材料为铟镓锌氧化物。
本发明还提供一种背沟道蚀刻型TFT基板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成栅极，在所述栅极与衬底基板上形成栅极绝缘层，在所述栅极绝缘层上形成对应于所述栅极上方的有源层，在所述有源层与栅极绝缘层上形成源极与漏极，所述源极与漏极分别与所述有源层的两侧相接触；
步骤S2、在所述源极、漏极、有源层及栅极绝缘层上沉积形成第一钝化层，在所述第一钝化层上沉积形成第二钝化层，其中，所述第一钝化层和第二钝化层均为氧化硅层，所述第一钝化层的沉积温度低于第二钝化层的沉积温度，所述第二钝化层的氧含量大于所述第一钝化层的氧含量；以及
步骤S3、采用含氮等离子体对所述第二钝化层表面进行处理。
所述有源层的材料为金属氧化物半导体。
所述有源层的材料为铟镓锌氧化物。
所述第二钝化层表面的湿润角大于60°。
所述第一钝化层的厚度大于第二钝化层的厚度。
本发明还提供一种背沟道蚀刻型TFT基板，包括衬底基板、设于所述衬底基板上的栅极、设于所述栅极与衬底基板上的栅极绝缘层、设于所述栅极绝缘层上且对应于所述栅极上方的有源层、设于所述有源层与栅极绝缘层上且分别与所述有源层的两侧相接触的源极与漏极、设于所述源极、漏极、有源层及栅极绝缘层上的第一钝化层以及设于所述第一钝化层上的第二钝化层，
其中所述第一钝化层和第二钝化层均为沉积形成的氧化硅层，所述第二钝化层的氧含量大于所述第一钝化层的氧含量；且
其中所述第二钝化层包括含氮物质。
所述有源层的材料为金属氧化物半导体。
所述有源层的材料为铟镓锌氧化物。
所述第二钝化层表面的湿润角大于60°。
所述第一钝化层的厚度大于第二钝化层的厚度。
 有益效果
本发明的有益效果：本发明提供的一种背沟道蚀刻型TFT基板的制作方法，通过两次沉积氧化硅层分别形成第一钝化层和第二钝化层，其中与有源层背沟道接触的第一钝化层选用较低温的沉积参数，与背沟道较远的第二钝化层选用较高温的沉积参数，且第二钝化层中的氧含量高于第一钝化层，并在沉积形成第二钝化层后采用含氮等离子体对所述第二钝化层表面进行处理，使所述第二钝化层表面的湿润角在60°以上，相比于采用单层氧化硅层对背沟道进行覆盖保护的现有技术方案，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，相比于采用氧化硅层与氮化硅层的组合对背沟道进行覆盖保护的另一现有技术方案，无需使用氮化硅层，可以避免氧化硅和氮化硅的沉积机台切换问题以及蚀刻选择比的问题，简化了制作工艺。本发明提供的背沟道蚀刻型TFT基板，使用两层氧化硅层覆盖保护有源层背沟道，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，并同时达到简化工艺的目的。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有一种背沟道蚀刻型TFT基板的结构示意图；
图2为现有另一种背沟道蚀刻型TFT基板的结构示意图；
图3本发明背沟道蚀刻型TFT基板的制作方法的流程示意图；
图4为本发明背沟道蚀刻型TFT基板的制作方法的步骤S1的示意图；
图5为本发明背沟道蚀刻型TFT基板的制作方法的步骤S2的示意图；
图6为本发明背沟道蚀刻型TFT基板的制作方法的步骤S3的示意图；
图7为本发明背沟道蚀刻型TFT基板的结构示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明首先提供一种背沟道蚀刻型TFT基板的制作方法，包括以下步骤：
步骤S1、如图4所示，提供一衬底基板10，在所述衬底基板10上形成栅极11，在所述栅极11与衬底基板10上形成栅极绝缘层12，在所述栅极绝缘层12上形成对应于所述栅极11上方的有源层20，在所述有源层20与栅极绝缘层12上形成源极31与漏极32，所述源极31与漏极32分别与所述有源层20的两侧相接触。
具体地，所述有源层20的材料为金属氧化物半导体。
优选地，所述有源层20的材料为铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）。
具体地，所述有源层20包括位于两端的源漏极接触区及位于中间的沟道区，所述源极31与漏极32分别与所述有源层20的源漏极接触区相接触，所述沟道区的表面即为背沟道。
步骤S2、如图5所示，在所述源极31、漏极32、有源层20及栅极绝缘层12上沉积形成第一钝化层41，在所述第一钝化层41上沉积形成第二钝化层42，其中，所述第一钝化层41和第二钝化层42均为氧化硅层，所述第一钝化层41的沉积温度低于第二钝化层42的沉积温度，所述第二钝化层42的氧含量大于所述第一钝化层41的氧含量。
具体地，所述第一钝化层41的厚度大于第二钝化层42的厚度。
具体地，所述第一钝化层41的厚度为100-250nm。
具体地，所述第二钝化层42的厚度为50-150nm。
步骤S3、如图6所示，在沉积形成第二钝化层42之后，立即采用含氮等离子体对所述第二钝化层42表面进行处理。
具体地，所述第二钝化层42表面经过含氮等离子体处理后，该第二钝化层42表面的湿润角大于60°。
具体地，所述步骤S3中采用氨气（NH 3）和氮气（N 2）作为反应气体在等离子体增强化学的气相沉积（Plasma Enhanced Chemical Vapor Deposition ，PECVD）设备内形成含氮的等离子对对所述第二钝化层42表面进行处理，
本发明的背沟道蚀刻型TFT基板的制作方法，通过两次沉积氧化硅层分别形成第一钝化层41和第二钝化层42，其中与有源层20背沟道接触的第一钝化层41选用较低温（LT）的沉积参数，与背沟道较远的第二钝化层42选用较高温（HT）的沉积参数，且第二钝化层42中的氧含量高于第一钝化层41，在沉积形成第二钝化层42后立即采用含氮等离子体对所述第二钝化层42表面进行处理，使所述第二钝化层42表面的湿润角在60°以上，相比于采用单层氧化硅层对背沟道进行覆盖保护的现有技术方案，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，相比于采用氧化硅层与氮化硅层的组合对背沟道进行覆盖保护的另一现有技术方案，无需使用氮化硅层，可以避免氧化硅和氮化硅的沉积机台切换问题以及蚀刻选择比的问题，简化了制作工艺。
请参阅图7，基于上述的背沟道蚀刻型TFT基板的制作方法，本发明还提供一种背沟道蚀刻型TFT基板，包括衬底基板10、设于所述衬底基板10上的栅极11、设于所述栅极11与衬底基板10上的栅极绝缘层12、设于所述栅极绝缘层12上且对应于所述栅极11上方的有源层20、设于所述有源层20与栅极绝缘层12上且分别与所述有源层20的两侧相接触的源极31与漏极32、设于所述源极31、漏极32、有源层20及栅极绝缘层12上的第一钝化层41以及设于所述第一钝化层41上的第二钝化层42；
所述第一钝化层41和第二钝化层42均为沉积形成的氧化硅层，所述第一钝化层41的沉积温度低于第二钝化层42的沉积温度，所述第二钝化层42的氧含量大于所述第一钝化层41的氧含量；
所述第二钝化层42表面经过含氮等离子体处理，所述第二钝化层42包括含氮物质。
具体地，所述第二钝化层42表面经过含氮等离子体处理后，该第二钝化层42表面的湿润角大于60°。
具体地，所述有源层20的材料为金属氧化物半导体。
优选地，所述有源层20的材料为铟镓锌氧化物。
具体地，所述有源层20包括位于两端的源漏极接触区及位于中间的沟道区，所述源极31与漏极32分别与所述有源层20的源漏极接触区相接触，所述沟道区的表面即为背沟道。
具体地，所述第一钝化层41的厚度大于第二钝化层42的厚度。
具体地，所述第一钝化层41的厚度为100-250nm。
具体地，所述第二钝化层42的厚度为50-150nm。
本发明的背沟道蚀刻型TFT基板，使用沉积形成的两层氧化硅层分别作为第一钝化层41和第二钝化层42覆盖保护有源层20的背沟道，其中所述第一钝化层41的沉积温度低于第二钝化层42的沉积温度，所述第二钝化层42的氧含量大于所述第一钝化层41的氧含量，所述第二钝化层42表面经过含氮等离子体处理，使得第二钝化层42表面的湿润角在60°以上，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，并同时达到简化工艺的目的。
综上所述，本发明提供的一种背沟道蚀刻型TFT基板的制作方法，通过两次沉积氧化硅层分别形成第一钝化层和第二钝化层，其中与有源层背沟道接触的第一钝化层选用较低温的沉积参数，与背沟道较远的第二钝化层选用较高温的沉积参数，且第二钝化层中的氧含量高于第一钝化层，并在沉积形成第二钝化层后采用含氮等离子体对所述第二钝化层表面进行处理，使所述第二钝化层表面的湿润角在60°以上，相比于采用单层氧化硅层对背沟道进行覆盖保护的现有技术方案，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，相比于采用氧化硅层与氮化硅层的组合对背沟道进行覆盖保护的另一现有技术方案，无需使用氮化硅层，可以避免氧化硅和氮化硅的沉积机台切换问题以及蚀刻选择比的问题，简化了制作工艺。本发明提供的背沟道蚀刻型TFT基板，使用两层氧化硅层覆盖保护有源层背沟道，可提升背沟道蚀刻型氧化物TFT阻抗水气的作用，提升TFT电性，并同时达到简化工艺的目的。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种背沟道蚀刻型TFT基板的制作方法，包括以下步骤：
    步骤S1、提供一衬底基板（10），在所述衬底基板（10）上形成栅极（11），在所述栅极（11）与衬底基板（10）上形成栅极绝缘层（12），在所述栅极绝缘层（12）上形成对应于所述栅极（11）上方的有源层（20），在所述有源层（20）与栅极绝缘层（12）上形成源极（31）与漏极（32），所述源极（31）与漏极（32）分别与所述有源层（20）的两侧相接触；
    步骤S2、在所述源极（31）、漏极（32）、有源层（20）及栅极绝缘层（12）上沉积形成第一钝化层（41），在所述第一钝化层（41）上沉积形成第二钝化层（42），其中，所述第一钝化层（41）和第二钝化层（42）均为氧化硅层，所述第一钝化层（41）的沉积温度低于第二钝化层（42）的沉积温度，所述第二钝化层（42）的氧含量大于所述第一钝化层（41）的氧含量，其中所述第一钝化层（41）的厚度大于第二钝化层（42）的厚度；以及
    步骤S3、采用含氮等离子体对所述第二钝化层（42）表面进行处理，其中所述第二钝化层（42）表面的湿润角大于60°。
  2. 如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其中所述有源层（20）的材料为金属氧化物半导体。
  3. 如权利要求2所述的背沟道蚀刻型TFT基板的制作方法，其中所述有源层（20）的材料为铟镓锌氧化物。
  4. 一种背沟道蚀刻型TFT基板的制作方法，包括以下步骤：
    步骤S1、提供一衬底基板（10），在所述衬底基板（10）上形成栅极（11），在所述栅极（11）与衬底基板（10）上形成栅极绝缘层（12），在所述栅极绝缘层（12）上形成对应于所述栅极（11）上方的有源层（20），在所述有源层（20）与栅极绝缘层（12）上形成源极（31）与漏极（32），所述源极（31）与漏极（32）分别与所述有源层（20）的两侧相接触；
    步骤S2、在所述源极（31）、漏极（32）、有源层（20）及栅极绝缘层（12）上沉积形成第一钝化层（41），在所述第一钝化层（41）上沉积形成第二钝化层（42），其中，所述第一钝化层（41）和第二钝化层（42）均为氧化硅层，所述第一钝化层（41）的沉积温度低于第二钝化层（42）的沉积温度，所述第二钝化层（42）的氧含量大于所述第一钝化层（41）的氧含量；以及
    步骤S3、采用含氮等离子体对所述第二钝化层（42）表面进行处理。
  5. 如权利要求4所述的背沟道蚀刻型TFT基板的制作方法，其中所述有源层（20）的材料为金属氧化物半导体。
  6. 如权利要求5所述的背沟道蚀刻型TFT基板的制作方法，其中所述有源层（20）的材料为铟镓锌氧化物。
  7. 如权利要求4所述的背沟道蚀刻型TFT基板的制作方法，其中所述第二钝化层（42）表面的湿润角大于60°。
  8. 如权利要求4所述的背沟道蚀刻型TFT基板的制作方法，其中所述第一钝化层（41）的厚度大于第二钝化层（42）的厚度。
  9. 一种背沟道蚀刻型TFT基板，包括：衬底基板（10）、设于所述衬底基板（10）上的栅极（11）、设于所述栅极（11）与衬底基板（10）上的栅极绝缘层（12）、设于所述栅极绝缘层（12）上且对应于所述栅极（11）上方的有源层（20）、设于所述有源层（20）与栅极绝缘层（12）上且分别与所述有源层（20）的两侧相接触的源极（31）与漏极（32）、设于所述源极（31）、漏极（32）、有源层（20）及栅极绝缘层（12）上的第一钝化层（41）以及设于所述第一钝化层（41）上的第二钝化层（42），
    其中所述第一钝化层（41）和第二钝化层（42）均为沉积形成的氧化硅层，所述第二钝化层（42）的氧含量大于所述第一钝化层（41）的氧含量；且
    其中所述第二钝化层（42）包括含氮物质。
  10. 如权利要求9所述的背沟道蚀刻型TFT基板，其中所述有源层（20）的材料为金属氧化物半导体。
  11. 如权利要求10所述的背沟道蚀刻型TFT基板，其中所述有源层（20）的材料为铟镓锌氧化物。
  12. 如权利要求9所述的背沟道蚀刻型TFT基板，其中所述第二钝化层（42）表面的湿润角大于60°。
  13. 如权利要求9所述的背沟道蚀刻型TFT基板，其中所述第一钝化层（41）的厚度大于第二钝化层（42）的厚度。
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