WO2020006858A1 - 一种薄膜晶体管及其制作方法 - Google Patents

一种薄膜晶体管及其制作方法 Download PDF

Info

Publication number
WO2020006858A1
WO2020006858A1 PCT/CN2018/104532 CN2018104532W WO2020006858A1 WO 2020006858 A1 WO2020006858 A1 WO 2020006858A1 CN 2018104532 W CN2018104532 W CN 2018104532W WO 2020006858 A1 WO2020006858 A1 WO 2020006858A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
source
drain
thin film
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/104532
Other languages
English (en)
French (fr)
Inventor
谢华飞
陈书志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/094,479 priority Critical patent/US11316049B2/en
Publication of WO2020006858A1 publication Critical patent/WO2020006858A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6725—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having supplementary regions or layers for improving the flatness of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the invention relates to the field of display technology, in particular to a thin film transistor and a manufacturing method thereof.
  • the existing thin film transistor structure includes a substrate, a first metal layer (forming a gate), an insulating layer, an active layer, a second metal layer (forming a source and drain), and the like. That is, in the existing thin film transistor, the second metal layer is deposited only after the active layer is prepared.
  • the material of the active layer is usually a new type of semiconductor material including graphene, carbon nanotubes, silicon carbide, molybdenum disulfide, and organic compounds.
  • the second metal layer is usually deposited by a physical vapor deposition process
  • the physical vapor deposition process will cause damage to new semiconductor materials, and because the new semiconductor materials have limited adhesion to metal and glass substrates, they are being prepared.
  • the transistor of the new semiconductor material reduces the performance of the thin film transistor.
  • An object of the present invention is to provide a thin film transistor and a manufacturing method thereof, which can improve the performance of the thin film transistor.
  • the present invention provides a method for manufacturing a thin film transistor, which includes:
  • the first portion is located between the source and the drain, the second portion is located on a side of the source, and the third portion is located on a side of the drain.
  • the first portion, The upper surfaces of the second portion and the third portion are both flush with the tops of the source and the drain to expose a portion of the source and the drain to the outside;
  • the material is a photosensitive insulating resin material;
  • a passivation layer is formed on the channel, the second portion, and the third portion.
  • the step of forming a flat layer on the source electrode, the drain electrode, and the gate insulating layer includes:
  • a curing process is performed on the material of the flat layer to form a flat layer.
  • the method further includes:
  • the channel is located on the first part, the source electrode, and the drain electrode.
  • a material of the active layer includes at least one of graphene, silicon carbide, molybdenum disulfide, organic semiconductor, and carbon nanotubes.
  • a material of the passivation layer includes at least one of an organic insulating material, SiN x , SiO 2 , HfO 2, and Al 2 O 3 .
  • the invention provides a method for manufacturing a thin film transistor, which includes:
  • first portion Located between the source and the drain, the second portion is located on one side of the source, and the third portion is located on one side of the drain, the first portion, the second portion Both the upper surface of the portion and the third portion are flush with the top of the source and the drain, so as to expose a portion of the source and the drain to the outside;
  • a passivation layer is formed on the channel, the second portion, and the third portion.
  • a material of the flat layer is a photosensitive insulating resin material.
  • the step of patterning the flat layer to form a first part, a second part, and a third part includes:
  • the flat layer is etched by a plasma processing method to form a first portion, a second portion, and a third portion.
  • the step of forming a flat layer on the source electrode, the drain electrode, and the gate insulating layer includes:
  • a curing process is performed on the material of the flat layer to form a flat layer.
  • the method further includes:
  • the channel is located on the first part, the source electrode, and the drain electrode.
  • a material of the active layer includes at least one of graphene, silicon carbide, molybdenum disulfide, organic semiconductor, and carbon nanotubes.
  • a material of the passivation layer includes at least one of an organic insulating material, SiN x , SiO 2 , HfO 2, and Al 2 O 3 .
  • the invention also provides a thin film transistor, which includes:
  • a gate provided on the substrate
  • a gate insulating layer provided on the gate and the substrate;
  • a flat layer provided on the source, drain, and gate insulating layers including a first portion disposed between the source and the drain, and a second portion disposed on a side of the source A portion and a third portion disposed on one side of the drain; the upper surfaces of the first portion, the second portion, and the third portion are flush with the top of the source and the drain, To expose a part of the source electrode and the drain electrode to the outside;
  • An active layer provided on the flat layer and the source and drain electrodes, the active layer being used to form a channel;
  • a passivation layer is provided on the channel, the second portion, and the third portion.
  • a material of the flat layer is a photosensitive insulating resin material.
  • a via hole is provided on the passivation layer, and the via hole penetrates the passivation layer and the third portion.
  • the channel is located on the first portion, the source, and the drain.
  • a material of the active layer includes at least one of graphene, silicon carbide, molybdenum disulfide, organic semiconductor, and carbon nanotubes.
  • a material of the passivation layer includes at least one of an organic insulating material, SiN x , SiO 2 , HfO 2, and Al 2 O 3 .
  • the thin film transistor and the manufacturing method thereof of the present invention prevent the channel material from being damaged by the deposition process of the second conductive layer by fabricating an active layer after the second conductive layer, and meanwhile, between the second conductive layer and the active layer Adding a flat layer enhances the adhesion between the active layer and the bottom layer and improves the performance of the thin film transistor.
  • FIG. 1 is a schematic structural diagram of a first step of a manufacturing method of a thin film transistor according to the present invention
  • FIG. 2 is a schematic structural diagram of a second step of a manufacturing method of a thin film transistor according to the present invention.
  • FIG. 3 is a schematic structural diagram of a first step in a third step of a method for manufacturing a thin film transistor according to the present invention.
  • FIG. 4 is a schematic structural diagram of a second step in a third step of a method for manufacturing a thin film transistor according to the present invention.
  • FIG. 5 is a schematic structural diagram of a first step in a fourth step of a method for manufacturing a thin film transistor according to the present invention.
  • FIG. 6 is a schematic structural diagram of a second step in a fourth step of a method for manufacturing a thin film transistor according to the present invention.
  • FIG. 7 is a schematic structural diagram of a first step in a fifth step of a method for manufacturing a thin film transistor according to the present invention.
  • FIG. 8 is a schematic structural diagram of a second step in a fifth step of a method of manufacturing a thin film transistor according to the present invention.
  • FIG. 9 is a schematic structural diagram of a sixth step of a manufacturing method of a thin film transistor according to the present invention.
  • FIG. 10 is a schematic structural diagram of a seventh step of a manufacturing method of a thin film transistor according to the present invention.
  • FIG. 1 is a schematic structural diagram of a first step of a manufacturing method of a thin film transistor according to the present invention.
  • the manufacturing method of the thin film transistor manufacturing method of the present invention mainly includes the following steps:
  • S101 forming a first conductive layer on a substrate, and patterning the first conductive layer to form a gate;
  • the substrate 11 is first cleaned, and then a whole conductive layer is deposited on the substrate 11 by physical vapor deposition (PVD) or vapor deposition, and a photoresist is coated on the conductive layer.
  • PVD physical vapor deposition
  • Photomask, etc. and then perform photolithography processes such as exposure, development, acid wet etching, and elution to pattern the conductive layer to obtain the gate electrode 12.
  • the material of the substrate 11 may be polyimide (PI), polyethylene terephthalate (PET), quartz, SiO 2 , glass, or the like.
  • the material of the first conductive layer is indium tin oxide (ITO), Mo / Al, Ti / Cu, Cr / Au, Ag, or the like.
  • an entire gate insulating layer 13 is prepared on the gate 12 by atomic layer deposition (ALD) or chemical vapor deposition (CVD).
  • the material of the gate insulating layer 13 may be an organic insulating material, SiNx, SiO 2 , HfO 2 , Al 2 O 3, or the like.
  • S103 forming a second conductive layer on the gate insulating layer, and patterning the second conductive layer to form a source and a drain;
  • the entire conductive layer 14 is deposited on the gate insulating layer 13 by means of physical vapor deposition (PVD) or evaporation, and then a photoresist is coated on the conductive layer 14 and exposed and developed After the processes such as wet etching with acid solution and photoresist elution, a patterned source / drain 14 ′ (S / D) is obtained, as shown in FIG. 4.
  • the material of the second conductive layer 14 is ITO, Mo / Al, Ti / Cu, Cr / Au, Ag, or the like.
  • S104 Form a flat layer on the source, drain, and gate insulation layers, and pattern the flat layer to form a first part, a second part, and a third part; the first part Located between the source and the drain, the second portion is located on one side of the source, and the third portion is located on one side of the drain, the first portion, the second portion A part and an upper surface of the third part are flush with the top of the source and the drain, so as to expose part of the source and the drain to the outside;
  • This step can include:
  • the entire layer of material of the flat layer is coated on the source and drain electrodes 14 ′ and the gate insulating layer 13, and then the material of the flat layer is pre-baked, exposed, developed, bleached, and baked Such processes as curing the organic material form the flat layer 15.
  • S1043 Perform a patterning process on the flat layer to form a first part, a second part, and a third part;
  • the flat layer 15 is dry-etched by plasma processing to form a first portion 151, a second portion 152, and a third portion 153.
  • the first portion 151 is located between the source and the drain.
  • the second portion 152 is located on the source side and the third portion 153 is located on the drain side.
  • the first portion 151, the second portion 152, and the third portion The upper surface of 153 is flush with the tops of the source and drain electrodes, that is, the upper surface of the patterned flat layer 15 (that is, the surface away from the second conductive layer side) and the source and drain electrodes.
  • the top of the 14 '(the middle raised part in the figure) is flush, so that part of the source and drain 14' (that is, the middle raised part) is exposed to facilitate connection with the active layer.
  • the material of the flat layer 15 has a photosensitive insulating resin material, such as an insulating resin material with negative photosensitivity or a positive sexy property. Light insulating resin material. That is, the adhesion between the active layer 16 and the second conductive layer 14 is enhanced by the flat layer 15.
  • An active layer is formed on the flat layer and the source and drain electrodes, and the active layer is used to form a channel.
  • a solution process or a transfer process is used to form an active layer 16 on the upper surfaces of the etched flat layer 15 and the source and drain electrodes 14 ′; thereafter, photolithography is coated on the active layer 16. And then performing photomask exposure, development, plasma dry etching, and photoresist elution to pattern the active layer 16 to obtain the channel 16 ', as shown in FIG. That is, the active layer 16 is used to form a channel.
  • the channel 16 ' is located on the first portion 151 and on the source and the drain.
  • the material of the active layer 16 includes at least one of graphene, silicon carbide (SiC), molybdenum disulfide (MoS 2 ), organic semiconductor, and carbon nanotubes.
  • a passivation layer is formed on the channel 16 ', the second portion 152, and the third portion 153.
  • an entire layer of passivation film is prepared over the channel 16 ′ by atomic layer deposition (ALD) or chemical vapor deposition (CVD), and is coated by photoresist, exposure, development, and plasma drying.
  • the passivation film is patterned by photolithography processes such as etching and elution to obtain a passivation layer 17.
  • the material of the passivation layer 17 includes at least one of an organic insulating material, SiNx, SiO 2 , HfO 2 , and Al 2 O 3 .
  • a patterning process is performed on the passivation layer 17 and the third portion 153 using a mask to obtain the via hole 101.
  • the via hole 101 extends from the passivation layer 17 to the third portion 153 of the flat layer.
  • the position of the via hole 101 corresponds to the position of the drain.
  • the drain is connected to the pixel electrode through the via hole 101.
  • this embodiment provides a thin film transistor including a first conductive layer, a gate insulating layer 13, a second conductive layer 14, a flat layer 15, an active layer 16, and a passivation layer which are sequentially located on a substrate 11. ⁇ ⁇ 17 ⁇ The layer 17.
  • the material of the substrate 11 may be polyimide (PI), polyethylene terephthalate (PET), quartz, SiO 2 , glass, or the like.
  • the first conductive layer is located on the substrate 11.
  • the first conductive layer includes a gate electrode 12.
  • the material of the first conductive layer is indium tin oxide (ITO), Mo / Al, Ti / Cu, Cr / Au, Ag, or the like.
  • the gate insulating layer 13 is located on the gate 12.
  • the material of the gate insulating layer 13 may be an organic insulating material, SiNx, SiO 2 , HfO 2 , Al 2 O 3, or the like.
  • a second conductive layer is located on the gate insulating layer 13, and the second conductive layer includes source and drain electrodes 14 '; the material of the second conductive layer is ITO, Mo / Al, Ti / Cu, Cr / Au, Ag Wait.
  • a planarization layer 15 is located on the source and drain electrodes 14 ′ and the gate insulating layer 13.
  • the planarization layer 15 includes a first portion 151 disposed between the source and drain electrodes, and a side of the source electrode.
  • a second portion 152 and a third portion 153 provided on one side of the drain; the upper surfaces of the first portion 151, the second portion 152, and the third portion 153 are in contact with the source and
  • the top of the drain is flush to expose a portion of the source and drain 14 '.
  • the upper surface of the etched flat layer 15 and the top of the source and drain 14 ' are flush with each other by patterning the material of the flat layer coated on the source and drain 14'.
  • the material of the flat layer 15 has a photosensitive insulating resin material, such as an insulating resin material having negative photosensitivity or a material having positive photosensitivity.
  • the insulating resin material that is, the adhesion between the active layer 16 and the second conductive layer 14 is enhanced by the flat layer 15.
  • the flat layer 15 is used to enhance adhesion between the active layer and the second conductive layer.
  • An active layer is located on the etched flat layer 15 and the source and drain electrodes 14 ', and the active layer is used to form a channel 16'.
  • the material of the active layer is graphene, SiC, MoS 2 , organic semiconductor, carbon nanotube, and the like.
  • the passivation layer 17 is located on the channel 16 ′ and the second portion 152 and the third portion 153.
  • the passivation layer 17 is provided with a via hole 101.
  • the via hole 101 penetrates the passivation layer 17 and the third portion 153.
  • the via hole 101 is used to connect the drain electrode and the pixel electrode.
  • the material of the passivation layer 17 may be an organic insulating material, SiNx, SiO 2 , HfO 2 , Al 2 O 3, or the like.
  • the thin film transistor and the manufacturing method thereof of the present invention prevent the channel material from being damaged by the deposition process of the second conductive layer by fabricating an active layer after the second conductive layer, and meanwhile, between the second conductive layer and the active layer Adding a flat layer enhances the adhesion between the active layer and the bottom layer and improves the performance of the thin film transistor.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

本发明提供一种薄膜晶体管及其制作方法，该制作方法包括：在基板上形成源极和漏极、平坦层，并对所述平坦层进行图案化处理形成位于所述源极和所述漏极之间的第一部分、位于所述源极的一侧的第二部分和位于所述漏极的一侧的第三部分；所述第一部分、所述第二部分和所述第三部分的上表面都与所述源极和所述漏极的顶部齐平。

Description

一种薄膜晶体管及其制作方法 技术领域
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管及其制作方法。
 背景技术
现有的薄膜晶体管的结构包括基板、第一金属层（形成栅极）、绝缘层、有源层、第二金属层（形成源漏极）等。也即现有的薄膜晶体管，在制备完有源层后才进行第二金属层的沉积。有源层的材料通常为石墨烯、碳纳米管、碳化硅、二硫化钼、有机化合物等在内的新型半导体材料。
 技术问题
但是由于第二金属层的沉积过程通常是采用物理气相沉积工艺，而物理气相沉积工艺会对具有新型半导体材料造成损伤，且由于新型半导体材料对金属及玻璃基板的粘附力有限，因而在制备上述新型半导体材料的晶体管时，降低了薄膜晶体管的性能。
 技术解决方案
本发明的目的在于提供一种薄膜晶体管及其制作方法，能够提高薄膜晶体管的性能。
为解决上述技术问题，本发明提供一种薄膜晶体管的制作方法，其包括：
在基板上形成第一导电层，对所述第一导电层进行图案化处理形成栅极；
在所述栅极和所述基板上形成栅极绝缘层；
在所述栅极绝缘层上形成第二导电层，对所述第二导电层进行图案化处理形成源极和漏极；
在所述源极、所述漏极和所述栅极绝缘层上形成平坦层，并通过等离子体处理法对所述平坦层进行刻蚀，以形成第一部分、第二部分和第三部分；所述第一部分位于所述源极和所述漏极之间、所述第二部分位于所述源极的一侧以及所述第三部分位于所述漏极的一侧，所述第一部分、所述第二部分和所述第三部分的上表面都与所述源极和所述漏极的顶部齐平，以将部分所述源极和所述漏极裸露在外；所述平坦层的材料为具有感光性的绝缘树脂材料；
在所述平坦层及所述源极和所述漏极上形成有源层，所述有源层用于形成沟道；
在所述沟道、所述第二部分和所述第三部分上形成钝化层。
在本发明的薄膜晶体管的制作方法中，所述在所述源极、所述漏极和栅极绝缘层上形成平坦层的步骤包括：
在所述源极、所述漏极和所述栅极绝缘层上涂布平坦层的材料；
对所述平坦层的材料进行固化处理，以形成平坦层。
在本发明的薄膜晶体管的制作方法中，所述在所述沟道、所述第二部分和第三部分上形成钝化层的步骤之后，所述方法还包括：
对所述钝化层和所述平坦层的第三部分进行图案化处理，得到过孔；所述过孔贯穿所述钝化层和所述第三部分。
在本发明的薄膜晶体管的制作方法中，所述沟道位于所述第一部分、所述源极以及所述漏极上。
在本发明的薄膜晶体管的制作方法中，所述有源层的材料包括石墨烯、碳化硅、二硫化钼、有机半导体以及碳纳米管中的至少一种。
在本发明的薄膜晶体管的制作方法中，所述钝化层的材料包括有机绝缘材料、SiN x、SiO 2、HfO 2以及Al 2O 3中的至少一种。
本发明提供一种薄膜晶体管的制作方法，其包括：
在基板上形成第一导电层，对所述第一导电层进行图案化处理形成栅极；
在所述栅极和所述基板上形成栅极绝缘层；
在所述栅极绝缘层上形成第二导电层，对所述第二导电层进行图案化处理形成源极和漏极；
在所述源极、所述漏极和所述栅极绝缘层上形成平坦层，并对所述平坦层进行图案化处理，以形成第一部分、第二部分和第三部分；所述第一部分位于所述源极和所述漏极之间、所述第二部分位于所述源极的一侧以及所述第三部分位于所述漏极的一侧，所述第一部分、所述第二部分和所述第三部分的上表面都与所述源极和所述漏极的顶部齐平，以将部分所述源极和所述漏极裸露在外；
在所述平坦层及所述源极和所述漏极上形成有源层，所述有源层用于形成沟道；
在所述沟道、所述第二部分和所述第三部分上形成钝化层。
在本发明的薄膜晶体管的制作方法中，所述平坦层的材料为具有感光性的绝缘树脂材料。
在本发明的薄膜晶体管的制作方法中，所述对所述平坦层进行图案化处理，以形成第一部分、第二部分、第三部分的步骤包括：
通过等离子体处理法对所述平坦层进行刻蚀，以形成第一部分、第二部分、第三部分。
在本发明的薄膜晶体管的制作方法中，所述在所述源极、所述漏极和栅极绝缘层上形成平坦层的步骤包括：
在所述源极、所述漏极和所述栅极绝缘层上涂布平坦层的材料；
对所述平坦层的材料进行固化处理，以形成平坦层。
在本发明的薄膜晶体管的制作方法中，所述在所述沟道、所述第二部分和第三部分上形成钝化层的步骤之后，所述方法还包括：
对所述钝化层和所述平坦层的第三部分进行图案化处理，得到过孔；所述过孔贯穿所述钝化层和所述第三部分。
在本发明的薄膜晶体管的制作方法中，所述沟道位于所述第一部分、所述源极以及所述漏极上。
在本发明的薄膜晶体管的制作方法中，所述有源层的材料包括石墨烯、碳化硅、二硫化钼、有机半导体以及碳纳米管中的至少一种。
在本发明的薄膜晶体管的制作方法中，所述钝化层的材料包括有机绝缘材料、SiN x、SiO 2、HfO 2以及Al 2O 3中的至少一种。
本发明还提供一种薄膜晶体管，其包括：
设于基板上的栅极；
设于所述栅极和所述基板上的栅极绝缘层；
设于所述栅极绝缘层上的源极和漏极；
设于所述源极、漏极和栅极绝缘层之上的平坦层，所述平坦层包括设置在源极和漏极之间的第一部分、设置在所述源极的一侧的第二部分以及设置在所述漏极的一侧的第三部分；所述第一部分、所述第二部分和所述第三部分的上表面与所述源极和所述漏极的顶部齐平，以将部分所述源极和所述漏极裸露在外；
设于所述平坦层及所述源极和所述漏极上的有源层，所述有源层用于形成沟道；
设于所述沟道、所述第二部分和所述第三部分上的钝化层。
在本发明的薄膜晶体管中，所述平坦层的材料为具有感光性的绝缘树脂材料。
在本发明的薄膜晶体管中，所述钝化层上设置有过孔，所述过孔贯穿所述钝化层和所述第三部分。
在本发明的薄膜晶体管中，所述沟道位于所述第一部分、所述源极以及所述漏极上。
在本发明的薄膜晶体管中，所述有源层的材料包括石墨烯、碳化硅、二硫化钼、有机半导体以及碳纳米管中的至少一种。
在本发明的薄膜晶体管中，所述钝化层的材料包括有机绝缘材料、SiN x、SiO 2、HfO 2以及Al 2O 3中的至少一种。
有益效果
本发明的薄膜晶体管及其制作方法，通过在第二导电层之后制作有源层，从而防止第二导电层的沉积工艺对沟道材料造成损坏，同时在第二导电层与有源层之间增加一平坦层，增强了有源层与底层的粘附性，提高了薄膜晶体管的性能。
 附图说明
图1为本发明薄膜晶体管的制作方法的第一步的结构示意图；
图2为本发明薄膜晶体管的制作方法的第二步的结构示意图；
图3为本发明薄膜晶体管的制作方法的第三步中第一分步的结构示意图；
图4为本发明薄膜晶体管的制作方法的第三步中第二分步的结构示意图；
图5为本发明薄膜晶体管的制作方法的第四步中第一分步的结构示意图；
图6为本发明薄膜晶体管的制作方法的第四步中第二分步的结构示意图；
图7为本发明薄膜晶体管的制作方法的第五步中第一分步的结构示意图；
图8为本发明薄膜晶体管的制作方法的第五步中第二分步的结构示意图；
图9为本发明薄膜晶体管的制作方法的第六步的结构示意图；
图10为本发明薄膜晶体管的制作方法的第七步的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明薄膜晶体管的制作方法的第一步的结构示意图。
如图1所示，本发明薄膜晶体管的制作方法的制作方法主要包括如下步骤：
S101、在基板上形成第一导电层，对所述第一导电层进行图案化处理形成栅极；
如图1所示，具体地先清洗基板11（base），然后以物理气相沉积（PVD）或蒸镀的方式在基板11上沉积整层的导电层，在该导电层上涂布光刻胶、光罩等、之后再对其进行曝光、显影、酸液湿刻以及洗脱等光刻工艺，以对导电层进行图案化处理，得到栅极12。
该基板11的材料可以为聚酰亚胺（PI）、聚对苯二甲酸乙二醇酯（PET）、石英、SiO 2、玻璃等。该第一导电层的材料为氧化铟锡（ITO）、Mo/Al、Ti/Cu、Cr/Au、Ag 等。
S102、在所述栅极和所述基板上形成栅极绝缘层；
如图2所示，通过原子层沉积（ALD）或化学气相沉积（CVD）在栅极12上制备整层的栅极绝缘层13（GI）。该栅极绝缘层13的材料可以为有机绝缘材料、SiNx、SiO 2、HfO 2、Al 2O 3等。
S103、在所述栅极绝缘层上形成第二导电层，对所述第二导电层进行图案化处理形成源极和漏极；
如图3所示，采用物理气相沉积（PVD）或蒸镀的方式在栅极绝缘层13上沉积整层的导电层14，之后在导电层14上涂布光刻胶，并进行曝光、显影、酸液湿刻以及洗脱光刻胶等工艺后，得到图案化的源漏极14’（S/D），如图4所示。该第二导电层14的材料为ITO、Mo/Al、Ti/Cu、Cr/Au、Ag等。
S104、在所述源极、漏极和所述栅极绝缘层上形成平坦层，并对所述平坦层进行图案化处理，以形成第一部分、第二部分、第三部分；所述第一部分位于所述源极和所述漏极之间、所述第二部分位于所述源极的一侧以及所述第三部分位于所述漏极的一侧，所述第一部分、所述第二部分、所述第三部分的上表面都与所述源极和所述漏极的顶部齐平，以将部分所述源极和所述漏极裸露在外；
该步骤可以包括：
S1041、在所述源极和漏极以及所述栅极绝缘层上涂布平坦层的材料；
S1042、对所述平坦层的材料进行固化处理，以形成平坦层；
例如，如图5所示，在源漏极14’以及栅极绝缘层13上涂布整层的平坦层的材料，之后对平坦层的材料进行预烘烤、曝光、显影、漂白、烘烤等工艺使有机材料固化，形成平坦层15。
S1043、对所述平坦层进行图案化处理，以形成第一部分、第二部分、第三部分；
如图6所示，通过等离子体处理对平坦层15进行干刻，以形成第一部分151、第二部分152、第三部分153，所述第一部分151位于所述源极和所述漏极之间、所述第二部分152位于所述源极的一侧以及所述第三部分153位于所述漏极的一侧，所述第一部分151、所述第二部分152、所述第三部分153的上表面都与所述源极和所述漏极的顶部齐平，也即图案化后的平坦层15的上表面（也即远离第二导电层侧的表面）与所述源漏极14’的顶部（图中中间凸起的部分）齐平，从而将部分所述源漏极14’（也即中间凸起部分）裸露在外，以便于与有源层连接。
优选地，为了进一步增强有源层与有源层下方膜层的粘附性，该平坦层15的材料具有感光性的绝缘树脂材料，比如为具有负性感光性的绝缘树脂材料或者具有正性感光性的绝缘树脂材料。也即，通过所述平坦层15增强了所述有源层16与所述第二导电层14之间的粘附性。
S105、在所述平坦层及所述源极和漏极上形成有源层，所述有源层用于形成沟道；
例如，如图7所示，采用溶液制程或转印工艺进行在刻蚀后的平坦层15及源漏极14’的上表面形成有源层16；之后在有源层16上涂布光刻胶、然后进行光罩曝光、显影、等离子体干刻、洗脱光刻胶等工艺以对有源层16进行图案化处理，得到沟道16’，如图8所示。也即该有源层16用来形成沟道。所述沟道16’位于所述第一部分151以及所述源极和所述漏极上。
所述有源层16的材料包括石墨烯、碳化硅（SiC）、二硫化钼（MoS 2）、有机半导体以及碳纳米管中的至少一种。
S106、在所述沟道16’、所述第二部分152和第三部分153上形成钝化层。
如图9所示，以原子层沉积（ALD）或化学气相沉积（CVD）在沟道16’的上方制备整层的钝化薄膜，并通过涂布光刻胶、曝光、显影、等离子体干刻、洗脱等光刻工艺对钝化薄膜进行图形化，得到钝化层17。
钝化层17的材料包括有机绝缘材料、SiNx、SiO 2、HfO 2、Al 2O 3中的至少一种。
S107、对所述钝化层和所述平坦层的第三部分进行图案化处理，得到过孔；所述过孔贯穿所述钝化层和所述第三部分。
如图10所示，使用一掩膜板对所述钝化层17和第三部分153进行图案化处理，得到所述过孔101。所述过孔101从钝化层17延伸到平坦层的第三部分153。其中过孔101的位置与漏极的位置对应。所述漏极通过所述过孔101与像素电极连接。
结合图1至10，本实施例提供一种薄膜晶体管，其包括依次位于基板11上的第一导电层、栅极绝缘层13、第二导电层14、平坦层15、有源层16、钝化层17。
该基板11的材料可以为聚酰亚胺（PI）、聚对苯二甲酸乙二醇酯（PET）、石英、SiO 2、玻璃等。该第一导电层位于基板11上，所述第一导电层包括栅极12。该第一导电层的材料为氧化铟锡（ITO）、Mo/Al、Ti/Cu、Cr/Au、Ag等。
栅极绝缘层13位于所述栅极12上。该栅极绝缘层13的材料可以为有机绝缘材料、SiNx、SiO 2、HfO 2、Al 2O 3等。
第二导电层位于所述栅极绝缘层13上，所述第二导电层包括源漏极14’；该第二导电层的材料为ITO、Mo/Al、Ti/Cu、Cr/Au、Ag 等。
平坦层15位于所述源漏极14’和所述栅极绝缘层13上，所述平坦层15包括设置在源极和漏极之间的第一部分151、设置在所述源极的一侧的第二部分152以及设置在所述漏极的一侧的第三部分153；所述第一部分151、所述第二部分152和所述第三部分153的上表面与所述源极和所述漏极的顶部齐平，以将部分所述源漏极14’裸露在外。
其中刻蚀后的平坦层15的上表面与所述源漏极14’的顶部齐平是通过对涂布在所述源漏极14’上的平坦层的材料进行图案化处理得到的。
为了进一步增强有源层与有源层下方膜层的粘附性，该平坦层15的材料具有感光性的绝缘树脂材料，比如为具有负性感光性的绝缘树脂材料或者具有正性感光性的绝缘树脂材料，也即通过所述平坦层15增强了所述有源层16与所述第二导电层14之间的粘附性。
所述平坦层15用于增强所述有源层与所述第二导电层之间的粘附性。
有源层位于所述刻蚀后的平坦层15及所述源漏极14’上，所述有源层用于形成沟道16’。所述有源层的材料为石墨烯、SiC、MoS 2、有机半导体、碳纳米管等。
钝化层17位于所述沟道16’以及第二部分152和第三部分153上。所述钝化层17上设置有过孔101，所述过孔101贯穿所述钝化层17和所述第三部分153，所述过孔101用于连接所述漏极和像素电极。所述钝化层17的材料可以为有机绝缘材料、SiNx、SiO 2、HfO 2、Al 2O 3等。
本发明的薄膜晶体管及其制作方法，通过在第二导电层之后制作有源层，从而防止第二导电层的沉积工艺对沟道材料造成损坏，同时在第二导电层与有源层之间增加一平坦层，增强了有源层与底层的粘附性，提高了薄膜晶体管的性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管的制作方法，其包括：
    在基板上形成第一导电层，对所述第一导电层进行图案化处理形成栅极；
    在所述栅极和所述基板上形成栅极绝缘层；
    在所述栅极绝缘层上形成第二导电层，对所述第二导电层进行图案化处理形成源极和漏极；
    在所述源极、所述漏极和所述栅极绝缘层上形成平坦层，并通过等离子体处理法对所述平坦层进行刻蚀，以形成第一部分、第二部分和第三部分；所述第一部分位于所述源极和所述漏极之间、所述第二部分位于所述源极的一侧以及所述第三部分位于所述漏极的一侧，所述第一部分、所述第二部分和所述第三部分的上表面都与所述源极和所述漏极的顶部齐平，以将部分所述源极和所述漏极裸露在外；所述平坦层的材料为具有感光性的绝缘树脂材料；
    在所述平坦层及所述源极和所述漏极上形成有源层，所述有源层用于形成沟道；以及
    在所述沟道、所述第二部分和所述第三部分上形成钝化层。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述在所述源极、所述漏极和栅极绝缘层上形成平坦层的步骤包括：
    在所述源极、所述漏极和所述栅极绝缘层上涂布平坦层的材料；以及
    对所述平坦层的材料进行固化处理，以形成平坦层。
  3. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述在所述沟道、所述第二部分和第三部分上形成钝化层的步骤之后，所述方法还包括：
    对所述钝化层和所述平坦层的第三部分进行图案化处理，得到过孔；所述过孔贯穿所述钝化层和所述第三部分。
  4. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述沟道位于所述第一部分、所述源极以及所述漏极上。
  5. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述有源层的材料包括石墨烯、碳化硅、二硫化钼、有机半导体以及碳纳米管中的至少一种。
  6. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述钝化层的材料包括有机绝缘材料、SiN x、SiO 2、HfO 2以及Al 2O 3中的至少一种。
  7. 一种薄膜晶体管的制作方法，其包括：
    在基板上形成第一导电层，对所述第一导电层进行图案化处理形成栅极；
    在所述栅极和所述基板上形成栅极绝缘层；
    在所述栅极绝缘层上形成第二导电层，对所述第二导电层进行图案化处理形成源极和漏极；
    在所述源极、所述漏极和所述栅极绝缘层上形成平坦层，并对所述平坦层进行图案化处理，以形成第一部分、第二部分和第三部分；所述第一部分位于所述源极和所述漏极之间、所述第二部分位于所述源极的一侧以及所述第三部分位于所述漏极的一侧，所述第一部分、所述第二部分和所述第三部分的上表面都与所述源极和所述漏极的顶部齐平，以将部分所述源极和所述漏极裸露在外；
    在所述平坦层及所述源极和所述漏极上形成有源层，所述有源层用于形成沟道；以及
    在所述沟道、所述第二部分和所述第三部分上形成钝化层。
  8. 根据权利要求7所述的薄膜晶体管的制作方法，其中
    所述平坦层的材料为具有感光性的绝缘树脂材料。
  9. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述对所述平坦层进行图案化处理，以形成第一部分、第二部分、第三部分的步骤包括：
    通过等离子体处理法对所述平坦层进行刻蚀，以形成第一部分、第二部分、第三部分。
  10. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述在所述源极、所述漏极和栅极绝缘层上形成平坦层的步骤包括：
    在所述源极、所述漏极和所述栅极绝缘层上涂布平坦层的材料；
    对所述平坦层的材料进行固化处理，以形成平坦层。
  11. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述在所述沟道、所述第二部分和第三部分上形成钝化层的步骤之后，所述方法还包括：
    对所述钝化层和所述平坦层的第三部分进行图案化处理，得到过孔；所述过孔贯穿所述钝化层和所述第三部分。
  12. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述沟道位于所述第一部分、所述源极以及所述漏极上。
  13. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述有源层的材料包括石墨烯、碳化硅、二硫化钼、有机半导体以及碳纳米管中的至少一种。
  14. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述钝化层的材料包括有机绝缘材料、SiN x、SiO 2、HfO 2以及Al 2O 3中的至少一种。
  15. 一种薄膜晶体管，其包括：
    设于基板上的栅极；
    设于所述栅极和所述基板上的栅极绝缘层；
    设于所述栅极绝缘层上的源极和漏极；
    设于所述源极、漏极和栅极绝缘层之上的平坦层，所述平坦层包括设置在源极和漏极之间的第一部分、设置在所述源极的一侧的第二部分以及设置在所述漏极的一侧的第三部分；所述第一部分、所述第二部分和所述第三部分的上表面与所述源极和所述漏极的顶部齐平，以将部分所述源极和所述漏极裸露在外；
    设于所述平坦层及所述源极和所述漏极上的有源层，所述有源层用于形成沟道；以及
    设于所述沟道、所述第二部分和所述第三部分上的钝化层。
  16. 根据权利要求15所述的薄膜晶体管，其中
    所述平坦层的材料为具有感光性的绝缘树脂材料。
  17. 根据权利要求15所述的薄膜晶体管，其中
    所述钝化层上设置有过孔，所述过孔贯穿所述钝化层和所述第三部分。
  18. 根据权利要求15所述的薄膜晶体管，其中所述沟道位于所述第一部分、所述源极以及所述漏极上。
  19. 根据权利要求15所述的薄膜晶体管，其中所述有源层的材料包括石墨烯、碳化硅、二硫化钼、有机半导体以及碳纳米管中的至少一种。
  20. 根据权利要求15所述的薄膜晶体管，其中所述钝化层的材料包括有机绝缘材料、SiN x、SiO 2、HfO 2以及Al 2O 3中的至少一种。
PCT/CN2018/104532 2018-07-05 2018-09-07 一种薄膜晶体管及其制作方法 Ceased WO2020006858A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/094,479 US11316049B2 (en) 2018-07-05 2018-09-07 Thin-film transistor and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810728134.3 2018-07-05
CN201810728134.3A CN108933179B (zh) 2018-07-05 2018-07-05 一种薄膜晶体管及其制作方法

Publications (1)

Publication Number Publication Date
WO2020006858A1 true WO2020006858A1 (zh) 2020-01-09

Family

ID=64446762

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/104532 Ceased WO2020006858A1 (zh) 2018-07-05 2018-09-07 一种薄膜晶体管及其制作方法

Country Status (3)

Country Link
US (1) US11316049B2 (zh)
CN (1) CN108933179B (zh)
WO (1) WO2020006858A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023014323A1 (en) 2021-08-05 2023-02-09 Sanel Sanayi̇ Elektroni̇ği̇ İmalat Ve Ti̇caret Anoni̇m Şi̇rketi̇ Frequency adjustment system and method for in-vehicle lighting

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109801954B (zh) * 2019-02-26 2021-04-09 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板及显示装置
CN110658649A (zh) * 2019-08-29 2020-01-07 深圳市科创数字显示技术有限公司 硅基液晶器件的制作方法及硅基液晶器件、波长选择开关
CN110707216B (zh) * 2019-10-24 2023-06-13 宁波石墨烯创新中心有限公司 石墨烯薄膜晶体管、其制备方法及显示装置
CN114496793A (zh) * 2020-11-13 2022-05-13 深圳柔宇显示技术有限公司 电子设备、显示屏、薄膜晶体管及其制备方法
CN115249617B (zh) * 2022-09-22 2023-02-10 广州粤芯半导体技术有限公司 半导体器件及其制备方法
CN119744367A (zh) * 2022-12-16 2025-04-01 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板、显示装置
CN115881799B (zh) * 2023-01-31 2023-06-02 广州粤芯半导体技术有限公司 半导体结构及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206166A (ja) * 1991-12-26 1993-08-13 Fuji Xerox Co Ltd 薄膜トランジスタ
US6344662B1 (en) * 1997-03-25 2002-02-05 International Business Machines Corporation Thin-film field-effect transistor with organic-inorganic hybrid semiconductor requiring low operating voltages
US20040023447A1 (en) * 2002-08-02 2004-02-05 Semiconductor Energy Laboratory Co., Ltd. Organic thin film transistor and method of manufacturing the same, and semiconductor device having the organic thin film transistor
CN1881549A (zh) * 2005-06-16 2006-12-20 财团法人工业技术研究院 薄膜晶体管的制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7411211B1 (en) * 1999-07-22 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
JP4289332B2 (ja) * 2004-09-30 2009-07-01 セイコーエプソン株式会社 Ｅｌ表示装置、ｅｌ表示装置の製造方法、及び電子機器
KR100787438B1 (ko) 2005-12-12 2007-12-26 삼성에스디아이 주식회사 유기 박막 트랜지스터, 이의 제조방법 및 이를 구비한 유기발광 디스플레이 장치
JP5355970B2 (ja) * 2008-09-16 2013-11-27 株式会社ジャパンディスプレイ 液晶表示装置
US20110227087A1 (en) * 2008-11-28 2011-09-22 Sharp Kabushiki Kaisha Substrate for display device, and display device
CN102655095B (zh) * 2011-06-01 2014-10-15 京东方科技集团股份有限公司 薄膜晶体管及阵列基板的制造方法
CN102881654B (zh) * 2012-09-29 2016-03-23 京东方科技集团股份有限公司 薄膜晶体管阵列基板及其制备方法、有源矩阵驱动显示装置
JP2014212070A (ja) * 2013-04-19 2014-11-13 ソニー株式会社 表示装置およびその製造方法、ならびに電子機器
JP6394171B2 (ja) * 2013-10-30 2018-09-26 株式会社リコー 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム
CN105206626B (zh) 2015-11-09 2018-11-20 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
US10818705B2 (en) * 2016-03-18 2020-10-27 Ricoh Company, Ltd. Method for manufacturing a field effect transistor, method for manufacturing a volatile semiconductor memory element, method for manufacturing a non-volatile semiconductor memory element, method for manufacturing a display element, method for manufacturing an image display device, and method for manufacturing a system
CN109791983B (zh) 2016-09-29 2023-06-16 富士胶片株式会社 微晶有机半导体膜、有机半导体晶体管及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206166A (ja) * 1991-12-26 1993-08-13 Fuji Xerox Co Ltd 薄膜トランジスタ
US6344662B1 (en) * 1997-03-25 2002-02-05 International Business Machines Corporation Thin-film field-effect transistor with organic-inorganic hybrid semiconductor requiring low operating voltages
US20040023447A1 (en) * 2002-08-02 2004-02-05 Semiconductor Energy Laboratory Co., Ltd. Organic thin film transistor and method of manufacturing the same, and semiconductor device having the organic thin film transistor
CN1881549A (zh) * 2005-06-16 2006-12-20 财团法人工业技术研究院 薄膜晶体管的制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023014323A1 (en) 2021-08-05 2023-02-09 Sanel Sanayi̇ Elektroni̇ği̇ İmalat Ve Ti̇caret Anoni̇m Şi̇rketi̇ Frequency adjustment system and method for in-vehicle lighting

Also Published As

Publication number Publication date
US11316049B2 (en) 2022-04-26
CN108933179A (zh) 2018-12-04
US20210226068A1 (en) 2021-07-22
CN108933179B (zh) 2020-06-16

Similar Documents

Publication Publication Date Title
CN108933179B (zh) 一种薄膜晶体管及其制作方法
CN109166865B (zh) 阵列基板及其制造方法、显示面板
US11121228B2 (en) Manufacturing method of thin film transistor
CN102651342B (zh) 阵列基板及其制造方法
CN104183648B (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示装置
WO2013026360A1 (zh) 有机薄膜晶体管阵列基板及其制作方法和显示装置
CN111048524A (zh) 阵列基板及制备方法、显示面板
CN110164873A (zh) 阵列基板的制作方法、阵列基板、显示面板及显示装置
WO2017215109A1 (zh) 双栅电极氧化物薄膜晶体管及其制备方法
CN110164875A (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2015143745A1 (zh) 一种阵列基板的制造方法
WO2021026990A1 (zh) 一种阵列基板及其制作方法
CN111312731B (zh) 一种阵列基板及其制备方法、显示面板
CN106229298B (zh) 一种阵列基板及其制作方法
CN105990332B (zh) 薄膜晶体管基板及其显示面板
CN109037241A (zh) Ltps阵列基板及其制造方法、显示面板
WO2019196191A1 (zh) 一种tft阵列基板的制备方法及tft阵列基板、显示面板
CN102655116B (zh) 阵列基板的制造方法
CN107706115A (zh) 一种薄膜晶体管及其制作方法
CN107611084B (zh) 一种阵列基板接触孔制备方法、阵列基板及显示器件
WO2023283998A1 (zh) 显示面板及其制备方法、显示装置
TW202113443A (zh) 半導體裝置
WO2014117444A1 (zh) 阵列基板及其制作方法、显示装置
CN104112711B (zh) 共平面型氧化物半导体tft基板的制作方法
CN102543861B (zh) 阵列基板的形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18925457

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18925457

Country of ref document: EP

Kind code of ref document: A1