WO2020006662A1 - 一种自终止写入电路及方法 - Google Patents

一种自终止写入电路及方法 Download PDF

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Publication number
WO2020006662A1
WO2020006662A1 PCT/CN2018/094070 CN2018094070W WO2020006662A1 WO 2020006662 A1 WO2020006662 A1 WO 2020006662A1 CN 2018094070 W CN2018094070 W CN 2018094070W WO 2020006662 A1 WO2020006662 A1 WO 2020006662A1
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Prior art keywords
gate
effect transistor
electrically connected
circuit
field effect
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PCT/CN2018/094070
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English (en)
French (fr)
Inventor
潘越
刘燕翔
段霑
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880091692.1A priority Critical patent/CN111902872B/zh
Priority to CN202211100672.0A priority patent/CN115497531A/zh
Priority to PCT/CN2018/094070 priority patent/WO2020006662A1/zh
Publication of WO2020006662A1 publication Critical patent/WO2020006662A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory

Definitions

  • the present application relates to the field of circuits, and in particular, to a self-terminating writing circuit and method.
  • STT-MRAM Spin-transfer torque magnetic memory
  • CMOS Complementary metal oxide semiconductor
  • the memory module usually has a structure composed of a metal oxide semiconductor (MOS) tube and a magnetic tunnel junction (MTJ). As shown in FIG. 1A, the memory module has three The two endpoints are word line (WL), bit line (BL), and source line (SL).
  • WL word line
  • BL bit line
  • SL source line
  • MTJ consists of a thin tunneling oxide layer (such as MgO) sandwiched between two ferromagnetic layers.
  • one of the ferromagnetic layers has a fixed magnetization direction, which is called a fixed layer; the other layer
  • the magnetization direction of a ferromagnetic layer can be freely reversed, which is called a free layer.
  • the resistance of the MTJ shows a lower resistance value.
  • the resistance of the MTJ appears to be lower. High resistance.
  • the existing solution provides a circuit capable of achieving self-termination for various write situations.
  • this solution adds a variable energy write (VEW) circuit to each column of the storage array. And its output controls a transmission gate connecting the bit line and the write circuit.
  • the VEW circuit includes two branches, which are respectively for the write AP state and the write P state, and each includes an inverter with a specially adjusted threshold for monitoring the write AP state and the write P state respectively. The voltage on the bit line changes and a corresponding signal is output. Because the VEW circuit introduces units such as flip-flops, static power consumption occurs even when no writing is needed, increasing the total power consumption of the circuit.
  • the embodiments of the present application provide a self-terminating write circuit and method, which are used to implement self-termination for memory array circuits in different states through the same control circuit, which reduces the circuit's overhead area and power consumption.
  • a first aspect of the embodiments of the present application provides a self-terminating write circuit, including: a sense amplifier 201 and a control circuit 202; the sense amplifier 201 is used to compare a reference voltage or a reference current output from a reference circuit 203 with an output of a memory array circuit 204 The control circuit 202 is used to generate a termination signal according to the comparison result, and feedback the termination signal to the memory array circuit 204. The termination signal is used to control the memory array circuit 204 to stop writing Into P state or AP state.
  • a termination write control circuit composed of a sensitive amplifier and a control circuit realizes self-termination of the write P state or AP state, which saves the circuit area of the circuit and reduces power consumption.
  • the self-terminating write circuit further includes the reference circuit 203, wherein: the resistance value of the reference circuit 203 is greater than a first threshold value and less than a second threshold value; the resistance value when the memory array circuit 204 is in the P state It is equal to the first threshold, and the resistance when the memory array circuit 204 is in the AP state is equal to the second threshold.
  • the resistance value of the reference circuit is limited, and the resistance range of the reference circuit is clarified, so that the reference voltage or current provided by the reference circuit for the sensitive amplifier is different from the voltage or current in the storage unit.
  • the reference circuit includes: a first branch and a second branch, a first end of the first branch is electrically connected to a first end of the second branch, and the first branch The second end of the circuit is electrically connected to the second end of the second branch.
  • the second end of the first branch is electrically connected to the second end of the second branch and outputs a reference voltage or reference current to the sense amplifier 201.
  • the first end of the first branch and the first end of the second branch are electrically connected to a voltage source.
  • the first branch includes N series magnetic tunnel junctions, and the second branch includes N series magnetic tunnels. Tunneling junction, N is a positive integer greater than 1.
  • the first branch includes a first magnetic tunneling junction 2031 and a third magnetic tunneling junction 2033
  • the second branch includes a second magnetic tunneling junction 2032 and a fourth magnetic tunneling junction 2034.
  • the free layer end of the first magnetic tunneling junction 2031 and the fixed layer end of the third magnetic tunneling junction 2033 are electrically connected, the free layer end of the second magnetic tunneling junction 2032 and the fixed layer of the fourth magnetic tunneling junction 2034.
  • the first magnetic tunnel junction 2031 is electrically connected to a voltage source.
  • the first magnetic tunnel junction 2031 is in an AP state
  • the second magnetic tunnel is electrically connected to a voltage source.
  • the piercing junction 2032 is in the P state
  • the third magnetic tunneling junction 2033 is in the P state
  • the fourth magnetic tunneling junction 2034 is in the AP state.
  • a specific structure of the reference circuit is provided to ensure that the resistance of the reference circuit is greater than the resistance value in the P state and less than the resistance value in the AP state, so that the reference voltage or current of the reference circuit The voltage or current varies, and the signal at the output of the sense amplifier is inverted.
  • the storage array circuit includes: a first field effect transistor P1, a second field effect transistor P2, a third field effect transistor N1, a fourth field effect transistor N2, a fifth field effect transistor N3, and A plurality of memory modules, each of which includes a magnetic tunnel junction and a field effect transistor, wherein: a bit line end of each memory module is connected to a source of the first field effect transistor P1 and a third field effect transistor N1
  • the drain is electrically connected, the source line end of each memory module, the source of the second field effect transistor P2 and the drain of the fourth field effect transistor N2 are electrically connected; the drain of the first field effect transistor P1 and the first transmission gate
  • the first terminal of the second field-effect transistor P2 is electrically connected to the first terminal of the second transmission gate, the source of the third field-effect transistor N1, the source of the fourth field-effect transistor N2, and the fifth
  • the drain of the field effect transistor N3 is electrically connected, the gate of the fifth field effect transistor N3 and the drain of the fifth field effect transistor N3
  • the sensitive amplifier includes: a differential amplifier and a tri-state gate 2011, wherein an output terminal of the tri-state gate 2011 is electrically connected to an output terminal of the differential amplifier after being inverted, and the tri-state gate 2011 is The input terminal receives an input data signal, and the control terminal of the tri-state gate 2011 is electrically connected to the word line of the memory array circuit 204 after being inverted; the first input terminal of the differential amplifier is connected to the gate of the fifth field effect transistor N3 of the memory array circuit 204 The second input terminal of the differential amplifier is electrically connected to the reference circuit 203 to receive the reference voltage or current. The output terminal of the differential amplifier outputs a comparison result.
  • the electrical connection relationship between the tri-state gate and the differential amplifier is refined. The opening or closing of the tri-state gate is used to control the difference amplifier to compare the reference voltage or reference current with the voltage or current of the storage array.
  • the differential amplifier includes a sixth field effect transistor P3, a seventh field effect transistor P4, an eighth field effect transistor N4, a ninth field effect transistor N5, a tenth field effect transistor N6, and a tenth field effect transistor.
  • Twelfth field effect The source of the transistor N8 is grounded, the drain of the sixth field-effect transistor P3 is electrically connected to the voltage source, and the drain of the seventh field-effect transistor P4 is electrically connected to the voltage source; the output terminal of the tri-state gate 2011 and the seventh field effect
  • the source of the transistor P4 and the drain of the ninth field effect transistor N5 are electrically connected to the output terminal of the sense amplifier 201.
  • the gate of the eighth field effect transistor N4 is electrically connected to the gate of the fifth field effect transistor N3 of the memory array circuit 204. connection.
  • a specific structure of the sensitive amplifier is provided to ensure that the sensitive amplifier can compare the reference voltage or reference current of the reference circuit with the voltage or current of the memory array circuit, and generate a corresponding output terminal signal to the control circuit.
  • the control circuit includes an exclusive OR gate 2021 and a first AND gate 2022, wherein a first input end of the exclusive OR gate 2021 is electrically connected to an input data signal line, and the exclusive OR gate 2021
  • the second input terminal of is electrically connected to the output terminal of the sense amplifier 201.
  • the first input terminal of the XOR gate 2021 receives an input data signal.
  • the second input terminal of the XOR gate 2021 receives a comparison result of the sense amplifier 201.
  • the output terminal of the OR gate 2021 is electrically connected to the first input terminal of the first AND gate 2022, the third terminal of the first transmission gate of the memory array circuit 204, and the third terminal of the second transmission gate of the memory array circuit 204.
  • the OR gate 2021 is used to output a termination signal according to the input data signal and the comparison result; the second input terminal of the first AND gate 2022 is electrically connected to the word line, and the third input terminal of the first AND gate 2022 is electrically connected to the write enable signal line.
  • the output terminal of the first AND gate 2022 is electrically connected to the gate of the tenth field effect transistor N6 of the sense amplifier 201.
  • the signal at the output terminal of the first AND gate 2022 is used to control the on or off of the sense amplifier 201; the memory array circuit First transmission of 204
  • the third end of the storage array circuit 204 receives the termination signal, and the third end of the second transmission gate of the memory array circuit 204 receives the termination signal.
  • the termination signal When the termination signal is valid, the first transmission gate and the second transmission gate of the storage array circuit 204 are closed at the same time. When the termination signal is invalid, the first transmission gate and the second transmission gate of the memory array circuit 204 are simultaneously opened.
  • a structural composition of the control circuit is provided to ensure that the control circuit can generate a termination signal according to the comparison result of the sense amplifier, and control the on and off of the sense amplifier.
  • the control circuit further includes: a second AND gate 2023, a third AND gate 2024, an OR gate 2025, and an inverter chain 2026; the inverter chain 2026 includes an odd number of sequentially electrically connected NOT gate; the output of the first AND gate 2022, the first input of the second AND gate 2023, the input of the inverter chain 2026 and the first input of the third AND gate 2024 are electrically connected, and the inverter chain
  • the output of 2026 is electrically connected to the second input of the second AND gate 2023, the output of the second AND gate 2023 is electrically connected to the first input of the OR gate 2025, and the output of the third AND gate 2024 is ANDed to the OR gate 2025
  • the second input of the third AND gate 2024 is electrically connected to an external delay circuit.
  • the external delay circuit is used to provide an external signal to control the output of the third AND gate 2024 after a certain delay.
  • a signal, or an output signal of the OR gate 2025, is used to control the on or off of the sense amplifier 201.
  • another structural composition of the control circuit is provided to ensure that the control circuit can generate a termination signal according to the comparison result of the sense amplifier, and control the on and off of the sense amplifier, reduce the time to control the on of the sense amplifier, and further reduce Power consumption.
  • the inverter chain 2026 includes a first NOT gate 20261, a second NOT gate 20262, and a third NOT gate 20263; the input of the first NOT gate 20261 and the output of the first AND gate 2022
  • the input of the second NOT gate 20262 is electrically connected to the output of the first NOT gate 20261; the input of the third NOT gate 20263 is electrically connected to the output of the second NOT gate 20262;
  • the output terminal is electrically connected to the second input terminal of the second AND gate 2023.
  • a second aspect of the embodiments of the present application provides a self-terminating writing method, which is applied to a self-terminating writing circuit, and includes: comparing a reference voltage or a reference current output from a reference circuit 203 with a voltage output from a memory array circuit 204 through a sense amplifier 201 Or the magnitude of the current, and feedback the comparison result to the control circuit 202; the control circuit 202 generates a termination signal according to the comparison result, and feedbacks the termination signal to the memory array circuit 204, which is used to control the memory array circuit 204 to stop writing to the P state Or AP status.
  • a self-terminating writing method is provided.
  • a termination writing control circuit composed of a sensitive amplifier and a control circuit is used to realize self-termination of writing the P state or AP state, which saves the circuit area and reduces power consumption.
  • the step of generating a termination signal according to the comparison result by the control circuit 202 and feeding back the termination signal to the memory array circuit 204 includes: determining whether the input data signal and the comparison result are at the same level through an exclusive OR gate 2021; When the input data signal and the comparison result are at the same level, a valid termination signal is generated by the exclusive OR gate 2021 and the valid termination signal is sent to the memory array circuit 204; when the input data signal and the comparison result are at different levels, the exclusive OR is passed The gate 2021 generates an invalid termination signal and sends the invalid termination signal to the memory array circuit 204.
  • the process of generating a termination signal and feeding back the termination signal to the memory array circuit is refined, and an implementation manner of the embodiment of the present application is added.
  • the step of generating a termination signal by the control circuit 202 according to the comparison result, and feeding back the termination signal to the memory array circuit 204 includes: when the memory array circuit is in a write preparation stage, controlling the write enable signal from being invalid The level is adjusted to an effective level, and the word line signal is controlled to an inactive level.
  • the word line signal is adjusted from an inactive level to an effective level; when the memory array circuit finishes writing to the AP, In the state, the input data signal is controlled to the effective level corresponding to the AP state; when the memory array circuit finishes writing the P state, the input data signal is controlled to the effective level corresponding to the P state.
  • a self-terminating writing method is provided.
  • a termination writing control circuit composed of a sensitive amplifier and a control circuit is used to realize self-termination of writing the P state or AP state, which saves the circuit area and reduces power consumption.
  • the write enable signal when the memory array circuit is in the initial stage of writing, the write enable signal is controlled to be an active level, and the word line signal is adjusted from an inactive level to an active level; when the memory array circuit finishes writing In the AP state, the write enable signal is controlled to be an active level, the word line signal is controlled to be an active level, and the input data signal is controlled to the active level corresponding to the AP state; when the memory array circuit finishes writing to the P state, the write enable is controlled The energy signal is an effective level, the control word line signal is an effective level, and the input data signal is controlled to be an effective level corresponding to the P state.
  • the specific signal control method is refined to ensure that the self-terminating writing circuit can control the self-termination of the writing state process according to different signals.
  • the self-terminating writing circuit includes: a sense amplifier 201 and a control circuit 202; the sense amplifier 201 is used to compare a reference voltage or a reference current output from the reference circuit 203 with the output of the memory array circuit 204 Voltage or current, and feedback the comparison result to the control circuit 202; the control circuit 202 is used to generate a termination signal and feedback the termination signal to the memory array circuit 204 according to the comparison result, and the termination signal is used to control the memory array circuit 204 to stop writing to P Status or AP status.
  • a termination write control circuit composed of a sense amplifier and a control circuit is used to realize self-termination of the write P state or the AP state, which saves the circuit area and reduces power consumption.
  • FIG. 1A is a schematic diagram of a structure of a memory module and a current direction when writing a P or AP state
  • 1B is a schematic diagram of the magnetization direction when the magnetic tunneling junction is in the P state and the magnetization direction when in the AP state;
  • FIG. 1C is a schematic structural diagram of a self-terminating write circuit of the existing scheme
  • FIG. 2 is a schematic structural diagram of a self-terminating write circuit in this application
  • FIG. 3 is another schematic structural diagram of a self-terminating write circuit in the present application.
  • FIG. 4 is another schematic structural diagram of a self-terminating write circuit in the present application.
  • FIG. 5 is a schematic diagram of an embodiment of a self-terminating writing method in the present application.
  • FIG. 6 is a schematic waveform diagram of writing an AP state to a storage array circuit in an AP state in the present application
  • FIG. 7 is a waveform diagram of writing an AP state to a memory array circuit in a P state in the present application.
  • the embodiments of the present application provide a self-terminating write circuit and method, which are used to implement self-termination for memory array circuits in different states through the same control circuit, which reduces the circuit's overhead area and power consumption.
  • references to "including” or “having” and any variations thereof in this application document are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that contains a series of steps or circuits need not be limited to Those steps or circuits that are explicitly listed may instead include other steps or circuits that are not explicitly listed or inherent to these processes, methods, products, or equipment.
  • STT-MRAM spin-transfer torque magnetic memory
  • RRAM resistive memory random access memory
  • This application provides a self-terminating writing circuit. Please refer to FIG. 2.
  • An embodiment of the self-terminating writing circuit in the embodiment of the present application includes:
  • the sense amplifier 201 is used to compare the reference voltage or current output from the reference circuit 203 with the voltage or current output from the memory array circuit 204, and feedback the comparison result to the control circuit 202;
  • the control circuit 202 is configured to generate a termination signal write_stop according to the comparison result and feedback the termination signal to the memory array circuit 204.
  • the termination signal is used to control the memory array circuit 204 to stop writing to the P state or the AP state.
  • the electrical connection may be a physical direct electrical connection, or an electrical electrical connection may be achieved through a field effect transistor (FET) or other components, which are not specifically limited here.
  • FET field effect transistor
  • the present application can indirectly compare the resistance of the reference circuit and the resistance of the storage array.
  • Those skilled in the art can compare the reference voltage and the storage array according to the actual situation.
  • the voltage of the circuit is converted into a current. Comparing the currents of the two, the resistance values of the reference circuit and the memory array circuit can also be determined, and details are not repeated here.
  • the reference voltage or reference current of the reference circuit and the voltage or current of the memory array circuit are compared by the sense amplifier, and the output terminal signal of the sense amplifier is sent to the control circuit according to the comparison result, so that the control circuit generates the
  • the termination signal controls the memory array circuit to stop writing.
  • a termination write control circuit composed of a sensitive amplifier and a control circuit realizes self-termination of the write P state or AP state, which saves the circuit area and reduces power consumption.
  • the self-terminating writing circuit further includes a reference circuit 203, where:
  • the resistance of the reference circuit 203 is greater than a first threshold and less than a second threshold
  • the resistance value when the memory array circuit 204 is in the P state is equal to the first threshold value, and the resistance value when the memory array circuit 204 is in the AP state is equal to the second threshold value.
  • the sense amplifier 201 and the reference circuit 203 can be specially designed to be added to the circuit, or the sense amplifier and the reference circuit already existing in the circuit can be modified to realize sharing, thereby saving circuit area.
  • a reference circuit can be used to provide a reference voltage or reference current for multiple sensitive amplifiers, or a reference circuit can be fixed to provide a reference voltage or reference current for a corresponding sensitive amplifier, which is not limited here.
  • the resistance value of the reference circuit is limited, and the resistance range of the reference circuit is clarified, so that the reference voltage or current provided by the reference circuit for the sensitive amplifier is different from the voltage or current in the storage unit.
  • the reference circuit includes:
  • a first branch and a second branch the first end of the first branch is electrically connected to the first end of the second branch, and the second end of the first branch is connected to the second end of the second branch Terminals are electrically connected, the second end of the first branch is electrically connected to the second end of the second branch and outputs a reference voltage or reference current to the sense amplifier 201, the first end of the first branch and the second branch
  • the first end of the branch is electrically connected to the voltage source.
  • the first branch includes N magnetic tunnel junctions connected in series
  • the second branch includes N magnetic tunnel junctions connected in series.
  • N is a positive integer greater than 1.
  • the specific composition of the reference circuit is detailed, and the connection relationship between the reference circuit and the sense amplifier is clarified, so that the reference circuit provides a reference voltage or a reference current for the sense amplifier.
  • the first branch includes a first magnetic tunneling junction 2031 and a third magnetic tunneling junction 2033
  • the second branch includes a second magnetic tunneling junction 2032 and a first magnetic tunneling junction 2032.
  • Four magnetic tunneling junction 2034 wherein the free layer end of the first magnetic tunneling junction 2031 and the fixed layer end of the third magnetic tunneling junction 2033 are electrically connected, and the free layer end of the second magnetic tunneling junction 2032 and the fourth magnetic field
  • the fixed layer end of the tunneling junction 2034 is electrically connected, the fixed layer end of the first magnetic tunneling junction 2031 and the fixed layer end of the second magnetic tunneling junction 2032 are electrically connected to the voltage source;
  • the first magnetic tunneling junction 2031 is an AP State
  • the second magnetic tunneling junction 2032 is in the P state
  • the third magnetic tunneling junction 2033 is in the P state
  • the fourth magnetic tunneling junction 2034 is in the AP state.
  • the positions of the first magnetic tunneling junction 2031 and the third magnetic tunneling junction 2033 can be exchanged, and the positions of the second magnetic tunneling junction 2032 and the fourth magnetic tunneling junction 2034 can also be exchanged, as long as Ensure that the total resistance of the reference circuit is between the resistance value of the P state and the resistance value of the AP state, where the resistance value of the P state and the resistance value of the AP state are fixed, within the error range of the magnetic tunnel junction, The resistance of the P state and the resistance of the AP state may fluctuate by ⁇ 5%.
  • a specific structure of a reference circuit is provided to ensure that the resistance value of the reference circuit is greater than the resistance value in the P state and less than the resistance value in the AP state, so that the reference voltage or reference current of the reference circuit Different from the voltage or current of the memory array circuit, the signal at the output of the sense amplifier is inverted.
  • the memory array circuit includes:
  • the bit line terminal of each memory module is electrically connected to the source of the first field effect transistor P1 and the drain of the third field effect transistor N1.
  • the source line terminal of each memory module and the source of the second field effect transistor P2 are The drain of the fourth field effect transistor N2 is electrically connected;
  • the drain of the first field effect transistor P1 is electrically connected to the first end of the first transmission gate
  • the drain of the second field effect transistor P2 is electrically connected to the first end of the second transmission gate
  • the source of the third field effect transistor N1 The source of the fourth field effect transistor N2 is electrically connected to the drain of the fifth field effect transistor N3, the gate of the fifth field effect transistor N3 and the drain of the fifth field effect transistor N3 are electrically connected to the sense amplifier 201
  • the source of the fifth field-effect transistor N3 is grounded, the second end of the first transmission gate is electrically connected to the voltage source, and the second end of the second transmission gate is electrically connected to the voltage source.
  • the level of the input data signal input_date results in different conduction conditions of the field effect transistors in the memory array. For example, when the input data signal is low, write 0 (write to AP status) ), The third field effect transistor N1 and the second field effect transistor P2 are turned on, the gate of the second field effect transistor P2 receives the write 0 signal, and the gate of the third field effect transistor N1 receives the reverse signal of the write 0 signal ( Write 1 signal); when the input data signal is high level, that is, write 1 (write P state), the fourth field effect transistor N2 and the first field effect transistor P1 are turned on, and the gate of the first field effect transistor P1 The write 1 signal is received, and the gate of the fourth field effect transistor N2 receives the reverse signal (write 0 signal) of the write 1 signal.
  • a specific structure of the memory array circuit is provided to ensure that the memory array circuit can write different states to the memory module according to an input data signal.
  • the sense amplifier includes:
  • the output terminal of the tri-state gate 2011 is electrically connected to the output terminal of the differential amplifier after being inverted.
  • the input terminal of the tri-state gate 2011 receives the input data signal. Electrical connection
  • the first input terminal of the differential amplifier is electrically connected to the gate of the fifth field effect transistor N3 of the memory array circuit 204 to receive the voltage or current output from the memory array circuit 204.
  • the second input terminal of the differential amplifier is electrically connected to the reference circuit 203. Connected to receive a reference voltage or reference current, the output of this differential amplifier outputs a comparison result.
  • the electrical connection relationship between the tri-state gate and the differential amplifier is refined, and the differential amplifier is controlled by opening or closing the tri-state gate to compare the reference voltage or reference current with the voltage or current of the storage array.
  • the differential amplifier includes a sixth field effect transistor P3, a seventh field effect transistor P4, an eighth field effect transistor N4, a ninth field effect transistor N5, a first Ten field-effect transistors N6, eleventh field-effect transistors N7, and twelfth field-effect transistors N8, of which:
  • the gate of the sixth field effect transistor P3 is electrically connected to the gate of the seventh field effect transistor P4.
  • the electrodes are electrically connected.
  • the source of the seventh field effect transistor P4 is electrically connected to the drain of the ninth field effect transistor N5.
  • the drain of the transistor N6, the gate of the tenth field effect transistor N6 is electrically connected to the gate of the eleventh field effect transistor N7, the source of the eleventh field effect transistor N7, and the drain of the twelfth field effect transistor N8.
  • the gate of the twelfth field effect transistor N8 is electrically connected to the gate of the ninth field effect transistor N5, the source of the tenth field effect transistor N6 is grounded, the source of the twelfth field effect transistor N8 is grounded, and the sixth field
  • the drain of the effect transistor P3 is electrically connected to the voltage source, and the drain of the seventh field effect transistor P4 is electrically connected to the voltage source;
  • the output terminal of the three-state gate 2011, the source of the seventh field-effect transistor P4, and the drain of the ninth field-effect transistor N5 are electrically connected to the output terminal of the sense amplifier 201.
  • the gates of the fifth field-effect transistor N3 of the circuit 204 are electrically connected.
  • the resistance of the reference circuit and the resistance of the storage array circuit are indirectly compared by comparing the reference voltage or the reference current of the reference circuit with the voltage or current of the storage array circuit.
  • the resistance of the reference circuit and the resistance of the memory array circuit can also be compared indirectly by comparing the current of the reference circuit and the current of the memory array, which will not be described in detail here.
  • the specific structure of the sensitive amplifier is provided in this implementation to ensure that the sensitive amplifier can compare the reference voltage or current of the reference circuit with the voltage or current of the memory array circuit, and generate the corresponding output signal to the control. Circuit.
  • control circuit includes:
  • a first input terminal of the XOR gate 2021 is electrically connected to an input data signal line, a second input terminal of the XOR gate 2021 is electrically connected to an output terminal of the sense amplifier 201, and a first input terminal of the XOR gate 2021 receives an input.
  • Data signal the second input of the XOR gate 2021 receives the comparison result of the sense amplifier 201, the output of the XOR gate 2021 and the first input of the first AND gate 2022, the first transmission gate of the memory array circuit 204
  • the third terminal of the second terminal is electrically connected to the third terminal of the second transmission gate of the memory array circuit 204, and the XOR gate 2021 is configured to output a termination signal according to the input data signal and the comparison result;
  • the second input terminal of the first AND gate 2022 is electrically connected to the word line, the third input terminal of the first AND gate 2022 is electrically connected to the write enable signal line, and the output terminal of the first AND gate 2022 is connected to the first
  • the gate of the ten field effect transistor N6 is electrically connected, and the output signal of the first AND gate 2022 is used to control the on or off of the sense amplifier 201;
  • the third end of the first transmission gate of the memory array circuit 204 receives a termination signal, and the third end of the second transmission gate of the memory array circuit 204 receives a termination signal, wherein when the termination signal is valid, the memory array circuit ( 204)
  • the first transmission gate and the second transmission gate are closed at the same time.
  • the termination signal is invalid, the first transmission gate and the second transmission gate of the memory array circuit (204) are opened at the same time.
  • control circuit in this implementation manner can be replaced, for example, the function of the first AND gate is realized by other components, as long as the same function of the control circuit can be realized under the same conditions, other implementations
  • the method is similar, and is not specifically limited here.
  • a structural composition of the control circuit is provided to ensure that the control circuit can generate a termination signal write_stop according to the comparison result of the sense amplifier, and control the on and off of the sense amplifier.
  • control circuit further includes:
  • the inverter chain 2026 includes an odd number of NOT gates electrically connected in sequence
  • the output of the first AND gate 2022, the first input of the second AND gate 2023, the input of the inverter chain 2026 are electrically connected to the first input of the third AND gate 2024, and the output of the inverter chain 2026 Is electrically connected to the second input of the second AND gate 2023, the output of the second AND gate 2023 is electrically connected to the first input of the OR gate 2025, and the output of the third AND gate 2024 is electrically connected to the second of the OR gate 2025
  • the input is electrically connected, and the second input of the third AND gate 2024 is electrically connected to an external delay circuit.
  • the external delay circuit is used to provide an external signal to control the signal of the output of the third AND gate 2024 after a certain delay, or
  • the output signal of the gate 2025 is used to control the on or off of the sense amplifier 201.
  • the second AND gate 2023 and the inverter chain 2026 form a first branch, and the first branch is used to handle the writing of the same state.
  • the storage array has stored the P state, and the input data signal is written. 1 signal, that is, the P state is written to the storage array again; the storage array has stored the AP state, and the input data signal is a write 0 signal, that is, the AP state is written to the storage array again.
  • the third AND gate 2024 constitutes a second branch separately. This second branch is used to handle the writing of different states.
  • the storage array has stored the P state, and the input data signal is the write 0 signal, that is, the data is written to the storage array again. Enter the AP state; the storage array has stored the AP state, and the input data signal is a write 1 signal, that is, the P state is written to the storage array again.
  • control circuit can generate a stop signal write_stop according to the comparison result of the sense amplifier, and control the on and off of the sense amplifier, reducing the time for controlling the on of the sense amplifier, and further reducing Low power consumption.
  • the inverter chain 2026 includes a first NOT gate 20261, a second NOT gate 20262, and a third NOT gate 20263.
  • An input terminal of the first NOT gate 20261 is electrically connected to an output terminal of the first AND gate 2022.
  • An input terminal of the second NOT gate 20262 is electrically connected to an output terminal of the first NOT gate 20261.
  • An input terminal of the third NOT gate 20263 is electrically connected to an output terminal of the second NOT gate 20262.
  • An output terminal of the third NOT gate 20263 is electrically connected to a second input terminal of the second AND gate 2023.
  • the specific composition of the inverter chain is limited, and the output signal of the first AND gate is delayed so that the controller circuit can temporarily output a high-level control signal.
  • an embodiment of the present application provides a self-terminating writing method, which is applied to the self-terminating writing circuit involved in the foregoing embodiments and various implementation manners, including:
  • the reference voltage or reference current output by the reference circuit is compared with the voltage or current output by the memory array circuit through a sense amplifier, and the comparison result is fed back to the control circuit.
  • the self-termination writing circuit compares the reference voltage or reference current output from the reference circuit 203 with the voltage or current output from the memory array circuit 204 through the sense amplifier 201, and feeds back the comparison result to the control circuit 202.
  • the write control enable signal is adjusted from an inactive level to an active level, and the word line signal is controlled to an inactive level.
  • the control write enable signal is adjusted from a low level to a high level, and the control word line signal is controlled to a low level, so that the tri-state gate is opened and the control signal is low.
  • Level, low level control signal controls the sensitive amplifier 201 to turn off, the output signal of the sensitive amplifier 201 maintains the opposite level to the input data signal, the termination signal is high level, and the high level termination signal is invalid. level.
  • the write enable signal is low level
  • the termination signal generated by the control circuit is low level
  • the memory array circuit 204 cannot write data ( status).
  • the write enable signal can be valid when the level is high, or it can be valid when the level is low (the circuit needs to be adjusted accordingly).
  • the input data signal can be high or low Level (the circuit needs to be adjusted accordingly, for example, adding a signal inversion module, specifically, the signal inversion module may be composed of an odd number of NOT gates), for convenience of description, this application is directed to the above-mentioned FIG. 3 and FIG. 4
  • the self-terminating write circuit is described in conjunction with specific components.
  • the write enable signal is controlled to be an effective level, and the word line signal is adjusted from an inactive level to an effective level.
  • the write enable signal is maintained at a high level, and the word line signal is adjusted from a low level to a high level, so that the tri-state gate is closed, and the control signal is changed from a low power.
  • the level is changed to a high level (that is, changed from an inactive level to an effective level).
  • the high-level control signal controls the sensitive amplifier 201 to be turned on.
  • the output signal of the sensitive amplifier 201 maintains an opposite level to the input data signal, and the termination signal It is high level, and the high-level termination signal is invalid level.
  • control the write enable signal to be an effective level
  • control the word line signal to be an effective level
  • control the input data signal to be an effective level corresponding to the AP state.
  • the write enable signal is maintained at a high level
  • the word line signal is maintained at a high level
  • the input data signal is controlled to be a low level (corresponding to the active level of the AP state).
  • the control signal changes from high level to low level (that is, from active level to inactive level)
  • the low level control signal controls the sensitive amplifier 201 to turn off
  • the termination signal changes from high level to low level (Ie, from an inactive level to an active level)
  • the memory array circuit 204 terminates the write AP state.
  • the waveforms of the various signals are shown in FIG. 6; When it is in the P state and needs to be written in the AP state), the waveform of each signal is shown in FIG. 7.
  • the signal out of the output terminal of the sense amplifier 201 can be quickly after the writing starts. It is flipped to "0" (that is, low level), so that the termination signal write_stop is 0, thereby achieving self-termination and avoiding unnecessary repeated writing. If the memory array circuit 204 is originally in the P state, after the writing is started, the output signal out of the sense amplifier 201 needs to wait until the state of the memory array circuit 204 is written as the AP state, and then becomes "0". In the case of the correct writing of the state, the write self-termination is realized.
  • control the write enable signal to be an effective level
  • control the word line signal to be an effective level
  • control the input data signal to be an effective level corresponding to the P state.
  • the write enable signal is kept at a high level
  • the word line signal is kept at a high level
  • the input data signal is controlled to be at a high level (corresponding to the active level of the P state).
  • the control signal changes from high level to low level (that is, from active level to inactive level)
  • the low level control signal controls the sensitive amplifier 201 to turn off
  • the termination signal changes from high level to low level ( That is, from the inactive level to the active level)
  • the memory array circuit 204 terminates the write P state.
  • the output signal of the sensitive amplifier can be quickly It is flipped to "1" (that is, high level), so that the termination signal write_stop is 0, thereby achieving self-termination and avoiding unnecessary repeated writing.
  • the output signal of the sense amplifier needs to wait until the state of the memory array circuit 204 is written to the P state before it becomes "1". In the guaranteed state Implements self-termination with correct writes.
  • the valid signal output by the second AND gate 2023 is turned off after a certain delay through the inverter chain 2026 in the first branch.
  • the second input terminal of the third AND gate 2024 in the second branch receives the delay signal of the external delay circuit, so that the output signal of the third AND gate 2024 is valid after a certain delay.
  • step 504 and step 505 are side-by-side steps, and one of the steps is performed at the same time, and details are not described herein again.
  • the memory array circuit by controlling the high and low levels of each signal, the memory array circuit is self-terminated after completing the state write, which saves the overhead area of the self-termination write circuit and reduces power consumption.
  • the disclosed device may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the circuit is only a logical function division.
  • multiple circuits or components may be combined or Can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or circuits, and may be electrical, mechanical or other forms.
  • circuits described as separate components may or may not be physically separated, and the components shown as circuits may or may not be physical circuits, that is, they may be located in one place, or may be distributed on multiple network circuits. Some or all of the circuits may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • the functional circuits in the embodiments of the present application may be integrated into one processing circuit, or each of the circuits may exist separately physically, or two or more circuits may be integrated into one circuit.
  • the above integrated circuit can be implemented in the form of hardware or in the form of software functional circuits.

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Abstract

本申请公开了一种自终止写入电路及方法，用于对处于不同状态的存储阵列电路通过同一个自终止写入控制电路实现自终止。本申请自终止写入电路，包括：灵敏放大器（201）和控制电路（202）；灵敏放大器（201）用于比较参考电路（203）输出的参考电压或参考电流和存储阵列电路（204）输出的电压或电流大小；控制电路（202）用于根据比较结果生成终止信号，并反馈所述终止信号至所述存储阵列电路（204），所述终止信号用于控制所述存储阵列电路（204）停止写入P状态或AP状态。在存储阵列电路（204）完成状态写入后实现写入自终止，节省了电路的开销面积，降低了功耗。

Description

一种自终止写入电路及方法 技术领域
本申请涉及电路领域，尤其涉及一种自终止写入电路及方法。
背景技术
自旋转移矩磁存储器(Spin-transfer torque magnetic random access memory，STT-MRAM)是一种极具潜力的新型存储器，具有读取速度较快，耐久(endurance)周期数长，集成度高，与互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺兼容等优点。
在STT-MRAM中，存储模块通常为由一个金属氧化物半导体(metal oxide semiconductor，MOS)管和一个磁隧穿结(magnetic tunnel junction，MTJ)组成的结构，如图1A所示，存储模块有三个端点，分别为字线(word line，WL)、位线(bit line，BL)、源线(source line，SL)。读取时，存储信息取决于读取到的MTJ的阻值，其电流方向可以是任意的；写入时，写入特定的状态(P状态或AP状态)需要采用相对应的电流方向，如图1A所示。MTJ由两层铁磁层中间夹一层很薄的隧穿氧化层(例如MgO)组成，如图1B所示，其中一层铁磁层其磁化方向是固定，称为固定层；另一层铁磁层其磁化方向可以自由翻转，称为自由层。当自由层的磁化方向与固定层平行时(即P状态)，MTJ的电阻呈现较低的阻值，当自由层的磁化方向与固定层平行相反时(即AP状态)，MTJ的电阻呈现较高的阻值。
现有方案中提供了一种能够针对各种写入情况实现自终止的电路，如图1C所示，该方案在存储阵列的每一列加入了可变能量写入(variable energy write，VEW)电路，并且其输出控制了一个传输门连接位线和写入电路。VEW电路中包含两条支路，分别针对写入AP状态和写入P状态两种情况，并且各包含一个阈值经过特殊调整的反相器，用于分别监测写AP状态和写P状态完成后在位线上的电压变化，并输出对应的信号。由于VEW电路引入了触发器等单元，即使在不需要写入的情况下也会静态功耗，增加了电路的总功耗。
发明内容
本申请实施例提供了一种自终止写入电路及方法，用于对处于不同状态的存储阵列电路通过同一个控制电路实现自终止，减小了电路的开销面积，降低了功耗。
本申请实施例的第一方面提供一种自终止写入电路，包括：灵敏放大器201和控制电路202；该灵敏放大器201用于比较参考电路203输出的参考电压或参考电流和存储阵列电路204输出的电压或电流大小，并将比较结果反馈至控制电路202；该控制电路202用于根据比较结果生成终止信号，并反馈终止信号至存储阵列电路204，终止信号用于控制存储阵列电路204停止写入P状态或AP状态。通过灵敏放大器比较参考电路的参考电压或参考电流和存储阵列电路的电压或电流大小，根据比较结果将灵敏放大器的输出端信号发送至控制电路，以使得控制电路生成的终止信号控制存储阵列电路停止写入。通过灵敏放大器、控制电路构成的一个终止写入控制电路，实现对写入P状态或AP状态的自终止，节 省了电路的开销面积，降低了功耗。
在一种可能的设计中，自终止写入电路还包括所述参考电路203，其中：参考电路203的阻值大于第一阈值且小于第二阈值；存储阵列电路204处于P状态时的阻值等于第一阈值，存储阵列电路204处于AP状态时的阻值等于第二阈值。对参考电路的阻值大小进行了限定，明确了参考电路的阻值范围，以使得参考电路为灵敏放大器提供的参考电压或参考电流与存储单元中的电压或电流存在差异。
在一种可能的设计中，所述参考电路包括：第一支路和第二支路，该第一支路的第一端与该第二支路的第一端电连接，该第一支路的第二端与该第二支路的第二端电连接，该第一支路的第二端和该第二支路的第二端电连接并输出参考电压或参考电流至灵敏放大器201，该第一支路的第一端和该第二支路的第一端与电压源电连接，第一支路包括N个串联的磁隧穿结，第二支路包括N个串联的磁隧穿结，N为大于1的正整数。细化了参考电路的具体组成，明确了参考电路和灵敏放大器的连接关系，以使得参考电路为灵敏放大器提供参考电压或参考电流。
在一种可能的设计中，第一支路包括第一磁隧穿结2031和第三磁隧穿结2033，第二支路包括第二磁隧穿结2032和第四磁隧穿结2034，其中，第一磁隧穿结2031的自由层端和第三磁隧穿结2033的固定层端电连接，第二磁隧穿结2032的自由层端和第四磁隧穿结2034的固定层端电连接，第一磁隧穿结2031的固定层端和第二磁隧穿结2032的固定层端与电压源电连接；该第一磁隧穿结2031为AP状态，该第二磁隧穿结2032为P状态，该第三磁隧穿结2033为P状态，该第四磁隧穿结2034为AP状态。本实现方式中，提供了参考电路的一种具体结构，确保参考电路的阻值大于P状态的阻值且小于AP状态的阻值，以使得参考电路的参考电压或参考电流与存储阵列电路的电压或电流大小不同，灵敏放大器的输出端信号发生翻转。
在一种可能的设计中，所述储阵列电路包括：第一场效应晶体管P1、第二场效应晶体管P2、第三场效应晶体管N1、第四场效应晶体管N2、第五场效应晶体管N3及多个存储模块，每个存储模块中包含一个磁隧穿结和一个场效应晶体管，其中：每个存储模块的位线端与第一场效应晶体管P1的源极、第三场效应晶体管N1的漏极电连接，每个存储模块的源线端、第二场效应晶体管P2的源极和第四场效应晶体管N2的漏极电连接；第一场效应晶体管P1的漏极与第一传输门的第一端电连接，第二场效应晶体管P2的漏极与第二传输门的第一端电连接，第三场效应晶体管N1的源极、第四场效应晶体管N2的源极与第五场效应晶体管N3的漏极电连接，第五场效应晶体管N3的栅极、第五场效应晶体管N3的漏极与灵敏放大器201电连接，第五场效应晶体管N3的源极接地，第一传输门的第二端与电压源电连接，第二传输门的第二端与电压源电连接。对存储阵列电路的具体结构进行了细化，明确了存储阵列电路中的电连接关系，以使得存储阵列电路能够根据输入数据信号向存储模块中写入不同的状态。
在一种可能的设计中，所述灵敏放大器包括：差分放大器和三态门2011，其中：该三态门2011的输出端经过翻转与该差分放大器的输出端电连接，该三态门2011的输入端接收输入数据信号，该三态门2011的控制端经过翻转与存储阵列电路204的字线电连接；该 差分放大器的第一输入端与存储阵列电路204的第五场效应晶体管N3的栅极电连接以接收存储阵列电路204输出的电压或电流，该差分放大器的第二输入端与参考电路203电连接以接收参考电压或参考电流，该差分放大器的输出端输出比较结果。细化了三态门与差分放大器的电连接关系，通过三态门的开启或关闭控制差分放大器比较参考电压或参考电流与存储阵列的电压或电流的大小。
在一种可能的设计中，所述差分放大器包括第六场效应晶体管P3、第七场效应晶体管P4、第八场效应晶体管N4、第九场效应晶体管N5、第十场效应晶体管N6、第十一场效应晶体管N7和第十二场效应晶体管N8，其中：第六场效应晶体管P3的栅极与第七场效应晶体管P4的栅极电连接，第六场效应晶体管P3的源极、第六场效应晶体管P3的栅极与第八场效应晶体管N4的漏极电连接，第七场效应晶体管P4的源极与第九场效应晶体管N5的漏极电连接，第八场效应晶体管N4的源极、第九场效应晶体管N5的源极、第十场效应晶体管N6的漏极、第十场效应晶体管N6的栅极与第十一场效应晶体管N7的栅极电连接，第十一场效应晶体管N7的源极、第十二场效应晶体管N8的漏极、第十二场效应晶体管N8的栅极与第九场效应晶体管N5的栅极电连接，第十场效应晶体管N6的源极接地，第十二场效应晶体管N8的源极接地，第六场效应晶体管P3的漏极与电压源电连接，第七场效应晶体管P4的漏极与电压源电连接；该三态门2011的输出端、第七场效应晶体管P4的源极、第九场效应晶体管N5的漏极与灵敏放大器201的输出端电连接，第八场效应晶体管N4的栅极与存储阵列电路204的第五场效应晶体管N3的栅极电连接。本实现方式中，提供了灵敏放大器的具体结构，确保灵敏放大器能够比较参考电路的参考电压或参考电流和存储阵列电路的电压或电流大小，并生成相应的输出端信号到控制电路。
在一种可能的设计中，所述控制电路包括：异或门2021和第一与门2022，其中：该异或门2021的第一输入端与输入数据信号线电连接，该异或门2021的第二输入端与灵敏放大器201的输出端电连接，该异或门2021的第一输入端接收输入数据信号，该异或门2021的第二输入端接收灵敏放大器201的比较结果，该异或门2021的输出端与第一与门2022的第一输入端、存储阵列电路204的第一传输门的第三端和存储阵列电路204的第二传输门的第三端电连接，该异或门2021用于根据输入数据信号和比较结果输出终止信号；该第一与门2022的第二输入端与字线电连接，第一与门2022的第三输入端与写使能信号线电连接，第一与门2022的输出端与灵敏放大器201的第十场效应晶体管N6的栅极电连接，第一与门2022的输出端信号用于控制灵敏放大器201的开启或关闭；存储阵列电路204的第一传输门的第三端接收终止信号，存储阵列电路204的第二传输门的第三端接收终止信号，其中，当终止信号有效时，存储阵列电路204的第一传输门和第二传输门同时关闭，当终止信号无效时，存储阵列电路204的第一传输门和第二传输门同时开启。本实现方式中，提供了控制电路的一种结构组成，确保控制电路能够根据灵敏放大器的比较结果生成终止信号，并控制灵敏放大器的开启和关闭。
在一种可能的设计中，所述控制电路还包括：第二与门2023、第三与门2024、或门2025和反相器链2026；该反相器链2026包含奇数个顺序电连接的非门；该第一与门2022的输出端、第二与门2023的第一输入端、反相器链2026的输入端与第三与门2024的第一 输入端电连接，反相器链2026的输出端与第二与门2023的第二输入端电连接，第二与门2023的输出端与或门2025的第一输入端电连接，第三与门2024的输出端与或门2025的第二输入端电连接，第三与门2024的第二输入端与外部时延电路电连接，外部时延电路用于在一定延时后提供一个外部信号控制第三与门2024的输出端的信号，或门2025的输出端信号用于控制灵敏放大器201的开启或关闭。本实现方式中，提供了控制电路的另一种结构组成，确保控制电路能够根据灵敏放大器的比较结果生成终止信号，并控制灵敏放大器的开启和关闭，减少控制灵敏放大器开启的时间，进一步减小功耗。
在一种可能的设计中，所述反相器链2026包含第一非门20261、第二非门20262、第三非门20263；第一非门20261的输入端与第一与门2022的输出端电连接；第二非门20262的输入端与第一非门20261的输出端电连接；第三非门20263的输入端与第二非门20262的输出端电连接；第三非门20263的输出端与第二与门2023的第二输入端电连接。本实现方式中，对反相器链的具体组成进行了限定，对第一与门的输出信号进行延迟，以使得控制器电路能短暂输出一个高电平的控制信号。
本申请实施例的第二方面提供一种自终止写入方法，应用于自终止写入电路，包括：通过灵敏放大器201比较参考电路203输出的参考电压或参考电流和存储阵列电路204输出的电压或电流大小，并将比较结果反馈至控制电路202；通过控制电路202根据比较结果生成终止信号，并反馈终止信号至存储阵列电路204，该终止信号用于控制存储阵列电路204停止写入P状态或AP状态。提供了一种自终止写入方法，通过灵敏放大器、控制电路构成的一个终止写入控制电路，实现对写入P状态或AP状态的自终止，节省了电路的开销面积，降低了功耗。
在一种可能的设计中，通过控制电路202根据比较结果生成终止信号，并反馈终止信号至存储阵列电路204的步骤包括：通过异或门2021判断输入数据信号和比较结果是否为相同电平；当输入数据信号和比较结果为相同电平时，通过异或门2021生成有效的终止信号并将有效的终止信号发送至存储阵列电路204；当输入数据信号和比较结果为不同电平时，通过异或门2021生成无效的终止信号并将无效的终止信号发送至存储阵列电路204。细化了生成终止信号并反馈终止信号至存储阵列电路的过程，增加了本申请实施例的实现方式。
在一种可能的设计中，通过控制电路202根据比较结果生成终止信号，并反馈终止信号至存储阵列电路204的步骤包括：当存储阵列电路处于写入准备阶段时，控制写使能信号从无效电平调整为有效电平，控制字线信号为无效电平；当存储阵列电路处于写入初始阶段时，将字线信号从无效电平调整为有效电平；当存储阵列电路完成写入AP状态时，控制输入数据信号为对应AP状态的有效电平；当存储阵列电路完成写入P状态时，控制输入数据信号为对应P状态的有效电平。提供了一种自终止写入方法，通过灵敏放大器、控制电路构成的一个终止写入控制电路，实现对写入P状态或AP状态的自终止，节省了电路的开销面积，降低了功耗。
在一种可能的设计中，当存储阵列电路处于写入初始阶段时，控制写使能信号为有效电平，将字线信号从无效电平调整为有效电平；当存储阵列电路完成写入AP状态时，控制 写使能信号为有效电平，控制字线信号为有效电平，控制输入数据信号为对应AP状态的有效电平；当存储阵列电路完成写入P状态时，控制写使能信号为有效电平，控制字线信号为有效电平，控制输入数据信号为对应P状态的有效电平。细化了具体的信号控制方法，确保自终止写入电路能够根据不同的信号控制写入状态过程的自终止。
本申请实施例提供的技术方案中，自终止写入电路，包括：灵敏放大器201和控制电路202；该灵敏放大器201用于比较参考电路203输出的参考电压或参考电流和存储阵列电路204输出的电压或电流大小，并将比较结果反馈至控制电路202；该控制电路202用于根据比较结果生成终止信号并反馈终止信号至存储阵列电路204，终止信号用于控制存储阵列电路204停止写入P状态或AP状态。本申请实施例中，通过灵敏放大器、控制电路构成的一个终止写入控制电路，实现对写入P状态或AP状态的自终止，节省了电路的开销面积，降低了功耗。
附图说明
图1A为存储模块的结构以及写入P或AP状态时的电流方向的示意图；
图1B为磁隧穿结处于P状态时的磁化方向和处于AP状态时的磁化方向的示意图；
图1C为现有方案的自终止写入电路的结构示意图；
图2为本申请中自终止写入电路的一个结构示意图；
图3为本申请中自终止写入电路的另一个结构示意图；
图4为本申请中自终止写入电路的另一个结构示意图；
图5为本申请中自终止写入方法的一个实施例示意图；
图6为本申请向AP状态的存储阵列电路中写入AP状态的波形示意图；
图7为本申请向P状态的存储阵列电路中写入AP状态的波形示意图。
具体实施方式
本申请实施例提供了一种自终止写入电路及方法，用于对处于不同状态的存储阵列电路通过同一个控制电路实现自终止，减小了电路的开销面积，降低了功耗。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本申请文件中提及的“第一”或“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。此外，本申请文件中提及的“包括”或“具有”及其任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或电路的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或电路，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或电路。
本申请应用于自旋转移矩磁存储器(Spin-transfer torque magnetic random access memory，STT-MRAM)中，可以理解的是，本申请还可以以应用在其他新型存储器中，例如，阻变存储器(resistive random access memory，RRAM)。对于RRAM器件，其两个状态(AP状态和P状态)的写入时长也不相同，同样可以采用本申请的方案来实现自终止， 节约功耗并减少平均写入时长。下面对本申请的方案进行具体说明。
本申请提供了一种自终止写入电路，请参阅图2，本申请实施例中自终止写入电路的一个实施例包括：
灵敏放大器201和控制电路202；
该灵敏放大器201用于比较参考电路203输出的参考电压或参考电流和存储阵列电路204输出的电压或电流大小，并将比较结果反馈至控制电路202；
该控制电路202用于根据所述比较结果生成终止信号write_stop并反馈该终止信号至存储阵列电路204，该终止信号用于控制存储阵列电路204停止写入P状态或AP状态。
可以理解的是，电连接可以是物理的直接电连接，也可以通过场效应晶体(field effect transistor，FET)或其他元件实现电学电连接，具体此处不做限定。
本申请除了可以通过比较参考电路的参考电压和存储阵列电路的电压大小，间接比较参考电路的阻值和存储阵列的阻值的大小，本领域技术人员可以根据实际情况，将参考电压和存储阵列电路的电压转换成电流，比较二者的电流大小，同样可以确定参考电路和存储阵列电路的阻值大小，具体此处不再赘述。
本申请实施例中，通过灵敏放大器比较参考电路的参考电压或参考电流和存储阵列电路的电压或电流的大小，根据比较结果将灵敏放大器的输出端信号发送至控制电路，以使得控制电路生成的终止信号控制存储阵列电路停止写入。通过灵敏放大器、控制电路构成的一个终止写入控制电路，实现对写入P状态或AP状态的自终止，节省了电路的开销面积，降低了功耗。
在一种可行的实现方式中，如图2或图3所示，自终止写入电路还包括参考电路203，其中：
参考电路203的阻值大于第一阈值且小于第二阈值；
存储阵列电路204处于P状态时的阻值等于第一阈值，存储阵列电路204处于AP状态时的阻值等于第二阈值。
需要说明的是，灵敏放大器201和参考电路203可以专门设计加入到电路中，也可以对电路中原本就有的灵敏放大器和参考电路改造以实现共享，从而节省电路面积。例如，可以通过一个参考电路为多个灵敏放大器提供参考电压或参考电流，也可以固定设计一个参考电路为对应的一个灵敏放大器提供参考电压或参考电流，具体此处不做限定。
本实现方式中，对参考电路的阻值大小进行了限定，明确了参考电路的阻值范围，以使得参考电路为灵敏放大器提供的参考电压或参考电流与存储单元中的电压或电流存在差异。
在一种可行的实现方式中，如图3所示，所述参考电路包括：
第一支路和第二支路，该第一支路的第一端与该第二支路的第一端电连接，该第一支路的第二端与该第二支路的第二端电连接，该第一支路的第二端和该第二支路的第二端电连接并输出参考电压或参考电流至灵敏放大器201，该第一支路的第一端和该第二支路的第一端与电压源电连接，第一支路包括N个串联的磁隧穿结，第二支路包括N个串联的磁隧穿结，N为大于1的正整数。
本实现方式中，细化了参考电路的具体组成，明确了参考电路和灵敏放大器的连接关系，以使得参考电路为灵敏放大器提供参考电压或参考电流。
在一种可行的实现方式中，如图3所示，第一支路包括第一磁隧穿结2031和第三磁隧穿结2033，第二支路包括第二磁隧穿结2032和第四磁隧穿结2034，其中，第一磁隧穿结2031的自由层端和第三磁隧穿结2033的固定层端电连接，第二磁隧穿结2032的自由层端和第四磁隧穿结2034的固定层端电连接，第一磁隧穿结2031的固定层端和第二磁隧穿结2032的固定层端与电压源电连接；该第一磁隧穿结2031为AP状态，该第二磁隧穿结2032为P状态，该第三磁隧穿结2033为P状态，该第四磁隧穿结2034为AP状态。
需要说明的是，第一磁隧穿结2031和第三磁隧穿结2033的位置可以交换，同时，第二磁隧穿结2032和第四磁隧穿结2034的位置也可以进行交换，只要确保参考电路的总电阻介于P状态的阻值和AP状态的阻值之间，其中，P状态的阻值和AP状态的阻值为固定的值，在磁隧穿结的误差范围内，P状态的阻值和AP状态的阻值可以存在±5％的波动。
本实现方式中，本实现方式中，提供了参考电路的一种具体结构，确保参考电路的阻值大于P状态的阻值且小于AP状态的阻值，以使得参考电路的参考电压或参考电流与存储阵列电路的电压或电流大小不同，灵敏放大器的输出端信号发生翻转。
在一种可行的实现方式中，如图2或图3所示，存储阵列电路包括：
第一场效应晶体管P1、第二场效应晶体管P2、第三场效应晶体管N1、第四场效应晶体管N2、第五场效应晶体管N3及多个存储模块，每个存储模块中包含一个磁隧穿结和一个场效应晶体管，其中：
每个存储模块的位线端与第一场效应晶体管P1的源极、第三场效应晶体管N1的漏极电连接，每个存储模块的源线端、第二场效应晶体管P2的源极和第四场效应晶体管N2的漏极电连接；
第一场效应晶体管P1的漏极与第一传输门的第一端电连接，第二场效应晶体管P2的漏极与第二传输门的第一端电连接，第三场效应晶体管N1的源极、第四场效应晶体管N2的源极与第五场效应晶体管N3的漏极电连接，第五场效应晶体管N3的栅极、第五场效应晶体管N3的漏极与灵敏放大器201电连接，第五场效应晶体管N3的源极接地，第一传输门的第二端与电压源电连接，第二传输门的第二端与电压源电连接。
需要说明的是，输入数据信号input_date中的电平的高低，导致存储阵列中各个场效应晶体管的导通情况不同，例如，当输入数据信号为低电平，即写入0(写入AP状态)时，第三场效应晶体管N1和第二场效应晶体管P2开启，第二场效应晶体管P2的栅极接收写0信号，第三场效应晶体管N1的栅极接收写0信号的反向信号(写1信号)；当输入数据信号为高电平，即写入1(写入P状态)时，第四场效应晶体管N2和第一场效应晶体管P1开启，第一场效应晶体管P1的栅极接收写1信号，第四场效应晶体管N2的栅极接收写1信号的反向信号(写0信号)。
本实现方式中，提供了存储阵列电路的具体结构，确保存储阵列电路能够根据输入数据信号向存储模块中写入不同的状态。
在一种可行的实现方式中，如图3或图4所示，灵敏放大器包括：
差分放大器和三态门2011，其中：
该三态门2011的输出端经过翻转与该差分放大器的输出端电连接，该三态门2011的输入端接收输入数据信号，该三态门2011的控制端经过翻转与存储阵列电路204的字线电连接；
该差分放大器的第一输入端与存储阵列电路204的第五场效应晶体管N3的栅极电连接以接收存储阵列电路204输出的电压或电流，该差分放大器的第二输入端与参考电路203电连接以接收参考电压或参考电流，该差分放大器的输出端输出比较结果。
本实现方式中，细化了三态门与差分放大器的电连接关系，通过三态门的开启或关闭控制差分放大器比较参考电压或参考电流与存储阵列的电压或电流的大小。
在一种可行的实现方式中，如图3或图4所示，差分放大器包括第六场效应晶体管P3、第七场效应晶体管P4、第八场效应晶体管N4、第九场效应晶体管N5、第十场效应晶体管N6、第十一场效应晶体管N7和第十二场效应晶体管N8，其中：
第六场效应晶体管P3的栅极与第七场效应晶体管P4的栅极电连接，第六场效应晶体管P3的源极、第六场效应晶体管P3的栅极与第八场效应晶体管N4的漏极电连接，第七场效应晶体管P4的源极与第九场效应晶体管N5的漏极电连接，第八场效应晶体管N4的源极、第九场效应晶体管N5的源极、第十场效应晶体管N6的漏极、第十场效应晶体管N6的栅极与第十一场效应晶体管N7的栅极电连接，第十一场效应晶体管N7的源极、第十二场效应晶体管N8的漏极、第十二场效应晶体管N8的栅极与第九场效应晶体管N5的栅极电连接，第十场效应晶体管N6的源极接地，第十二场效应晶体管N8的源极接地，第六场效应晶体管P3的漏极与电压源电连接，第七场效应晶体管P4的漏极与电压源电连接；
该三态门2011的输出端、第七场效应晶体管P4的源极、第九场效应晶体管N5的漏极与灵敏放大器201的输出端电连接，第八场效应晶体管N4的栅极与存储阵列电路204的第五场效应晶体管N3的栅极电连接。
需要说明的是，本申请实施例中，通过比较参考电路的参考电压或参考电流和存储阵列电路的电压或电流大小，即间接比较参考电路的电阻和存储阵列电路的电阻大小。
可以理解的是，还可以通过比较参考电路的电流和存储阵列的电流间接比较比较参考电路的电阻和存储阵列电路的电阻大小，具体此处不再赘述。
本实现方式中，本实现方式中，提供了灵敏放大器的具体结构，确保灵敏放大器能够比较参考电路的参考电压或参考电流和存储阵列电路的电压或电流大小，并生成相应的输出端信号到控制电路。
在一种可行的实现方式中，如图3所示，控制电路包括：
异或门2021和第一与门2022，其中：
该异或门2021的第一输入端与输入数据信号线电连接，该异或门2021的第二输入端与灵敏放大器201的输出端电连接，该异或门2021的第一输入端接收输入数据信号，该异或门2021的第二输入端接收灵敏放大器201的比较结果，该异或门2021的输出端与第一与门2022的第一输入端、存储阵列电路204的第一传输门的第三端和存储阵列电路204的第二传输门的第三端电连接，该异或门2021用于根据输入数据信号和比较结果输出终止信 号；
该第一与门2022的第二输入端与字线电连接，第一与门2022的第三输入端与写使能信号线电连接，第一与门2022的输出端与灵敏放大器201的第十场效应晶体管N6的栅极电连接，第一与门2022的输出端信号用于控制灵敏放大器201的开启或关闭；
存储阵列电路204的第一传输门的第三端接收终止信号，存储阵列电路204的第二传输门的第三端接收终止信号，其中，当所述终止信号有效时，所述存储阵列电路(204)的第一传输门和第二传输门同时关闭，当所述终止信号无效时，所述存储阵列电路(204)的第一传输门和第二传输门同时开启。
需要说明的是，本实现方式中控制电路的具体元件可以进行替换，例如，通过其他元器件实现第一与门的功能，只要能在相同的条件下实现控制电路的相同功能即可，其他实现方式中也类似，具体此处不做限定。
本实现方式中，提供了控制电路的一种结构组成，确保控制电路能够根据灵敏放大器的比较结果生成终止信号write_stop，并控制灵敏放大器的开启和关闭。
在一种可行的实现方式中，如图4所示，控制电路还包括：
第二与门2023、第三与门2024、或门2025和反相器链2026；
该反相器链2026包含奇数个顺序电连接的非门；
该第一与门2022的输出端、第二与门2023的第一输入端、反相器链2026的输入端与第三与门2024的第一输入端电连接，反相器链2026的输出端与第二与门2023的第二输入端电连接，第二与门2023的输出端与或门2025的第一输入端电连接，第三与门2024的输出端与或门2025的第二输入端电连接，第三与门2024的第二输入端与外部时延电路电连接，外部时延电路用于在一定延时后提供一个外部信号控制第三与门2024的输出端的信号，或门2025的输出端信号用于控制灵敏放大器201的开启或关闭。
需要说明的是，第二与门2023和反相器链2026组成第一支路，该第一支路用于处理同状态写入情况，例如，存储阵列已经存储P状态，输入数据信号为写1信号，即向存储阵列中再次写入P状态；存储阵列已经存储AP状态，输入数据信号为写0信号，即向存储阵列中再次写入AP状态。
第三与门2024单独组成第二支路，该第二支路用于处理异状态写入情况，例如，存储阵列已经存储P状态，输入数据信号为写0信号，即向存储阵列中再次写入AP状态；存储阵列已经存储AP状态，输入数据信号为写1信号，即向存储阵列中再次写入P状态。
本实现方式中，提供了控制电路的另一种结构组成，确保控制电路能够根据灵敏放大器的比较结果生成终止信号write_stop，并控制灵敏放大器的开启和关闭，减少控制灵敏放大器开启的时间，进一步减小功耗。
在一种可行的实现方式中，如图4所示，所述反相器链2026包含第一非门20261、第二非门20262、第三非门20263；
第一非门20261的输入端与第一与门2022的输出端电连接；
第二非门20262的输入端与第一非门20261的输出端电连接；
第三非门20263的输入端与第二非门20262的输出端电连接；
第三非门20263的输出端与第二与门2023的第二输入端电连接。
本实现方式中，对反相器链的具体组成进行了限定，对第一与门的输出信号进行延迟，以使得控制器电路能短暂输出一个高电平的控制信号。
请参阅图5，本申请实施例提供了一种自终止写入方法，应用在上述实施例及各个实现方式中涉及的自终止写入电路，包括：
501、通过灵敏放大器比较参考电路输出的参考电压或参考电流和存储阵列电路输出的电压或电流大小，并将比较结果反馈至控制电路。
自终止写入电路通过灵敏放大器201比较参考电路203输出的参考电压或参考电流和存储阵列电路204输出的电压或电流大小，并将比较结果反馈至控制电路202。
502、当存储阵列电路处于写入准备阶段时，控制写使能信号从无效电平调整为有效电平，控制字线信号为无效电平。
具体的，当存储阵列电路204处于写入准备阶段时，控制写使能信号从低电平调整为高电平，控制字线信号为低电平，以使得三态门开启，控制信号为低电平，低电平的控制信号控制灵敏放大器201关闭，灵敏放大器201的输出端信号保持与输入数据信号相反的电平，终止信号为高电平，此时高电平的终止信号为无效电平。
需要说明的是，在不需要向存储阵列电路204写入数据(状态)时，写使能信号为低电平，控制电路生成的终止信号为低电平，存储阵列电路204不能写入数据(状态)。
可以理解的是，各种信号用什么电平(高电平或低电平)表示有效是可以人为设定的。例如，写使能信号可以是高电平时表示有效，也可以是低电平时表示有效(电路要做相应调整)；例如，写AP状态时，输入数据信号可以是高电平，也可以是低电平(电路要做相应调整，例如，增加一个信号取反模块，具体的，信号取反模块可以由奇数个非门组成)，为了便于描述，本申请针对上述图3和图4所示的自终止写入电路，结合具体元器件进行说明。
503、当存储阵列电路处于写入初始阶段时，控制写使能信号为有效电平，将字线信号从无效电平调整为有效电平。
具体的，当存储阵列电路204处于写入阶段时，保持写使能信号为高电平，将字线信号从低电平调整为高电平，以使得三态门关闭，控制信号从低电平变为高电平(即从无效电平变为有效电平)，高电平的控制信号控制灵敏放大器201开启，灵敏放大器201的输出端信号保持与输入数据信号相反的电平，终止信号为高电平，此时高电平的终止信号为无效电平。
504、当存储阵列电路完成写入AP状态时，控制写使能信号为有效电平，控制字线信号为有效电平，控制输入数据信号为对应AP状态的有效电平。
具体的，当存储阵列电路204完成写入AP状态时，保持写使能信号为高电平，保持字线信号为高电平，控制输入数据信号为低电平(对应AP状态的有效电平)，以使得三态门关闭，灵敏放大器201的输出端信号取决于灵敏放大器201对参考电路203和存储阵列电路204的电压或电流的比较结果，输出端信号翻转为与输入数据信号相同的电平，控制信号从高电平变为低电平(即从有效电平变为无效电平)，低电平的控制信号控制灵敏放大器 201关闭，终止信号从高电平变为低电平(即从无效电平变为有效电平)，存储阵列电路204终止写入AP状态。对于同状态写入AP状态(即存储阵列电路204本身为AP状态，需要写入AP状态)时，各个信号的波形如图6所示；对于异状态写入AP状态(即存储阵列电路204本身为P状态，需要写入AP状态)时，各个信号的波形如图7所示。
需要说明的是，当应用在如图4所示的自终止写入电路时，如果存储阵列电路本来就处于AP状态，则当写入开始之后，灵敏放大器201的输出端信号out很快就能被翻转成“0”(即低电平)，使得终止信号write_stop为0，从而实现自终止，避免不必要的重复写入。如果存储阵列电路204本来处于P状态，则当写入开始之后，灵敏放大器201的输出端信号out需要等到该存储阵列电路204的状态被写为AP状态时才会变为“0”，在保证状态的正确写入的情况下实现写入自终止。
505、当存储阵列电路完成写入P状态时，控制写使能信号为有效电平，控制字线信号为有效电平，控制输入数据信号为对应P状态的有效电平。
具体的，当存储阵列电路204完成写入P状态时，保持写使能信号为高电平，保持字线信号为高电平，控制输入数据信号为高电平(对应P状态的有效电平)，以使得三态门关闭，灵敏放大器201的输出端信号取决于灵敏放大器201对参考电路203和存储阵列电路204的电压或电流的比较结果，输出端信号翻转为与输入数据信号相同的电平，控制信号从高电平变为低电平(即从有效电平变为无效电平)，低电平的控制信号控制灵敏放大器201关闭，终止信号从高电平变为低电平(即从无效电平变为有效电平)，存储阵列电路204终止写入P状态。
需要说明的是，当应用在如图4所示的自终止写入电路时，如果存储阵列电路204本来就处于P状态，则当写入开始之后，灵敏放大器的输出端信号out很快就能被翻转成“1”(即高电平)，使得终止信号write_stop为0，从而实现自终止，避免不必要的重复写入。如果存储阵列电路204本来处于AP状态，则当写入开始之后，灵敏放大器的输出端信号out需要等到该存储阵列电路204的状态被写为P状态时才会变为“1”，在保证状态的正确写入的情况下实现自终止。
对于异状态写入情况，对于图4中控制电路202的第一支路，通过第一支路中的反相器链2026，把第二与门2023输出的有效信号在一定时延之后关断。通过第二支路中第三与门2024的第二输入端接收外部时延电路的时延信号，使得在一定时延后第三与门2024的输出信号为有效。
可以理解的是，步骤504和步骤505为并列步骤，在同一时间执行其中一个步骤，具体此处不再赘述。
本申请实施例中，通过控制各个信号的高低电平，实现对存储阵列电路在完成状态写入后实现自终止，节省自终止写入电路的开销面积，并降低了功耗。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述电路的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个电路或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互 之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或电路的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的电路可以是或者也可以不是物理上分开的，作为电路显示的部件可以是或者也可以不是物理电路，即可以位于一个地方，或者也可以分布到多个网络电路上。可以根据实际的需要选择其中的部分或者全部电路来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能电路可以集成在一个处理电路中，也可以是各个电路单独物理存在，也可以两个或两个以上电路集成在一个电路中。上述集成的电路既可以采用硬件的形式实现，也可以采用软件功能电路的形式实现。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (12)

  1. 一种自终止写入电路，其特征在于，包括：
    灵敏放大器(201)和控制电路(202)；
    所述灵敏放大器(201)用于比较参考电路(203)输出的参考电压或参考电流和存储阵列电路(204)输出的电压或电流大小，并将比较结果反馈至所述控制电路(202)；
    所述控制电路(202)用于根据所述比较结果生成终止信号，并反馈所述终止信号至所述存储阵列电路(204)，所述终止信号用于控制所述存储阵列电路(204)停止写入P状态或AP状态。
  2. 根据权利要求1所述的自终止写入电路，其特征在于，所述自终止写入电路还包括所述参考电路(203)，其中：
    所述参考电路(203)的阻值大于第一阈值且小于第二阈值：
    所述存储阵列电路(204)处于所述P状态时的阻值等于所述第一阈值，所述存储阵列电路(204)处于所述AP状态时的阻值等于所述第二阈值。
  3. 根据权利要求1或2所述的自终止写入电路，其特征在于，所述参考电路包括：
    第一支路和第二支路，所述第一支路的第一端与所述第二支路的第一端电连接，所述第一支路的第二端与所述第二支路的第二端电连接，所述第一支路的第二端和所述第二支路的第二端电连接并输出所述参考电压或所述参考电流至所述灵敏放大器(201)，所述第一支路的第一端和所述第二支路的第一端与电压源电连接，所述第一支路包括N个串联的磁隧穿结，所述第二支路包括N个串联的磁隧穿结，所述N为大于1的正整数。
  4. 根据权利要求3所述的自终止写入电路，其特征在于，
    所述第一支路包括第一磁隧穿结(2031)和第三磁隧穿结(2033)，所述第二支路包括第二磁隧穿结(2032)和第四磁隧穿结(2034)，其中，所述第一磁隧穿结(2031)的自由层端和第三磁隧穿结(2033)的固定层端电连接，所述第二磁隧穿结(2032)的自由层端和第四磁隧穿结(2034)的固定层端电连接，所述第一磁隧穿结(2031)的固定层端和第二磁隧穿结(2032)的固定层端与电压源电连接；
    所述第一磁隧穿结(2031)为所述AP状态，所述第二磁隧穿结(2032)为所述P状态，所述第三磁隧穿结(2033)为所述P状态，所述第四磁隧穿结(2034)为所述AP状态。
  5. 根据权利要求1或2所述的自终止写入电路，其特征在于，所述储阵列电路包括：
    第一场效应晶体管(P1)、第二场效应晶体管(P2)、第三场效应晶体管(N1)、第四场效应晶体管(N2)、第五场效应晶体管(N3)及多个存储模块，其中：
    每个所述存储模块中包含一个磁隧穿结和一个场效应晶体管；
    每个所述存储模块的位线端与所述第一场效应晶体管(P1)的源极、所述第三场效应晶体管(N1)的漏极电连接，每个所述存储模块的源线端、所述第二场效应晶体管(P2)的源极和所述第四场效应晶体管(N2)的漏极电连接；
    所述第一场效应晶体管(P1)的漏极与第一传输门的第一端电连接，所述第二场效应晶体管(P2)的漏极与第二传输门的第一端电连接，所述第三场效应晶体管(N1)的源极、所述第四场效应晶体管(N2)的源极与所述第五场效应晶体管(N3)的漏极电连接，所述 第五场效应晶体管(N3)的栅极、所述第五场效应晶体管(N3)的漏极与所述灵敏放大器(201)电连接，所述第五场效应晶体管(N3)的源极接地，所述第一传输门的第二端与电压源电连接，所述第二传输门的第二端与电压源电连接。
  6. 根据权利要求1-5任一所述的自终止写入电路，其特征在于，所述灵敏放大器包括：
    差分放大器和三态门(2011)，其中：
    所述三态门(2011)的输出端经过翻转与所述差分放大器的输出端电连接，所述三态门(2011)的输入端接收输入数据信号，所述存储阵列电路(204)的字线经过翻转与所述三态门(2011)的控制端电连接；
    所述差分放大器的第一输入端与所述存储阵列电路(204)的第五场效应晶体管(N3)的栅极电连接以接收所述存储阵列电路(204)输出的所述电压或所述电流，所述差分放大器的第二输入端与所述参考电路(203)电连接以接收所述参考电压或所述参考电流，所述差分放大器的输出端输出所述比较结果。
  7. 根据权利要求6所述的自终止写入电路，其特征在于，
    所述差分放大器包括第六场效应晶体管(P3)、第七场效应晶体管(P4)、第八场效应晶体管(N4)、第九场效应晶体管(N5)、第十场效应晶体管(N6)、第十一场效应晶体管(N7)和第十二场效应晶体管(N8)，其中：
    所述第六场效应晶体管(P3)的栅极与第七场效应晶体管(P4)的栅极电连接，所述第六场效应晶体管(P3)的源极、所述第六场效应晶体管(P3)的栅极与所述第八场效应晶体管(N4)的漏极电连接，所述第七场效应晶体管(P4)的源极与所述第九场效应晶体管(N5)的漏极电连接，所述第八场效应晶体管(N4)的源极、所述第九场效应晶体管(N5)的源极、所述第十场效应晶体管(N6)的漏极、所述第十场效应晶体管(N6)的栅极与所述第十一场效应晶体管(N7)的栅极电连接，所述第十一场效应晶体管(N7)的源极、所述第十二场效应晶体管(N8)的漏极、所述第十二场效应晶体管(N8)的栅极与所述第九场效应晶体管(N5)的栅极电连接，所述第十场效应晶体管(N6)的源极接地，所述第十二场效应晶体管(N8)的源极接地，所述第六场效应晶体管(P3)的漏极与电压源电连接，所述第七场效应晶体管(P4)的漏极与电压源电连接；
    所述三态门(2011)的输出端、所述第七场效应晶体管(P4)的源极、所述第九场效应晶体管(N5)的漏极与所述灵敏放大器(201)的输出端电连接，所述第八场效应晶体管(N4)的栅极与所述存储阵列电路(204)的第五场效应晶体管(N3)的栅极电连接。
  8. 根据权利要求1-7任一所述的自终止写入电路，其特征在于，所述控制电路包括：
    异或门(2021)和第一与门(2022)，其中：
    所述异或门(2021)的第一输入端与输入数据信号线电连接，所述异或门(2021)的第二输入端与所述灵敏放大器(201)的输出端电连接，所述异或门(2021)的第一输入端接收输入数据信号，所述异或门(2021)的第二输入端接收所述灵敏放大器(201)的比较结果，所述异或门(2021)的输出端与所述第一与门(2022)的第一输入端、所述存储阵列电路(204)的第一传输门的第三端和所述存储阵列电路(204)的第二传输门的第三端电连接，所述异或门(2021)用于根据所述输入数据信号和所述比较结果输出所述终止信 号；
    所述第一与门(2022)的第二输入端与所述字线电连接，所述第一与门(2022)的第三输入端与写使能信号线电连接，所述第一与门(2022)的输出端与所述灵敏放大器(201)的第十场效应晶体管(N6)的栅极电连接，所述第一与门(2022)的输出端信号用于控制所述灵敏放大器(201)的开启或关闭；
    所述存储阵列电路(204)的第一传输门的第三端接收所述终止信号，所述存储阵列电路(204)的第二传输门的第三端接收所述终止信号，其中，当所述终止信号有效时，所述存储阵列电路(204)的第一传输门和第二传输门同时关闭，当所述终止信号无效时，所述存储阵列电路(204)的第一传输门和第二传输门同时开启。
  9. 根据权利要求7所述的自终止写入电路，其特征在于，所述控制电路还包括：
    第二与门(2023)、第三与门(2024)、或门(2025)和反相器链(2026)；
    所述反相器链(2026)包含奇数个顺序电连接的非门；
    所述第一与门(2022)的输出端、所述第二与门(2023)的第一输入端、所述反相器链(2026)的输入端与所述第三与门(2024)的第一输入端电连接，所述反相器链(2026)的输出端与所述第二与门(2023)的第二输入端电连接，所述第二与门(2023)的输出端与所述或门(2025)的第一输入端电连接，所述第三与门(2024)的输出端与所述或门(2025)的第二输入端电连接，所述第三与门(2024)的第二输入端与外部时延电路电连接，所述外部时延电路用于在一定延时后提供一个外部信号控制所述第三与门(2024)的输出端的信号，所述或门(2025)的输出端信号用于控制所述灵敏放大器(201)的开启或关闭。
  10. 根据权利要求9所述的自终止写入电路，其特征在于，
    所述反相器链(2026)包含第一非门(20261)、第二非门(20262)、第三非门(20263)；
    所述第一非门(20261)的输入端与所述第一与门(2022)的输出端电连接；
    所述第二非门(20262)的输入端与所述第一非门(20261)的输出端电连接；
    所述第三非门(20263)的输入端与所述第二非门(20262)的输出端电连接；
    所述第三非门(20263)的输出端与所述第二与门(2023)的第二输入端电连接。
  11. 一种自终止写入方法，其特征在于，应用于自终止写入电路，包括：
    通过灵敏放大器(201)比较参考电路(203)输出的参考电压或参考电流和存储阵列电路(204)输出的电压或电流大小，并将比较结果反馈至所述控制电路(202)；
    通过所述控制电路(202)根据所述比较结果生成终止信号，并反馈所述终止信号至所述存储阵列电路(204)，所述终止信号用于控制所述存储阵列电路(204)停止写入P状态或AP状态。
  12. 根据权利要求11所述的自终止写入方法，其特征在于，通过所述控制电路(202)根据所述比较结果生成终止信号，并反馈所述终止信号至所述存储阵列电路(204)的步骤包括：
    通过异或门(2021)判断输入数据信号和所述比较结果是否为相同电平；
    当所述输入数据信号和所述比较结果为相同电平时，通过所述异或门(2021)生成有效的终止信号并将所述有效的终止信号发送至存储阵列电路(204)；
    当所述输入数据信号和所述比较结果为不同电平时，通过所述异或门(2021)生成无效的终止信号并将所述无效的终止信号发送至存储阵列电路(204)。
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