WO2019230555A1 - Amplificateur de type cascode et dispositif de communication sans fil - Google Patents

Amplificateur de type cascode et dispositif de communication sans fil Download PDF

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Publication number
WO2019230555A1
WO2019230555A1 PCT/JP2019/020448 JP2019020448W WO2019230555A1 WO 2019230555 A1 WO2019230555 A1 WO 2019230555A1 JP 2019020448 W JP2019020448 W JP 2019020448W WO 2019230555 A1 WO2019230555 A1 WO 2019230555A1
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Prior art keywords
transistor
type
gate
resistor
cascode amplifier
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PCT/JP2019/020448
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English (en)
Japanese (ja)
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真一 堀
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日本電気株式会社
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Priority to JP2020522139A priority Critical patent/JP6981548B2/ja
Publication of WO2019230555A1 publication Critical patent/WO2019230555A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to a cascode amplifier and a radio communication device, and more particularly, to a broadband cascode amplifier.
  • a transmission unit of a wireless communication device such as a mobile phone or a wireless LAN (Local Area Network) is required to operate with low power consumption while ensuring the accuracy of a transmission signal regardless of the magnitude of output power.
  • the power amplifier at the final stage of the transmission unit of the wireless communication device occupies 50% or more of the power consumption of the entire wireless communication device, and thus is required to have high power efficiency.
  • switching amplifiers have attracted attention as power amplifiers that are expected to have high power efficiency.
  • This switching amplifier assumes a pulse waveform signal as an input signal, and can amplify power while maintaining the waveform of the input signal.
  • the pulse waveform signal amplified by the switching amplifier is radiated from the antenna into the air after sufficiently suppressing frequency components other than the desired frequency component by the filter element.
  • Patent Document 1 relates to such a switching amplifier, and is based on a class D amplifier in which two switch elements are inserted in series between a power source and a ground (GND) and a connection point of the switch elements is an output terminal. Switching amplifiers have been proposed. In the switching amplifier of Patent Document 1, complementary pulse signals are input to the two switch elements, and only one of the two switch elements is controlled to be in the ON state. Further, in Patent Document 1, as a circuit technique for improving the withstand voltage of a class D amplifier to be higher than the withstand voltage of a switch element constituting the class D amplifier, it is called a cascode amplifier in which a cascode transistor is inserted between each switch element and an output terminal. A configuration is proposed. However, in Patent Document 1, there is no specific configuration that maintains the voltage applied to the inserted cascode transistor below the breakdown voltage.
  • Non-Patent Document 1 relates to a millimeter-wave high-power DAC (Digital-to-Analog Converter) transmitter, and a D-class CMOS (Complementary Metal-Oxide Semiconductor) amplifier in the output stage has been proposed.
  • CMOS Complementary Metal-Oxide Semiconductor
  • a high gain D is obtained by using circuit elements such as resistors, capacitors, and inductors constituting the class D CMOS amplifier for input signals having frequencies of 45 GHz, 90 GHz, 110 GHz, and 138 GHz.
  • Class CMOS amplifier can be realized.
  • FIG. 18 is a circuit diagram showing an example of a cascode amplifier having a circuit configuration similar to that of the output stage class D CMOS amplifier proposed by Non-Patent Document 1.
  • the cascode amplifier in FIG. 18 is an amplifier that inverts and amplifies a sine wave that changes between 1 V and 0 V, for example, from a signal source.
  • the cascode amplifier in FIG. 18 includes a P-type first transistor MP11 that inputs a signal obtained by level-shifting an input signal by a fourth power supply V4 (V DD ⁇ 3) to the gate, and between the first transistor MP11 and the output terminal.
  • P-type second transistor MP12, third transistor MP13, and fourth transistor MP14 connected in cascade.
  • the 18 includes an N-type first transistor MN11 that inputs an input signal to the gate, an N-type second transistor MN12 that is connected in cascade between the first transistor MN11 and the output terminal, A transistor MN13 and a fourth transistor MN14 are included.
  • the first transistor MP11, the second transistor MP12, the third transistor MP13, the fourth transistor MP14, the first transistor MN11, the second transistor MN12, the third transistor MN13, and the fourth transistor MN14 are connected to the second power source V2 (V DD ⁇ 4) and the third power supply V3 (GND) are connected in cascade.
  • the cascode amplifier of FIG. 18 includes a capacitor connected between the gate terminal of the cascode transistor and GND.
  • a sine wave input signal that changes between 1 V and 0 V, for example, from a signal source is inverted and amplified, and a sine wave output signal that changes between 0 V and 4 V from the output terminal.
  • the voltage applied to the cascode transistors constituting the cascode amplifier can be biased by a resistor connected between the gates of adjacent cascode transistors while maintaining the voltage below the breakdown voltage.
  • the admittance of this capacitance and the drain ⁇ can be designed to an appropriate value so that the potential difference between the drain and gate falls within the breakdown voltage. Note that the admittance of the resistor connected to the gate terminal is required to be designed to a value that is negligibly small compared to each capacitor.
  • Patent Document 2 relates to a traveling wave amplifier in which a plurality of differential amplifiers are connected in parallel to each other with a delay element interposed therebetween, and a collector output of a cascode transistor is fed back to a base input via a resistance voltage dividing circuit. It has been proposed to configure such that.
  • the switching amplifier Assuming application of a switching amplifier to a 5G base station for wireless communication, the switching amplifier is required to be able to amplify a wide band 1-bit modulation signal up to 20 Gbps, for example.
  • the capacitance of a capacitor connected to the gate of each cascode transistor is set to specify a high frequency region.
  • it can be designed so that the potential between terminals of each transistor is within the device breakdown voltage.
  • the admittance of the drain-gate capacitance of the transistor is small, and even if the admittance of the resistor connected to the gate is small, the amplitude of the drain terminal may be large.
  • the amplitude of the gate is small, and a potential that exceeds the device breakdown voltage is generated between the drain and gate terminals.
  • An object of the present invention is to provide a cascode amplifier and a wireless communication device that realize a wide band from a direct current to a high frequency region while maintaining a voltage applied to a component below a withstand voltage.
  • a cascode amplifier comprises: A cascode amplifier including a plurality of transistors, Includes a configuration in which the output signal is divided into resistors and fed back to the gate of the cascode transistor.
  • a wireless communication device The cascode amplifier, and An antenna connected to the output of the cascode amplifier; including.
  • FIG. 1 is a circuit block of the feedback circuit of FIG. 1 and the like
  • (b) is a circuit diagram showing a specific configuration example 1 of the feedback circuit of (a)
  • (c) is a circuit diagram of the feedback circuit of (a).
  • FIG. 2nd Embodiment It is a circuit diagram for demonstrating the cascode type
  • FIG. 1 is a circuit diagram for explaining an embodiment of a cascode amplifier according to a superordinate concept of the present invention.
  • the cascode amplifier 10 in FIG. 1 is a cascode amplifier including a plurality of transistors, and includes a configuration in which an output signal is resistance-divided and fed back to the gate of the cascode transistor.
  • the cascode amplifier 10 of FIG. 1 includes a first conductivity type first transistor M1 in which an input signal from an input terminal is input to a gate, and a first conductivity type cascaded between the first transistor M1 and an output terminal. Second transistor M2. Further, the cascode amplifier 10 of FIG. 1 includes a second conductivity type third transistor M3 whose gate is an input signal from the input terminal, and a second conductivity type connected in cascade between the third transistor M3 and the output terminal. Type fourth transistor M4.
  • the cascode amplifier 10 of FIG. 1 is connected between the first resistor R1 connected between the first node N and the gate of the first transistor M1, and between the gate of the first transistor M1 and the second power supply V2.
  • Second resistor R2. 1 is connected between the first node N and the gate of the third transistor M3, and between the gate of the third transistor M3 and the third power supply V3.
  • a fourth resistor R4 is connected between the first resistor R1 connected between the first node N and the gate of the first transistor M1, and between the gate of the first transistor M1 and the second power supply V2.
  • the cascode amplifier 10 of FIG. 1 includes a configuration in which an output signal is fed back to the gate of the second transistor M2 and the gate of the fourth transistor M4 through a feedback circuit.
  • the feedback circuit is configured by a resistance divider circuit, attenuates the output signal by resistance division, and feeds back to each gate terminal of the second transistor M2 / fourth transistor M4.
  • the feedback circuit may have a circuit configuration as shown in (b) of FIG. 2 or (c) of FIG. 2A is a circuit block of the feedback circuit of FIG. 1 and the like, and FIG. 2B is a circuit diagram showing a specific configuration example 1 of the feedback circuit of FIG. (C) of FIG. 2 is a circuit diagram showing a specific configuration example 2 of the feedback circuit of FIG. 2 (a).
  • the first to fourth resistors R1 to R4 change the gate-source voltages and the gate-to-drain voltages of the first to fourth transistors M1 to M4 included in the cascode amplifier 10, respectively. It can be kept below the element breakdown voltage of the four transistors M4, and the first to fourth transistors M1 to M4 can be prevented from being destroyed.
  • the feedback circuit of the cascode amplifier 10 of FIG. 1, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, etc. do not have frequency characteristics.
  • the cascode amplifier can be widened while maintaining the breakdown voltage of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 within an allowable range.
  • FIG. 3 is a circuit diagram for explaining the cascode amplifier according to the first embodiment.
  • FIG. 4 is an explanatory diagram for explaining signal waveforms of the cascode amplifier according to the first embodiment.
  • the cascode amplifier 1 of FIG. 3 includes a P-type first transistor MP11 as an example of a first conductivity type in which an input signal from an input terminal is input to a gate, and a cascade connection between the first transistor MP11 and the output terminal.
  • a P-type second transistor MP12, a third transistor MP13, and a fourth transistor MP14 are connected.
  • it is assumed that one of the two input signals is given to the gate of the P-type first transistor MP11 via the fourth power supply V4.
  • the cascode amplifier 1 of FIG. 3 includes an N-type first transistor MN11 as an example of a second conductivity type in which an input signal from an input terminal is input to the gate, an N-type first transistor MN11, and an output terminal.
  • N-type second transistor MN12, third transistor MN13, and fourth transistor MN14 connected in cascade.
  • the cascode amplifier 1 of FIG. 3 has a configuration in which the output signal of the cascode amplifier 1 is resistance-divided and fed back to the gate of each transistor.
  • the first resistor R11 connected between the output terminal and the first node N, and the first power supply V1 (V DD ⁇ 2) and the first node N are connected.
  • the second resistor R12 is included, and the output signal is divided into resistors and fed back to the gate of the cascode transistor.
  • the cascode amplifier 1 of FIG. 3 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 1 of FIG. 3 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2 (V DD ⁇ 4). Further, the cascode amplifier 1 of FIG. 3 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11. Further, the cascode amplifier 1 of FIG. 3 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3 (GND).
  • connection point between the third resistor R13 and the fourth resistor R14 is connected to the gate of the P-type third transistor MP13, and the connection point between the fourth resistor R14 and the fifth resistor R15 is P It is connected to the gate of the second transistor MP12 of the type.
  • connection point between the seventh resistor R17 and the eighth resistor R18 is connected to the gate of the N-type third transistor MN13, and the connection point between the eighth resistor R18 and the ninth resistor R19 is N
  • the second transistor MN12 of the type is connected to the gate.
  • the source of the P-type first transistor MP11 is connected to the second power supply V2 (V DD ⁇ 4), and the source of the N-type first transistor MN11 is connected to the third power supply V3 (GND). Yes.
  • FIG. 4 shows a state in which the signal source 6 is connected to the input terminal of the cascode amplifier 1 of FIG.
  • the signal source 6 outputs a pulse signal of “0” or “1”, which is a 1-bit modulated signal in a wide band up to 20 Gbps, for example.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example. In the following description, it is assumed that the power supply voltage V DD is set to a value equal to the element breakdown voltage and is 1V.
  • the first power supply V1 to the third power supply V3 output the following voltages with the power supply voltage V DD as a reference. That is, the first power supply V1 outputs a voltage of V DD ⁇ 2 that is twice the power supply voltage V DD .
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the fourth power supply V4 outputs a voltage of V DD ⁇ 3 that is three times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, the second resistor R12 in FIG. 3, and the first resistor R11 in FIG. 3 is between 3V and 1V. It changes with.
  • the output terminal of the cascode amplifier 1 in FIG. 4 outputs 4 V or 0 V in response to a pulse signal (0 V or 1 V) of “0” or “1” from the signal source 6.
  • the cascode amplifier 1 of FIG. 3 do not have frequency characteristics.
  • the cascode amplifier can be widened from a direct current to a high frequency region while maintaining the voltage applied to the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 below the breakdown voltage.
  • the cascode amplifier 1 of FIG. 3 three transistors are connected in cascade between the P-type first transistor MP11 and the output terminal, and three transistors are connected between the N-type first transistor MN11 and the output terminal.
  • the number of stages of transistors connected in cascade is not limited to this.
  • a transistor connected in cascade between a P-type first transistor MP11 and an output terminal, an N-type first transistor MN11, an output terminal For example, the number of transistors connected in cascade may be increased.
  • FIG. 5 is a circuit diagram for explaining a cascode amplifier according to the second embodiment.
  • FIG. 6 is an explanatory diagram for explaining a signal waveform of the cascode amplifier according to the second embodiment.
  • the cascode amplifier according to the second embodiment is a modification of the cascode amplifier according to the first embodiment. Elements similar to those of the cascode amplifier of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 2 of FIG. 5 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascaded connection between the first transistor MP11 and the output terminal.
  • the cascode amplifier 2 of FIG. 5 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 2 of FIG. 5 includes a first resistor R11 connected between the output terminal and the first node N, and between the first power supply V1 and the first node N. And a second resistor R12 connected thereto. Further, the cascode amplifier 2 of FIG. 5 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 2 of FIG. 5 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 2 of FIG.
  • the cascode amplifier 2 of FIG. 5 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND is connected between the gate of the P-type third transistor MP13 and GND.
  • the fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND and the gate connected to the gate of the N-type third transistor MN13 and GND.
  • a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
  • the first resistor R11 connected between the output terminal and the first node N, the first power supply V1 (V DD ⁇ 2), and the first node And a second resistor R12 connected to N, and realizes a configuration in which the output signal is resistance-divided and fed back to the gate of the cascode transistor.
  • This configuration corresponds to a specific configuration example 1 of the feedback circuit shown in FIG.
  • FIG. 6 shows a state where the signal source 6 is connected to the input terminal of the cascode amplifier 2 of FIG. As in the first embodiment, the signal source 6 outputs a pulse signal of “0” or “1”.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example. In the following description, it is assumed that the power supply voltage V DD is set to a value equal to the element breakdown voltage and is 1V.
  • the first power supply V1 to the third power supply V3 output the following voltages with the power supply voltage V DD as a reference. That is, the first power supply V1 outputs a voltage of V DD ⁇ 2 that is twice the power supply voltage V DD .
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the fourth power supply V4 outputs a voltage of V DD ⁇ 3 that is three times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, the second resistor R12, and the first resistor R11 varies between 3V and 1V.
  • the output terminal of the cascode amplifier 2 in FIG. 6 outputs 4 V or 0 V in accordance with the pulse signal (0 V or 1 V) of “0” or “1” from the signal source 6.
  • the cascode amplifier 2 of FIG. 5 do not have frequency characteristics.
  • the cascode amplifier is widened from DC to high frequency while maintaining the element breakdown voltage of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. be able to.
  • a capacitor is inserted between the gate terminal of each transistor and GND. However, in the high frequency region, this capacitor is similar to the background art shown in FIG.
  • the cascode amplifier of FIG. 6 can cope with a higher frequency region.
  • the first capacitor C1 is connected to the gate of the P-type fourth transistor MP14
  • the second capacitor C2 is connected to the gate of the P-type third transistor MP13
  • a third capacitor C3 is connected to the second capacitor C3.
  • the fourth capacitor C4 is connected to the gate of the N-type fourth transistor MN14
  • the fifth capacitor C5 is connected to the gate of the N-type third transistor MN13
  • the N-type second transistor MN12 is connected.
  • a sixth capacitor C6 is connected to the gate.
  • the third capacitor C3 is connected to the gate of the P-type second transistor MP12 and divides the capacitance from the parasitic capacitance between the gate and the source of the P-type second transistor MP12 and the parasitic capacitance between the gate and the drain.
  • the combination of the resistance division by the fourth resistor R14 and the fifth resistor R15 and the capacitance division by the third capacitor C3 connected to the gate of the P-type second transistor MP12 gives to the gate of the P-type second transistor MP12. Voltage is stabilized.
  • the effect of the third capacitor C3 is the same in the first capacitor C1 connected to the gate of the P-type fourth transistor MP14 and the second capacitor C2 connected to the gate of the P-type third transistor MP13. .
  • the fourth capacitor C4 connected to the gate of the N-type fourth transistor MN14, the fifth capacitor C5 connected to the gate of the N-type third transistor MN13, and the gate of the N-type second transistor MN12 are connected.
  • the overall operation of the cascode amplifier 2 can be stabilized.
  • FIG. 7 is a circuit diagram for explaining the cascode amplifier according to the third embodiment.
  • the cascode amplifier according to the third embodiment is a modification of the cascode amplifier according to the first embodiment. Elements similar to those of the cascode amplifier of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 3 in FIG. 7 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascaded between the first transistor MP11 and the output terminal.
  • the cascode amplifier 3 of FIG. 7 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 3 of FIG. 7 includes a first resistor R11 connected between the output terminal and the first node N, a second resistor R12 connected to the first node N, ,including. Further, the cascode amplifier 3 of FIG. 7 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 3 of FIG. 7 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 3 of FIG.
  • the cascode amplifier 3 in FIG. 7 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the cascode amplifier 3 of FIG. 7 includes an eleventh resistor R21 and a thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND.
  • the second resistor R12 is connected between the first node N and the connection point of the eleventh resistor R21 and the thirteenth resistor R23 connected in series.
  • the cascode amplifier 3 in FIG. 7 includes a first resistor R11, a second resistor R12, an eleventh resistor R21, and a thirteenth resistor R23, and realizes a configuration in which the output signal is divided by resistance and fed back to the gate of the cascode transistor. doing.
  • This configuration corresponds to a specific configuration example 2 of the feedback circuit shown in FIG.
  • the cascode amplifier 3 of FIG. Since the resistor does not have frequency characteristics, the first resistor R11, second resistor R12, third resistor R13, seventh resistor R17, eleventh resistor R21, thirteenth resistor R23, etc. of the cascode amplifier 3 of FIG. Do not have.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are set as in the first embodiment.
  • the cascode amplifier can be widened while maintaining within an allowable range.
  • the first power supply V1 (V1 (V) of the first embodiment and the second embodiment is obtained by resistance division of the eleventh resistor R21 and the thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND. A voltage corresponding to DD ⁇ 2) is generated. As a result, a dedicated voltage source for the first power supply V1 (V DD ⁇ 2) can be omitted, and the power supply unit can be shared.
  • FIG. 8 is a circuit diagram for explaining a cascode amplifier according to the fourth embodiment.
  • the cascode amplifier according to the fourth embodiment is a modification of the cascode amplifier according to the second embodiment or the third embodiment. Elements similar to those of the cascode amplifiers of the second and third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 4 of FIG. 8 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascade connected between the first transistor MP11 and the output terminal.
  • the cascode amplifier 4 of FIG. 8 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 4 of FIG. 8 includes a first resistor R11 connected between the output terminal and the first node N, and a second resistor R12 connected to the first node N. ,including. Furthermore, the cascode amplifier 4 of FIG. 8 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 4 of FIG. 8 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 4 of FIG.
  • the cascode amplifier 4 of FIG. 8 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND, and the P-type third transistor MP13.
  • a second capacitor C2 connected between the gate and GND; and a third capacitor C3 connected between the gate of the P-type second transistor MP12 and GND.
  • the fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND, and the N-type third transistor MN13.
  • a fifth capacitor C5 connected between the gate and GND, and a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
  • the cascode amplifier 4 of FIG. 8 is different from the second embodiment in the connection of the second resistor R12.
  • the cascode amplifier 4 of FIG. 8 includes an eleventh resistor R21 and a thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND.
  • the second resistor R12 is connected between the first node N and the connection point of the eleventh resistor R21 and the thirteenth resistor R23 connected in series.
  • the cascode amplifier 4 of FIG. 8 includes a first resistor R11, a second resistor R12, an eleventh resistor R21, and a thirteenth resistor R23.
  • a configuration for returning to the gate is realized. This configuration corresponds to a specific configuration example 2 of the feedback circuit shown in FIG.
  • the cascode amplifier 4 of FIG. Since the resistor does not have frequency characteristics, the first resistor R11, the second resistor R12, the third resistor R13, the seventh resistor R17, the eleventh resistor R21, the thirteenth resistor R23, etc. of the cascode amplifier 4 of FIG. Do not have.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are set as in the first embodiment.
  • the cascode amplifier can be widened while maintaining within an allowable range.
  • the first power supply V1 (V1 (V) of the first embodiment and the second embodiment is obtained by resistance division of the eleventh resistor R21 and the thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND. A voltage corresponding to DD ⁇ 2) is generated. As a result, a dedicated voltage source for the first power supply V1 (V DD ⁇ 2) can be omitted, and the power supply unit can be shared.
  • FIG. 9 is a circuit diagram for explaining the cascode amplifier according to the fifth embodiment.
  • the cascode amplifier of the fifth embodiment is a modification of the cascode amplifier of the fourth embodiment. Elements similar to those of the cascode amplifier of the fourth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 5a of FIG. 9 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascade connected between the first transistor MP11 and the output terminal.
  • the cascode amplifier 5a of FIG. 9 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 5a shown in FIG. further includes a feedback circuit connected between the output terminal and the first node N.
  • the cascode amplifier 5a shown in FIG. includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11.
  • the cascode amplifier 5a of FIG. 9 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2.
  • the cascode amplifier 5a of FIG. 9 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11.
  • the cascode amplifier 5a of FIG. 9 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND, and the P-type amplifier It includes a second capacitor C2 connected between the gate of the third transistor MP13 and GND, and a third capacitor C3 connected between the gate of the P-type second transistor MP12 and GND.
  • a fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND It includes a fifth capacitor C5 connected between the gate of the third transistor MN13 and GND, and a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
  • the cascode amplifier 5a of FIG. 9 has a configuration in which the output signal of the cascode amplifier 5a is resistance-divided and fed back to the gate of the P-type fourth transistor MP14 and the gate of the N-type fourth transistor MN14.
  • the cascode amplifier 5a of FIG. 9 includes a feedback circuit connected between the output terminal and the gate of the P-type fourth transistor MP14 and the gate of the N-type fourth transistor MN14.
  • the feedback circuit shown in FIG. 2C used in the third and fourth embodiments can be used.
  • the cascode amplifier 5a of FIG. 9 includes a latch circuit LATCH1 connected to the gate of the P-type first transistor MP11, and an eleventh capacitor inserted between the input terminal and the gate of the P-type first transistor MP11. And C11.
  • the latch circuit LATCH1 is composed of a pair of inverter circuits in which inputs as shown in FIG. 9 are connected to outputs, for example.
  • the latch circuit LATCH1 holds a high level or low level voltage applied to the gate of the P-type first transistor MP11.
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 of FIG.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5a in FIG. 9 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
  • the feedback circuit of the cascode amplifier 5a of FIG. 9, the third resistor R13, the seventh resistor R17, and the like do not have frequency characteristics.
  • the cascode amplifier 5a can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the eleventh capacitor inserted between the input terminal and the gate of the P-type first transistor MP11. C11.
  • a voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5a. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5a, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • FIG. 11 is a circuit diagram for explaining a cascode amplifier according to the sixth embodiment.
  • the cascode amplifier according to the sixth embodiment is a modification of the cascode amplifier according to the fifth embodiment. Elements similar to those of the cascode amplifier of the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 5b of FIG. 11 further includes a thirteenth capacitor C13 in addition to the same configuration as that of the fifth embodiment.
  • the thirteenth capacitor C13 is inserted between one end different from one end connected to the gate of the P-type first transistor MP11 of the latch circuit LATCH1 and a wiring to which a predetermined potential is applied.
  • the latch circuit LATCH1 and the thirteenth capacitor C13 are connected in series between a wiring to which a predetermined potential is applied and the gate of the P-type first transistor MP11.
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given. It is assumed that a potential obtained by inverting the pulse signal of “0” or “1” of the input of the cascode amplifier 5b is applied to a wiring to which a predetermined potential is connected, one end of which is connected to the thirteenth capacitor C13. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 with the sixth resistor R16 or the like.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5b in FIG. 12 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
  • the feedback circuit of the cascode amplifier 5b, the third resistor R13, the seventh resistor R17, and the like of FIG. 11 do not have frequency characteristics.
  • the cascode amplifier 5b can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the input terminal and the gate of the P-type first transistor MP11 are arranged. And an eleventh capacitor C11 inserted into the.
  • a voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal “0” or “1” at the input of the cascode amplifier 5b. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5b, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • a potential obtained by inverting the pulse signal of the input “0” or “1” of the cascode amplifier 5b is connected to a wiring to which a predetermined potential is connected to one end of the thirteenth capacitor C13. Is given.
  • the voltage that is held by the latch circuit LATCH1 and applied to the gate of the P-type first transistor MP11 can follow the change of the input “0” or “1” of the cascode-type amplifier 5b. This can be improved over the amplifier 5a.
  • FIG. 13 is a circuit diagram for explaining the cascode amplifier according to the seventh embodiment.
  • the cascode amplifier according to the seventh embodiment is a modification of the cascode amplifier according to the fifth embodiment. Elements similar to those of the cascode amplifier of the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 5c of FIG. 13 has the same configuration as that of the fifth embodiment, a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11, an input terminal, and the gate of the N-type first transistor MN11. And a twelfth capacitor C12 inserted between the first and second capacitors.
  • the latch circuit LATCH2 is composed of a pair of inverter circuits whose inputs are connected to the outputs as shown in FIG. 13, for example.
  • the latch circuit LATCH2 holds a high level or low level voltage applied to the gate of the N-type first transistor MN11.
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 with the sixth resistor R16 or the like.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5c in FIG. 14 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
  • the feedback circuit of the cascode amplifier 5c of FIG. 13, the third resistor R13, the seventh resistor R17, and the like do not have frequency characteristics.
  • the cascode amplifier 5c can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the input terminal and the gate of the P-type first transistor MP11 are arranged. And an eleventh capacitor C11 inserted into the.
  • a voltage obtained by resistance-dividing the second power source V2 with the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5c. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5c, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 and a twelfth capacitor inserted between the input terminal and the gate of the N-type first transistor MN11. C12.
  • a voltage obtained by dividing the third power source V3 by a tenth resistor R20 or the like at the gate of the N-type first transistor MN11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5c. 1V or 0V can be applied.
  • the latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 improves the follow-up to the input change of the cascode amplifier 5c, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • the cascode amplifier 5c of FIG. 13 includes a latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11. This improves the symmetry of the overall circuit configuration of the cascode amplifier 5c.
  • FIG. 15 is a circuit diagram for explaining a cascode amplifier according to an eighth embodiment.
  • the cascode amplifier according to the eighth embodiment is a modification of the cascode amplifier according to the fifth to seventh embodiments. Elements similar to those of the cascode amplifiers of the fifth to seventh embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the latch circuit 15 has a configuration similar to that of the fifth embodiment, a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11, an input terminal, and a gate of the N-type first transistor MN11. And a twelfth capacitor C12 inserted between the first and second capacitors.
  • the latch circuit LATCH2 is composed of a pair of inverter circuits whose inputs are connected to the outputs, for example, as shown in FIG.
  • the latch circuit LATCH2 holds a high level or low level voltage applied to the gate of the N-type first transistor MN11.
  • the second power supply V2 With reference to the power supply voltage V DD , the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5d in FIG. 16 outputs 4V or 0V according to the pulse signal (0V or 1V) of “0” or “1” from the signal source 6.
  • the cascode amplifier 5d can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11, the input terminal, and the gate of the P-type first transistor MP11 And an eleventh capacitor C11 inserted therebetween.
  • a voltage obtained by resistance-dividing the second power source V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal “0” or “1” at the input of the cascode amplifier 5d. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5d, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • the latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 and the twelfth capacitor inserted between the input terminal and the gate of the N-type first transistor MN11. C12.
  • a voltage obtained by resistance-dividing the third power source V3 by the tenth resistor R20 or the like at the gate of the N-type first transistor MN11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5d. 1V or 0V can be applied.
  • the latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 improves the follow-up to the input change of the cascode amplifier 5d, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • a potential obtained by inverting the pulse signal of “0” or “1” input to the input terminal (input 1) of the cascode amplifier 5d is given from the input terminal (input 2).
  • the voltage held by the latch circuit LATCH1 and applied to the gate of the P-type first transistor MP11 and the voltage held by the latch circuit LATCH2 and applied to the gate of the N-type first transistor MN11 are stabilized.
  • the followability with respect to the change of the input “0” or “1” to the input terminal (input 1) of the cascode amplifier 5d can be improved as compared with the cascode amplifier 5a of FIG.
  • the symmetry of the circuit configuration of the cascode amplifier is improved.
  • FIG. 17 is a block diagram for explaining a wireless communication device according to another embodiment.
  • the 17 includes a cascode amplifier 101 that amplifies and outputs an input signal, and an antenna 102 that is connected to the output of the cascode amplifier 101 and transmits a radio signal.
  • the cascode amplifier 101 the cascode amplifiers of the first to eighth embodiments described above can be used.
  • the wireless communication device 100 of FIG. 17 employing this can be miniaturized. Therefore, according to the wireless communication device 100 of FIG.
  • the present invention has been described above, but the present invention is not limited to this.
  • the case where the element withstand voltage of the transistors constituting the cascode amplifier is 1 V has been described, but the present invention is not limited to this.
  • the case where the output level of the signal source 6 is 0V or 1V has been described.
  • the present invention is not limited to this.
  • the specific values of the potentials of the first power supply V1, the second power supply V2, the third power supply V3, the fourth power supply V4 and the like are not limited to the above-described embodiments, and may be set as appropriate while maintaining the mutual magnitude relationship. It goes without saying that various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
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Abstract

L'invention concerne : un amplificateur de type cascode dans lequel un élargissement de bande est obtenu tandis que la tension de tenue d'élément d'un élément constitutif est maintenue dans une plage admissible ; et un dispositif de communication sans fil. L'amplificateur de type cascode comprend une pluralité de transistors, et a une configuration dans laquelle un signal de sortie est soumis à une division résistive à renvoyer à des grilles de transistors cascodes.
PCT/JP2019/020448 2018-05-31 2019-05-23 Amplificateur de type cascode et dispositif de communication sans fil WO2019230555A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152845A (en) * 1978-05-24 1979-12-01 Hitachi Ltd High dielectric strength mosfet circuit
JP2010141496A (ja) * 2008-12-10 2010-06-24 Seiko Epson Corp 半導体集積回路、半導体集積回路の駆動方法、電子機器および電子機器の駆動方法
JP2014220735A (ja) * 2013-05-10 2014-11-20 富士通セミコンダクター株式会社 出力回路および電圧信号出力方法
WO2016021092A1 (fr) * 2014-08-04 2016-02-11 日本電気株式会社 Amplificateur à commutation et transmetteur radio

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Publication number Priority date Publication date Assignee Title
US6137367A (en) * 1998-03-24 2000-10-24 Amcom Communications, Inc. High power high impedance microwave devices for power applications
JP2012238929A (ja) * 2011-05-09 2012-12-06 Waseda Univ 増幅回路
CN107534442B (zh) * 2015-05-20 2021-05-14 新唐科技日本株式会社 差动输出电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152845A (en) * 1978-05-24 1979-12-01 Hitachi Ltd High dielectric strength mosfet circuit
JP2010141496A (ja) * 2008-12-10 2010-06-24 Seiko Epson Corp 半導体集積回路、半導体集積回路の駆動方法、電子機器および電子機器の駆動方法
JP2014220735A (ja) * 2013-05-10 2014-11-20 富士通セミコンダクター株式会社 出力回路および電圧信号出力方法
WO2016021092A1 (fr) * 2014-08-04 2016-02-11 日本電気株式会社 Amplificateur à commutation et transmetteur radio

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