WO2019230555A1 - Cascode-type amplifier and wireless communication device - Google Patents

Cascode-type amplifier and wireless communication device Download PDF

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Publication number
WO2019230555A1
WO2019230555A1 PCT/JP2019/020448 JP2019020448W WO2019230555A1 WO 2019230555 A1 WO2019230555 A1 WO 2019230555A1 JP 2019020448 W JP2019020448 W JP 2019020448W WO 2019230555 A1 WO2019230555 A1 WO 2019230555A1
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Prior art keywords
transistor
type
gate
resistor
cascode amplifier
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PCT/JP2019/020448
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French (fr)
Japanese (ja)
Inventor
真一 堀
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日本電気株式会社
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Priority to JP2020522139A priority Critical patent/JP6981548B2/en
Publication of WO2019230555A1 publication Critical patent/WO2019230555A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to a cascode amplifier and a radio communication device, and more particularly, to a broadband cascode amplifier.
  • a transmission unit of a wireless communication device such as a mobile phone or a wireless LAN (Local Area Network) is required to operate with low power consumption while ensuring the accuracy of a transmission signal regardless of the magnitude of output power.
  • the power amplifier at the final stage of the transmission unit of the wireless communication device occupies 50% or more of the power consumption of the entire wireless communication device, and thus is required to have high power efficiency.
  • switching amplifiers have attracted attention as power amplifiers that are expected to have high power efficiency.
  • This switching amplifier assumes a pulse waveform signal as an input signal, and can amplify power while maintaining the waveform of the input signal.
  • the pulse waveform signal amplified by the switching amplifier is radiated from the antenna into the air after sufficiently suppressing frequency components other than the desired frequency component by the filter element.
  • Patent Document 1 relates to such a switching amplifier, and is based on a class D amplifier in which two switch elements are inserted in series between a power source and a ground (GND) and a connection point of the switch elements is an output terminal. Switching amplifiers have been proposed. In the switching amplifier of Patent Document 1, complementary pulse signals are input to the two switch elements, and only one of the two switch elements is controlled to be in the ON state. Further, in Patent Document 1, as a circuit technique for improving the withstand voltage of a class D amplifier to be higher than the withstand voltage of a switch element constituting the class D amplifier, it is called a cascode amplifier in which a cascode transistor is inserted between each switch element and an output terminal. A configuration is proposed. However, in Patent Document 1, there is no specific configuration that maintains the voltage applied to the inserted cascode transistor below the breakdown voltage.
  • Non-Patent Document 1 relates to a millimeter-wave high-power DAC (Digital-to-Analog Converter) transmitter, and a D-class CMOS (Complementary Metal-Oxide Semiconductor) amplifier in the output stage has been proposed.
  • CMOS Complementary Metal-Oxide Semiconductor
  • a high gain D is obtained by using circuit elements such as resistors, capacitors, and inductors constituting the class D CMOS amplifier for input signals having frequencies of 45 GHz, 90 GHz, 110 GHz, and 138 GHz.
  • Class CMOS amplifier can be realized.
  • FIG. 18 is a circuit diagram showing an example of a cascode amplifier having a circuit configuration similar to that of the output stage class D CMOS amplifier proposed by Non-Patent Document 1.
  • the cascode amplifier in FIG. 18 is an amplifier that inverts and amplifies a sine wave that changes between 1 V and 0 V, for example, from a signal source.
  • the cascode amplifier in FIG. 18 includes a P-type first transistor MP11 that inputs a signal obtained by level-shifting an input signal by a fourth power supply V4 (V DD ⁇ 3) to the gate, and between the first transistor MP11 and the output terminal.
  • P-type second transistor MP12, third transistor MP13, and fourth transistor MP14 connected in cascade.
  • the 18 includes an N-type first transistor MN11 that inputs an input signal to the gate, an N-type second transistor MN12 that is connected in cascade between the first transistor MN11 and the output terminal, A transistor MN13 and a fourth transistor MN14 are included.
  • the first transistor MP11, the second transistor MP12, the third transistor MP13, the fourth transistor MP14, the first transistor MN11, the second transistor MN12, the third transistor MN13, and the fourth transistor MN14 are connected to the second power source V2 (V DD ⁇ 4) and the third power supply V3 (GND) are connected in cascade.
  • the cascode amplifier of FIG. 18 includes a capacitor connected between the gate terminal of the cascode transistor and GND.
  • a sine wave input signal that changes between 1 V and 0 V, for example, from a signal source is inverted and amplified, and a sine wave output signal that changes between 0 V and 4 V from the output terminal.
  • the voltage applied to the cascode transistors constituting the cascode amplifier can be biased by a resistor connected between the gates of adjacent cascode transistors while maintaining the voltage below the breakdown voltage.
  • the admittance of this capacitance and the drain ⁇ can be designed to an appropriate value so that the potential difference between the drain and gate falls within the breakdown voltage. Note that the admittance of the resistor connected to the gate terminal is required to be designed to a value that is negligibly small compared to each capacitor.
  • Patent Document 2 relates to a traveling wave amplifier in which a plurality of differential amplifiers are connected in parallel to each other with a delay element interposed therebetween, and a collector output of a cascode transistor is fed back to a base input via a resistance voltage dividing circuit. It has been proposed to configure such that.
  • the switching amplifier Assuming application of a switching amplifier to a 5G base station for wireless communication, the switching amplifier is required to be able to amplify a wide band 1-bit modulation signal up to 20 Gbps, for example.
  • the capacitance of a capacitor connected to the gate of each cascode transistor is set to specify a high frequency region.
  • it can be designed so that the potential between terminals of each transistor is within the device breakdown voltage.
  • the admittance of the drain-gate capacitance of the transistor is small, and even if the admittance of the resistor connected to the gate is small, the amplitude of the drain terminal may be large.
  • the amplitude of the gate is small, and a potential that exceeds the device breakdown voltage is generated between the drain and gate terminals.
  • An object of the present invention is to provide a cascode amplifier and a wireless communication device that realize a wide band from a direct current to a high frequency region while maintaining a voltage applied to a component below a withstand voltage.
  • a cascode amplifier comprises: A cascode amplifier including a plurality of transistors, Includes a configuration in which the output signal is divided into resistors and fed back to the gate of the cascode transistor.
  • a wireless communication device The cascode amplifier, and An antenna connected to the output of the cascode amplifier; including.
  • FIG. 1 is a circuit block of the feedback circuit of FIG. 1 and the like
  • (b) is a circuit diagram showing a specific configuration example 1 of the feedback circuit of (a)
  • (c) is a circuit diagram of the feedback circuit of (a).
  • FIG. 2nd Embodiment It is a circuit diagram for demonstrating the cascode type
  • FIG. 1 is a circuit diagram for explaining an embodiment of a cascode amplifier according to a superordinate concept of the present invention.
  • the cascode amplifier 10 in FIG. 1 is a cascode amplifier including a plurality of transistors, and includes a configuration in which an output signal is resistance-divided and fed back to the gate of the cascode transistor.
  • the cascode amplifier 10 of FIG. 1 includes a first conductivity type first transistor M1 in which an input signal from an input terminal is input to a gate, and a first conductivity type cascaded between the first transistor M1 and an output terminal. Second transistor M2. Further, the cascode amplifier 10 of FIG. 1 includes a second conductivity type third transistor M3 whose gate is an input signal from the input terminal, and a second conductivity type connected in cascade between the third transistor M3 and the output terminal. Type fourth transistor M4.
  • the cascode amplifier 10 of FIG. 1 is connected between the first resistor R1 connected between the first node N and the gate of the first transistor M1, and between the gate of the first transistor M1 and the second power supply V2.
  • Second resistor R2. 1 is connected between the first node N and the gate of the third transistor M3, and between the gate of the third transistor M3 and the third power supply V3.
  • a fourth resistor R4 is connected between the first resistor R1 connected between the first node N and the gate of the first transistor M1, and between the gate of the first transistor M1 and the second power supply V2.
  • the cascode amplifier 10 of FIG. 1 includes a configuration in which an output signal is fed back to the gate of the second transistor M2 and the gate of the fourth transistor M4 through a feedback circuit.
  • the feedback circuit is configured by a resistance divider circuit, attenuates the output signal by resistance division, and feeds back to each gate terminal of the second transistor M2 / fourth transistor M4.
  • the feedback circuit may have a circuit configuration as shown in (b) of FIG. 2 or (c) of FIG. 2A is a circuit block of the feedback circuit of FIG. 1 and the like, and FIG. 2B is a circuit diagram showing a specific configuration example 1 of the feedback circuit of FIG. (C) of FIG. 2 is a circuit diagram showing a specific configuration example 2 of the feedback circuit of FIG. 2 (a).
  • the first to fourth resistors R1 to R4 change the gate-source voltages and the gate-to-drain voltages of the first to fourth transistors M1 to M4 included in the cascode amplifier 10, respectively. It can be kept below the element breakdown voltage of the four transistors M4, and the first to fourth transistors M1 to M4 can be prevented from being destroyed.
  • the feedback circuit of the cascode amplifier 10 of FIG. 1, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, etc. do not have frequency characteristics.
  • the cascode amplifier can be widened while maintaining the breakdown voltage of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 within an allowable range.
  • FIG. 3 is a circuit diagram for explaining the cascode amplifier according to the first embodiment.
  • FIG. 4 is an explanatory diagram for explaining signal waveforms of the cascode amplifier according to the first embodiment.
  • the cascode amplifier 1 of FIG. 3 includes a P-type first transistor MP11 as an example of a first conductivity type in which an input signal from an input terminal is input to a gate, and a cascade connection between the first transistor MP11 and the output terminal.
  • a P-type second transistor MP12, a third transistor MP13, and a fourth transistor MP14 are connected.
  • it is assumed that one of the two input signals is given to the gate of the P-type first transistor MP11 via the fourth power supply V4.
  • the cascode amplifier 1 of FIG. 3 includes an N-type first transistor MN11 as an example of a second conductivity type in which an input signal from an input terminal is input to the gate, an N-type first transistor MN11, and an output terminal.
  • N-type second transistor MN12, third transistor MN13, and fourth transistor MN14 connected in cascade.
  • the cascode amplifier 1 of FIG. 3 has a configuration in which the output signal of the cascode amplifier 1 is resistance-divided and fed back to the gate of each transistor.
  • the first resistor R11 connected between the output terminal and the first node N, and the first power supply V1 (V DD ⁇ 2) and the first node N are connected.
  • the second resistor R12 is included, and the output signal is divided into resistors and fed back to the gate of the cascode transistor.
  • the cascode amplifier 1 of FIG. 3 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 1 of FIG. 3 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2 (V DD ⁇ 4). Further, the cascode amplifier 1 of FIG. 3 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11. Further, the cascode amplifier 1 of FIG. 3 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3 (GND).
  • connection point between the third resistor R13 and the fourth resistor R14 is connected to the gate of the P-type third transistor MP13, and the connection point between the fourth resistor R14 and the fifth resistor R15 is P It is connected to the gate of the second transistor MP12 of the type.
  • connection point between the seventh resistor R17 and the eighth resistor R18 is connected to the gate of the N-type third transistor MN13, and the connection point between the eighth resistor R18 and the ninth resistor R19 is N
  • the second transistor MN12 of the type is connected to the gate.
  • the source of the P-type first transistor MP11 is connected to the second power supply V2 (V DD ⁇ 4), and the source of the N-type first transistor MN11 is connected to the third power supply V3 (GND). Yes.
  • FIG. 4 shows a state in which the signal source 6 is connected to the input terminal of the cascode amplifier 1 of FIG.
  • the signal source 6 outputs a pulse signal of “0” or “1”, which is a 1-bit modulated signal in a wide band up to 20 Gbps, for example.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example. In the following description, it is assumed that the power supply voltage V DD is set to a value equal to the element breakdown voltage and is 1V.
  • the first power supply V1 to the third power supply V3 output the following voltages with the power supply voltage V DD as a reference. That is, the first power supply V1 outputs a voltage of V DD ⁇ 2 that is twice the power supply voltage V DD .
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the fourth power supply V4 outputs a voltage of V DD ⁇ 3 that is three times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, the second resistor R12 in FIG. 3, and the first resistor R11 in FIG. 3 is between 3V and 1V. It changes with.
  • the output terminal of the cascode amplifier 1 in FIG. 4 outputs 4 V or 0 V in response to a pulse signal (0 V or 1 V) of “0” or “1” from the signal source 6.
  • the cascode amplifier 1 of FIG. 3 do not have frequency characteristics.
  • the cascode amplifier can be widened from a direct current to a high frequency region while maintaining the voltage applied to the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 below the breakdown voltage.
  • the cascode amplifier 1 of FIG. 3 three transistors are connected in cascade between the P-type first transistor MP11 and the output terminal, and three transistors are connected between the N-type first transistor MN11 and the output terminal.
  • the number of stages of transistors connected in cascade is not limited to this.
  • a transistor connected in cascade between a P-type first transistor MP11 and an output terminal, an N-type first transistor MN11, an output terminal For example, the number of transistors connected in cascade may be increased.
  • FIG. 5 is a circuit diagram for explaining a cascode amplifier according to the second embodiment.
  • FIG. 6 is an explanatory diagram for explaining a signal waveform of the cascode amplifier according to the second embodiment.
  • the cascode amplifier according to the second embodiment is a modification of the cascode amplifier according to the first embodiment. Elements similar to those of the cascode amplifier of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 2 of FIG. 5 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascaded connection between the first transistor MP11 and the output terminal.
  • the cascode amplifier 2 of FIG. 5 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 2 of FIG. 5 includes a first resistor R11 connected between the output terminal and the first node N, and between the first power supply V1 and the first node N. And a second resistor R12 connected thereto. Further, the cascode amplifier 2 of FIG. 5 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 2 of FIG. 5 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 2 of FIG.
  • the cascode amplifier 2 of FIG. 5 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND is connected between the gate of the P-type third transistor MP13 and GND.
  • the fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND and the gate connected to the gate of the N-type third transistor MN13 and GND.
  • a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
  • the first resistor R11 connected between the output terminal and the first node N, the first power supply V1 (V DD ⁇ 2), and the first node And a second resistor R12 connected to N, and realizes a configuration in which the output signal is resistance-divided and fed back to the gate of the cascode transistor.
  • This configuration corresponds to a specific configuration example 1 of the feedback circuit shown in FIG.
  • FIG. 6 shows a state where the signal source 6 is connected to the input terminal of the cascode amplifier 2 of FIG. As in the first embodiment, the signal source 6 outputs a pulse signal of “0” or “1”.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example. In the following description, it is assumed that the power supply voltage V DD is set to a value equal to the element breakdown voltage and is 1V.
  • the first power supply V1 to the third power supply V3 output the following voltages with the power supply voltage V DD as a reference. That is, the first power supply V1 outputs a voltage of V DD ⁇ 2 that is twice the power supply voltage V DD .
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the fourth power supply V4 outputs a voltage of V DD ⁇ 3 that is three times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, the second resistor R12, and the first resistor R11 varies between 3V and 1V.
  • the output terminal of the cascode amplifier 2 in FIG. 6 outputs 4 V or 0 V in accordance with the pulse signal (0 V or 1 V) of “0” or “1” from the signal source 6.
  • the cascode amplifier 2 of FIG. 5 do not have frequency characteristics.
  • the cascode amplifier is widened from DC to high frequency while maintaining the element breakdown voltage of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. be able to.
  • a capacitor is inserted between the gate terminal of each transistor and GND. However, in the high frequency region, this capacitor is similar to the background art shown in FIG.
  • the cascode amplifier of FIG. 6 can cope with a higher frequency region.
  • the first capacitor C1 is connected to the gate of the P-type fourth transistor MP14
  • the second capacitor C2 is connected to the gate of the P-type third transistor MP13
  • a third capacitor C3 is connected to the second capacitor C3.
  • the fourth capacitor C4 is connected to the gate of the N-type fourth transistor MN14
  • the fifth capacitor C5 is connected to the gate of the N-type third transistor MN13
  • the N-type second transistor MN12 is connected.
  • a sixth capacitor C6 is connected to the gate.
  • the third capacitor C3 is connected to the gate of the P-type second transistor MP12 and divides the capacitance from the parasitic capacitance between the gate and the source of the P-type second transistor MP12 and the parasitic capacitance between the gate and the drain.
  • the combination of the resistance division by the fourth resistor R14 and the fifth resistor R15 and the capacitance division by the third capacitor C3 connected to the gate of the P-type second transistor MP12 gives to the gate of the P-type second transistor MP12. Voltage is stabilized.
  • the effect of the third capacitor C3 is the same in the first capacitor C1 connected to the gate of the P-type fourth transistor MP14 and the second capacitor C2 connected to the gate of the P-type third transistor MP13. .
  • the fourth capacitor C4 connected to the gate of the N-type fourth transistor MN14, the fifth capacitor C5 connected to the gate of the N-type third transistor MN13, and the gate of the N-type second transistor MN12 are connected.
  • the overall operation of the cascode amplifier 2 can be stabilized.
  • FIG. 7 is a circuit diagram for explaining the cascode amplifier according to the third embodiment.
  • the cascode amplifier according to the third embodiment is a modification of the cascode amplifier according to the first embodiment. Elements similar to those of the cascode amplifier of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 3 in FIG. 7 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascaded between the first transistor MP11 and the output terminal.
  • the cascode amplifier 3 of FIG. 7 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 3 of FIG. 7 includes a first resistor R11 connected between the output terminal and the first node N, a second resistor R12 connected to the first node N, ,including. Further, the cascode amplifier 3 of FIG. 7 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 3 of FIG. 7 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 3 of FIG.
  • the cascode amplifier 3 in FIG. 7 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the cascode amplifier 3 of FIG. 7 includes an eleventh resistor R21 and a thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND.
  • the second resistor R12 is connected between the first node N and the connection point of the eleventh resistor R21 and the thirteenth resistor R23 connected in series.
  • the cascode amplifier 3 in FIG. 7 includes a first resistor R11, a second resistor R12, an eleventh resistor R21, and a thirteenth resistor R23, and realizes a configuration in which the output signal is divided by resistance and fed back to the gate of the cascode transistor. doing.
  • This configuration corresponds to a specific configuration example 2 of the feedback circuit shown in FIG.
  • the cascode amplifier 3 of FIG. Since the resistor does not have frequency characteristics, the first resistor R11, second resistor R12, third resistor R13, seventh resistor R17, eleventh resistor R21, thirteenth resistor R23, etc. of the cascode amplifier 3 of FIG. Do not have.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are set as in the first embodiment.
  • the cascode amplifier can be widened while maintaining within an allowable range.
  • the first power supply V1 (V1 (V) of the first embodiment and the second embodiment is obtained by resistance division of the eleventh resistor R21 and the thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND. A voltage corresponding to DD ⁇ 2) is generated. As a result, a dedicated voltage source for the first power supply V1 (V DD ⁇ 2) can be omitted, and the power supply unit can be shared.
  • FIG. 8 is a circuit diagram for explaining a cascode amplifier according to the fourth embodiment.
  • the cascode amplifier according to the fourth embodiment is a modification of the cascode amplifier according to the second embodiment or the third embodiment. Elements similar to those of the cascode amplifiers of the second and third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 4 of FIG. 8 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascade connected between the first transistor MP11 and the output terminal.
  • the cascode amplifier 4 of FIG. 8 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 4 of FIG. 8 includes a first resistor R11 connected between the output terminal and the first node N, and a second resistor R12 connected to the first node N. ,including. Furthermore, the cascode amplifier 4 of FIG. 8 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 4 of FIG. 8 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 4 of FIG.
  • the cascode amplifier 4 of FIG. 8 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND, and the P-type third transistor MP13.
  • a second capacitor C2 connected between the gate and GND; and a third capacitor C3 connected between the gate of the P-type second transistor MP12 and GND.
  • the fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND, and the N-type third transistor MN13.
  • a fifth capacitor C5 connected between the gate and GND, and a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
  • the cascode amplifier 4 of FIG. 8 is different from the second embodiment in the connection of the second resistor R12.
  • the cascode amplifier 4 of FIG. 8 includes an eleventh resistor R21 and a thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND.
  • the second resistor R12 is connected between the first node N and the connection point of the eleventh resistor R21 and the thirteenth resistor R23 connected in series.
  • the cascode amplifier 4 of FIG. 8 includes a first resistor R11, a second resistor R12, an eleventh resistor R21, and a thirteenth resistor R23.
  • a configuration for returning to the gate is realized. This configuration corresponds to a specific configuration example 2 of the feedback circuit shown in FIG.
  • the cascode amplifier 4 of FIG. Since the resistor does not have frequency characteristics, the first resistor R11, the second resistor R12, the third resistor R13, the seventh resistor R17, the eleventh resistor R21, the thirteenth resistor R23, etc. of the cascode amplifier 4 of FIG. Do not have.
  • the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are set as in the first embodiment.
  • the cascode amplifier can be widened while maintaining within an allowable range.
  • the first power supply V1 (V1 (V) of the first embodiment and the second embodiment is obtained by resistance division of the eleventh resistor R21 and the thirteenth resistor R23 connected in series between V DD ⁇ 4 and GND. A voltage corresponding to DD ⁇ 2) is generated. As a result, a dedicated voltage source for the first power supply V1 (V DD ⁇ 2) can be omitted, and the power supply unit can be shared.
  • FIG. 9 is a circuit diagram for explaining the cascode amplifier according to the fifth embodiment.
  • the cascode amplifier of the fifth embodiment is a modification of the cascode amplifier of the fourth embodiment. Elements similar to those of the cascode amplifier of the fourth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 5a of FIG. 9 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascade connected between the first transistor MP11 and the output terminal.
  • the cascode amplifier 5a of FIG. 9 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal.
  • the cascode amplifier 5a shown in FIG. further includes a feedback circuit connected between the output terminal and the first node N.
  • the cascode amplifier 5a shown in FIG. includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11.
  • the cascode amplifier 5a of FIG. 9 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2.
  • the cascode amplifier 5a of FIG. 9 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11.
  • the cascode amplifier 5a of FIG. 9 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
  • the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND, and the P-type amplifier It includes a second capacitor C2 connected between the gate of the third transistor MP13 and GND, and a third capacitor C3 connected between the gate of the P-type second transistor MP12 and GND.
  • a fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND It includes a fifth capacitor C5 connected between the gate of the third transistor MN13 and GND, and a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
  • the cascode amplifier 5a of FIG. 9 has a configuration in which the output signal of the cascode amplifier 5a is resistance-divided and fed back to the gate of the P-type fourth transistor MP14 and the gate of the N-type fourth transistor MN14.
  • the cascode amplifier 5a of FIG. 9 includes a feedback circuit connected between the output terminal and the gate of the P-type fourth transistor MP14 and the gate of the N-type fourth transistor MN14.
  • the feedback circuit shown in FIG. 2C used in the third and fourth embodiments can be used.
  • the cascode amplifier 5a of FIG. 9 includes a latch circuit LATCH1 connected to the gate of the P-type first transistor MP11, and an eleventh capacitor inserted between the input terminal and the gate of the P-type first transistor MP11. And C11.
  • the latch circuit LATCH1 is composed of a pair of inverter circuits in which inputs as shown in FIG. 9 are connected to outputs, for example.
  • the latch circuit LATCH1 holds a high level or low level voltage applied to the gate of the P-type first transistor MP11.
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 of FIG.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5a in FIG. 9 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
  • the feedback circuit of the cascode amplifier 5a of FIG. 9, the third resistor R13, the seventh resistor R17, and the like do not have frequency characteristics.
  • the cascode amplifier 5a can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the eleventh capacitor inserted between the input terminal and the gate of the P-type first transistor MP11. C11.
  • a voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5a. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5a, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • FIG. 11 is a circuit diagram for explaining a cascode amplifier according to the sixth embodiment.
  • the cascode amplifier according to the sixth embodiment is a modification of the cascode amplifier according to the fifth embodiment. Elements similar to those of the cascode amplifier of the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 5b of FIG. 11 further includes a thirteenth capacitor C13 in addition to the same configuration as that of the fifth embodiment.
  • the thirteenth capacitor C13 is inserted between one end different from one end connected to the gate of the P-type first transistor MP11 of the latch circuit LATCH1 and a wiring to which a predetermined potential is applied.
  • the latch circuit LATCH1 and the thirteenth capacitor C13 are connected in series between a wiring to which a predetermined potential is applied and the gate of the P-type first transistor MP11.
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given. It is assumed that a potential obtained by inverting the pulse signal of “0” or “1” of the input of the cascode amplifier 5b is applied to a wiring to which a predetermined potential is connected, one end of which is connected to the thirteenth capacitor C13. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 with the sixth resistor R16 or the like.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5b in FIG. 12 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
  • the feedback circuit of the cascode amplifier 5b, the third resistor R13, the seventh resistor R17, and the like of FIG. 11 do not have frequency characteristics.
  • the cascode amplifier 5b can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the input terminal and the gate of the P-type first transistor MP11 are arranged. And an eleventh capacitor C11 inserted into the.
  • a voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal “0” or “1” at the input of the cascode amplifier 5b. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5b, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • a potential obtained by inverting the pulse signal of the input “0” or “1” of the cascode amplifier 5b is connected to a wiring to which a predetermined potential is connected to one end of the thirteenth capacitor C13. Is given.
  • the voltage that is held by the latch circuit LATCH1 and applied to the gate of the P-type first transistor MP11 can follow the change of the input “0” or “1” of the cascode-type amplifier 5b. This can be improved over the amplifier 5a.
  • FIG. 13 is a circuit diagram for explaining the cascode amplifier according to the seventh embodiment.
  • the cascode amplifier according to the seventh embodiment is a modification of the cascode amplifier according to the fifth embodiment. Elements similar to those of the cascode amplifier of the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the cascode amplifier 5c of FIG. 13 has the same configuration as that of the fifth embodiment, a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11, an input terminal, and the gate of the N-type first transistor MN11. And a twelfth capacitor C12 inserted between the first and second capacitors.
  • the latch circuit LATCH2 is composed of a pair of inverter circuits whose inputs are connected to the outputs as shown in FIG. 13, for example.
  • the latch circuit LATCH2 holds a high level or low level voltage applied to the gate of the N-type first transistor MN11.
  • the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 with the sixth resistor R16 or the like.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5c in FIG. 14 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
  • the feedback circuit of the cascode amplifier 5c of FIG. 13, the third resistor R13, the seventh resistor R17, and the like do not have frequency characteristics.
  • the cascode amplifier 5c can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the input terminal and the gate of the P-type first transistor MP11 are arranged. And an eleventh capacitor C11 inserted into the.
  • a voltage obtained by resistance-dividing the second power source V2 with the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5c. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5c, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 and a twelfth capacitor inserted between the input terminal and the gate of the N-type first transistor MN11. C12.
  • a voltage obtained by dividing the third power source V3 by a tenth resistor R20 or the like at the gate of the N-type first transistor MN11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5c. 1V or 0V can be applied.
  • the latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 improves the follow-up to the input change of the cascode amplifier 5c, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • the cascode amplifier 5c of FIG. 13 includes a latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11. This improves the symmetry of the overall circuit configuration of the cascode amplifier 5c.
  • FIG. 15 is a circuit diagram for explaining a cascode amplifier according to an eighth embodiment.
  • the cascode amplifier according to the eighth embodiment is a modification of the cascode amplifier according to the fifth to seventh embodiments. Elements similar to those of the cascode amplifiers of the fifth to seventh embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the latch circuit 15 has a configuration similar to that of the fifth embodiment, a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11, an input terminal, and a gate of the N-type first transistor MN11. And a twelfth capacitor C12 inserted between the first and second capacitors.
  • the latch circuit LATCH2 is composed of a pair of inverter circuits whose inputs are connected to the outputs, for example, as shown in FIG.
  • the latch circuit LATCH2 holds a high level or low level voltage applied to the gate of the N-type first transistor MN11.
  • the second power supply V2 With reference to the power supply voltage V DD , the second power supply V2 outputs a voltage of V DD ⁇ 4 that is four times the power supply voltage V DD .
  • the third power supply V3 is GND, and 0 V (V DD ⁇ 0) is given.
  • connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V
  • the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
  • the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do.
  • the output terminal of the cascode amplifier 5d in FIG. 16 outputs 4V or 0V according to the pulse signal (0V or 1V) of “0” or “1” from the signal source 6.
  • the cascode amplifier 5d can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11, the input terminal, and the gate of the P-type first transistor MP11 And an eleventh capacitor C11 inserted therebetween.
  • a voltage obtained by resistance-dividing the second power source V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal “0” or “1” at the input of the cascode amplifier 5d. 4V or 3V can be applied.
  • the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5d, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • the latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 and the twelfth capacitor inserted between the input terminal and the gate of the N-type first transistor MN11. C12.
  • a voltage obtained by resistance-dividing the third power source V3 by the tenth resistor R20 or the like at the gate of the N-type first transistor MN11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5d. 1V or 0V can be applied.
  • the latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 improves the follow-up to the input change of the cascode amplifier 5d, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
  • a potential obtained by inverting the pulse signal of “0” or “1” input to the input terminal (input 1) of the cascode amplifier 5d is given from the input terminal (input 2).
  • the voltage held by the latch circuit LATCH1 and applied to the gate of the P-type first transistor MP11 and the voltage held by the latch circuit LATCH2 and applied to the gate of the N-type first transistor MN11 are stabilized.
  • the followability with respect to the change of the input “0” or “1” to the input terminal (input 1) of the cascode amplifier 5d can be improved as compared with the cascode amplifier 5a of FIG.
  • the symmetry of the circuit configuration of the cascode amplifier is improved.
  • FIG. 17 is a block diagram for explaining a wireless communication device according to another embodiment.
  • the 17 includes a cascode amplifier 101 that amplifies and outputs an input signal, and an antenna 102 that is connected to the output of the cascode amplifier 101 and transmits a radio signal.
  • the cascode amplifier 101 the cascode amplifiers of the first to eighth embodiments described above can be used.
  • the wireless communication device 100 of FIG. 17 employing this can be miniaturized. Therefore, according to the wireless communication device 100 of FIG.
  • the present invention has been described above, but the present invention is not limited to this.
  • the case where the element withstand voltage of the transistors constituting the cascode amplifier is 1 V has been described, but the present invention is not limited to this.
  • the case where the output level of the signal source 6 is 0V or 1V has been described.
  • the present invention is not limited to this.
  • the specific values of the potentials of the first power supply V1, the second power supply V2, the third power supply V3, the fourth power supply V4 and the like are not limited to the above-described embodiments, and may be set as appropriate while maintaining the mutual magnitude relationship. It goes without saying that various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention.

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Abstract

Provided are: a cascode-type amplifier in which band widening is achieved while the element withstanding voltage of a constituting element is maintained in an allowable range; and a wireless communication device. The cascode-type amplifier includes a plurality of transistors, and has a configuration in which an output signal is subjected to resistive division to be fed back to gates of cascode transistors.

Description

カスコード型増幅器、及び無線通信機Cascode amplifier and wireless communication device
　本発明は、カスコード型増幅器、及び無線通信機に関し、特にカスコード型増幅器の広帯域化に関する。 The present invention relates to a cascode amplifier and a radio communication device, and more particularly, to a broadband cascode amplifier.
　携帯電話や無線ＬＡＮ（Local Area Network）等の無線通信機器の送信部には、出力電力の大きさに関係なく、送信信号の精度を確保しつつ、低消費電力で動作することが求められる。特に、無線通信機器の送信部最終段の電力増幅器は、無線通信機器全体の消費電力の５０％以上を占めるため、高い電力効率であることが求められる。 A transmission unit of a wireless communication device such as a mobile phone or a wireless LAN (Local Area Network) is required to operate with low power consumption while ensuring the accuracy of a transmission signal regardless of the magnitude of output power. In particular, the power amplifier at the final stage of the transmission unit of the wireless communication device occupies 50% or more of the power consumption of the entire wireless communication device, and thus is required to have high power efficiency.
　近年、高い電力効率を有していると期待される電力増幅器として、スイッチング増幅器が注目されている。このスイッチング増幅器は、入力信号としてパルス波形信号を想定し、入力信号の波形を維持して電力増幅することが可能である。スイッチング増幅器によって増幅されたパルス波形信号は、フィルタ素子により所望の周波数成分以外の周波数成分を十分に抑圧した後、アンテナより空中に放射される。 In recent years, switching amplifiers have attracted attention as power amplifiers that are expected to have high power efficiency. This switching amplifier assumes a pulse waveform signal as an input signal, and can amplify power while maintaining the waveform of the input signal. The pulse waveform signal amplified by the switching amplifier is radiated from the antenna into the air after sufficiently suppressing frequency components other than the desired frequency component by the filter element.
　特許文献１は、このようなスイッチング増幅器に関するものであり、電源とグランド（ＧＮＤ）との間に、２つのスイッチ素子が直列に挿入され、スイッチ素子の接続点を出力端子とするＤ級増幅器によるスイッチング増幅器が提案されている。特許文献１のスイッチング増幅器では、２つのスイッチ素子には相補的なパルス信号が入力され、２つのスイッチ素子のうちいずれか一方のスイッチ素子のみがＯＮ状態となるように制御される。さらに特許文献１ではＤ級増幅器の耐圧を、Ｄ級増幅器を構成するスイッチ素子の耐圧以上に向上させる回路技術として、各スイッチ素子と出力端子との間にカスコードトランジスタを挿入したカスコード型増幅器と呼ばれる構成が、提案されている。しかしながら、特許文献１では挿入されたカスコードトランジスタに印加される電圧を耐圧以下に維持する、具体的な構成は見当たらない。 Patent Document 1 relates to such a switching amplifier, and is based on a class D amplifier in which two switch elements are inserted in series between a power source and a ground (GND) and a connection point of the switch elements is an output terminal. Switching amplifiers have been proposed. In the switching amplifier of Patent Document 1, complementary pulse signals are input to the two switch elements, and only one of the two switch elements is controlled to be in the ON state. Further, in Patent Document 1, as a circuit technique for improving the withstand voltage of a class D amplifier to be higher than the withstand voltage of a switch element constituting the class D amplifier, it is called a cascode amplifier in which a cascode transistor is inserted between each switch element and an output terminal. A configuration is proposed. However, in Patent Document 1, there is no specific configuration that maintains the voltage applied to the inserted cascode transistor below the breakdown voltage.
　非特許文献１は、ミリ波の高出力ＤＡＣ（Digital to Analog Converter）送信器に関するものであり、出力段のＤ級ＣＭＯＳ（Complementary Metal Oxide Semiconductor）増幅器が提案されている。非特許文献１のＤ級ＣＭＯＳ増幅器では、４５ＧＨｚ、９０ＧＨｚ、１１０ＧＨｚや１３８ＧＨｚといった周波数の入力信号に対し、Ｄ級ＣＭＯＳ増幅器を構成する抵抗、キャパシタやインダクタなどの回路素子を用いることにより高利得のＤ級ＣＭＯＳ増幅器を実現することができる。 Non-Patent Document 1 relates to a millimeter-wave high-power DAC (Digital-to-Analog Converter) transmitter, and a D-class CMOS (Complementary Metal-Oxide Semiconductor) amplifier in the output stage has been proposed. In the class D CMOS amplifier of Non-Patent Document 1, a high gain D is obtained by using circuit elements such as resistors, capacitors, and inductors constituting the class D CMOS amplifier for input signals having frequencies of 45 GHz, 90 GHz, 110 GHz, and 138 GHz. Class CMOS amplifier can be realized.
　図１８は、非特許文献１が提案する出力段のＤ級ＣＭＯＳ増幅器と同様な回路構成のカスコード型増幅器の一例を示す回路図である。図１８のカスコード型増幅器は、信号源からの例えば１Ｖと０Ｖとの間で変化するサイン波を反転して増幅する増幅器である。図１８のカスコード型増幅器は、入力信号を第４電源Ｖ４（ＶＤＤ×３）によってレベルシフトした信号をゲートに入力するＰ型の第１トランジスタＭＰ１１と、第１トランジスタＭＰ１１と出力端子との間に縦続接続されたＰ型の第２トランジスタＭＰ１２、第３トランジスタＭＰ１３、及び第４トランジスタＭＰ１４と、を含む。さらに図１８のカスコード型増幅器は、入力信号をゲートに入力するＮ型の第１トランジスタＭＮ１１と、第１トランジスタＭＮ１１と出力端子との間に縦続接続されたＮ型の第２トランジスタＭＮ１２、第３トランジスタＭＮ１３、及び第４トランジスタＭＮ１４と、を含む。第１トランジスタＭＰ１１、第２トランジスタＭＰ１２、第３トランジスタＭＰ１３、第４トランジスタＭＰ１４、第１トランジスタＭＮ１１、第２トランジスタＭＮ１２、第３トランジスタＭＮ１３、及び第４トランジスタＭＮ１４は、第２電源Ｖ２（ＶＤＤ×４）と第３電源Ｖ３（ＧＮＤ）との間に縦続接続されている。 FIG. 18 is a circuit diagram showing an example of a cascode amplifier having a circuit configuration similar to that of the output stage class D CMOS amplifier proposed by Non-Patent Document 1. The cascode amplifier in FIG. 18 is an amplifier that inverts and amplifies a sine wave that changes between 1 V and 0 V, for example, from a signal source. The cascode amplifier in FIG. 18 includes a P-type first transistor MP11 that inputs a signal obtained by level-shifting an input signal by a fourth power supply V4 (V DD × 3) to the gate, and between the first transistor MP11 and the output terminal. P-type second transistor MP12, third transistor MP13, and fourth transistor MP14 connected in cascade. 18 includes an N-type first transistor MN11 that inputs an input signal to the gate, an N-type second transistor MN12 that is connected in cascade between the first transistor MN11 and the output terminal, A transistor MN13 and a fourth transistor MN14 are included. The first transistor MP11, the second transistor MP12, the third transistor MP13, the fourth transistor MP14, the first transistor MN11, the second transistor MN12, the third transistor MN13, and the fourth transistor MN14 are connected to the second power source V2 (V DD × 4) and the third power supply V3 (GND) are connected in cascade.
　さらに図１８のカスコード型増幅器は、隣接するカスコードトランジスタのゲート間に接続された抵抗を含む。例えば、第３トランジスタＭＰ１３のゲートと、第４トランジスタＭＰ１４のゲートとの間や、第４トランジスタＭＰ１４のゲートと、第４トランジスタＭＮ１４のゲートとの間にはそれぞれ抵抗が接続されている。さらに図１８のカスコード型増幅器は、カスコードトランジスタのゲート端子とＧＮＤとの間に接続されたキャパシタを含む。 18 further includes a resistor connected between the gates of adjacent cascode transistors. For example, resistors are connected between the gate of the third transistor MP13 and the gate of the fourth transistor MP14, and between the gate of the fourth transistor MP14 and the gate of the fourth transistor MN14, respectively. Further, the cascode amplifier of FIG. 18 includes a capacitor connected between the gate terminal of the cascode transistor and GND.
　図１８のカスコード型増幅器によれば、信号源からの例えば１Ｖから０Ｖの間で変化するサイン波の入力信号を反転増幅して、出力端子から０Ｖから４Ｖの間で変化するサイン波の出力信号を得ることができる。さらに、隣接するカスコードトランジスタのゲート間に接続された抵抗によって、カスコード型増幅器を構成するカスコードトランジスタに印加される電圧を、耐圧以下に維持しながらバイアスすることができる。また、高周波では、ドレイン端子の電位が大きく振れても、カスコードトランジスタとＧＮＤとの間に接続された容量を適切な値に設定しておくことで、本容量のアドミタンスと、各トランジスタのドレイン－ゲート間容量のアドミタンスの比率により、ドレイン－ゲート間の電位差を耐圧内に収めるように、ゲートの振幅を適切な値に設計することができる。なお、ゲート端子に接続された抵抗のアドミタンスは、各容量に比較して、無視できるほど小さくなる値に設計されることが条件である。 According to the cascode amplifier of FIG. 18, a sine wave input signal that changes between 1 V and 0 V, for example, from a signal source is inverted and amplified, and a sine wave output signal that changes between 0 V and 4 V from the output terminal. Can be obtained. Further, the voltage applied to the cascode transistors constituting the cascode amplifier can be biased by a resistor connected between the gates of adjacent cascode transistors while maintaining the voltage below the breakdown voltage. At high frequencies, even if the potential of the drain terminal fluctuates greatly, by setting the capacitance connected between the cascode transistor and GND to an appropriate value, the admittance of this capacitance and the drain − Depending on the admittance ratio of the capacitance between the gates, the gate amplitude can be designed to an appropriate value so that the potential difference between the drain and gate falls within the breakdown voltage. Note that the admittance of the resistor connected to the gate terminal is required to be designed to a value that is negligibly small compared to each capacitor.
　特許文献２は、複数の差動増幅器が遅延素子を介在させて互いに並列に接続された進行波型増幅器に関するものであり、カスコードトランジスタのコレクタ出力がベース入力に抵抗分圧回路を介して帰還されるように構成することが提案されている。 Patent Document 2 relates to a traveling wave amplifier in which a plurality of differential amplifiers are connected in parallel to each other with a delay element interposed therebetween, and a collector output of a cascode transistor is fed back to a base input via a resistance voltage dividing circuit. It has been proposed to configure such that.
国際公開第２０１６／０２１０９２号International Publication No. 2016/021092 特開２０１４－２２０７７０号公報JP 2014-220770 A
　無線通信の５Ｇ基地局へのスイッチング増幅器の適用を想定すると、スイッチング増幅器は例えば２０Ｇｂｐｓまでに到る広帯域の１ｂｉｔ変調信号を増幅できることが求められる。本変調信号は、直流（＝０Ｈｚ）から１０ＧＨｚ以上の高周波帯までの信号成分を持つ。 Assuming application of a switching amplifier to a 5G base station for wireless communication, the switching amplifier is required to be able to amplify a wide band 1-bit modulation signal up to 20 Gbps, for example. This modulation signal has a signal component from a direct current (= 0 Hz) to a high frequency band of 10 GHz or more.
　図１８のような回路接続のカスコード型増幅器では、無線通信の５Ｇ基地局へのスイッチング増幅器に適用した場合、各カスコードトランジスタのゲートに接続されたキャパシタの容量を設定することにより、高周波領域の特定周波数帯の信号に対しては、各トランジスタの端子間電位が素子耐圧以内に収まるように、設計することができる。 In the case of a cascode amplifier having a circuit connection as shown in FIG. 18, when applied to a switching amplifier for a 5G base station for wireless communication, the capacitance of a capacitor connected to the gate of each cascode transistor is set to specify a high frequency region. For a signal in a frequency band, it can be designed so that the potential between terminals of each transistor is within the device breakdown voltage.
　しかしながら、特に、低周波信号に対しては、トランジスタのドレイン－ゲート間容量のアドミタンスが小さくなり、ゲートに接続された抵抗のアドミタンスに比較しても小さくなると、ドレイン端子の振幅が大きくなっても、ゲートの振幅は小さく、ドレイン－ゲート端子間で、素子耐圧を超えてしまう電位が発生する。 However, particularly for low-frequency signals, the admittance of the drain-gate capacitance of the transistor is small, and even if the admittance of the resistor connected to the gate is small, the amplitude of the drain terminal may be large. The amplitude of the gate is small, and a potential that exceeds the device breakdown voltage is generated between the drain and gate terminals.
　結果として、図１８のような回路接続のカスコード型増幅器に、直流から１０ＧＨｚ以上にまでわたる信号成分を持つ２０Ｇｂｐｓまでに到る広帯域の１ｂｉｔ変調信号を入力した場合、各素子において、耐圧以下での動作が保証されなくなる。 As a result, when a broadband 1-bit modulation signal ranging from DC to 20 Gbps having a signal component ranging from DC to 10 GHz or more is input to the circuit-connected cascode amplifier as shown in FIG. Operation is not guaranteed.
　本発明の目的は、構成素子に印加される電圧を耐圧以下に維持しつつ、直流から高周波領域までの広帯域化を実現するカスコード型増幅器、及び無線通信機を提供することにある。 An object of the present invention is to provide a cascode amplifier and a wireless communication device that realize a wide band from a direct current to a high frequency region while maintaining a voltage applied to a component below a withstand voltage.
　前記目的を達成するため、本発明に係るカスコード型増幅器は、
　複数のトランジスタ
　　を含む、カスコード型増幅器であって、
　出力信号を抵抗分割してカスコードトランジスタのゲートに帰還する構成
　　を含む。 In order to achieve the above object, a cascode amplifier according to the present invention comprises:
A cascode amplifier including a plurality of transistors,
Includes a configuration in which the output signal is divided into resistors and fed back to the gate of the cascode transistor.
　また本発明に係る無線通信機は、
　上記カスコード型増幅器と、
　上記カスコード型増幅器の出力に接続されたアンテナと、
　　を含む。 A wireless communication device according to the present invention
The cascode amplifier, and
An antenna connected to the output of the cascode amplifier;
including.
　本発明によれば、構成素子の素子耐圧を許容範囲内に維持しつつ、広帯域化を実現するカスコード型増幅器を提供できる。 According to the present invention, it is possible to provide a cascode amplifier that realizes a wide band while maintaining the element breakdown voltage within the allowable range.
上位概念による実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of embodiment by a high-order concept. （ａ）は図１などの帰還回路の回路ブロックであり、（ｂ）は（ａ）の帰還回路の具体的構成例１を示す回路図であり、（ｃ）は（ａ）の帰還回路の具体的構成例２を示す回路図である。(A) is a circuit block of the feedback circuit of FIG. 1 and the like, (b) is a circuit diagram showing a specific configuration example 1 of the feedback circuit of (a), and (c) is a circuit diagram of the feedback circuit of (a). It is a circuit diagram which shows the specific structural example 2. FIG. 第１実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 1st Embodiment. 第１実施形態のカスコード型増幅器の信号波形を説明するための説明図である。It is explanatory drawing for demonstrating the signal waveform of the cascode type | mold amplifier of 1st Embodiment. 第２実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 2nd Embodiment. 第２実施形態のカスコード型増幅器の信号波形を説明するための説明図である。It is explanatory drawing for demonstrating the signal waveform of the cascode type | mold amplifier of 2nd Embodiment. 第３実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 3rd Embodiment. 第４実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 4th Embodiment. 第５実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 5th Embodiment. 第５実施形態のカスコード型増幅器の信号波形を説明するための説明図である。It is explanatory drawing for demonstrating the signal waveform of the cascode type | mold amplifier of 5th Embodiment. 第６実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 6th Embodiment. 第６実施形態のカスコード型増幅器の信号波形を説明するための説明図である。It is explanatory drawing for demonstrating the signal waveform of the cascode type | mold amplifier of 6th Embodiment. 第７実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 7th Embodiment. 第７実施形態のカスコード型増幅器の信号波形を説明するための説明図である。It is explanatory drawing for demonstrating the signal waveform of the cascode type | mold amplifier of 7th Embodiment. 第８実施形態のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of 8th Embodiment. 第８実施形態のカスコード型増幅器の信号波形を説明するための説明図である。It is explanatory drawing for demonstrating the signal waveform of the cascode type | mold amplifier of 8th Embodiment. 実施形態のカスコード型増幅器を用いた無線通信機を説明するためのブロック図である。It is a block diagram for demonstrating the radio | wireless communication apparatus using the cascode type | mold amplifier of embodiment. 背景技術のカスコード型増幅器を説明するための回路図である。It is a circuit diagram for demonstrating the cascode type | mold amplifier of background art.
　本発明の好ましい実施形態について、図面を参照しながら詳細に説明する。具体的な実施形態を説明する前に、上位概念による実施形態について説明する。図１は、本発明の上位概念による実施形態のカスコード型増幅器を説明するための回路図である。 Preferred embodiments of the present invention will be described in detail with reference to the drawings. Before describing a specific embodiment, an embodiment based on a superordinate concept will be described. FIG. 1 is a circuit diagram for explaining an embodiment of a cascode amplifier according to a superordinate concept of the present invention.
　図１のカスコード型増幅器１０は、複数のトランジスタを含むカスコード型増幅器であって、出力信号を抵抗分割してカスコードトランジスタのゲートに帰還する構成を含むものである。 The cascode amplifier 10 in FIG. 1 is a cascode amplifier including a plurality of transistors, and includes a configuration in which an output signal is resistance-divided and fed back to the gate of the cascode transistor.
　図１のカスコード型増幅器１０は、入力端子からの入力信号がゲートに入力する第１導電型の第１トランジスタＭ１と、第１トランジスタＭ１と出力端子との間に縦続接続された第１導電型の第２トランジスタＭ２と、を含む。さらに図１のカスコード型増幅器１０は、入力端子からの入力信号がゲートにされる第２導電型の第３トランジスタＭ３と、第３トランジスタＭ３と出力端子との間に縦続接続された第２導電型の第４トランジスタＭ４と、を含む。 The cascode amplifier 10 of FIG. 1 includes a first conductivity type first transistor M1 in which an input signal from an input terminal is input to a gate, and a first conductivity type cascaded between the first transistor M1 and an output terminal. Second transistor M2. Further, the cascode amplifier 10 of FIG. 1 includes a second conductivity type third transistor M3 whose gate is an input signal from the input terminal, and a second conductivity type connected in cascade between the third transistor M3 and the output terminal. Type fourth transistor M4.
　さらに図１のカスコード型増幅器１０は、第１ノードＮと第１トランジスタＭ１のゲートとの間に接続された第１抵抗Ｒ１と、第１トランジスタＭ１のゲートと第２電源Ｖ２との間に接続された第２抵抗Ｒ２と、を含む。さらに図１のカスコード型増幅器１０は、第１ノードＮと第３トランジスタＭ３のゲートとの間に接続された第３抵抗Ｒ３と、第３トランジスタＭ３のゲートと第３電源Ｖ３との間に接続された第４抵抗Ｒ４と、を含む。 Further, the cascode amplifier 10 of FIG. 1 is connected between the first resistor R1 connected between the first node N and the gate of the first transistor M1, and between the gate of the first transistor M1 and the second power supply V2. Second resistor R2. 1 is connected between the first node N and the gate of the third transistor M3, and between the gate of the third transistor M3 and the third power supply V3. And a fourth resistor R4.
　さらに図１のカスコード型増幅器１０は、出力信号を帰還回路を介して第２トランジスタＭ２のゲート及び第４トランジスタＭ４のゲートに帰還する構成を含む。帰還回路は、抵抗分割回路で構成され、出力信号を抵抗分割により減衰させて、第２トランジスタＭ２／第４トランジスタＭ４の各ゲート端子に帰還する。帰還回路としては、図２の（ｂ）や図２の（ｃ）のような回路構成とすることができる。図２の（ａ）は図１などの帰還回路の回路ブロックであり、図２の（ｂ）は図２の（ａ）の帰還回路の具体的構成例１を示す回路図であり、図２の（ｃ）は図２の（ａ）の帰還回路の具体的構成例２を示す回路図である。 Further, the cascode amplifier 10 of FIG. 1 includes a configuration in which an output signal is fed back to the gate of the second transistor M2 and the gate of the fourth transistor M4 through a feedback circuit. The feedback circuit is configured by a resistance divider circuit, attenuates the output signal by resistance division, and feeds back to each gate terminal of the second transistor M2 / fourth transistor M4. The feedback circuit may have a circuit configuration as shown in (b) of FIG. 2 or (c) of FIG. 2A is a circuit block of the feedback circuit of FIG. 1 and the like, and FIG. 2B is a circuit diagram showing a specific configuration example 1 of the feedback circuit of FIG. (C) of FIG. 2 is a circuit diagram showing a specific configuration example 2 of the feedback circuit of FIG. 2 (a).
　図１のカスコード型増幅器１０では、入力信号を増幅して出力することができる。その際、第１抵抗Ｒ１乃至第４抵抗Ｒ４により、カスコード型増幅器１０に含まれる第１トランジスタＭ１乃至第４トランジスタＭ４のゲート・ソース間電圧、ゲート・ドレイン間電圧を、第１トランジスタＭ１乃至第４トランジスタＭ４の素子耐圧未満に維持することができ、第１トランジスタＭ１乃至第４トランジスタＭ４の破壊を防止することができる。 1 can amplify an input signal and output the amplified signal. At this time, the first to fourth resistors R1 to R4 change the gate-source voltages and the gate-to-drain voltages of the first to fourth transistors M1 to M4 included in the cascode amplifier 10, respectively. It can be kept below the element breakdown voltage of the four transistors M4, and the first to fourth transistors M1 to M4 can be prevented from being destroyed.
　抵抗は周波数特性を持たないので、図１のカスコード型増幅器１０の帰還回路、第１抵抗Ｒ１、第２抵抗Ｒ２、第３抵抗Ｒ３、第４抵抗Ｒ４などは周波数特性を持たない。これにより第１トランジスタＭ１、第２トランジスタＭ２、第３トランジスタＭ３、第４トランジスタＭ４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器を広帯域化することができる。 Since the resistors do not have frequency characteristics, the feedback circuit of the cascode amplifier 10 of FIG. 1, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, etc. do not have frequency characteristics. As a result, the cascode amplifier can be widened while maintaining the breakdown voltage of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 within an allowable range.
　以下、より具体的な実施形態について説明する。 Hereinafter, more specific embodiments will be described.
　〔第１実施形態〕
　次に、第１実施形態によるカスコード型増幅器について、図面を参照しながら説明する。図３は、第１実施形態のカスコード型増幅器を説明するための回路図である。図４は、第１実施形態のカスコード型増幅器の信号波形を説明するための説明図である。 [First Embodiment]
Next, the cascode amplifier according to the first embodiment will be described with reference to the drawings. FIG. 3 is a circuit diagram for explaining the cascode amplifier according to the first embodiment. FIG. 4 is an explanatory diagram for explaining signal waveforms of the cascode amplifier according to the first embodiment.
　図３のカスコード型増幅器１は、入力端子からの入力信号がゲートに入力される第１導電型の一例としてのＰ型の第１トランジスタＭＰ１１と、第１トランジスタＭＰ１１と出力端子との間に縦続接続されたＰ型の第２トランジスタＭＰ１２、第３トランジスタＭＰ１３、及び第４トランジスタＭＰ１４と、を含む。なおここで、２つの入力信号のうち一方の信号は、第４電源Ｖ４を介してＰ型の第１トランジスタＭＰ１１のゲートへ与えられるものとする。 The cascode amplifier 1 of FIG. 3 includes a P-type first transistor MP11 as an example of a first conductivity type in which an input signal from an input terminal is input to a gate, and a cascade connection between the first transistor MP11 and the output terminal. A P-type second transistor MP12, a third transistor MP13, and a fourth transistor MP14 are connected. Here, it is assumed that one of the two input signals is given to the gate of the P-type first transistor MP11 via the fourth power supply V4.
　さらに図３のカスコード型増幅器１は、入力端子からの入力信号がゲートに入力される第２導電型の一例としてのＮ型の第１トランジスタＭＮ１１と、Ｎ型の第１トランジスタＭＮ１１と出力端子との間に縦続接続されたＮ型の第２トランジスタＭＮ１２、第３トランジスタＭＮ１３、及び第４トランジスタＭＮ１４と、を含む。 Further, the cascode amplifier 1 of FIG. 3 includes an N-type first transistor MN11 as an example of a second conductivity type in which an input signal from an input terminal is input to the gate, an N-type first transistor MN11, and an output terminal. N-type second transistor MN12, third transistor MN13, and fourth transistor MN14 connected in cascade.
　さらに図３のカスコード型増幅器１は、カスコード型増幅器１の出力信号を抵抗分割して、各トランジスタのゲートに帰還する構成を持つ。 Further, the cascode amplifier 1 of FIG. 3 has a configuration in which the output signal of the cascode amplifier 1 is resistance-divided and fed back to the gate of each transistor.
　図３のカスコード型増幅器１では、出力端子と第１ノードＮとの間に接続された第１抵抗Ｒ１１と、第１電源Ｖ１（ＶＤＤ×２）と第１ノードＮとの間に接続された第２抵抗Ｒ１２と、を含んで、出力信号を抵抗分割してカスコードトランジスタのゲートに帰還する構成を実現している。この構成は、図２の（ｂ）に示される帰還回路の具体的構成例１に対応する。 In the cascode amplifier 1 of FIG. 3, the first resistor R11 connected between the output terminal and the first node N, and the first power supply V1 (V DD × 2) and the first node N are connected. The second resistor R12 is included, and the output signal is divided into resistors and fed back to the gate of the cascode transistor. This configuration corresponds to a specific configuration example 1 of the feedback circuit shown in FIG.
　さらに図３のカスコード型増幅器１は、第１ノードＮとＰ型の第１トランジスタＭＰ１１のゲートとの間に直列接続された第３抵抗Ｒ１３、第４抵抗Ｒ１４、第５抵抗Ｒ１５を含む。さらに図３のカスコード型増幅器１は、Ｐ型の第１トランジスタＭＰ１１のゲートと第２電源Ｖ２（ＶＤＤ×４）との間に接続された第６抵抗Ｒ１６と、を含む。さらに図３のカスコード型増幅器１は、第１ノードＮとＮ型の第１トランジスタＭＮ１１のゲートとの間に直列接続された第７抵抗Ｒ１７、第８抵抗Ｒ１８、第９抵抗Ｒ１９を含む。さらに図３のカスコード型増幅器１は、Ｎ型の第１トランジスタＭＮ１１のゲートと第３電源Ｖ３（ＧＮＤ）との間に接続された第１０抵抗Ｒ２０と、を含む。 Further, the cascode amplifier 1 of FIG. 3 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 1 of FIG. 3 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2 (V DD × 4). Further, the cascode amplifier 1 of FIG. 3 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11. Further, the cascode amplifier 1 of FIG. 3 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3 (GND).
　なおここで、第３抵抗Ｒ１３と第４抵抗Ｒ１４との接続点は、Ｐ型の第３トランジスタＭＰ１３のゲートに接続されており、第４抵抗Ｒ１４と第５抵抗Ｒ１５との接続点は、Ｐ型の第２トランジスタＭＰ１２のゲートに接続されている。なおここで、第７抵抗Ｒ１７と第８抵抗Ｒ１８との接続点は、Ｎ型の第３トランジスタＭＮ１３のゲートに接続されており、第８抵抗Ｒ１８と第９抵抗Ｒ１９との接続点は、Ｎ型の第２トランジスタＭＮ１２のゲートに接続されている。 Here, the connection point between the third resistor R13 and the fourth resistor R14 is connected to the gate of the P-type third transistor MP13, and the connection point between the fourth resistor R14 and the fifth resistor R15 is P It is connected to the gate of the second transistor MP12 of the type. Here, the connection point between the seventh resistor R17 and the eighth resistor R18 is connected to the gate of the N-type third transistor MN13, and the connection point between the eighth resistor R18 and the ninth resistor R19 is N The second transistor MN12 of the type is connected to the gate.
　さらにＰ型の第１トランジスタＭＰ１１のソースは、第２電源Ｖ２（ＶＤＤ×４）に接続されており、Ｎ型の第１トランジスタＭＮ１１のソースは、第３電源Ｖ３（ＧＮＤ）に接続されている。 Further, the source of the P-type first transistor MP11 is connected to the second power supply V2 (V DD × 4), and the source of the N-type first transistor MN11 is connected to the third power supply V3 (GND). Yes.
　（実施形態の動作）
　次に図３のカスコード型増幅器１の動作について、図４を参照して説明する。図４では、図３のカスコード型増幅器１の入力端子に信号源６が接続された状態を示す。信号源６は、例えば２０Ｇｂｐｓまでに到る広帯域の１ｂｉｔ変調信号である”０”又は”１”のパルス信号を出力するものとする。Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧は、一例として１Ｖであるものとして説明する。また、以下、電源電圧ＶＤＤは、素子耐圧と等しい値に設定されており、１Ｖであるものとして説明する。 (Operation of the embodiment)
Next, the operation of the cascode amplifier 1 of FIG. 3 will be described with reference to FIG. 4 shows a state in which the signal source 6 is connected to the input terminal of the cascode amplifier 1 of FIG. The signal source 6 outputs a pulse signal of “0” or “1”, which is a 1-bit modulated signal in a wide band up to 20 Gbps, for example. The element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example. In the following description, it is assumed that the power supply voltage V DD is set to a value equal to the element breakdown voltage and is 1V.
　電源電圧ＶＤＤを基準として、第１電源Ｖ１乃至第３電源Ｖ３は次の電圧を出力するものとする。すなわち、第１電源Ｖ１は電源電圧ＶＤＤの２倍のＶＤＤ×２の電圧を出力する。第２電源Ｖ２は、電源電圧ＶＤＤの４倍のＶＤＤ×４の電圧を出力する。第４電源Ｖ４は電源電圧ＶＤＤの３倍のＶＤＤ×３の電圧を出力する。第３電源Ｖ３はＧＮＤであり、０Ｖ（ＶＤＤ×０）が与えられるものとする。 The first power supply V1 to the third power supply V3 output the following voltages with the power supply voltage V DD as a reference. That is, the first power supply V1 outputs a voltage of V DD × 2 that is twice the power supply voltage V DD . The second power supply V2 outputs a voltage of V DD × 4 that is four times the power supply voltage V DD . The fourth power supply V4 outputs a voltage of V DD × 3 that is three times the power supply voltage V DD . The third power supply V3 is GND, and 0 V (V DD × 0) is given.
　信号源６からの”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートには４Ｖ又は３Ｖが与えられ、Ｎ型の第１トランジスタＭＮ１１のゲートには０Ｖ又は１Ｖが与えられる。これに伴って、縦続接続されたＰ型の第１トランジスタＭＰ１１と第２トランジスタＭＰ１２との接続点は４Ｖと３Ｖとの間で変化し、縦続接続されたＰ型の第２トランジスタＭＰ１２と第３トランジスタＭＰ１３との接続点は４Ｖと２Ｖとの間で変化し、縦続接続されたＰ型の第３トランジスタＭＰ１３と第４トランジスタＭＰ１４との接続点は４Ｖと１Ｖとの間で変化する。また、縦続接続されたＮ型の第１トランジスタＭＮ１１と第２トランジスタＭＮ１２との接続点は１Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第２トランジスタＭＮ１２と第３トランジスタＭＮ１３との接続点は２Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第３トランジスタＭＮ１３と第４トランジスタＭＮ１４との接続点は３Ｖと０Ｖとの間で変化する。 In response to a pulse signal (0V or 1V) of “0” or “1” from the signal source 6, 4V or 3V is applied to the gate of the P-type first transistor MP11, and the N-type first transistor MN11 0V or 1V is applied to the gate. Accordingly, the connection point between the cascaded P-type first transistor MP11 and the second transistor MP12 changes between 4V and 3V, and the cascade-connected P-type second transistor MP12 and the third transistor MP12 are connected to each other. The connection point with the transistor MP13 changes between 4V and 2V, and the connection point between the cascaded P-type third transistor MP13 and the fourth transistor MP14 changes between 4V and 1V. Also, the connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V, and the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
　さらにＰ型の第４トランジスタＭＰ１４のゲート、Ｎ型の第４トランジスタＭＮ１４のゲート、図３の第２抵抗Ｒ１２、及び図３の第１抵抗Ｒ１１の接続点の電位は、３Ｖと１Ｖとの間で変化する。その結果、信号源６からの”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、図４のカスコード型増幅器１の出力端子は４Ｖ又は０Ｖを出力する。 Further, the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, the second resistor R12 in FIG. 3, and the first resistor R11 in FIG. 3 is between 3V and 1V. It changes with. As a result, the output terminal of the cascode amplifier 1 in FIG. 4 outputs 4 V or 0 V in response to a pulse signal (0 V or 1 V) of “0” or “1” from the signal source 6.
　（実施形態の効果）
　以上、図３のカスコード型増幅器１の、信号源６からのパルス信号（０Ｖまたは１Ｖ）に応じた動作において、各トランジスタが持つ３つの端子である、ドレイン、ソース、ゲートの、どの端子間の電圧も、１Ｖもしくは、それ以下になる。すなわち、本カスコード型増幅器１においては、構成素子に印加される電圧は、耐圧以下に維持される。 (Effect of embodiment)
As described above, in the operation according to the pulse signal (0 V or 1 V) from the signal source 6 of the cascode amplifier 1 of FIG. 3, between which of the three terminals of each transistor, the drain, the source, and the gate, The voltage is also 1V or less. That is, in the cascode amplifier 1, the voltage applied to the constituent elements is maintained below the withstand voltage.
　また、抵抗は周波数特性を持たないので、図３のカスコード型増幅器１の第１抵抗Ｒ１１、第２抵抗Ｒ１２、第３抵抗Ｒ１３、第７抵抗Ｒ１７などは周波数特性を持たない。これによりＰ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４に印加される電圧を耐圧以下に維持しつつ、カスコード型増幅器を直流から高周波領域まで広帯域化することができる。 Also, since the resistors do not have frequency characteristics, the first resistor R11, the second resistor R12, the third resistor R13, the seventh resistor R17, etc. of the cascode amplifier 1 of FIG. 3 do not have frequency characteristics. As a result, the cascode amplifier can be widened from a direct current to a high frequency region while maintaining the voltage applied to the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 below the breakdown voltage. Can be
　なお図３のカスコード型増幅器１では、Ｐ型の第１トランジスタＭＰ１１と出力端子との間に３つのトランジスタが縦続接続され、Ｎ型の第１トランジスタＭＮ１１と出力端子との間に３つのトランジスタが縦続接続された場合を示しているが、縦続接続されるトランジスタの段数はこれに限られない。 In the cascode amplifier 1 of FIG. 3, three transistors are connected in cascade between the P-type first transistor MP11 and the output terminal, and three transistors are connected between the N-type first transistor MN11 and the output terminal. Although the case of cascade connection is shown, the number of stages of transistors connected in cascade is not limited to this.
　入力信号に対してより高出力のカスコード型増幅器を構成したいときは、Ｐ型の第１トランジスタＭＰ１１と出力端子との間に縦続接続されるトランジスタと、Ｎ型の第１トランジスタＭＮ１１と出力端子との間に縦続接続されるトランジスタの段数を増やすなどすればよい。 When it is desired to configure a higher output cascode amplifier for an input signal, a transistor connected in cascade between a P-type first transistor MP11 and an output terminal, an N-type first transistor MN11, an output terminal, For example, the number of transistors connected in cascade may be increased.
　〔第２実施形態〕
　次に、第２実施形態によるカスコード型増幅器について、図面を参照しながら説明する。図５は、第２実施形態のカスコード型増幅器を説明するための回路図である。図６は、第２実施形態のカスコード型増幅器の信号波形を説明するための説明図である。 [Second Embodiment]
Next, a cascode amplifier according to a second embodiment will be described with reference to the drawings. FIG. 5 is a circuit diagram for explaining a cascode amplifier according to the second embodiment. FIG. 6 is an explanatory diagram for explaining a signal waveform of the cascode amplifier according to the second embodiment.
　第２実施形態のカスコード型増幅器は、第１実施形態のカスコード型増幅器の変形例である。第１実施形態のカスコード型増幅器と同様な要素に対しては、同じ参照番号を付してその詳細な説明を省略することとする。 The cascode amplifier according to the second embodiment is a modification of the cascode amplifier according to the first embodiment. Elements similar to those of the cascode amplifier of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　図５のカスコード型増幅器２は第１実施形態と同様に、第１導電型の一例としてのＰ型の第１トランジスタＭＰ１１と、第１トランジスタＭＰ１１と出力端子との間に縦続接続されたＰ型の第２トランジスタＭＰ１２、第３トランジスタＭＰ１３、及び第４トランジスタＭＰ１４と、を含む。 As in the first embodiment, the cascode amplifier 2 of FIG. 5 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascaded connection between the first transistor MP11 and the output terminal. Second transistor MP12, third transistor MP13, and fourth transistor MP14.
　さらに図５のカスコード型増幅器２は第１実施形態と同様に、第２導電型の一例としてのＮ型の第１トランジスタＭＮ１１と、Ｎ型の第１トランジスタＭＮ１１と出力端子との間に縦続接続されたＮ型の第２トランジスタＭＮ１２、第３トランジスタＭＮ１３、及び第４トランジスタＭＮ１４と、を含む。 Further, as in the first embodiment, the cascode amplifier 2 of FIG. 5 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal. N-type second transistor MN12, third transistor MN13, and fourth transistor MN14.
　さらに図５のカスコード型増幅器２は第１実施形態と同様に、出力端子と第１ノードＮとの間に接続された第１抵抗Ｒ１１と、第１電源Ｖ１と第１ノードＮとの間に接続された第２抵抗Ｒ１２と、を含む。さらに図５のカスコード型増幅器２は、第１ノードＮとＰ型の第１トランジスタＭＰ１１のゲートとの間に直列接続された第３抵抗Ｒ１３、第４抵抗Ｒ１４、第５抵抗Ｒ１５を含む。さらに図５のカスコード型増幅器２は、Ｐ型の第１トランジスタＭＰ１１のゲートと第２電源Ｖ２との間に接続された第６抵抗Ｒ１６と、を含む。さらに図５のカスコード型増幅器２は、第１ノードＮとＮ型の第１トランジスタＭＮ１１のゲートとの間に直列接続された第７抵抗Ｒ１７、第８抵抗Ｒ１８、第９抵抗Ｒ１９を含む。さらに図５のカスコード型増幅器２は、Ｎ型の第１トランジスタＭＮ１１のゲートと第３電源Ｖ３との間に接続された第１０抵抗Ｒ２０と、を含む。 Further, as in the first embodiment, the cascode amplifier 2 of FIG. 5 includes a first resistor R11 connected between the output terminal and the first node N, and between the first power supply V1 and the first node N. And a second resistor R12 connected thereto. Further, the cascode amplifier 2 of FIG. 5 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 2 of FIG. 5 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 2 of FIG. 5 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11. Further, the cascode amplifier 2 of FIG. 5 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
　さらに図５のカスコード型増幅器２では、Ｐ型の第４トランジスタＭＰ１４のゲートとＧＮＤとの間に接続された第１キャパシタＣ１と、Ｐ型の第３トランジスタＭＰ１３のゲートとＧＮＤとの間に接続された第２キャパシタＣ２と、Ｐ型の第２トランジスタＭＰ１２のゲートとＧＮＤとの間に接続された第３キャパシタＣ３と、を含む。 Further, in the cascode amplifier 2 of FIG. 5, the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND is connected between the gate of the P-type third transistor MP13 and GND. And a third capacitor C3 connected between the gate of the P-type second transistor MP12 and GND.
　さらに図５のカスコード型増幅器２では、Ｎ型の第４トランジスタＭＮ１４のゲートとＧＮＤとの間に接続された第４キャパシタＣ４と、Ｎ型の第３トランジスタＭＮ１３のゲートとＧＮＤとの間に接続された第５キャパシタＣ５と、Ｎ型の第２トランジスタＭＮ１２のゲートとＧＮＤとの間に接続された第６キャパシタＣ６と、を含む。 Further, in the cascode amplifier 2 of FIG. 5, the fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND and the gate connected to the gate of the N-type third transistor MN13 and GND. And a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
　図５のカスコード型増幅器２では第１実施形態と同様に、出力端子と第１ノードＮとの間に接続された第１抵抗Ｒ１１と、第１電源Ｖ１（ＶＤＤ×２）と第１ノードＮとの間に接続された第２抵抗Ｒ１２と、を含んで、出力信号を抵抗分割してカスコードトランジスタのゲートに帰還する構成を実現している。この構成は、図２の（ｂ）に示される帰還回路の具体的構成例１に対応する。 In the cascode amplifier 2 of FIG. 5, as in the first embodiment, the first resistor R11 connected between the output terminal and the first node N, the first power supply V1 (V DD × 2), and the first node And a second resistor R12 connected to N, and realizes a configuration in which the output signal is resistance-divided and fed back to the gate of the cascode transistor. This configuration corresponds to a specific configuration example 1 of the feedback circuit shown in FIG.
　（実施形態の動作）
　次に図５のカスコード型増幅器２の動作について、図６を参照して説明する。図６では、図５のカスコード型増幅器２の入力端子に信号源６が接続された状態を示す。信号源６は第１実施形態と同様に、”０”又は”１”のパルス信号を出力するものとする。Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧は、一例として１Ｖであるものとして説明する。また、以下、電源電圧ＶＤＤは、素子耐圧と等しい値に設定されており、１Ｖであるものとして説明する。 (Operation of the embodiment)
Next, the operation of the cascode amplifier 2 of FIG. 5 will be described with reference to FIG. FIG. 6 shows a state where the signal source 6 is connected to the input terminal of the cascode amplifier 2 of FIG. As in the first embodiment, the signal source 6 outputs a pulse signal of “0” or “1”. The element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example. In the following description, it is assumed that the power supply voltage V DD is set to a value equal to the element breakdown voltage and is 1V.
　電源電圧ＶＤＤを基準として、第１電源Ｖ１乃至第３電源Ｖ３は次の電圧を出力するものとする。すなわち、第１電源Ｖ１は電源電圧ＶＤＤの２倍のＶＤＤ×２の電圧を出力する。第２電源Ｖ２は、電源電圧ＶＤＤの４倍のＶＤＤ×４の電圧を出力する。第４電源Ｖ４は電源電圧ＶＤＤの３倍のＶＤＤ×３の電圧を出力する。第３電源Ｖ３はＧＮＤであり、０Ｖ（ＶＤＤ×０）が与えられるものとする。 The first power supply V1 to the third power supply V3 output the following voltages with the power supply voltage V DD as a reference. That is, the first power supply V1 outputs a voltage of V DD × 2 that is twice the power supply voltage V DD . The second power supply V2 outputs a voltage of V DD × 4 that is four times the power supply voltage V DD . The fourth power supply V4 outputs a voltage of V DD × 3 that is three times the power supply voltage V DD . The third power supply V3 is GND, and 0 V (V DD × 0) is given.
　信号源６からの”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートには４Ｖ又は３Ｖが与えられ、Ｎ型の第１トランジスタＭＮ１１のゲートには０Ｖ又は１Ｖが与えられる。これに伴って、縦続接続されたＰ型の第１トランジスタＭＰ１１と第２トランジスタＭＰ１２との接続点は４Ｖと３Ｖとの間で変化し、縦続接続されたＰ型の第２トランジスタＭＰ１２と第３トランジスタＭＰ１３との接続点は４Ｖと２Ｖとの間で変化し、縦続接続されたＰ型の第３トランジスタＭＰ１３と第４トランジスタＭＰ１４との接続点は４Ｖと１Ｖとの間で変化する。また、縦続接続されたＮ型の第１トランジスタＭＮ１１と第２トランジスタＭＮ１２との接続点は１Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第２トランジスタＭＮ１２と第３トランジスタＭＮ１３との接続点は２Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第３トランジスタＭＮ１３と第４トランジスタＭＮ１４との接続点は３Ｖと０Ｖとの間で変化する。 In response to a pulse signal (0V or 1V) of “0” or “1” from the signal source 6, 4V or 3V is applied to the gate of the P-type first transistor MP11, and the N-type first transistor MN11 0V or 1V is applied to the gate. Accordingly, the connection point between the cascaded P-type first transistor MP11 and the second transistor MP12 changes between 4V and 3V, and the cascade-connected P-type second transistor MP12 and the third transistor MP12 are connected to each other. The connection point with the transistor MP13 changes between 4V and 2V, and the connection point between the cascaded P-type third transistor MP13 and the fourth transistor MP14 changes between 4V and 1V. Also, the connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V, and the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
　さらにＰ型の第４トランジスタＭＰ１４のゲート、Ｎ型の第４トランジスタＭＮ１４のゲート、第２抵抗Ｒ１２、及び第１抵抗Ｒ１１の接続点の電位は、３Ｖと１Ｖとの間で変化する。その結果、信号源６からの”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、図６のカスコード型増幅器２の出力端子は４Ｖ又は０Ｖを出力する。 Further, the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, the second resistor R12, and the first resistor R11 varies between 3V and 1V. As a result, the output terminal of the cascode amplifier 2 in FIG. 6 outputs 4 V or 0 V in accordance with the pulse signal (0 V or 1 V) of “0” or “1” from the signal source 6.
　（実施形態の効果）
　以上、図６のカスコード型増幅器２の、信号源６からのパルス信号（０Ｖまたは１Ｖ）に応じた動作において、各トランジスタが持つ３つの端子である、ドレイン、ソース、ゲートの、どの端子間の電圧も、１Ｖもしくは、それ以下になる。すなわち、本カスコード型増幅器２においては、構成素子に印加される電圧は、耐圧以下に維持される。 (Effect of embodiment)
As described above, in the operation according to the pulse signal (0 V or 1 V) from the signal source 6 of the cascode amplifier 2 of FIG. 6, between which terminals of the drain, source, and gate, which are the three terminals of each transistor. The voltage is also 1V or less. That is, in the cascode amplifier 2, the voltage applied to the constituent elements is maintained below the withstand voltage.
　また、抵抗は周波数特性を持たないので、図５のカスコード型増幅器２の第１抵抗Ｒ１１、第２抵抗Ｒ１２、第３抵抗Ｒ１３、第７抵抗Ｒ１７などは周波数特性を持たない。これによりＰ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器を直流から高周波まで広帯域化することができる。また、図６のカスコード型増幅器においては、各トランジスタのゲート端子とＧＮＤ間に容量が挿入されているが、本容量は、高周波領域では、図１８に示した背景技術と同様に、各トランジスタのドレイン－ゲート間容量のアドミタンスの比率を適切に設定することで、耐圧以内に収める働きをする。よって、本容量を含まない図３、図４に記載のカスコード型増幅器に比較して、図６のカスコード型増幅器は、より高周波領域まで対応することができる。 Further, since the resistors do not have frequency characteristics, the first resistor R11, the second resistor R12, the third resistor R13, the seventh resistor R17, etc. of the cascode amplifier 2 of FIG. 5 do not have frequency characteristics. As a result, the cascode amplifier is widened from DC to high frequency while maintaining the element breakdown voltage of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. be able to. Further, in the cascode amplifier of FIG. 6, a capacitor is inserted between the gate terminal of each transistor and GND. However, in the high frequency region, this capacitor is similar to the background art shown in FIG. By properly setting the drain-gate capacitance admittance ratio, it works to keep it within the breakdown voltage. Therefore, as compared with the cascode amplifiers shown in FIGS. 3 and 4 that do not include this capacitor, the cascode amplifier of FIG. 6 can cope with a higher frequency region.
　本実施形態では、Ｐ型の第４トランジスタＭＰ１４のゲートに第１キャパシタＣ１が接続され、Ｐ型の第３トランジスタＭＰ１３のゲートに第２キャパシタＣ２が接続され、Ｐ型の第２トランジスタＭＰ１２のゲートに第３キャパシタＣ３が接続されている。さらに本実施形態では、Ｎ型の第４トランジスタＭＮ１４のゲートに第４キャパシタＣ４が接続され、Ｎ型の第３トランジスタＭＮ１３のゲートに第５キャパシタＣ５が接続され、Ｎ型の第２トランジスタＭＮ１２のゲートに第６キャパシタＣ６が接続されている。 In the present embodiment, the first capacitor C1 is connected to the gate of the P-type fourth transistor MP14, the second capacitor C2 is connected to the gate of the P-type third transistor MP13, and the gate of the P-type second transistor MP12. A third capacitor C3 is connected to the second capacitor C3. Further, in the present embodiment, the fourth capacitor C4 is connected to the gate of the N-type fourth transistor MN14, the fifth capacitor C5 is connected to the gate of the N-type third transistor MN13, and the N-type second transistor MN12 is connected. A sixth capacitor C6 is connected to the gate.
　例えば、第３キャパシタＣ３はＰ型の第２トランジスタＭＰ１２のゲートに接続されて、Ｐ型の第２トランジスタＭＰ１２のゲート・ソース間の寄生容量や、ゲート・ドレイン間の寄生容量と容量分割する。第４抵抗Ｒ１４や第５抵抗Ｒ１５による抵抗分割と、Ｐ型の第２トランジスタＭＰ１２のゲートに接続された第３キャパシタＣ３による容量分割との組合せにより、Ｐ型の第２トランジスタＭＰ１２のゲートへ与えられる電圧が安定する。この第３キャパシタＣ３による効果は、Ｐ型の第４トランジスタＭＰ１４のゲートに接続された第１キャパシタＣ１や、Ｐ型の第３トランジスタＭＰ１３のゲートに接続された第２キャパシタＣ２においても同様である。またＮ型の第４トランジスタＭＮ１４のゲートに接続された第４キャパシタＣ４、Ｎ型の第３トランジスタＭＮ１３のゲートに接続された第５キャパシタＣ５や、Ｎ型の第２トランジスタＭＮ１２のゲートに接続された第６キャパシタＣ６においても同様である。これにより、カスコード型増幅器２の全体の動作を安定させることができる。 For example, the third capacitor C3 is connected to the gate of the P-type second transistor MP12 and divides the capacitance from the parasitic capacitance between the gate and the source of the P-type second transistor MP12 and the parasitic capacitance between the gate and the drain. The combination of the resistance division by the fourth resistor R14 and the fifth resistor R15 and the capacitance division by the third capacitor C3 connected to the gate of the P-type second transistor MP12 gives to the gate of the P-type second transistor MP12. Voltage is stabilized. The effect of the third capacitor C3 is the same in the first capacitor C1 connected to the gate of the P-type fourth transistor MP14 and the second capacitor C2 connected to the gate of the P-type third transistor MP13. . The fourth capacitor C4 connected to the gate of the N-type fourth transistor MN14, the fifth capacitor C5 connected to the gate of the N-type third transistor MN13, and the gate of the N-type second transistor MN12 are connected. The same applies to the sixth capacitor C6. As a result, the overall operation of the cascode amplifier 2 can be stabilized.
　なお図５のカスコード型増幅器では、Ｐ型の第４トランジスタＭＰ１４のゲートとＮ型の第４トランジスタＭＮ１４のゲートはいずれも第１ノードＮに接続されているので、第１キャパシタと第４キャパシタとをそれぞれ設ける構成とする代わりに、第１ノードＮとＧＮＤとの間に接続された一つのキャパシタを設ける構成としてもよい。 In the cascode amplifier of FIG. 5, since the gate of the P-type fourth transistor MP14 and the gate of the N-type fourth transistor MN14 are both connected to the first node N, the first capacitor, the fourth capacitor, Instead of the configuration in which each is provided, one capacitor connected between the first node N and GND may be provided.
　〔第３実施形態〕
　次に、本発明の第３実施形態によるカスコード型増幅器について、説明する。図７は、第３実施形態のカスコード型増幅器を説明するための回路図である。 [Third Embodiment]
Next, a cascode amplifier according to a third embodiment of the present invention will be described. FIG. 7 is a circuit diagram for explaining the cascode amplifier according to the third embodiment.
　第３実施形態のカスコード型増幅器は、第１実施形態のカスコード型増幅器の変形例である。第１実施形態のカスコード型増幅器と同様な要素に対しては、同じ参照番号を付してその詳細な説明を省略することとする。 The cascode amplifier according to the third embodiment is a modification of the cascode amplifier according to the first embodiment. Elements similar to those of the cascode amplifier of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　図７のカスコード型増幅器３は第１実施形態と同様に、第１導電型の一例としてのＰ型の第１トランジスタＭＰ１１と、第１トランジスタＭＰ１１と出力端子との間に縦続接続されたＰ型の第２トランジスタＭＰ１２、第３トランジスタＭＰ１３、及び第４トランジスタＭＰ１４と、を含む。 As in the first embodiment, the cascode amplifier 3 in FIG. 7 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascaded between the first transistor MP11 and the output terminal. Second transistor MP12, third transistor MP13, and fourth transistor MP14.
　さらに図７のカスコード型増幅器３は第１実施形態と同様に、第２導電型の一例としてのＮ型の第１トランジスタＭＮ１１と、Ｎ型の第１トランジスタＭＮ１１と出力端子との間に縦続接続されたＮ型の第２トランジスタＭＮ１２、第３トランジスタＭＮ１３、及び第４トランジスタＭＮ１４と、を含む。 Further, as in the first embodiment, the cascode amplifier 3 of FIG. 7 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal. N-type second transistor MN12, third transistor MN13, and fourth transistor MN14.
　さらに図７のカスコード型増幅器３は第１実施形態と同様に、出力端子と第１ノードＮとの間に接続された第１抵抗Ｒ１１と、第１ノードＮに接続された第２抵抗Ｒ１２と、を含む。さらに図７のカスコード型増幅器３は、第１ノードＮとＰ型の第１トランジスタＭＰ１１のゲートとの間に直列接続された第３抵抗Ｒ１３、第４抵抗Ｒ１４、第５抵抗Ｒ１５を含む。さらに図７のカスコード型増幅器３は、Ｐ型の第１トランジスタＭＰ１１のゲートと第２電源Ｖ２との間に接続された第６抵抗Ｒ１６と、を含む。さらに図７のカスコード型増幅器３は、第１ノードＮとＮ型の第１トランジスタＭＮ１１のゲートとの間に直列接続された第７抵抗Ｒ１７、第８抵抗Ｒ１８、第９抵抗Ｒ１９を含む。さらに図７のカスコード型増幅器３は、Ｎ型の第１トランジスタＭＮ１１のゲートと第３電源Ｖ３との間に接続された第１０抵抗Ｒ２０と、を含む。 Further, as in the first embodiment, the cascode amplifier 3 of FIG. 7 includes a first resistor R11 connected between the output terminal and the first node N, a second resistor R12 connected to the first node N, ,including. Further, the cascode amplifier 3 of FIG. 7 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 3 of FIG. 7 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 3 of FIG. 7 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11. Further, the cascode amplifier 3 in FIG. 7 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
　さらに図７のカスコード型増幅器３では、ＶＤＤ×４とＧＮＤとの間に直列接続された第１１抵抗Ｒ２１及び第１３抵抗Ｒ２３を含む。そして第２抵抗Ｒ１２は、第１ノードＮと、直列接続された第１１抵抗Ｒ２１及び第１３抵抗Ｒ２３の接続点との間に接続されている。 Further, the cascode amplifier 3 of FIG. 7 includes an eleventh resistor R21 and a thirteenth resistor R23 connected in series between V DD × 4 and GND. The second resistor R12 is connected between the first node N and the connection point of the eleventh resistor R21 and the thirteenth resistor R23 connected in series.
　図７のカスコード型増幅器３では、第１抵抗Ｒ１１、第２抵抗Ｒ１２、第１１抵抗Ｒ２１、及び第１３抵抗Ｒ２３を含んで、出力信号を抵抗分割してカスコードトランジスタのゲートに帰還する構成を実現している。この構成は、図２の（ｃ）に示される帰還回路の具体的構成例２に対応する。 The cascode amplifier 3 in FIG. 7 includes a first resistor R11, a second resistor R12, an eleventh resistor R21, and a thirteenth resistor R23, and realizes a configuration in which the output signal is divided by resistance and fed back to the gate of the cascode transistor. doing. This configuration corresponds to a specific configuration example 2 of the feedback circuit shown in FIG.
　（実施形態の効果）
　抵抗は周波数特性を持たないので、図７のカスコード型増幅器３の第１抵抗Ｒ１１、第２抵抗Ｒ１２、第３抵抗Ｒ１３、第７抵抗Ｒ１７、第１１抵抗Ｒ２１、第１３抵抗Ｒ２３などは周波数特性を持たない。これにより本実施形態のカスコード型増幅器によれば、第１実施形態と同様に、Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器を広帯域化することができる。 (Effect of embodiment)
Since the resistor does not have frequency characteristics, the first resistor R11, second resistor R12, third resistor R13, seventh resistor R17, eleventh resistor R21, thirteenth resistor R23, etc. of the cascode amplifier 3 of FIG. Do not have. Thus, according to the cascode amplifier of the present embodiment, the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are set as in the first embodiment. The cascode amplifier can be widened while maintaining within an allowable range.
　さらに本実施形態では、ＶＤＤ×４とＧＮＤとの間に直列接続された第１１抵抗Ｒ２１及び第１３抵抗Ｒ２３の抵抗分割によって、第１実施形態や第２実施形態の第１電源Ｖ１（ＶＤＤ×２）に対応する電圧を発生させている。これにより第１電源Ｖ１（ＶＤＤ×２）のための専用の電圧源を省略し、電源ユニットの共有化を図ることができる。 Further, in the present embodiment, the first power supply V1 (V1 (V) of the first embodiment and the second embodiment is obtained by resistance division of the eleventh resistor R21 and the thirteenth resistor R23 connected in series between V DD × 4 and GND. A voltage corresponding to DD × 2) is generated. As a result, a dedicated voltage source for the first power supply V1 (V DD × 2) can be omitted, and the power supply unit can be shared.
　〔第４実施形態〕
　次に、本発明の第４実施形態によるカスコード型増幅器について、説明する。図８は、第４実施形態のカスコード型増幅器を説明するための回路図である。第４実施形態のカスコード型増幅器は、第２実施形態や第３実施形態のカスコード型増幅器の変形例である。第２実施形態や第３実施形態のカスコード型増幅器と同様な要素に対しては、同じ参照番号を付してその詳細な説明を省略することとする。 [Fourth Embodiment]
Next, a cascode amplifier according to a fourth embodiment of the present invention will be described. FIG. 8 is a circuit diagram for explaining a cascode amplifier according to the fourth embodiment. The cascode amplifier according to the fourth embodiment is a modification of the cascode amplifier according to the second embodiment or the third embodiment. Elements similar to those of the cascode amplifiers of the second and third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
　図８のカスコード型増幅器４は第２実施形態と同様に、第１導電型の一例としてのＰ型の第１トランジスタＭＰ１１と、第１トランジスタＭＰ１１と出力端子との間に縦続接続されたＰ型の第２トランジスタＭＰ１２、第３トランジスタＭＰ１３、及び第４トランジスタＭＰ１４と、を含む。 As in the second embodiment, the cascode amplifier 4 of FIG. 8 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascade connected between the first transistor MP11 and the output terminal. Second transistor MP12, third transistor MP13, and fourth transistor MP14.
　さらに図８のカスコード型増幅器４は第２実施形態と同様に、第２導電型の一例としてのＮ型の第１トランジスタＭＮ１１と、Ｎ型の第１トランジスタＭＮ１１と出力端子との間に縦続接続されたＮ型の第２トランジスタＭＮ１２、第３トランジスタＭＮ１３、及び第４トランジスタＭＮ１４と、を含む。 Further, as in the second embodiment, the cascode amplifier 4 of FIG. 8 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal. N-type second transistor MN12, third transistor MN13, and fourth transistor MN14.
　さらに図８のカスコード型増幅器４は第２実施形態と同様に、出力端子と第１ノードＮとの間に接続された第１抵抗Ｒ１１と、第１ノードＮに接続された第２抵抗Ｒ１２と、を含む。さらに図８のカスコード型増幅器４は、第１ノードＮとＰ型の第１トランジスタＭＰ１１のゲートとの間に直列接続された第３抵抗Ｒ１３、第４抵抗Ｒ１４、第５抵抗Ｒ１５を含む。さらに図８のカスコード型増幅器４は、Ｐ型の第１トランジスタＭＰ１１のゲートと第２電源Ｖ２との間に接続された第６抵抗Ｒ１６と、を含む。さらに図８のカスコード型増幅器４は、第１ノードＮとＮ型の第１トランジスタＭＮ１１のゲートとの間に直列接続された第７抵抗Ｒ１７、第８抵抗Ｒ１８、第９抵抗Ｒ１９を含む。さらに図８のカスコード型増幅器４は、Ｎ型の第１トランジスタＭＮ１１のゲートと第３電源Ｖ３との間に接続された第１０抵抗Ｒ２０と、を含む。 Further, as in the second embodiment, the cascode amplifier 4 of FIG. 8 includes a first resistor R11 connected between the output terminal and the first node N, and a second resistor R12 connected to the first node N. ,including. Furthermore, the cascode amplifier 4 of FIG. 8 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 4 of FIG. 8 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 4 of FIG. 8 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11. Furthermore, the cascode amplifier 4 of FIG. 8 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
　さらに図８のカスコード型増幅器４では、第２実施形態と同様に、Ｐ型の第４トランジスタＭＰ１４のゲートとＧＮＤとの間に接続された第１キャパシタＣ１と、Ｐ型の第３トランジスタＭＰ１３のゲートとＧＮＤとの間に接続された第２キャパシタＣ２と、Ｐ型の第２トランジスタＭＰ１２のゲートとＧＮＤとの間に接続された第３キャパシタＣ３と、を含む。さらに図８のカスコード型増幅器４では、第２実施形態と同様に、Ｎ型の第４トランジスタＭＮ１４のゲートとＧＮＤとの間に接続された第４キャパシタＣ４と、Ｎ型の第３トランジスタＭＮ１３のゲートとＧＮＤとの間に接続された第５キャパシタＣ５と、Ｎ型の第２トランジスタＭＮ１２のゲートとＧＮＤとの間に接続された第６キャパシタＣ６と、を含む。 Further, in the cascode amplifier 4 of FIG. 8, as in the second embodiment, the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND, and the P-type third transistor MP13. A second capacitor C2 connected between the gate and GND; and a third capacitor C3 connected between the gate of the P-type second transistor MP12 and GND. Further, in the cascode amplifier 4 of FIG. 8, as in the second embodiment, the fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND, and the N-type third transistor MN13. A fifth capacitor C5 connected between the gate and GND, and a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
　ここで図８のカスコード型増幅器４は、第２抵抗Ｒ１２の接続が第２実施形態とは異なる。図８のカスコード型増幅器４では第３実施形態と同様に、ＶＤＤ×４とＧＮＤとの間に直列接続された第１１抵抗Ｒ２１及び第１３抵抗Ｒ２３を含む。そして第２抵抗Ｒ１２は、第１ノードＮと、直列接続された第１１抵抗Ｒ２１及び第１３抵抗Ｒ２３の接続点との間に接続されている。 Here, the cascode amplifier 4 of FIG. 8 is different from the second embodiment in the connection of the second resistor R12. As in the third embodiment, the cascode amplifier 4 of FIG. 8 includes an eleventh resistor R21 and a thirteenth resistor R23 connected in series between V DD × 4 and GND. The second resistor R12 is connected between the first node N and the connection point of the eleventh resistor R21 and the thirteenth resistor R23 connected in series.
　図８のカスコード型増幅器４では第３実施形態と同様に、第１抵抗Ｒ１１、第２抵抗Ｒ１２、第１１抵抗Ｒ２１、及び第１３抵抗Ｒ２３を含んで、出力信号を抵抗分割してカスコードトランジスタのゲートに帰還する構成を実現している。この構成は、図２の（ｃ）に示される帰還回路の具体的構成例２に対応する。 As in the third embodiment, the cascode amplifier 4 of FIG. 8 includes a first resistor R11, a second resistor R12, an eleventh resistor R21, and a thirteenth resistor R23. A configuration for returning to the gate is realized. This configuration corresponds to a specific configuration example 2 of the feedback circuit shown in FIG.
　（実施形態の効果）
　抵抗は周波数特性を持たないので、図８のカスコード型増幅器４の第１抵抗Ｒ１１、第２抵抗Ｒ１２、第３抵抗Ｒ１３、第７抵抗Ｒ１７、第１１抵抗Ｒ２１、第１３抵抗Ｒ２３などは周波数特性を持たない。これにより本実施形態のカスコード型増幅器によれば、第１実施形態と同様に、Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器を広帯域化することができる。 (Effect of embodiment)
Since the resistor does not have frequency characteristics, the first resistor R11, the second resistor R12, the third resistor R13, the seventh resistor R17, the eleventh resistor R21, the thirteenth resistor R23, etc. of the cascode amplifier 4 of FIG. Do not have. Thus, according to the cascode amplifier of the present embodiment, the element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are set as in the first embodiment. The cascode amplifier can be widened while maintaining within an allowable range.
　さらに第２実施形態のカスコード型増幅器２と同様に、第１キャパシタＣ１乃至第６キャパシタＣ６を接続したことによる容量分割と、第４抵抗Ｒ１４や第５抵抗Ｒ１５などによる抵抗分割との組合せによって、カスコードトランジスタのゲートへ与えられる電圧が安定し、カスコード型増幅器４の全体の動作を安定させることができる。 Further, similarly to the cascode amplifier 2 of the second embodiment, by combining the capacitance division by connecting the first capacitor C1 to the sixth capacitor C6 and the resistance division by the fourth resistor R14, the fifth resistor R15, etc., The voltage applied to the gate of the cascode transistor is stabilized, and the entire operation of the cascode amplifier 4 can be stabilized.
　さらに本実施形態では、ＶＤＤ×４とＧＮＤとの間に直列接続された第１１抵抗Ｒ２１及び第１３抵抗Ｒ２３の抵抗分割によって、第１実施形態や第２実施形態の第１電源Ｖ１（ＶＤＤ×２）に対応する電圧を発生させている。これにより第１電源Ｖ１（ＶＤＤ×２）のための専用の電圧源を省略し、電源ユニットの共有化を図ることができる。 Further, in the present embodiment, the first power supply V1 (V1 (V) of the first embodiment and the second embodiment is obtained by resistance division of the eleventh resistor R21 and the thirteenth resistor R23 connected in series between V DD × 4 and GND. A voltage corresponding to DD × 2) is generated. As a result, a dedicated voltage source for the first power supply V1 (V DD × 2) can be omitted, and the power supply unit can be shared.
　〔第５実施形態〕
　次に、本発明の第５実施形態によるカスコード型増幅器について、説明する。図９は、第５実施形態のカスコード型増幅器を説明するための回路図である。第５実施形態のカスコード型増幅器は、第４実施形態などのカスコード型増幅器の変形例である。第４実施形態などのカスコード型増幅器と同様な要素に対しては、同じ参照番号を付してその詳細な説明を省略することとする。 [Fifth Embodiment]
Next, a cascode amplifier according to a fifth embodiment of the invention will be described. FIG. 9 is a circuit diagram for explaining the cascode amplifier according to the fifth embodiment. The cascode amplifier of the fifth embodiment is a modification of the cascode amplifier of the fourth embodiment. Elements similar to those of the cascode amplifier of the fourth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　図９のカスコード型増幅器５ａは第４実施形態と同様に、第１導電型の一例としてのＰ型の第１トランジスタＭＰ１１と、第１トランジスタＭＰ１１と出力端子との間に縦続接続されたＰ型の第２トランジスタＭＰ１２、第３トランジスタＭＰ１３、及び第４トランジスタＭＰ１４と、を含む。 As in the fourth embodiment, the cascode amplifier 5a of FIG. 9 includes a P-type first transistor MP11 as an example of the first conductivity type, and a P-type cascade connected between the first transistor MP11 and the output terminal. Second transistor MP12, third transistor MP13, and fourth transistor MP14.
　さらに図９のカスコード型増幅器５ａは第４実施形態と同様に、第２導電型の一例としてのＮ型の第１トランジスタＭＮ１１と、Ｎ型の第１トランジスタＭＮ１１と出力端子との間に縦続接続されたＮ型の第２トランジスタＭＮ１２、第３トランジスタＭＮ１３、及び第４トランジスタＭＮ１４と、を含む。 Further, as in the fourth embodiment, the cascode amplifier 5a of FIG. 9 is connected in cascade between the N-type first transistor MN11 as an example of the second conductivity type, and the N-type first transistor MN11 and the output terminal. N-type second transistor MN12, third transistor MN13, and fourth transistor MN14.
　さらに図９のカスコード型増幅器５ａは、出力端子と第１ノードＮとの間に接続された帰還回路を含む。さらに図９のカスコード型増幅器５ａは、第１ノードＮとＰ型の第１トランジスタＭＰ１１のゲートとの間に直列接続された第３抵抗Ｒ１３、第４抵抗Ｒ１４、第５抵抗Ｒ１５を含む。さらに図９のカスコード型増幅器５ａは、Ｐ型の第１トランジスタＭＰ１１のゲートと第２電源Ｖ２との間に接続された第６抵抗Ｒ１６と、を含む。さらに図９のカスコード型増幅器５ａは、第１ノードＮとＮ型の第１トランジスタＭＮ１１のゲートとの間に直列接続された第７抵抗Ｒ１７、第８抵抗Ｒ１８、第９抵抗Ｒ１９を含む。さらに図９のカスコード型増幅器５ａは、Ｎ型の第１トランジスタＭＮ１１のゲートと第３電源Ｖ３との間に接続された第１０抵抗Ｒ２０と、を含む。 9 further includes a feedback circuit connected between the output terminal and the first node N. The cascode amplifier 5a shown in FIG. Further, the cascode amplifier 5a of FIG. 9 includes a third resistor R13, a fourth resistor R14, and a fifth resistor R15 connected in series between the first node N and the gate of the P-type first transistor MP11. Further, the cascode amplifier 5a of FIG. 9 includes a sixth resistor R16 connected between the gate of the P-type first transistor MP11 and the second power supply V2. Further, the cascode amplifier 5a of FIG. 9 includes a seventh resistor R17, an eighth resistor R18, and a ninth resistor R19 connected in series between the first node N and the gate of the N-type first transistor MN11. Further, the cascode amplifier 5a of FIG. 9 includes a tenth resistor R20 connected between the gate of the N-type first transistor MN11 and the third power supply V3.
　さらに図９のカスコード型増幅器５ａでは、第２実施形態や第４実施形態と同様に、Ｐ型の第４トランジスタＭＰ１４のゲートとＧＮＤとの間に接続された第１キャパシタＣ１と、Ｐ型の第３トランジスタＭＰ１３のゲートとＧＮＤとの間に接続された第２キャパシタＣ２と、Ｐ型の第２トランジスタＭＰ１２のゲートとＧＮＤとの間に接続された第３キャパシタＣ３と、を含む。さらに図９のカスコード型増幅器５ａでは、第２実施形態や第４実施形態と同様に、Ｎ型の第４トランジスタＭＮ１４のゲートとＧＮＤとの間に接続された第４キャパシタＣ４と、Ｎ型の第３トランジスタＭＮ１３のゲートとＧＮＤとの間に接続された第５キャパシタＣ５と、Ｎ型の第２トランジスタＭＮ１２のゲートとＧＮＤとの間に接続された第６キャパシタＣ６と、を含む。 Further, in the cascode amplifier 5a of FIG. 9, as in the second and fourth embodiments, the first capacitor C1 connected between the gate of the P-type fourth transistor MP14 and GND, and the P-type amplifier It includes a second capacitor C2 connected between the gate of the third transistor MP13 and GND, and a third capacitor C3 connected between the gate of the P-type second transistor MP12 and GND. Further, in the cascode amplifier 5a of FIG. 9, as in the second and fourth embodiments, a fourth capacitor C4 connected between the gate of the N-type fourth transistor MN14 and GND, It includes a fifth capacitor C5 connected between the gate of the third transistor MN13 and GND, and a sixth capacitor C6 connected between the gate of the N-type second transistor MN12 and GND.
　さらに図９のカスコード型増幅器５ａは、カスコード型増幅器５ａの出力信号を抵抗分割してＰ型の第４トランジスタＭＰ１４のゲート及びＮ型の第４トランジスタＭＮ１４のゲートに帰還する構成を持つ。言い換えると、図９のカスコード型増幅器５ａでは、出力端子とＰ型の第４トランジスタＭＰ１４のゲート及びＮ型の第４トランジスタＭＮ１４のゲートとの間に接続された帰還回路を含む。この図９のカスコード型増幅器５ａの帰還回路としては、第３実施形態や第４実施形態で用いた、図２の（ｃ）に示される帰還回路を用いることができる。 Further, the cascode amplifier 5a of FIG. 9 has a configuration in which the output signal of the cascode amplifier 5a is resistance-divided and fed back to the gate of the P-type fourth transistor MP14 and the gate of the N-type fourth transistor MN14. In other words, the cascode amplifier 5a of FIG. 9 includes a feedback circuit connected between the output terminal and the gate of the P-type fourth transistor MP14 and the gate of the N-type fourth transistor MN14. As the feedback circuit of the cascode amplifier 5a shown in FIG. 9, the feedback circuit shown in FIG. 2C used in the third and fourth embodiments can be used.
　さらに図９のカスコード型増幅器５ａは、Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１と、入力端子とＰ型の第１トランジスタＭＰ１１のゲートとの間に挿入された第１１キャパシタＣ１１とをさらに含む。ラッチ回路ＬＡＴＣＨ１は、例えば図９に示すような入力が出力に接続された一対のインバータ回路から構成される。ラッチ回路ＬＡＴＣＨ１は、Ｐ型の第１トランジスタＭＰ１１のゲートへ与えられるハイレベル又はローレベルの電圧を保持する。 Further, the cascode amplifier 5a of FIG. 9 includes a latch circuit LATCH1 connected to the gate of the P-type first transistor MP11, and an eleventh capacitor inserted between the input terminal and the gate of the P-type first transistor MP11. And C11. The latch circuit LATCH1 is composed of a pair of inverter circuits in which inputs as shown in FIG. 9 are connected to outputs, for example. The latch circuit LATCH1 holds a high level or low level voltage applied to the gate of the P-type first transistor MP11.
　（実施形態の動作）
　次に図９のカスコード型増幅器５ａの動作について、図１０を参照して説明する。図９のカスコード型増幅器５ａの入力には”０”又は”１”のパルス信号が入力される。Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧は、一例として１Ｖであるものとして説明する。 (Operation of the embodiment)
Next, the operation of the cascode amplifier 5a of FIG. 9 will be described with reference to FIG. A pulse signal of “0” or “1” is input to the input of the cascode amplifier 5a of FIG. The element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example.
　電源電圧ＶＤＤを基準として、第２電源Ｖ２は、電源電圧ＶＤＤの４倍のＶＤＤ×４の電圧を出力する。第３電源Ｖ３はＧＮＤであり、０Ｖ（ＶＤＤ×０）が与えられるものとする。Ｐ型の第１トランジスタＭＰ１１のゲートには、第２電源Ｖ２を図９の第６抵抗Ｒ１６などで抵抗分割した電圧として、４Ｖ又は３Ｖが与えられる。 With reference to the power supply voltage V DD , the second power supply V2 outputs a voltage of V DD × 4 that is four times the power supply voltage V DD . The third power supply V3 is GND, and 0 V (V DD × 0) is given. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 of FIG.
　入力の”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートには４Ｖ又は３Ｖが与えられ、Ｎ型の第１トランジスタＭＮ１１のゲートには０Ｖ又は１Ｖが与えられる。これに伴って、縦続接続されたＰ型の第１トランジスタＭＰ１１と第２トランジスタＭＰ１２との接続点は４Ｖと３Ｖとの間で変化し、縦続接続されたＰ型の第２トランジスタＭＰ１２と第３トランジスタＭＰ１３との接続点は４Ｖと２Ｖとの間で変化し、縦続接続されたＰ型の第３トランジスタＭＰ１３と第４トランジスタＭＰ１４との接続点は４Ｖと１Ｖとの間で変化する。また、縦続接続されたＮ型の第１トランジスタＭＮ１１と第２トランジスタＭＮ１２との接続点は１Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第２トランジスタＭＮ１２と第３トランジスタＭＮ１３との接続点は２Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第３トランジスタＭＮ１３と第４トランジスタＭＮ１４との接続点は３Ｖと０Ｖとの間で変化する。 Depending on the input “0” or “1” pulse signal (0V or 1V), 4V or 3V is applied to the gate of the P-type first transistor MP11, and the gate of the N-type first transistor MN11 is applied to the gate. 0V or 1V is applied. Accordingly, the connection point between the cascaded P-type first transistor MP11 and the second transistor MP12 changes between 4V and 3V, and the cascade-connected P-type second transistor MP12 and the third transistor MP12 are connected to each other. The connection point with the transistor MP13 changes between 4V and 2V, and the connection point between the cascaded P-type third transistor MP13 and the fourth transistor MP14 changes between 4V and 1V. Also, the connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V, and the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
　さらにＰ型の第４トランジスタＭＰ１４のゲート、Ｎ型の第４トランジスタＭＮ１４のゲート、第１キャパシタＣ１の一端、及び第４キャパシタＣ４の一端の接続点の電位は、３Ｖと１Ｖとの間で変化する。その結果、入力の”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、図９のカスコード型増幅器５ａの出力端子は４Ｖ又は０Ｖを出力する。 Furthermore, the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do. As a result, the output terminal of the cascode amplifier 5a in FIG. 9 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
　（実施形態の効果）
　抵抗は周波数特性を持たないので、図９のカスコード型増幅器５ａの帰還回路、第３抵抗Ｒ１３、第７抵抗Ｒ１７などは周波数特性を持たない。これによりＰ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器５ａを広帯域化することができる。 (Effect of embodiment)
Since the resistor does not have frequency characteristics, the feedback circuit of the cascode amplifier 5a of FIG. 9, the third resistor R13, the seventh resistor R17, and the like do not have frequency characteristics. As a result, the cascode amplifier 5a can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
　さらに図９のカスコード型増幅器５ａでは、Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１と、入力端子とＰ型の第１トランジスタＭＰ１１のゲートとの間に挿入された第１１キャパシタＣ１１と、を含んでいる。カスコード型増幅器５ａの入力の”０”又は”１”のパルス信号の変化に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートに、第２電源Ｖ２を第６抵抗Ｒ１６などで抵抗分割した電圧として、４Ｖ又は３Ｖを与えることができる。Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１によって、カスコード型増幅器５ａの入力変化への追従性が向上し、構成素子の素子耐圧を許容範囲内に維持しつつ、広帯域化を実現することができる。 Further, in the cascode amplifier 5a of FIG. 9, the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the eleventh capacitor inserted between the input terminal and the gate of the P-type first transistor MP11. C11. A voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5a. 4V or 3V can be applied. The latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5a, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
　〔第６実施形態〕
　次に、本発明の第６実施形態によるカスコード型増幅器について、説明する。図１１は、第６実施形態のカスコード型増幅器を説明するための回路図である。第６実施形態のカスコード型増幅器は、第５実施形態のカスコード型増幅器の変形例である。第５実施形態のカスコード型増幅器と同様な要素に対しては、同じ参照番号を付してその詳細な説明を省略することとする。 [Sixth Embodiment]
Next, a cascode amplifier according to a sixth embodiment of the present invention will be described. FIG. 11 is a circuit diagram for explaining a cascode amplifier according to the sixth embodiment. The cascode amplifier according to the sixth embodiment is a modification of the cascode amplifier according to the fifth embodiment. Elements similar to those of the cascode amplifier of the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　図１１のカスコード型増幅器５ｂは第５実施形態と同様な構成に加えて、第１３キャパシタＣ１３をさらに含む。第１３キャパシタＣ１３は、ラッチ回路ＬＡＴＣＨ１のＰ型の第１トランジスタＭＰ１１のゲートに接続された一端とは別の一端と、所定の電位が与えられる配線との間に挿入されている。言い換えると、所定の電位が与えられる配線とＰ型の第１トランジスタＭＰ１１のゲートとの間に、ラッチ回路ＬＡＴＣＨ１と第１３キャパシタＣ１３とが直列接続されている。 The cascode amplifier 5b of FIG. 11 further includes a thirteenth capacitor C13 in addition to the same configuration as that of the fifth embodiment. The thirteenth capacitor C13 is inserted between one end different from one end connected to the gate of the P-type first transistor MP11 of the latch circuit LATCH1 and a wiring to which a predetermined potential is applied. In other words, the latch circuit LATCH1 and the thirteenth capacitor C13 are connected in series between a wiring to which a predetermined potential is applied and the gate of the P-type first transistor MP11.
　（実施形態の動作）
　次に図１１のカスコード型増幅器５ｂの動作について、図１２を参照して説明する。図１２のカスコード型増幅器５ｂの入力には”０”又は”１”のパルス信号が入力される。Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧は、一例として１Ｖであるものとして説明する。 (Operation of the embodiment)
Next, the operation of the cascode amplifier 5b shown in FIG. 11 will be described with reference to FIG. A pulse signal of “0” or “1” is input to the input of the cascode amplifier 5b of FIG. The element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example.
　電源電圧ＶＤＤを基準として、第２電源Ｖ２は、電源電圧ＶＤＤの４倍のＶＤＤ×４の電圧を出力する。第３電源Ｖ３はＧＮＤであり、０Ｖ（ＶＤＤ×０）が与えられるものとする。一端が第１３キャパシタＣ１３に接続される所定の電位が与えられる配線には、カスコード型増幅器５ｂの入力”０”又は”１”のパルス信号を反転した電位が与えられるものとする。Ｐ型の第１トランジスタＭＰ１１のゲートには、第２電源Ｖ２を第６抵抗Ｒ１６などで抵抗分割した電圧として、４Ｖ又は３Ｖが与えられる。 With reference to the power supply voltage V DD , the second power supply V2 outputs a voltage of V DD × 4 that is four times the power supply voltage V DD . The third power supply V3 is GND, and 0 V (V DD × 0) is given. It is assumed that a potential obtained by inverting the pulse signal of “0” or “1” of the input of the cascode amplifier 5b is applied to a wiring to which a predetermined potential is connected, one end of which is connected to the thirteenth capacitor C13. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 with the sixth resistor R16 or the like.
　入力の”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートには４Ｖ又は３Ｖが与えられ、Ｎ型の第１トランジスタＭＮ１１のゲートには０Ｖ又は１Ｖが与えられる。これに伴って、縦続接続されたＰ型の第１トランジスタＭＰ１１と第２トランジスタＭＰ１２との接続点は４Ｖと３Ｖとの間で変化し、縦続接続されたＰ型の第２トランジスタＭＰ１２と第３トランジスタＭＰ１３との接続点は４Ｖと２Ｖとの間で変化し、縦続接続されたＰ型の第３トランジスタＭＰ１３と第４トランジスタＭＰ１４との接続点は４Ｖと１Ｖとの間で変化する。また、縦続接続されたＮ型の第１トランジスタＭＮ１１と第２トランジスタＭＮ１２との接続点は１Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第２トランジスタＭＮ１２と第３トランジスタＭＮ１３との接続点は２Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第３トランジスタＭＮ１３と第４トランジスタＭＮ１４との接続点は３Ｖと０Ｖとの間で変化する。 Depending on the input “0” or “1” pulse signal (0V or 1V), 4V or 3V is applied to the gate of the P-type first transistor MP11, and the gate of the N-type first transistor MN11 is applied to the gate. 0V or 1V is applied. Accordingly, the connection point between the cascaded P-type first transistor MP11 and the second transistor MP12 changes between 4V and 3V, and the cascade-connected P-type second transistor MP12 and the third transistor MP12 are connected to each other. The connection point with the transistor MP13 changes between 4V and 2V, and the connection point between the cascaded P-type third transistor MP13 and the fourth transistor MP14 changes between 4V and 1V. Also, the connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V, and the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
　さらにＰ型の第４トランジスタＭＰ１４のゲート、Ｎ型の第４トランジスタＭＮ１４のゲート、第１キャパシタＣ１の一端、及び第４キャパシタＣ４の一端の接続点の電位は、３Ｖと１Ｖとの間で変化する。その結果、入力の”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、図１２のカスコード型増幅器５ｂの出力端子は４Ｖ又は０Ｖを出力する。 Furthermore, the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do. As a result, the output terminal of the cascode amplifier 5b in FIG. 12 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
　（実施形態の効果）
　抵抗は周波数特性を持たないので、図１１のカスコード型増幅器５ｂの帰還回路、第３抵抗Ｒ１３、第７抵抗Ｒ１７などは周波数特性を持たない。これによりＰ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器５ｂを広帯域化することができる。 (Effect of embodiment)
Since the resistor does not have frequency characteristics, the feedback circuit of the cascode amplifier 5b, the third resistor R13, the seventh resistor R17, and the like of FIG. 11 do not have frequency characteristics. As a result, the cascode amplifier 5b can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
　さらに図１１のカスコード型増幅器５ｂでは第５実施形態と同様に、Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１と、入力端子とＰ型の第１トランジスタＭＰ１１のゲートとの間に挿入された第１１キャパシタＣ１１と、を含んでいる。カスコード型増幅器５ｂの入力の”０”又は”１”のパルス信号の変化に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートに、第２電源Ｖ２を第６抵抗Ｒ１６などで抵抗分割した電圧として、４Ｖ又は３Ｖを与えることができる。Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１によって、カスコード型増幅器５ｂの入力変化への追従性が向上し、構成素子の素子耐圧を許容範囲内に維持しつつ、広帯域化を実現することができる。 Further, in the cascode amplifier 5b of FIG. 11, as in the fifth embodiment, the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the input terminal and the gate of the P-type first transistor MP11 are arranged. And an eleventh capacitor C11 inserted into the. A voltage obtained by resistance-dividing the second power supply V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal “0” or “1” at the input of the cascode amplifier 5b. 4V or 3V can be applied. The latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5b, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
　さらに図１１のカスコード型増幅器５ｂでは、一端が第１３キャパシタＣ１３に接続される所定の電位が与えられる配線には、カスコード型増幅器５ｂの入力”０”又は”１”のパルス信号を反転した電位が与えられる。これにより、ラッチ回路ＬＡＴＣＨ１が保持し、Ｐ型の第１トランジスタＭＰ１１のゲートへ与えられる電圧について、カスコード型増幅器５ｂの入力”０”又は”１”の変化への追従性が図９のカスコード型増幅器５ａより向上させることができる。 Further, in the cascode amplifier 5b of FIG. 11, a potential obtained by inverting the pulse signal of the input “0” or “1” of the cascode amplifier 5b is connected to a wiring to which a predetermined potential is connected to one end of the thirteenth capacitor C13. Is given. As a result, the voltage that is held by the latch circuit LATCH1 and applied to the gate of the P-type first transistor MP11 can follow the change of the input “0” or “1” of the cascode-type amplifier 5b. This can be improved over the amplifier 5a.
　〔第７実施形態〕
　次に、本発明の第７実施形態によるカスコード型増幅器について、説明する。図１３は、第７実施形態のカスコード型増幅器を説明するための回路図である。第７実施形態のカスコード型増幅器は、第５実施形態のカスコード型増幅器の変形例である。第５実施形態のカスコード型増幅器と同様な要素に対しては、同じ参照番号を付してその詳細な説明を省略することとする。 [Seventh Embodiment]
Next, a cascode amplifier according to a seventh embodiment of the present invention will be described. FIG. 13 is a circuit diagram for explaining the cascode amplifier according to the seventh embodiment. The cascode amplifier according to the seventh embodiment is a modification of the cascode amplifier according to the fifth embodiment. Elements similar to those of the cascode amplifier of the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　図１３のカスコード型増幅器５ｃは第５実施形態と同様な構成に加えて、Ｎ型の第１トランジスタＭＮ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ２と、入力端子とＮ型の第１トランジスタＭＮ１１のゲートとの間に挿入された第１２キャパシタＣ１２とをさらに含む。ラッチ回路ＬＡＴＣＨ２は、例えば図１３に示すような入力が出力に接続された一対のインバータ回路から構成される。ラッチ回路ＬＡＴＣＨ２は、Ｎ型の第１トランジスタＭＮ１１のゲートへ与えられるハイレベル又はローレベルの電圧を保持する。 The cascode amplifier 5c of FIG. 13 has the same configuration as that of the fifth embodiment, a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11, an input terminal, and the gate of the N-type first transistor MN11. And a twelfth capacitor C12 inserted between the first and second capacitors. The latch circuit LATCH2 is composed of a pair of inverter circuits whose inputs are connected to the outputs as shown in FIG. 13, for example. The latch circuit LATCH2 holds a high level or low level voltage applied to the gate of the N-type first transistor MN11.
　（実施形態の動作）
　次に図１３のカスコード型増幅器５ｃの動作について、図１４を参照して説明する。図１４のカスコード型増幅器５ｃの入力には”０”又は”１”のパルス信号が入力される。Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧は、一例として１Ｖであるものとして説明する。 (Operation of the embodiment)
Next, the operation of the cascode amplifier 5c shown in FIG. 13 will be described with reference to FIG. A pulse signal of “0” or “1” is input to the input of the cascode amplifier 5c in FIG. The element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example.
　電源電圧ＶＤＤを基準として、第２電源Ｖ２は、電源電圧ＶＤＤの４倍のＶＤＤ×４の電圧を出力する。第３電源Ｖ３はＧＮＤであり、０Ｖ（ＶＤＤ×０）が与えられるものとする。Ｐ型の第１トランジスタＭＰ１１のゲートには、第２電源Ｖ２を第６抵抗Ｒ１６などで抵抗分割した電圧として、４Ｖ又は３Ｖが与えられる。 With reference to the power supply voltage V DD , the second power supply V2 outputs a voltage of V DD × 4 that is four times the power supply voltage V DD . The third power supply V3 is GND, and 0 V (V DD × 0) is given. 4V or 3V is applied to the gate of the P-type first transistor MP11 as a voltage obtained by resistance-dividing the second power supply V2 with the sixth resistor R16 or the like.
　入力の”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートには４Ｖ又は３Ｖが与えられ、Ｎ型の第１トランジスタＭＮ１１のゲートには０Ｖ又は１Ｖが与えられる。これに伴って、縦続接続されたＰ型の第１トランジスタＭＰ１１と第２トランジスタＭＰ１２との接続点は４Ｖと３Ｖとの間で変化し、縦続接続されたＰ型の第２トランジスタＭＰ１２と第３トランジスタＭＰ１３との接続点は４Ｖと２Ｖとの間で変化し、縦続接続されたＰ型の第３トランジスタＭＰ１３と第４トランジスタＭＰ１４との接続点は４Ｖと１Ｖとの間で変化する。また、縦続接続されたＮ型の第１トランジスタＭＮ１１と第２トランジスタＭＮ１２との接続点は１Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第２トランジスタＭＮ１２と第３トランジスタＭＮ１３との接続点は２Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第３トランジスタＭＮ１３と第４トランジスタＭＮ１４との接続点は３Ｖと０Ｖとの間で変化する。 Depending on the input “0” or “1” pulse signal (0V or 1V), 4V or 3V is applied to the gate of the P-type first transistor MP11, and the gate of the N-type first transistor MN11 is applied to the gate. 0V or 1V is applied. Accordingly, the connection point between the cascaded P-type first transistor MP11 and the second transistor MP12 changes between 4V and 3V, and the cascade-connected P-type second transistor MP12 and the third transistor MP12 are connected to each other. The connection point with the transistor MP13 changes between 4V and 2V, and the connection point between the cascaded P-type third transistor MP13 and the fourth transistor MP14 changes between 4V and 1V. Also, the connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V, and the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
　さらにＰ型の第４トランジスタＭＰ１４のゲート、Ｎ型の第４トランジスタＭＮ１４のゲート、第１キャパシタＣ１の一端、及び第４キャパシタＣ４の一端の接続点の電位は、３Ｖと１Ｖとの間で変化する。その結果、入力の”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、図１４のカスコード型増幅器５ｃの出力端子は４Ｖ又は０Ｖを出力する。 Furthermore, the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do. As a result, the output terminal of the cascode amplifier 5c in FIG. 14 outputs 4V or 0V according to the input “0” or “1” pulse signal (0V or 1V).
　（実施形態の効果）
　抵抗は周波数特性を持たないので、図１３のカスコード型増幅器５ｃの帰還回路、第３抵抗Ｒ１３、第７抵抗Ｒ１７などは周波数特性を持たない。これによりＰ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器５ｃを広帯域化することができる。 (Effect of embodiment)
Since the resistor does not have frequency characteristics, the feedback circuit of the cascode amplifier 5c of FIG. 13, the third resistor R13, the seventh resistor R17, and the like do not have frequency characteristics. As a result, the cascode amplifier 5c can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
　さらに図１３のカスコード型増幅器５ｃでは第５実施形態と同様に、Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１と、入力端子とＰ型の第１トランジスタＭＰ１１のゲートとの間に挿入された第１１キャパシタＣ１１と、を含んでいる。カスコード型増幅器５ｃの入力の”０”又は”１”のパルス信号の変化に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートに、第２電源Ｖ２を第６抵抗Ｒ１６などで抵抗分割した電圧として、４Ｖ又は３Ｖを与えることができる。Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１によって、カスコード型増幅器５ｃの入力変化への追従性が向上し、構成素子の素子耐圧を許容範囲内に維持しつつ、広帯域化を実現することができる。 Further, in the cascode amplifier 5c of FIG. 13, as in the fifth embodiment, the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and the input terminal and the gate of the P-type first transistor MP11 are arranged. And an eleventh capacitor C11 inserted into the. A voltage obtained by resistance-dividing the second power source V2 with the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5c. 4V or 3V can be applied. The latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5c, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
　さらに図１３のカスコード型増幅器５ｃでは、Ｎ型の第１トランジスタＭＮ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ２と、入力端子とＮ型の第１トランジスタＭＮ１１のゲートとの間に挿入された第１２キャパシタＣ１２と、を含んでいる。カスコード型増幅器５ｃの入力の”０”又は”１”のパルス信号の変化に応じて、Ｎ型の第１トランジスタＭＮ１１のゲートに、第３電源Ｖ３を第１０抵抗Ｒ２０などで抵抗分割した電圧として、１Ｖ又は０Ｖを与えることができる。Ｎ型の第１トランジスタＭＮ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ２によって、カスコード型増幅器５ｃの入力変化への追従性が向上し、構成素子の素子耐圧を許容範囲内に維持しつつ、広帯域化を実現することができる。 Further, in the cascode amplifier 5c of FIG. 13, a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 and a twelfth capacitor inserted between the input terminal and the gate of the N-type first transistor MN11. C12. A voltage obtained by dividing the third power source V3 by a tenth resistor R20 or the like at the gate of the N-type first transistor MN11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5c. 1V or 0V can be applied. The latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 improves the follow-up to the input change of the cascode amplifier 5c, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
　さらに図１３のカスコード型増幅器５ｃでは、Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１と、Ｎ型の第１トランジスタＭＮ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ２とを含んで構成することにより、カスコード型増幅器５ｃの全体の回路構成の対称性が向上する。 Further, the cascode amplifier 5c of FIG. 13 includes a latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 and a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11. This improves the symmetry of the overall circuit configuration of the cascode amplifier 5c.
　〔第８実施形態〕
　次に、本発明の第８実施形態によるカスコード型増幅器について、説明する。図１５は、第８実施形態のカスコード型増幅器を説明するための回路図である。第８実施形態のカスコード型増幅器は、第５実施形態乃至第７実施形態のカスコード型増幅器の変形例である。第５実施形態乃至第７実施形態のカスコード型増幅器と同様な要素に対しては、同じ参照番号を付してその詳細な説明を省略することとする。 [Eighth Embodiment]
Next, a cascode amplifier according to an eighth embodiment of the present invention will be described. FIG. 15 is a circuit diagram for explaining a cascode amplifier according to an eighth embodiment. The cascode amplifier according to the eighth embodiment is a modification of the cascode amplifier according to the fifth to seventh embodiments. Elements similar to those of the cascode amplifiers of the fifth to seventh embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.
　図１５のカスコード型増幅器５ｄは第５実施形態と同様な構成に加えて、Ｎ型の第１トランジスタＭＮ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ２と、入力端子とＮ型の第１トランジスタＭＮ１１のゲートとの間に挿入された第１２キャパシタＣ１２とをさらに含む。ラッチ回路ＬＡＴＣＨ２は、例えば図１５に示すような入力が出力に接続された一対のインバータ回路から構成される。ラッチ回路ＬＡＴＣＨ２は、Ｎ型の第１トランジスタＭＮ１１のゲートへ与えられるハイレベル又はローレベルの電圧を保持する。 15 has a configuration similar to that of the fifth embodiment, a latch circuit LATCH2 connected to the gate of the N-type first transistor MN11, an input terminal, and a gate of the N-type first transistor MN11. And a twelfth capacitor C12 inserted between the first and second capacitors. The latch circuit LATCH2 is composed of a pair of inverter circuits whose inputs are connected to the outputs, for example, as shown in FIG. The latch circuit LATCH2 holds a high level or low level voltage applied to the gate of the N-type first transistor MN11.
　さらに入力端子（入力２）とラッチ回路ＬＡＴＣＨ１の一端との間に挿入された第１３キャパシタＣ１３と、入力端子（入力２）とラッチ回路ＬＡＴＣＨ２の一端との間に挿入された第１４キャパシタＣ１４と、をさらに含む。 Furthermore, a thirteenth capacitor C13 inserted between the input terminal (input 2) and one end of the latch circuit LATCH1, and a fourteenth capacitor C14 inserted between the input terminal (input 2) and one end of the latch circuit LATCH2; Further included.
　（実施形態の動作）
　次に図１５のカスコード型増幅器５ｄの動作について、図１６を参照して説明する。図１６のカスコード型増幅器５ｄの入力端子（入力１）には相補的な２つの入力信号のうち一方の信号が入力され、入力端子（入力２）には相補的な２つの入力信号のうち他方の信号が入力される。図１６では入力端子（入力１）には”０”又は”１”のパルス信号が入力され、入力端子（入力２）には”１”又は”０”のパルス信号が入力される。Ｐ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧は、一例として１Ｖであるものとして説明する。 (Operation of the embodiment)
Next, the operation of the cascode amplifier 5d shown in FIG. 15 will be described with reference to FIG. One of the two complementary input signals is input to the input terminal (input 1) of the cascode amplifier 5d in FIG. 16, and the other of the two complementary input signals is input to the input terminal (input 2). Signal is input. In FIG. 16, a pulse signal of “0” or “1” is input to the input terminal (input 1), and a pulse signal of “1” or “0” is input to the input terminal (input 2). The element breakdown voltages of the P-type first transistor MP11 to the fourth transistor MP14 and the N-type first transistor MN11 to the fourth transistor MN14 are assumed to be 1 V as an example.
　電源電圧ＶＤＤを基準として、第２電源Ｖ２は、電源電圧ＶＤＤの４倍のＶＤＤ×４の電圧を出力する。第３電源Ｖ３はＧＮＤであり、０Ｖ（ＶＤＤ×０）が与えられるものとする。 With reference to the power supply voltage V DD , the second power supply V2 outputs a voltage of V DD × 4 that is four times the power supply voltage V DD . The third power supply V3 is GND, and 0 V (V DD × 0) is given.
　入力端子（入力１）への”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートには４Ｖ又は３Ｖが与えられ、Ｎ型の第１トランジスタＭＮ１１のゲートには０Ｖ又は１Ｖが与えられる。これに伴って、縦続接続されたＰ型の第１トランジスタＭＰ１１と第２トランジスタＭＰ１２との接続点は４Ｖと３Ｖとの間で変化し、縦続接続されたＰ型の第２トランジスタＭＰ１２と第３トランジスタＭＰ１３との接続点は４Ｖと２Ｖとの間で変化し、縦続接続されたＰ型の第３トランジスタＭＰ１３と第４トランジスタＭＰ１４との接続点は４Ｖと１Ｖとの間で変化する。また、縦続接続されたＮ型の第１トランジスタＭＮ１１と第２トランジスタＭＮ１２との接続点は１Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第２トランジスタＭＮ１２と第３トランジスタＭＮ１３との接続点は２Ｖと０Ｖとの間で変化し、縦続接続されたＮ型の第３トランジスタＭＮ１３と第４トランジスタＭＮ１４との接続点は３Ｖと０Ｖとの間で変化する。 Depending on the pulse signal (0V or 1V) of “0” or “1” to the input terminal (input 1), 4V or 3V is applied to the gate of the P-type first transistor MP11, and the N-type first 0V or 1V is applied to the gate of the transistor MN11. Accordingly, the connection point between the cascaded P-type first transistor MP11 and the second transistor MP12 changes between 4V and 3V, and the cascade-connected P-type second transistor MP12 and the third transistor MP12 are connected to each other. The connection point with the transistor MP13 changes between 4V and 2V, and the connection point between the cascaded P-type third transistor MP13 and the fourth transistor MP14 changes between 4V and 1V. Also, the connection point between the cascaded N-type first transistor MN11 and the second transistor MN12 varies between 1V and 0V, and the cascaded N-type second transistor MN12 and third transistor MN13 The connecting point of the N-type third transistor MN13 and the fourth transistor MN14 connected in cascade changes between 3V and 0V.
　さらにＰ型の第４トランジスタＭＰ１４のゲート、Ｎ型の第４トランジスタＭＮ１４のゲート、第１キャパシタＣ１の一端、及び第４キャパシタＣ４の一端の接続点の電位は、３Ｖと１Ｖとの間で変化する。その結果、信号源６からの”０”又は”１”のパルス信号（０Ｖ又は１Ｖ）に応じて、図１６のカスコード型増幅器５ｄの出力端子は４Ｖ又は０Ｖを出力する。 Furthermore, the potential at the connection point of the gate of the P-type fourth transistor MP14, the gate of the N-type fourth transistor MN14, one end of the first capacitor C1, and one end of the fourth capacitor C4 varies between 3V and 1V. To do. As a result, the output terminal of the cascode amplifier 5d in FIG. 16 outputs 4V or 0V according to the pulse signal (0V or 1V) of “0” or “1” from the signal source 6.
　（実施形態の効果）
　抵抗は周波数特性を持たないので、図１５のカスコード型増幅器５ｄの帰還回路、第３抵抗Ｒ１３、第７抵抗Ｒ１７などは周波数特性を持たない。これによりＰ型の第１トランジスタＭＰ１１～第４トランジスタＭＰ１４、Ｎ型の第１トランジスタＭＮ１１～第４トランジスタＭＮ１４の素子耐圧を許容範囲内に維持しつつ、カスコード型増幅器５ｄを広帯域化することができる。 (Effect of embodiment)
Since the resistor does not have frequency characteristics, the feedback circuit, the third resistor R13, the seventh resistor R17, and the like of the cascode amplifier 5d in FIG. 15 do not have frequency characteristics. As a result, the cascode amplifier 5d can be widened while maintaining the element breakdown voltages of the P-type first transistor MP11 to fourth transistor MP14 and the N-type first transistor MN11 to fourth transistor MN14 within an allowable range. .
　さらに図１５のカスコード型増幅器５ｄでは第５実施形態などと同様に、Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１と、入力端子とＰ型の第１トランジスタＭＰ１１のゲートとの間に挿入された第１１キャパシタＣ１１と、を含んでいる。カスコード型増幅器５ｄの入力の”０”又は”１”のパルス信号の変化に応じて、Ｐ型の第１トランジスタＭＰ１１のゲートに、第２電源Ｖ２を第６抵抗Ｒ１６などで抵抗分割した電圧として、４Ｖ又は３Ｖを与えることができる。Ｐ型の第１トランジスタＭＰ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ１によって、カスコード型増幅器５ｄの入力変化への追従性が向上し、構成素子の素子耐圧を許容範囲内に維持しつつ、広帯域化を実現することができる。 Further, in the cascode amplifier 5d of FIG. 15, as in the fifth embodiment, the latch circuit LATCH1 connected to the gate of the P-type first transistor MP11, the input terminal, and the gate of the P-type first transistor MP11 And an eleventh capacitor C11 inserted therebetween. A voltage obtained by resistance-dividing the second power source V2 by the sixth resistor R16 or the like at the gate of the P-type first transistor MP11 in accordance with the change of the pulse signal “0” or “1” at the input of the cascode amplifier 5d. 4V or 3V can be applied. The latch circuit LATCH1 connected to the gate of the P-type first transistor MP11 improves the follow-up to the input change of the cascode amplifier 5d, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
　さらに図１５のカスコード型増幅器５ｄでは、Ｎ型の第１トランジスタＭＮ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ２と、入力端子とＮ型の第１トランジスタＭＮ１１のゲートとの間に挿入された第１２キャパシタＣ１２と、を含んでいる。カスコード型増幅器５ｄの入力の”０”又は”１”のパルス信号の変化に応じて、Ｎ型の第１トランジスタＭＮ１１のゲートに、第３電源Ｖ３を第１０抵抗Ｒ２０などで抵抗分割した電圧として、１Ｖ又は０Ｖを与えることができる。Ｎ型の第１トランジスタＭＮ１１のゲートに接続されたラッチ回路ＬＡＴＣＨ２によって、カスコード型増幅器５ｄの入力変化への追従性が向上し、構成素子の素子耐圧を許容範囲内に維持しつつ、広帯域化を実現することができる。 Further, in the cascode amplifier 5d of FIG. 15, the latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 and the twelfth capacitor inserted between the input terminal and the gate of the N-type first transistor MN11. C12. A voltage obtained by resistance-dividing the third power source V3 by the tenth resistor R20 or the like at the gate of the N-type first transistor MN11 in accordance with the change of the pulse signal of “0” or “1” at the input of the cascode amplifier 5d. 1V or 0V can be applied. The latch circuit LATCH2 connected to the gate of the N-type first transistor MN11 improves the follow-up to the input change of the cascode amplifier 5d, and increases the bandwidth while maintaining the element breakdown voltage within the allowable range. Can be realized.
　さらに図１５のカスコード型増幅器５ｄでは入力端子（入力２）から、カスコード型増幅器５ｄの入力端子（入力１）への入力”０”又は”１”のパルス信号を反転した電位が与えられる。これにより、ラッチ回路ＬＡＴＣＨ１が保持しＰ型の第１トランジスタＭＰ１１のゲートへ与えられる電圧と、ラッチ回路ＬＡＴＣＨ２が保持しＮ型の第１トランジスタＭＮ１１のゲートへ与えられる電圧がそれぞれ安定する。これにより、カスコード型増幅器５ｄの入力端子（入力１）への入力”０”又は”１”の変化に対する追従性を、図９のカスコード型増幅器５ａなどより向上させることができる。 Further, in the cascode amplifier 5d of FIG. 15, a potential obtained by inverting the pulse signal of “0” or “1” input to the input terminal (input 1) of the cascode amplifier 5d is given from the input terminal (input 2). As a result, the voltage held by the latch circuit LATCH1 and applied to the gate of the P-type first transistor MP11 and the voltage held by the latch circuit LATCH2 and applied to the gate of the N-type first transistor MN11 are stabilized. As a result, the followability with respect to the change of the input “0” or “1” to the input terminal (input 1) of the cascode amplifier 5d can be improved as compared with the cascode amplifier 5a of FIG.
　さらに第５実施形態のカスコード型増幅器５ａや第６実施形態のカスコード型増幅器５ｂと比較して、カスコード型増幅器の回路構成の対称性が向上する。 Furthermore, as compared with the cascode amplifier 5a of the fifth embodiment and the cascode amplifier 5b of the sixth embodiment, the symmetry of the circuit configuration of the cascode amplifier is improved.
　〔その他の実施形態〕
　上述した第１乃至第８実施形態のカスコード型増幅器は、無線通信機の送信器の出力段に用いることができる。図１７は、その他の実施形態の無線通信機を説明するためのブロック図である。 [Other Embodiments]
The cascode amplifiers of the first to eighth embodiments described above can be used for the output stage of the transmitter of the wireless communication device. FIG. 17 is a block diagram for explaining a wireless communication device according to another embodiment.
　図１７の無線通信機１００は、入力信号を増幅して出力するカスコード型増幅器１０１と、カスコード型増幅器１０１の出力に接続されて無線信号を送出するアンテナ１０２と、を含む。カスコード型増幅器１０１には、上述した第１乃至第８実施形態のカスコード型増幅器を用いることができる。 17 includes a cascode amplifier 101 that amplifies and outputs an input signal, and an antenna 102 that is connected to the output of the cascode amplifier 101 and transmits a radio signal. As the cascode amplifier 101, the cascode amplifiers of the first to eighth embodiments described above can be used.
　第１乃至第８実施形態のカスコード型増幅器が素子耐圧を許容範囲内に維持しつつ、広帯域化を実現したことにより、これを採用した図１７の無線通信機１００は小型化が可能となる。よって図１７の無線通信機１００によれば、５Ｇ基地局の小型化への大きな貢献が期待できる。 Since the cascode amplifiers according to the first to eighth embodiments realize a wide band while maintaining the element breakdown voltage within an allowable range, the wireless communication device 100 of FIG. 17 employing this can be miniaturized. Therefore, according to the wireless communication device 100 of FIG.
　以上、本発明の好ましい実施形態を説明したが、本発明はこれに限定されるものではない。上述した実施形態では、カスコード型増幅器を構成するトランジスタの素子耐圧が１Ｖの場合で説明したが、これには限られない。上述した実施形態では、信号源６の出力レベルが０Ｖ又は１Ｖの場合で説明したが、これには限られない。第１電源Ｖ１、第２電源Ｖ２、第３電源Ｖ３、第４電源Ｖ４などの電位の具体値は上述した実施形態に限られず、お互いの大小関係を維持しつつ、適宜設定すればよい。請求の範囲に記載した発明の範囲内で、種々の変形が可能であり、それらも本発明の範囲に含まれることはいうまでもない。 The preferred embodiment of the present invention has been described above, but the present invention is not limited to this. In the above-described embodiment, the case where the element withstand voltage of the transistors constituting the cascode amplifier is 1 V has been described, but the present invention is not limited to this. In the above-described embodiment, the case where the output level of the signal source 6 is 0V or 1V has been described. However, the present invention is not limited to this. The specific values of the potentials of the first power supply V1, the second power supply V2, the third power supply V3, the fourth power supply V4 and the like are not limited to the above-described embodiments, and may be set as appropriate while maintaining the mutual magnitude relationship. It goes without saying that various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention.
　以上、上述した実施形態を模範的な例として本発明を説明した。しかしながら、本発明は、上述した実施形態には限定されない。即ち、本発明は、本発明のスコープ内において、当業者が理解し得る様々な態様を適用することができる。 The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.
　この出願は、２０１８年５月３１日に出願された日本出願特願２０１８－１０４３４９号を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2018-104349 filed on May 31, 2018, the entire disclosure of which is incorporated herein.
　１、２、３、４、５、１０、１０１　　カスコード型増幅器
　６　　信号源
　１００　　無線通信機
　１０２　　アンテナ 1, 2, 3, 4, 5, 10, 101 Cascode amplifier 6 Signal source 100 Wireless communication device 102 Antenna

Claims (10)

  1. 　複数のトランジスタ
    　　を含む、カスコード型増幅器であって、
    　出力信号を抵抗分割してカスコードトランジスタのゲートに帰還する構成
    　　を含む、カスコード型増幅器。     A cascode amplifier including a plurality of transistors,
    A cascode amplifier including a configuration in which an output signal is divided into resistors and fed back to the gate of a cascode transistor.
  2. 　前記構成は、
    　　第１抵抗と、
    　　第２抵抗と、
    　　　を含み、
    　　前記第１抵抗は、
    　　　出力端子と、第１ノードと、の間に接続され、
    　　前記第２抵抗は、
    　　　第１電源と、前記第１ノードと、の間に接続されている、請求項１に記載のカスコード型増幅器。     The configuration is as follows:
    A first resistor;
    A second resistor;
    Including
    The first resistor is
    Connected between the output terminal and the first node;
    The second resistor is
    The cascode amplifier according to claim 1, wherein the cascode amplifier is connected between a first power source and the first node.
  3. 　前記構成は、
    　　第１抵抗と、
    　　第２抵抗と、
    　　　を含み、
    　　前記第１抵抗は、
    　　　出力端子と、第１ノードと、の間に接続され、
    　　前記第２抵抗は、
    　　　第２電源と第３電源との間に直列接続された第３抵抗及び第４抵抗の接続点と、前記第１ノードと、の間に接続されている、請求項１に記載のカスコード型増幅器。     The configuration is as follows:
    A first resistor;
    A second resistor;
    Including
    The first resistor is
    Connected between the output terminal and the first node;
    The second resistor is
    2. The cascode amplifier according to claim 1, wherein the cascode amplifier is connected between a connection point of a third resistor and a fourth resistor connected in series between a second power source and a third power source and the first node. .
  4. 　前記複数のトランジスタは、
    　　第１トランジスタと、
    　　第２トランジスタと、
    　　第３トランジスタと、
    　　第４トランジスタと、
    　　　を含み、
    　　前記第１トランジスタおよび前記第３トランジスタは、
    　　　入力端子からの入力信号がゲートに入力され、
    　　前記第２トランジスタは、
    　　　前記第１トランジスタと、出力端子と、の間に縦続接続され、
    　　前記第４トランジスタは、
    　　　前記第３トランジスタと、出力端子と、の間に縦続接続され、前記カスコード型増幅器は、
    　第５抵抗と、
    　第６抵抗と、
    　第７抵抗と、
    　第８抵抗と、
    　　を含み、
    　前記第５抵抗は、
    　　第１ノードと、前記第１トランジスタのゲートと、の間に接続され、
    　前記第６抵抗は、
    　　前記第１トランジスタのゲートと、第２電源と、の間に接続され
    　前記第７抵抗は、
    　　前記第１ノードと、前記第３トランジスタのゲートと、の間に接続され、
    　前記第８抵抗は、
    　　前記第３トランジスタのゲートと、第３電源と、の間に接続されている、請求項１から請求項３のいずれかに記載のカスコード型増幅器。     The plurality of transistors are:
    A first transistor;
    A second transistor;
    A third transistor;
    A fourth transistor;
    Including
    The first transistor and the third transistor are:
    The input signal from the input terminal is input to the gate,
    The second transistor is
    Cascaded between the first transistor and the output terminal;
    The fourth transistor includes:
    The cascode amplifier is connected in cascade between the third transistor and an output terminal.
    A fifth resistor;
    A sixth resistor;
    A seventh resistor;
    An eighth resistor;
    Including
    The fifth resistor is
    Connected between the first node and the gate of the first transistor;
    The sixth resistor is
    The seventh resistor connected between the gate of the first transistor and a second power source,
    Connected between the first node and the gate of the third transistor;
    The eighth resistor is
    The cascode amplifier according to any one of claims 1 to 3, wherein the cascode amplifier is connected between a gate of the third transistor and a third power source.
  5. 　第１キャパシタと、
    　第２キャパシタと、
    　　を含み、
    　前記第１キャパシタは、
    　　前記第２トランジスタのゲートと、前記第３電源と、の間に接続され、
    　前記第２キャパシタは、
    　　前記第４トランジスタのゲートと、前記第３電源と、の間に接続されている、請求項４に記載のカスコード型増幅器。     A first capacitor;
    A second capacitor;
    Including
    The first capacitor is
    Connected between the gate of the second transistor and the third power source;
    The second capacitor is
    The cascode amplifier according to claim 4, wherein the cascode amplifier is connected between a gate of the fourth transistor and the third power source.
  6. 　第３キャパシタと、
    　第１ラッチ回路と、
    　　を含み、
    　前記第３キャパシタは、
    　　前記入力端子と、前記第１トランジスタのゲートと、の間に接続され、
    　前記第１ラッチ回路は、
    　　一端が、前記第１トランジスタのゲートに、接続されている、請求項４または請求項５に記載のカスコード型増幅器。     A third capacitor;
    A first latch circuit;
    Including
    The third capacitor is
    Connected between the input terminal and the gate of the first transistor;
    The first latch circuit includes:
    The cascode amplifier according to claim 4, wherein one end is connected to a gate of the first transistor.
  7. 　第４キャパシタ
    　　を含み、
    　前記第４キャパシタは、
    　　前記第１ラッチ回路の前記一端とは異なる他端と、所定の電位が与えられる配線と、の間に接続されている、請求項６に記載のカスコード型増幅器。     Including a fourth capacitor,
    The fourth capacitor is
    The cascode amplifier according to claim 6, connected between the other end different from the one end of the first latch circuit and a wiring to which a predetermined potential is applied.
  8. 　第５キャパシタと、
    　第２ラッチ回路と、
    　　を含み、
    　前記第５キャパシタは、
    　　前記入力端子と、前記第３トランジスタのゲートと、の間に接続され、
    　前記第２ラッチ回路は、
    　　一端が、前記第３トランジスタのゲートに、接続されている、請求項６に記載のカスコード型増幅器。     A fifth capacitor;
    A second latch circuit;
    Including
    The fifth capacitor is
    Connected between the input terminal and the gate of the third transistor;
    The second latch circuit includes:
    The cascode amplifier according to claim 6, wherein one end is connected to a gate of the third transistor.
  9. 　前記入力端子は、
    　　第１入力端子と、
    　　第２入力端子と、
    　　　を含み、前記カスコード型増幅器は、
    　第６キャパシタと、
    　第７キャパシタと、
    　　を含み、
    　前記第６キャパシタは、
    　　前記第１ラッチ回路の前記一端とは異なる他端と、前記第２入力端子と、の間に接続され、
    　前記第７キャパシタは、
    　　前記第２ラッチ回路の前記一端とは異なる他端と、前記第２入力端子と、の間に接続されている、請求項８に記載のカスコード型増幅器。     The input terminal is
    A first input terminal;
    A second input terminal;
    The cascode amplifier includes:
    A sixth capacitor;
    A seventh capacitor;
    Including
    The sixth capacitor includes:
    The other end different from the one end of the first latch circuit is connected between the second input terminal,
    The seventh capacitor is
    The cascode amplifier according to claim 8, connected between the other end different from the one end of the second latch circuit and the second input terminal.
  10. 　請求項１から請求項９のいずれかに記載のカスコード型増幅器と、
    　前記カスコード型増幅器の出力に接続されたアンテナと、
    　　を含む無線通信機。     A cascode amplifier according to any one of claims 1 to 9,
    An antenna connected to the output of the cascode amplifier;
    Including wireless communication equipment.
PCT/JP2019/020448 2018-05-31 2019-05-23 Cascode-type amplifier and wireless communication device WO2019230555A1 (en)

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JPS54152845A (en) * 1978-05-24 1979-12-01 Hitachi Ltd High dielectric strength mosfet circuit
JP2010141496A (en) * 2008-12-10 2010-06-24 Seiko Epson Corp Semiconductor integrated circuit, driving method of semiconductor integrated circuit, electronic device, and driving method of electronic device
JP2014220735A (en) * 2013-05-10 2014-11-20 富士通セミコンダクター株式会社 Output circuit and voltage signal output method
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