WO2019218596A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2019218596A1
WO2019218596A1 PCT/CN2018/111717 CN2018111717W WO2019218596A1 WO 2019218596 A1 WO2019218596 A1 WO 2019218596A1 CN 2018111717 W CN2018111717 W CN 2018111717W WO 2019218596 A1 WO2019218596 A1 WO 2019218596A1
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WIPO (PCT)
Prior art keywords
signal line
line
display panel
display
display area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2018/111717
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English (en)
French (fr)
Inventor
秦旭
杭玉莹
张金方
张露
胡思明
韩珍珍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Priority to US16/435,558 priority Critical patent/US10797085B2/en
Publication of WO2019218596A1 publication Critical patent/WO2019218596A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application relates to the field of display, and in particular to display panels and display devices.
  • a non-rectangular display is called a shaped display.
  • the shaped display includes a shaped display area and a non-shaped display area.
  • the number of pixel units per row of the shaped display area is different from the number of pixel units per line of the non-shaped display area.
  • the heterogeneous display area and the non-aliased display area may have different loads on the scan line due to the difference in the number of pixel units in each row.
  • a power compensation unit is disposed in the non-display area of the display panel.
  • the parasitic capacitance of the power line and the scan line is increased, thereby increasing the load of the scan line.
  • the difference between the power supply compensation unit and the power supply line width without the compensation unit is large, the difference in resistance and capacitance on the power supply line is large, and the brightness of the displayed image is uneven, which affects the display effect.
  • a display panel includes a display area and a non-display area disposed around the display area;
  • the display area includes a first display area and a second display area, the first display area includes a pixel unit arranged in an array and a first scan line connecting the pixel units of each row; the second display area includes an array Arranged pixel units;
  • the non-display area includes a fixed potential signal line, the fixed potential signal line includes a first signal line and a second signal line, the second signal line is connected to the first signal line, and the second signal line includes a connecting portion and spaced apart strip portions connected to the connecting portion, a width of the second signal line being greater than a width of the first signal line;
  • the display panel further includes a lead line corresponding to the first scan line and extending to overlap the non-display area and the second signal line, the second signal line and the lead line
  • the heterogeneous layer is disposed between the second signal line and the lead line for generating a parasitic capacitance to compensate a load of the first scan line.
  • the number of pixel cells per row in the first display region is less than the number of pixel cells in each row in the second display region.
  • the width of the strip portion is the same as the width of the first signal line.
  • the number of pixel units on at least two rows in the first display area is different, and the lengths of the lead lines corresponding to the pixel units on the different rows are different.
  • the length of the leader line increases as the number of pixel cells in the row corresponding to the leader line decreases.
  • the display panel includes a slotted area, the slotted area is disposed in the non-display area, and adjacent to the first display area, so that each row of pixels in the first display area The number of cells is less than the number of pixel cells per row in the second display region.
  • the display panel includes a front surface having a display area
  • the projection of the grooved area on the front side includes a bottom edge and sides disposed on both sides of the bottom edge, the first signal line edge The side is disposed, and the second signal line is disposed along the bottom edge.
  • the lead wires are disposed along the side edges and extend from the side edges to the bottom edges.
  • the fixed potential signal line includes a power signal line.
  • the second display area includes a second scan line connecting each row of pixel units, and the number of strip portions of the second signal line overlapping the lead line, and the first scan line
  • the number of pixel cells on is proportional to the difference in the number of pixel cells on the second scan line.
  • the power signal line is coupled to the lead line to form a parasitic capacitance, and the load of the first scan line is compensated such that the load of the first scan line is the same as the load of the second scan line.
  • the display panel is further provided with a first metal layer, which is a gate metal layer of a transistor in the display panel, and the lead line is also performed with the first metal layer of the display panel. Coupling, forming a parasitic capacitance, and performing load compensation on the first scan line.
  • the lead line is located between the second signal line and the first metal layer of the display panel.
  • a display device includes the aforementioned display panel.
  • the display device further includes a sensor disposed in the slotted area.
  • the display panel and the display device are coupled to each other by using a second signal line having a wide width and a lead line of the first scan line to form a parasitic capacitance, and compensating for a load of the first scan line to load the first scan line and the second
  • the load on the scan lines is the same.
  • the second signal line in the present application includes a plurality of strip portions arranged at intervals, and the first signal line and the second signal line can be reduced by using strip-shaped power lines arranged at intervals compared with the conventional full-surface power signal line.
  • the difference in line width further reduces the voltage difference between the pixel cells connected to the first signal line and the second signal line, so that the voltages of the pixel cells are the same, and the pixel currents are also the same, which improves the uniformity of display.
  • FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a fixed potential signal line provided by another embodiment of the present application.
  • FIG. 3 is a schematic diagram of a power signal line with a compensation unit in the prior art
  • FIG. 4 is a schematic diagram of a power signal line without a compensation unit in the prior art.
  • an embodiment of the present application provides a display panel 100 including a display area 110 and a non-display area 120 disposed around the display area 110 .
  • the display area 110 includes a first display area 111 and a second display area 112.
  • the first display area 111 includes an array of pixel units 101 and a first scan line 102 connecting each row of pixel units.
  • the second display area 112 includes an array of pixel units 101 and a second scan line 103 connecting each row of pixel units 101.
  • the number of pixel units 101 in each row in the first display area 111 is smaller than the number of pixel units 101 in each row in the second display area 112.
  • the non-display area 120 is provided with a fixed potential signal line 104.
  • the fixed potential signal line 104 includes a first signal line 105 and a second signal line 106.
  • the second signal line 106 includes a connecting portion (not shown in FIG. 1) and spaced apart strip portions (not shown in FIG. 1) connected to the connecting portion.
  • the first signal line 105 and the connecting portion extend in the first direction
  • the strip portion extends in the second direction
  • the first direction is perpendicular to the second direction.
  • the width of the first signal line 105 in the second direction is smaller than the width of the second signal line 106 in the same direction.
  • the first signal line 105 and the second signal line 106 are continuous one fixed potential signal lines, that is, the first signal line 105 and the second signal line 106 may be two signal lines electrically connected to each other, or may be one signal. The two parts of the line.
  • the display panel 100 further includes a lead line 107 that is connected in one-to-one correspondence with the first scan line 102, and the lead line 107 extends to the non-display area 120 and overlaps with the projection of the second signal line 106 on the display panel 100.
  • the fixed potential signal line 104 and the lead line 107 are disposed in different layers.
  • the second signal line 106 and the lead line 107 are disposed in different layers, that is, the second signal line 106 and the lead line 107 are separated by an insulating medium.
  • a parasitic capacitance can be generated between the lead line 107 and the second signal line 106 for load compensation of the first scan line 103.
  • the display panel provided in this embodiment performs load compensation on the first scan line 102 by using a fixed potential signal line 104 and a lead line 107 of the first scan line 102 to form a parasitic capacitance, thereby making the first scan line 102 and the first scan line 102
  • the load of the two scanning lines 103 is the same.
  • the fixed potential signal line includes the first signal line 105 and the second signal line 106 of two widths, the total width of the second signal line 106 is greater than the width of the first signal line 105, and the second signal line 106 includes a plurality of interval settings.
  • the strip portion 1062, the line width of each strip portion 1062 in the first direction and the line width of the first signal line 105 in the second direction are smaller, and the line resistance of the strip portion 1062 and the first signal line
  • the on-line resistance difference of 105 is small, and the voltage difference of the on-line resistance loss is small, thereby further reducing the voltage difference between the pixel unit connected to the first signal line 105 and the pixel unit of the second signal line 106, thereby improving uniformity of display brightness. Sex and improve the display.
  • the fixed potential signal line 104 includes a first signal line 105 and a second signal line 106.
  • the second signal line 106 includes a connecting portion 1061 and a plurality of strip portions 1062 connected to the connecting portion 1061 and spaced apart from each other.
  • the first signal line 105 and the connecting portion 1061 extend in the first direction D1
  • the strip portion 1062 extends in the second direction D2
  • the first direction D1 is perpendicular to the second direction D2.
  • the width of each strip portion 1062 in the first direction D1 is equal to the width of the first signal line 105 in the second direction D2.
  • the fixed potential signal line 104 may be a power signal line.
  • the power signal line is coupled to the lead line 107 to form a parasitic capacitance, and the load of the first scan line 102 is compensated so that the load amount of the first scan line 102 is the same as the load amount of the second scan line 103.
  • One end of the lead line 107 is connected to the first scan line 102, and the other end is extended by the frame trace to overlap with the second signal line 106.
  • the second signal line 106 is connected to the first signal line 105 through the connection portion 1061.
  • the second signal line 106 further includes a strip portion 1062 that is spaced apart from the connection portion 1061.
  • the lead wire 107 extends to overlap the strip portion 1062. Since the lead wire 107 and the strip portion 1062 are disposed separately from each other with an insulating medium interposed therebetween, a portion where the lead wire 107 overlaps the strip portion 1062 can form a parasitic capacitance, and load compensation can be performed on the lead wire 107.
  • the lead line 107 can also be coupled to the first metal layer (not shown in FIG. 1) of the display panel 100 to form yet another parasitic capacitance.
  • the first metal layer is a gate metal layer of a transistor in the display panel 100. Therefore, the lead line 107 may be located between the second signal line 106 and the first metal layer of the display panel 100, and coupled with the second signal line 106 and the first metal layer to form a parasitic capacitance, respectively, to load-compensate the first scan line 102.
  • the width of the strip portion 1062 in the first direction D1 is the same as the width of the first signal line 105 in the second direction D2, and the width of the connecting portion 1061 along the second direction D2 is the same as the first signal line.
  • the width of the two directions D2 is the same, and the connecting portion 1061, the strip portion 1062 and the first signal line 105 belong to the same power signal line. Since the line widths of the power signal lines are the same, the resistances around the power signal lines are approximated. Since the first signal 105 is connected to each column of the pixel unit 101 in the first display area 111, the second signal line 106 is connected to each column of the pixel unit 101 in the second display area 112, and the power supply voltage is supplied to the pixel unit 101.
  • the first signal line 105 and the second signal line 106 have the same resistance on the line, and the consumed resistance is also the same.
  • the first signal line 105 is distributed to the power supply voltage of the pixel unit 101 in the first display area 111, and is the same as the power supply voltage of the second signal line 106 allocated to the pixel unit 101 in the second display area 112.
  • the pixel unit in the first display area 111 The pixel current of 101 is also the same as the pixel current of the pixel unit 101 in the second display area 112, and the brightness of the display panel 100 is the same, which improves the display effect.
  • the width of the strip portion 1062 may not be equal to the width of the first signal line 105. According to the requirement, the width of the strip portion 1062 is minimized to be close to the width of the first signal line 105 to reduce the line width difference between the strip portion and the first signal line, in accordance with the size of the required compensation capacitor. Further, the on-line resistance difference of different regions on the same power signal line is reduced, and the voltage difference of the pixel units connected to the power signal lines of different widths is reduced, thereby improving the brightness uniformity of the display panel.
  • the pixel units connected to different widths on the power signal line are respectively P1, P2, P3, and P4, wherein P1 and P4 are connected to the first signal line, and P2 and P3 are connected to the second signal line.
  • 3 is a power signal line 300 without a compensation unit, and the same pixel unit P1, P2, P3, P4 are connected at the same position.
  • 4 is a power signal line 400 having a full-face compensation unit connected to the same pixel unit P1, P2, P3, P4 at the same position, wherein P1, P4 are connected to a portion 402 having no compensation unit, and P2, P3 are connected with a compensation unit. Part 401.
  • the power signal line having the strip portion 1062 is compared with the power signal line 300 having no compensation unit in FIG. 3, and the current variation between the different pixel units, and the power signal line 400 having the entire surface compensation unit of FIG. Figure 3 shows the current variation between different pixel units compared to the power signal line 300 without the compensation unit as shown in the following table:
  • the first current difference change rate is a ratio between a difference between a current drop value of the scheme shown in FIG. 4 and a current drop value of the scheme shown in FIG. 3 and a current drop value of the scheme shown in FIG. 3.
  • the second current difference change rate is a ratio between the difference between the current drop value of the embodiment of the present embodiment and the current drop value of the scheme shown in FIG. 3 and the current drop value of the scheme shown in FIG.
  • the larger the pixel current drop value the greater the difference in luminance between different pixels.
  • the current difference change rate represents the rate of change of the pixel current between the pixel units connected to the power signal lines of different line widths. The greater the rate of change of the current difference, the greater the difference in luminance between pixels, and the more serious the split-screen phenomenon.
  • the power signal line 400, the current drop value of P1 to P2, and the current drop value of P3 to P4 in the scheme shown in FIG. 4 are both It is larger than the current drop value of P1 to P2 and the current drop value of P3 to P4 in the scheme shown in FIG.
  • the power supply signal line 400 having the full-surface compensation unit shown in FIG. 4 performs load compensation on the first scan line 102 in the first display area 111, so that the load of the first scan line 102 is the same as the load of the second scan line 103.
  • the load difference of the scan lines is compensated for, but since the line width difference between the portion 401 having the compensation unit on the power signal line 400 and the portion 402 having no compensation unit is large, the resistance difference on the power signal line 400 is large.
  • the power supply voltage obtained by the pixel unit connected to the power signal line 400 of the portion 401 having the compensation unit is smaller than the power supply voltage obtained by connecting the pixel unit of the power supply signal line 400 of the portion 402 having no compensation unit, and the pixel current is also small, still A split screen phenomenon will occur.
  • the power signal line having the strip portion 1062 provided in this embodiment can reduce the difference in line width of each region on the same power signal line, that is, the difference in line resistance on the same power signal line.
  • the rate of change of the second current difference corresponding to the solution provided in this embodiment is smaller than the rate of change of the first current difference corresponding to the solution shown in FIG. That is, in the present case, the difference in power supply voltage between the pixel unit connected to the second signal line 106 and the pixel unit 101 connected to the first signal line 105 is smaller than that in the scheme shown in FIG. 4, and the pixel current difference is also small, thereby improving. Split screen phenomenon.
  • the number of pixel units 101 of at least two rows in the first display area 111 is different, and the lengths of the lead lines 107 corresponding to the pixel units 101 on different rows are also different.
  • the number of the at least two rows of pixel units 101 in the first display area 111 is different, and the load amounts of the at least two rows of the first scan lines 102 are different. Since the number of pixel units 101 in each row in the second display area 112 is the same, the load amount of the second scan lines 103 in each row is the same. Therefore, the difference in the load amount between the first scan line 102 and the second scan line 103 in different rows is different.
  • One end of the lead line 107 is connected to the first scan line 102, and the other end is extended to the non-display area 120 and overlaps with the second signal line 106.
  • a region where the lead line 107 overlaps with the strip portion 1062 of the second signal line 106 forms a parasitic capacitance.
  • the larger the area of the overlap region the larger the capacity of the parasitic capacitance, and the more the load on the first scan line 102 is compensated. Since the amount of load to be compensated for the first scanning line 102 on different rows is different, the lengths of the overlapping portions of the different lead lines 107 and the second signal lines 106 are different, and the areas of the overlapping areas of the lead lines 107 and the strip portions 1062 are also different.
  • the extending direction of the lead line 107 and the extending direction of the strip portion 1062 are perpendicular to each other.
  • the lead line 107 intersects with the strip portion 1062, an overlapping area is generated, and the overlapping area can be used as the first scanning line 102.
  • the arrangement direction of the plurality of strip portions 1062 is the same as the extension direction of the lead line 107.
  • the lead line 107 extends longer, the number of strip portions 1062 overlapping the lead line 107 increases, and the compensation of the connection on the lead line 107 The more the number of units.
  • the lead lines 107 can be set differently according to the difference between the number of the pixel units 101 of each of the first scan lines 102 and the second scan lines 103.
  • the number of strips 1062 overlap to compensate for the first scan line 102 to facilitate determining the amount of load each of the first scan lines 102 needs to compensate.
  • the display panel 100 is provided with a grooved area 130.
  • the grooved area 130 is disposed in the non-display area 120 and adjacent to the first display area 111. Due to the arrangement of the grooved regions 130, the number of pixel units 101 in each row in the first display region 111 is smaller than the number of pixel cells 101 in each row in the second display region 112.
  • the slotted area 130 can be used to set functional components such as sensors to provide functions such as imaging for electronic devices.
  • the display panel 100 includes a front surface having a display area 110, and the projection of the grooved area 130 on the front surface of the display panel includes a bottom edge and sides disposed on both sides of the bottom edge, wherein the first signal line 105 is along the side Side setting, the second signal line 106 is disposed along the bottom edge.
  • the display panel 100 is a rectangular screen body with chamfering.
  • the non-display area 120 of the display panel 100 includes an upper frame and a lower frame extending along the first direction D1, and a first side frame and a second side frame extending along the second direction D2, the first direction D1 being perpendicular to the second direction D2 .
  • the slotted area 130 is formed by recessing the side of the upper frame into the display area 110.
  • the fixed potential signal line 104 is disposed on the upper frame. Since the grooved region 130 is recessed inward, the upper frame includes a bottom edge portion and a side edge portion that abut the grooved region 130.
  • the first signal line 105 is disposed along the side edge, and is disposed on the curved frame of the side portion.
  • the second signal line 106 is disposed along the bottom edge and is disposed on the bottom border portion.
  • the upper frame further includes a straight line frame connecting the two side portions, and the second signal line 106 is disposed on the line border.
  • the first signal line 105 and the second signal line 106 are consecutive one entire power signal line.
  • the first signal disposed on the curved frame is provided.
  • Line 105 is narrow in width.
  • the area of the straight line frame is large, so the second signal line 106 disposed on the line frame has a wide width, and can be used to couple with the lead line 107 to form a parasitic capacitance, and load compensation is performed on the first scan line 102 to make the first scan line 102.
  • the load amount of the second scanning line 103 is equal, the pixel current is the same, and the light emission luminance is also the same.
  • a display device including a package case and a display panel packaged in the package case.
  • the display device also includes a sensor disposed in the slotted area.
  • the sensor may be any one of a camera, a fingerprint recognition component, an iris recognition component, and an earpiece.

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Abstract

一种显示面板（100）和显示装置，显示面板（100）包括第一显示区（111）、第二显示区（112）和非显示区（120），第一显示区（111）内像素单元（101）数量小于第二显示区（112）内像素单元（101）数量。第一显示区（111）包括第一扫描线（102）；非显示区（120）的固定电位信号线（104）包括第一信号线（105）和第二信号线（106），第二信号线（106）与第一信号线（105）连接，第二信号线（106）包括连接部（1061）和连接于连接部（1061）的间隔设置的条形部（1062），第二信号线（106）的宽度大于第一信号线（105）的宽度；第一扫描线（102）通过引出线（107）延伸至非显示区（120）与第二信号线（106）重叠产生寄生电容，用以对第一扫描线（102）进行负载补偿。第二信号线（106）采用间隔设置的条形部（1062），可减小第一信号线（105）与第二信号线（106）的线宽差异，进而减小连接于第一信号线（105）和第二信号线（106）上的像素单元（101）的电压差异，使像素电流相同，提高了显示的均一性。

Description

显示面板和显示装置 技术领域
本申请涉及显示领域，尤其涉及显示面板和显示装置。
背景技术
目前，常见的显示装置，例如显示器、电视机、手机、平板电脑等，其显示屏通常为规则的矩形。随着显示技术的发展，矩形的显示屏已经不能满足用户多样化的使用需求。因而，显示屏的形状越来越多样化。
通常，非矩形的显示屏称为异形显示屏。异形显示屏包括异形显示区与非异形显示区。异形显示区的每行像素单元个数与非异形显示区的每行像素单元个数不同。当扫描线为对应行上的像素单元提供相同的扫描信号时，异形显示区与非异形显示区因各自的每行像素单元个数不同，会导致扫描线上的负载不同。
在传统技术中，显示面板中的非显示区中设置有电源补偿单元，通过增大电源补偿单元的整面线宽，增大电源线与扫描线形成寄生电容，进而增大扫描线的负载。然而，由于电源补偿单元与不具有补偿单元的电源线宽差异较大，导致电源线上的电阻、电容差异较大，使显示的图像亮度不均，影响显示效果。
发明内容
基于此，有必要针对电源线宽度差异的问题，提供一种显示面板和显示装置。
一种显示面板，包括显示区和围绕显示区设置的非显示区；
所述显示区包括第一显示区和第二显示区，所述第一显示区包括阵列排布的像素单元和连接每行所述像素单元的第一扫描线；所述第二显示区包括阵列排布的像素单元；
所述非显示区包括固定电位信号线，所述固定电位信号线包括第一信号线和第二信号线，所述第二信号线与所述第一信号线连接，所述第二信号线包括连接部和连接于所述连接部的间隔设置的条形部，所述第二信号线的宽度大于所述第一信号线的宽度；并且
所述显示面板还包括引出线，所述引出线对应连接所述第一扫描线，并延伸至所述非显示区与所述第二信号线重叠，所述第二信号线与所述引出线异层设置，所述第二信号线与所述引出线之间用于产生寄生电容以补偿所述第一扫描线的负载。
在其中一个实施例中，所述第一显示区内每行像素单元的数量小于所述第二显示区内每行像素单元的数量。
在其中一个实施例中，所述条形部的宽度与所述第一信号线的宽度相同。
在其中一个实施例中，所述第一显示区内至少两行上的像素单元的数量不同，所述不同行上像素单元对应的引出线长度不同。
在其中一个实施例中，所述引出线的长度随引出线所对应行的像素单元数量的减少而增加。
在其中一个实施例中，所述显示面板包括开槽区，所述开槽区设置于所述非显示区，并邻接所述第一显示区，以使所述第一显示区内每行像素单元的数量小于所述第二显示区内每行像素单元的数量。
在其中一个实施例中，所述显示面板包括具有显示区的正面，所述开槽区在所述正面的投影包括底边和分布于底边两侧的侧边，所述第一信号线沿所述侧边设置，所述第二信号线沿所述底边设置。
在其中一个实施例中，所述引出线沿所述侧边设置，并从所述侧边延伸至所述底边。
在其中一个实施例中，所述固定电位信号线包括电源信号线。
在其中一个实施例中，所述第二显示区包括连接每行像素单元的第二扫描线，并且，所述第二信号线的与引出线重叠的条形部的数量，和第一扫描线上的像素单元的数量与第二扫描线上的像素单元的数量的差值成正比。
在其中一个实施例中，所述电源信号线与引出线耦合，形成寄生电容，对第一扫描线的负载进行补偿，使第一扫描线的负载量与第二扫描线的负载量相同。
在其中一个实施例中，所述显示面板还设有第一金属层，所述第一金属层为显示面板中晶体管的栅极金属层，所述引出线还与显示面板的第一金属层进行耦合，形成寄生电容，对第一扫描线进行负载补偿。
在其中一个实施例中，所述引出线位于第二信号线和显示面板的第一金属层之间。
一种显示装置，包括前述显示面板。
在其中一个实施例中，所述显示装置还包括传感器，所述传感器设置于所述开槽区中。
上述显示面板和显示装置通过采用宽度较宽第二信号线与第一扫描线的引出线进行耦合，形成寄生电容，对第一扫描线的负载进行补偿，使第一扫描线的负载与第二扫描线的负载相同。本申请中的第二信号线包括若干间隔设置的条形部，相较于传统的使用整面电源信号线，采用间隔设置的条形电源线，可减小第一信号线与第二信号线的线宽差异，进而减小连接于第一信号线和第二信号线上的像素单元的电压差异，使各像素单元的电压相同，像素电流也相同，提高了显示的均一性。
附图说明
图1为本申请的一个实施例提供的显示面板示意图；
图2为本申请的又一实施例提供的固定电位信号线示意图；
图3为现有技术中具有补偿单元的电源信号线示意图；
图4为现有技术中不具有补偿单元的电源信号线示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
需要说明的是，当元件被称为“设置于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施方式。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是在于限制本申请。
请参阅图1，本申请的一个实施例提供一种显示面板100，包括显示区110和围绕显示区110设置的非显示区120。显示区110包括第一显示区111和第二显示区112。第一显示区111包括阵列排布的像素单元101和连接每行像素单元的第一扫描线102。第二显示区112包括阵列排布的像素单元101和连接每行像素单元101的第二扫描线103。第一显示区111内每行像素单元101的数量小于第二显示区112内每行像素单元101的数量。
非显示区120设置有固定电位信号线104。固定电位信号线104包括第一信号线105和第二信号线106。其中，第二信号线106包括连接部(图1未示出)和连接于连接部的间隔设置的条形部(图1未示出)。第一信号线105与连接部沿第一方向延伸，条形部沿第二方向延伸，且第一方向与第二方向垂直。第一信号线105的沿第二方向的宽度小于第二信号线106沿同一方向的宽度。第一信号线105和第二信号线106为连续的一整条固定电位信号线，即第一信号线105以及第二信号线106可为相互电连接的两条信号线，也可为一条信号线的两个部分。
显示面板100还包括引出线107，引出线107与第一扫描线102一一对应连接，且引出线107延伸至非显示区120，并与第二信号线106在显示面板100上的投影重叠。固定电位 信号线104与引出线107异层设置，进一步，第二信号线106与引出线107异层设置，即第二信号线106与引出线107中间间隔有绝缘介质。引出线107与第二信号线106之间可产生寄生电容，用于对第一扫描线103进行负载补偿。
本实施例提供的显示面板通过利用固定电位信号线104与第一扫描线102的引出线107异层设置形成寄生电容，对第一扫描线102进行负载补偿，进而使得第一扫描线102与第二扫描线103的负载量相同。且固定电位信号线包括两种宽度的第一信号线105和第二信号线106，第二信号线106的总宽度大于第一信号线105的宽度，且第二信号线106包括多条间隔设置的条形部1062，每个条形部1062沿第一方向的线宽与第一信号线105沿第二方向的线宽差异较小，则条形部1062的线上电阻与第一信号线105的线上电阻差异较小，线上电阻损耗的电压差小，进而可减小连接于第一信号线105的像素单元与第二信号线106的像素单元的电压差异，提高显示亮度的均一性，并提高显示效果。
请参阅图2，作为其中一个实施例，固定电位信号线104包括第一信号线105和第二信号线106。其中，第二信号线106包括连接部1061和连接于连接部1061上且间隔设置的多个条形部1062。第一信号线105与连接部1061沿第一方向D1延伸，条形部1062沿第二方向D2延伸，且第一方向D1与第二方向D2垂直。每个条形部1062沿第一方向D1的宽度与第一信号线105沿第二方向D2的宽度相等。
具体地，在本实施例中，固定电位信号线104可以是电源信号线。电源信号线与引出线107耦合，形成寄生电容，对第一扫描线102的负载进行补偿，使第一扫描线102的负载量与第二扫描线103的负载量相同。引出线107一端连接第一扫描线102，另一端通过边框走线延伸至与第二信号线106重叠。
第二信号线106通过连接部1061与第一信号线105连接。第二信号线106还包括连接于连接部1061上间隔设置的条形部1062。引出线107延伸至与条形部1062重叠。由于引出线107与条形部1062异层设置，且中间间隔有绝缘介质，故引出线107与条形部1062重叠的部分可形成寄生电容，对引出线107进行负载补偿。
另外，引出线107同时还可与显示面板100的第一金属层(图1未示出)进行耦合，形成又一个寄生电容。其中，第一金属层为显示面板100中晶体管的栅极金属层。故引出线107可位于第二信号线106和显示面板100的第一金属层之间，并分别与第二信号线106和第一金属层耦合形成寄生电容对第一扫描线102进行负载补偿。
在本实施例中，条形部1062沿第一方向D1的宽度与第一信号线105沿第二方向D2的宽度相同，且连接部1061沿第二方向D2的宽度与第一信号线沿第二方向D2的宽度相同，连接部1061、条形部1062与第一信号线105属于同一电源信号线，由于电源信号线上各处 线宽相同，故电源信号线上各处的电阻近似。由于第一信号105连接第一显示区111内每列像素单元101，第二信号线106连接第二显示区112内每列像素单元101，并为像素单元101提供电源电压。因此，第一信号线105与第二信号线106线上电阻相同，消耗的电阻也相同。第一信号线105分配至第一显示区111内像素单元101的电源电压，与第二信号线106分配至第二显示区112内像素单元101的电源电压相同，第一显示区111内像素单元101的像素电流与第二显示区112内像素单元101的像素电流也相同，进而显示面板100各处的发光亮度相同，提高了显示效果。
当然，条形部1062的宽度也可以不等于第一信号线105的宽度。可根据需求，在满足需要的补偿电容的大小情况下，尽量降低条形部1062的宽度，使其接近第一信号线105的宽度，以缩小条形部与第一信号线的线宽差异，进而减小同一电源信号线上不同区域的线上电阻差异，缩小连接于不同宽度电源信号线的像素单元的电压差异，从而提高显示面板的亮度均一性。
本实施例中，电源信号线上不同宽度连接的像素单元分别为P1、P2、P3、P4，其中P1、P4连接第一信号线，P2、P3连接第二信号线。图3为不具有补偿单元的电源信号线300，在相同位置连接相同的像素单元P1、P2、P3、P4。图4为具有整面补偿单元的电源信号线400在相同位置连接相同的像素单元P1、P2、P3、P4，其中P1、P4连接不具有补偿单元的部分402，P2、P3连接具有补偿单元的部分401。
本实施例具有条形部1062的电源信号线与图3不具有补偿单元的电源信号线300相比，不同像素单元之间的电流变化，以及图4具有整面补偿单元的电源信号线400与图3不具有补偿单元的电源信号线300相比，不同像素单元之间的电流变化如下表所示：
  P1到P2 P3到P4
图3所示方案的电流下降值 0.36 0.92
图4所示方案的电流下降值 0.53 1.18
本实施例方案的电流下降值 0.41 1.07
第一电流差值变化率 47.2％ 28.2％
第二电流差值变化率 13.89％ 16.3％
其中，第一电流差值变化率为图4所示方案的电流下降值与图3所示方案的电流下降值之间的差值和图3所示方案的电流下降值之间的比例。第二电流差值变化率为本实施例方案的电流下降值与图3所示方案的电流下降值之间的差值和图3所示方案的电流下降值之间的比例。像素电流下降值越大，不同像素之间的发光亮度差异也越大。电流差值变化率代表不同线宽的电源信号线连接的像素单元之间像素电流的变化率，电流差值变化率越大，则像素 之间发光亮度差异越大，分屏现象越严重。
由表中数据可以看出，相较于不具有补偿单元的电源信号线300，图4所示方案中的电源信号线400，P1到P2的电流下降值和P3到P4的电流下降值，均大于图3所示方案中，P1到P2的电流下降值和P3到P4的电流下降值。图4所示具有整面补偿单元的电源信号线400虽然对第一显示区111内第一扫描线102进行了负载补偿，使第一扫描线102的负载与第二扫描线103的负载相同，弥补了扫描线的负载差异，但是由于电源信号线400上具有补偿单元的部分401与不具有补偿单元的部分402的线宽差异较大，导致电源信号线400上电阻差异较大。连接于具有补偿单元的部分401的电源信号线400的像素单元所得的电源电压，比连接不具有补偿单元的部分402的电源信号线400的像素单元所得的电源电压小，像素电流也小，仍会产生分屏现象。
本实施例提供的具有条形部1062的电源信号线可减小同一电源信号线上各区域的线宽差异，也即同一电源信号线上的线上电阻差异。由上表数据可以看出，本实施例提供的方案对应的第二电流差值变化率比图3所示方案对应的第一电流差值变化率小。即本案中，第二信号线106连接的像素单元与101与第一信号线105连接的像素单元101所得的电源电压差异相较于图4所示方案小，像素电流差值也小，进而改善了分屏现象。
作为其中一个实施例，第一显示区111内至少两行的像素单元101数量不同，不同行上的像素单元101对应的引出线107的长度也不同。
具体地，第一显示区111内至少两行像素单元101数量不同，则至少两行第一扫描线102的负载量不同。由于第二显示区112内每行像素单元101数量均相同，因此每行第二扫描线103的负载量相同。故不同行的第一扫描线102与第二扫描线103的负载量差异不同。
引出线107一端对应连接第一扫描线102，另一端延伸至非显示区120，并与第二信号线106重叠。引出线107与第二信号线106的条形部1062重叠的区域形成寄生电容。重叠区域的面积越大，寄生电容的容量越大，对第一扫描线102的负载量补偿的越多。由于不同行上第一扫描线102需要补偿的负载量不同，故不同的引出线107与第二信号线106重叠部分的长度不同，引出线107与条形部1062重叠区域的面积也不同。
在本实施例中，引出线107的延伸方向与条形部1062的延伸方向互相垂直，当引出线107与一个条形部1062交叉时产生重叠区域，重叠区域即可作为第一扫描线102上连接的一个补偿单元。多个条形部1062的排布方向与引出线107的延伸方向相同，当引出线107延伸地越长时，与引出线107重叠的条形部1062数量越多，引出线107上连接的补偿单元数量越多。
故当第一扫描线102连接的像素单元101越少，即负载越小，第一扫描线102与第二扫 描线103的负载差值便越大，则需要补偿的负载越多。故当第一扫描线102连接的像素单元101越少时，需要连接的补偿单元便越多，则该第一扫描线102对应的引出线107越长。即与第一扫描线102连接的补偿单元的数量，和第一扫描线102上的像素单元101的数量与第二扫描线103上的像素单元101的数量的差值成正比。也即与引出线107重叠的条形部1062的数量，和第一扫描线102上的像素单元101的数量与第二扫描线103上的像素单元101的数量的差值成正比。
本实施例通过将第二信号线106设计为间隔设置的条形部1062，可以根据每条第一扫描线102与第二扫描线103的像素单元101数量的差值，设置引出线107与不同数量的条形部1062重叠，以对第一扫描线102进行补偿，便于确定每条第一扫描线102需要补偿的负载量。
作为其中一个实施例，显示面板100设有开槽区130。开槽区130设置于非显示区120内，并且邻接第一显示区111。由于开槽区130的设置，导致第一显示区111内每行像素单元101的数量小于第二显示区112内每行像素单元101的数量。开槽区130可用于设置传感器等功能元件，为电子设备提供摄像等功能。
作为其中一个实施例，显示面板100包括具有显示区110的正面，开槽区130在显示面板正面的投影包括底边和分布于底边两侧的侧边，其中，第一信号线105沿侧边设置，第二信号线106沿底边设置。
具体的，在本实施例中，显示面板100为具有倒角的矩形屏体。显示面板100的非显示区120包括沿第一方向D1延伸的上边框和下边框，以及沿第二方向D2延伸的第一侧边框和第二侧边框，第一方向D1与第二方向D2垂直。开槽区130为上边框的侧边向显示区110内凹陷形成。固定电位信号线104设置于上边框。由于开槽区130向内凹陷，上边框包括邻接开槽区130的底边部分和侧边部分。第一信号线105沿侧边设置，设置于侧边部分的弧形边框，第二信号线106沿底边设置，设置于底边部分的直线边框。上边框还包括分别连接两个侧边部分的直线边框，且直线边框上设置第二信号线106。在本实施例中，第一信号线105与第二信号线106为连续的一整条电源信号线。
在本实施例中，由于弧形边框区域小，且引出线107设置于侧边的弧形边框，并从弧形边框部分走线并延伸至直线边框，故设置于弧形边框的第一信号线105宽度窄。直线边框的区域较大，故设置于直线边框的第二信号线106宽度较宽，可用于与引出线107耦合形成寄生电容，对第一扫描线102进行负载补偿，以使第一扫描线102与第二扫描线103的负载量相等，像素电流相同，发光亮度也相同。
本申请的又一实施例提供一种显示装置，包括封装壳和封装于所述封装壳内的显示面板。显示装置还包括传感器，设置于开槽区中。其中，传感器可以是摄像头、指纹识别元件、虹 膜识别元件、听筒中的任意一种。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种显示面板，包括显示区和围绕显示区设置的非显示区；
    所述显示区包括第一显示区和第二显示区，所述第一显示区包括阵列排布的像素单元和连接每行所述像素单元的第一扫描线；所述第二显示区包括阵列排布的像素单元；
    所述非显示区设置有固定电位信号线，所述固定电位信号线包括第一信号线和第二信号线，所述第二信号线与所述第一信号线连接，所述第二信号线包括连接部和连接于所述连接部的间隔设置的条形部，所述第二信号线的宽度大于所述第一信号线的宽度；并且
    所述显示面板还包括引出线，所述引出线对应连接所述第一扫描线，并延伸至所述非显示区与所述第二信号线重叠，所述第二信号线与所述引出线异层设置，所述第二信号线与所述引出线之间用于产生寄生电容以补偿所述第一扫描线的负载。
  2. 根据权利要求1所述的显示面板，其中，所述第一显示区内每行像素单元的数量小于所述第二显示区内每行像素单元的数量。
  3. 根据权利要求1所述的显示面板，其中，所述条形部的宽度与所述第一信号线的宽度相同。
  4. 根据权利要求1所述的显示面板，其中，所述第一显示区内至少两行上的像素单元的数量不同，所述不同行上像素单元对应的引出线长度不同。
  5. 根据权利要求4所述的显示面板，其中，所述引出线的长度随引出线所对应行的像素单元数量的减少而增加。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板包括开槽区，所述开槽区设置于所述非显示区，并邻接所述第一显示区，以使所述第一显示区内每行像素单元的数量小于所述第二显示区内每行像素单元的数量。
  7. 根据权利要求6所述的显示面板，其中，所述显示面板包括具有显示区的正面，所述开槽区在所述正面的投影包括底边和分布于底边两侧的侧边，所述第一信号线沿所述侧边设置，所述第二信号线沿所述底边设置。
  8. 根据权利要求7所述的显示面板，其中，所述引出线沿所述侧边设置，并从所述侧边延伸至所述底边。
  9. 根据权利要求1所述的显示面板，其中，所述固定电位信号线包括电源信号线。
  10. 根据权利要求9所述的显示面板，其中，所述第二显示区包括连接每行像素单元的第二扫描线，并且，所述第二信号线的与引出线重叠的条形部的数量，和第一扫描线上的像素单元的数量与第二扫描线上的像素单元的数量的差值成正比。
  11. 根据权利要求10所述的显示面板，其中，所述电源信号线与引出线耦合，形成寄生 电容，对第一扫描线的负载进行补偿，使第一扫描线的负载量与第二扫描线的负载量相同。
  12. 根据权利要求11所述的显示面板，其中，所述显示面板还设有第一金属层，所述第一金属层为显示面板中晶体管的栅极金属层，所述引出线还与显示面板的第一金属层进行耦合，形成寄生电容，对第一扫描线进行负载补偿。
  13. 根据权利要求12所述的显示面板，其中所述引出线位于第二信号线和显示面板的第一金属层之间。
  14. 一种显示装置，包括权利要求1所述的显示面板。
  15. 根据权利要求14所述的显示装置，其特征在于，所述显示装置还包括传感器，所述传感器设置于所述开槽区中。
PCT/CN2018/111717 2018-05-14 2018-10-24 显示面板和显示装置 Ceased WO2019218596A1 (zh)

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