WO2019214547A1 - 像素电路及其驱动方法、显示基板、显示装置 - Google Patents

像素电路及其驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2019214547A1
WO2019214547A1 PCT/CN2019/085540 CN2019085540W WO2019214547A1 WO 2019214547 A1 WO2019214547 A1 WO 2019214547A1 CN 2019085540 W CN2019085540 W CN 2019085540W WO 2019214547 A1 WO2019214547 A1 WO 2019214547A1
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Prior art keywords
circuit
driving
node
signal
pixel circuit
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PCT/CN2019/085540
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English (en)
French (fr)
Inventor
岳晗
陈小川
玄明花
张粲
王灿
杨明
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京东方科技集团股份有限公司
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Priority to US16/611,387 priority Critical patent/US11200835B2/en
Publication of WO2019214547A1 publication Critical patent/WO2019214547A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • MicroLED is a light-emitting device using an inorganic material as a light-emitting material.
  • a display device using a MicroLED as a light-emitting device has advantages of high brightness, fast response, and high stability.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a driving circuit and a compensation circuit; the driving circuit is respectively connected to a gate line, a data line, a first power terminal, a control node, and a first driving node, wherein the driving circuit Configuring to write a data signal of the data line to the control node in response to a gate drive signal of the gate line, and to drive the first drive node under control of a voltage signal of the control node
  • the first power terminal is connected to receive a first power signal, and the first driving node is connected to one pole of the light emitting component;
  • the compensation circuit is respectively connected to the second power terminal, the third power terminal, the control node, and the second a driving node and an output terminal, the compensation circuit configured to, in response to the voltage signal of the control node and the signal of the second driving node, the first driving node and the second one of the another pixel circuit
  • the power terminal is connected to receive a second power signal, and the second driver node is coupled
  • the output terminal is connected to another light-emitting element included in a current driving circuit where the first driving node or the output terminal of the other pixel circuit is located.
  • the compensation circuit includes a compensation sub-circuit and a switch sub-circuit; the compensation sub-circuit is respectively connected to the second power terminal, the control node, and the switch a sub-circuit connection, the compensating sub-circuit is configured to input the second power signal to the switch sub-circuit in response to a voltage signal of the control node; the switch sub-circuit and the third power end, respectively Connecting the second driving node and the output end, the switch sub-circuit is configured to connect the compensation sub-circuit to the output end under the control of the level of the second driving node, to The output terminal inputs the second power signal.
  • the compensation sub-circuit includes: a first transistor; a gate of the first transistor is connected to the control node, and a first pole of the first transistor And connecting to the second power terminal to receive the second power signal, and the second pole of the first transistor is connected to the switch sub-circuit.
  • the switch sub-circuit includes: a second transistor; a gate of the second transistor is connected to the second driving node, and a second transistor A pole is coupled to the second pole of the first transistor, and a second pole of the second transistor is coupled to the output.
  • the switch sub-circuit further includes a resistor; one end of the resistor is connected to the second driving node, and the other end of the resistor and the third power source The terminal is connected to receive the third power signal.
  • the driving circuit includes: a driving sub circuit, a data writing sub circuit, and a storage sub circuit; the driving sub circuit includes a control end, a first end, and a second And configured to control a driving current for driving the light emitting element to emit light in response to a voltage signal of the control node, the first end of the driving subcircuit being configured to receive the first power signal from the first power terminal; a data write subcircuit coupled to the memory circuit, the gate line, the data line, and the control node, and configured to responsive to a gate drive signal of the gate line to a data signal of the data line Writing to the control node and the storage sub-circuit; the storage sub-circuit is coupled to the control node and the first power supply terminal, and configured to store the data written by the data write sub-circuit signal.
  • the data writing sub-circuit includes a switching transistor; a gate of the switching transistor is connected to the gate line to receive the gate driving signal, A first pole of the switching transistor is coupled to the data line to receive the data signal, and a second pole of the switching transistor is coupled to the control node.
  • the driving sub-circuit includes a driving transistor, a gate of the driving transistor is connected to the control node, and a first pole of the driving transistor and the first A power terminal is connected to receive the first power signal, and a second pole of the driving transistor is connected to the first driving node.
  • the memory subcircuit includes a capacitor, one end of the capacitor is connected to the first power terminal to receive the first power signal, and the capacitor is another One end is connected to the control node.
  • the first power terminal and the second power terminal are the same power terminal or different power terminals.
  • At least one embodiment of the present disclosure further provides a driving method of a pixel circuit for driving a pixel circuit according to any embodiment of the present disclosure.
  • the driving method includes: the gate line provides a gate driving signal of a first potential, The data line provides the data signal, and the driving circuit inputs the first power signal from the first power terminal to the first driving node in response to the gate driving signal and the data signal;
  • the first driving node is connected to the second driving node, and the compensation circuit is turned off under the control of the level of the second driving node; when the light emitting element is not
  • the first driving node is disconnected from the second driving node, and the third power terminal inputs a third power signal to the second driving node, and the compensation circuit is at the second driving node. Under the control of the level, a second power signal from the second power terminal is input to the output terminal.
  • the potential of the first power signal and the potential of the second power signal are both a second potential
  • the potential of the third power signal is The first potential
  • the compensation circuit includes a compensation sub-circuit and a switch sub-circuit, and when the light-emitting element is not working normally, the compensation sub-circuit is responsive to the Controlling a voltage signal of the node, the switch sub-circuit is turned on under the control of the level of the second driving node, so that the second power terminal is connected to the output terminal to receive the second power source The second power signal at the end.
  • the driving circuit includes: a driving sub circuit, a data writing sub circuit, and a storage sub circuit, and the driving method further includes a data writing phase and a light emitting Phase: in the data writing phase, inputting the gate driving signal and the data signal, turning on the data writing sub-circuit, the data writing sub-circuit writing the data signal to the control node and the The memory circuit is turned on, and the driving sub-circuit is turned on under the control of the voltage signal of the control node, and a driving current is applied to the first driving node.
  • At least one embodiment of the present disclosure also provides a display substrate including a plurality of pixel units arranged in an array, wherein each of the pixel units includes a pixel circuit and a light emitting element provided by at least one embodiment of the present disclosure; each of the pixels The output of the circuit is each coupled to a first drive node of another pixel circuit or to another illumination element of the current pixel circuit.
  • another pixel circuit connected to an output end of each of the pixel circuits is located in the same row or in the same column as the pixel circuit; each of the pixel circuits The other pixel circuit connected to the output terminal is closest to the pixel circuit, and the pixel units to which the two belong are the same color.
  • the light emitting element is a miniature light emitting diode.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate provided by any embodiment of the present disclosure.
  • 1A is a schematic diagram of a 2T1C pixel circuit
  • FIG. 1B is a schematic diagram of another 2T1C pixel circuit
  • FIG. 2A is a schematic block diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 2B is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 2C is a schematic block diagram of the driving circuit shown in FIG. 2A or 2B;
  • FIG. 3 is a circuit diagram showing a specific implementation example of the pixel circuit shown in FIG. 2B;
  • FIG. 4 is a circuit diagram showing another specific implementation example of the pixel circuit shown in FIG. 2B;
  • FIG. 5 is a flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 6 is a schematic block diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic block diagram of another display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic block diagram of a display device according to at least one embodiment of the present disclosure.
  • an array-arranged thin film transistor (for example, the switching transistor T0 and the driving transistor N0 shown in FIG. 1A or FIG. 1B) is first formed on the circuit substrate, that is, a backplane is fabricated; And forming a plurality of microLEDs arranged in an array on another substrate.
  • the material of the substrate may be inorganic materials such as single crystal silicon or gallium arsenide; and finally, a plurality of micro LEDs formed on the substrate are bulk-transferred to be formed.
  • a pixel circuit structure such as that shown in FIG. 1A or FIG. 1B can be formed.
  • the size of the MicroLED (eg, the long side of a rectangle or the side length of a square) is less than 100 microns, for example, less than 50 microns.
  • 1A and 1B are schematic views showing two 2T1C pixel circuits, respectively.
  • a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs.
  • the gate of the switching transistor T0 is connected to the scan line to receive the gate driving signal Scan1, for example, the source is connected to the data line to receive the data signal Vdata, the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 Connected to the first voltage terminal to receive the first voltage Vdd (high voltage), the drain is connected to the positive terminal of the MicroLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected The source of the driving transistor N0 and the first voltage terminal are received to receive the first voltage Vdd; the negative terminal of the MicroLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the gate driving signal Scan1 is applied through the scan line to turn on the switching transistor T0
  • the data signal Vdata fed by the data driving circuit through the data line charges the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor.
  • the stored data signal Vdata controls the degree of conduction of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor to drive the micro LED to emit light, that is, the current determines the gray scale of the pixel illumination.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but the connection mode thereof is slightly changed, and the driving transistor N0 is an N-type transistor.
  • the variation of the pixel circuit of FIG. 1B with respect to FIG. 1A includes that the positive terminal of the MicroLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the drain of the driving transistor N0, the driving transistor The source of N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the operation mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and details are not described herein again.
  • a compensation circuit (eg, may be implemented as a compensation transistor, not shown) to compensate for the threshold voltage or power line of the driving transistor N0 (eg, providing The voltage drop of a voltage Vdd).
  • the compensation circuit includes a first end, a second end, and a control end, respectively, with a gate of the driving transistor N0, a drain of the driving transistor N0, and a compensation signal line (not shown in the drawing, for example, may be a scan line) )connection.
  • the compensation circuit is electrically connected in response to the compensation signal provided by the compensation signal line, and the gate and the drain of the driving transistor N0 can be electrically connected, so that the information about the threshold voltage of the driving transistor N0 can be stored in the corresponding state.
  • the threshold voltage of the driving transistor N0 is compensated so that the driving current flowing through the MicroLED is only related to the data signal and the like in the light-emitting phase, and is no longer related to the threshold voltage of the driving transistor N0, thereby achieving
  • the compensation of the pixel circuit solves the problem that the threshold voltage drift of the driving transistor N0 due to the process process and long-time operation, etc., and the display unevenness caused by the influence of the threshold voltage on the driving current is eliminated, and in some examples, The driving current flowing through the MicroLED is no longer related to the first voltage Vdd, thereby solving the problem of display unevenness of the display panel caused by the deviation of the first voltage Vdd caused by the voltage drop of the power line.
  • the compensation circuit not shown in FIG. 2B works in a similar manner to FIG. 2A, and details are not described herein again.
  • the switching transistor T0 is not limited to the N-type transistor, and may be a P-type transistor as needed, thereby controlling the polarity of the gate driving signal Scan1 that is turned on or off. Change accordingly.
  • the pixel circuit shown in FIG. 1A or FIG. 1B does not have a MicroLED, thereby affecting the display effect of the display device and reducing the display quality of the display device.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a driving circuit and a compensation circuit.
  • the driving circuit is respectively connected to the gate line, the data line, the first power terminal, the control node, and the first driving node, and the driving circuit is configured to write the data signal of the data line to the control node in response to the gate driving signal of the gate line, and Controlling, by the control of the voltage signal of the control node, the first driving node and the first power terminal to receive the first power signal, the first driving node is connected to one pole of the light emitting component;
  • the compensation circuit is respectively connected to the second power terminal and the third
  • the power terminal, the control node, the second driving node, and the output terminal are connected, and the compensation circuit is configured to connect the output terminal to the second power terminal to receive the second power signal in response to the voltage signal of the control node and the signal of the second driving node.
  • the second drive node is coupled to the other pole of the light emitting element.
  • At least one embodiment of the present disclosure also provides a driving method, a display substrate, and a display device corresponding to the above pixel circuit.
  • the pixel circuit provided in the above embodiment of the present disclosure may input a second power signal to the output terminal when the light-emitting element connected to the pixel circuit fails to emit light normally, thereby enhancing the light-emitting element connected to the other pixel circuit.
  • the illuminating brightness or driving the substitute illuminating element emits light, which ensures the display effect of the display device and improves the display quality of the display device.
  • the transistors employed in all of the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • the transistors employed in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first pole and the drain is referred to as a second pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure may be any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the level of the gate is low, at the gate When the level is high, the N-type switching transistor is turned on when the level of the gate is high, and is turned off when the level of the gate is low.
  • the plurality of signals in the various embodiments of the present disclosure correspond to the first potential and the second potential, and the first potential and the second potential only represent two different state quantities of the potential of the signal, which does not represent the first in the text.
  • the potential or the second potential has a specific value.
  • the first potential is a low level and the second potential is a high level. It should be noted that the level of the first potential and the second potential are set according to actual conditions, and the embodiment of the present disclosure does not limit this.
  • FIG. 2A is a schematic block diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit 1 is used to, for example, drive a light-emitting element in a sub-pixel of a display panel to emit light.
  • the display panel is prepared by, for example, a glass substrate, and the specific structure and the preparation process may adopt a method in the art, which is not described in detail herein, and the embodiments of the present disclosure are not limited thereto.
  • the light emitting element may be a MicroLED, or may be an OLED (Organic Light Emitting Diode) or a QLED (Quantum Dot Light Emitting Diodes), and the corresponding display panel is a Micro LED display panel, or an OLED display. Panel or QLED display panel, etc.
  • OLED Organic Light Emitting Diode
  • QLED Quadantum Dot Light Emitting Diodes
  • the corresponding display panel is a Micro LED display panel, or an OLED display.
  • the following description is made by taking a light-emitting element or a micro LED display panel as an example, and the embodiment of the present disclosure does not limit this.
  • the pixel circuit 1 may include a driving circuit 10 and a compensation circuit 20, which may include a driving transistor (not shown in FIG. 2A).
  • the driving circuit 10 can be connected to the gate line G, the data line D, the first power terminal VDD, the control node N, and the first driving node P1, respectively.
  • the driving circuit 10 is configured to write the data signal of the data line D to the control node N in response to the gate driving signal of the gate line G, and to drive the first driving node P1 and the first under the control of the voltage signal of the control node
  • a power terminal VDD is connected to receive the first power signal.
  • the first driving node P1 is connected to one pole of the light-emitting element L.
  • the first driving node P1 may be connected to the anode of the light emitting element L.
  • the drive circuit 10 may include a drive sub-circuit 11, a data write sub-circuit 12, and a storage sub-circuit 13.
  • the drive circuit 10 is used, for example, to control a drive current that drives the light-emitting element L to emit light.
  • the driving sub-circuit 11 includes a control terminal 130 (for example, the gate of the driving transistor M0 shown in FIG. 3), a first terminal 110 (for example, the first electrode of the driving transistor M0 shown in FIG. 3) and The second terminal 120 (for example, the second pole of the driving transistor M0 shown in FIG. 3) is configured to control a driving current for driving the light emitting element L to emit light in response to a voltage signal of the control node N, and drive the first end of the sub-circuit 11 110 is configured to receive a first power signal from the first power terminal VDD.
  • a control terminal 130 for example, the gate of the driving transistor M0 shown in FIG. 3
  • the second terminal 120 for example, the second pole of the driving transistor M0 shown in FIG. 3
  • the second terminal 120 is configured to control a driving current for driving the light emitting element L to emit light in response to a voltage signal of the control node N
  • drive the first end of the sub-circuit 11 110 is configured to receive a first power signal from the first power terminal
  • the data writing sub-circuit 12 is connected to the memory circuit 13, the gate line G, the data line D, and the control node N, and is configured to write the data signal of the data line D to the control node N in response to the gate driving signal of the gate line G. And storage sub-circuit 13.
  • the data writing sub-circuit 12 can be turned on in response to the gate driving signal, so that the data signal can be written to the control terminal 130 of the driving sub-circuit 11 (ie, the control node N and the storage circuit 13), The data signal can then be stored in a storage sub-circuit 13 which will be used to control the degree of opening of the drive sub-circuit 11 to control the generation of a drive current that drives the illumination of the illumination device.
  • the storage sub-circuit 13 is connected to the control node N and the first power supply terminal VDD of the drive sub-circuit 11, and is configured to store the data signal written by the data write sub-circuit 12.
  • the data sub-circuit 12 is turned on, and the data signal is written.
  • the node N and the storage circuit 13 are controlled.
  • the driving sub-circuit 11 is turned on under the control of the control node N, and may input a first power signal from the first power terminal VDD to the first driving node P1, and the potential of the first power signal may be a second potential, and the The second potential can be an inactive potential.
  • the second potential is higher than the first potential.
  • the compensation circuit 20 can be respectively connected to the second power terminal VDD', the third power terminal VSS, the control node N (for example, the gate of the driving transistor (not shown in FIG. 2A)), and the second driving node P2. And the output terminal OUT is connected, the compensation circuit 20 can be configured to connect the output terminal OUT with the second power terminal VDD' to receive the second power signal in response to the voltage signal of the control node N and the signal of the second driving node P2.
  • the second drive node P2 is connected to the other pole of the light-emitting element L.
  • the second drive node P2 can be connected to the cathode of the light-emitting element L.
  • the output terminal OUT can be connected to a first driving node (not shown) in another pixel circuit or another lighting element (not shown) of the current pixel circuit.
  • the other light-emitting element (not shown) belongs to the current pixel circuit and is connected to the compensation circuit 20.
  • the other light-emitting element serves as a substitute light-emitting element, and when the light-emitting element L fails or the transfer fails, the light-emitting element L can be used instead of the light-emitting element L to emit light.
  • the following is an example of the output terminal OUT and the first driving node in another pixel circuit.
  • the circuit connection and driving method are also applicable to the case where the output terminal OUT is connected to another light emitting element of the current pixel circuit. The embodiments of the present disclosure will not be described again.
  • the first power terminal VDD and the second power terminal VDD' may be different power terminals, or may be the same power terminal (as shown in FIG. 4), which is not limited by the embodiment of the present disclosure.
  • the light-emitting element L in the pixel circuit 1 may be a micro-LED light-emitting device, or may be a light-emitting device such as an LED or an OLED.
  • the malfunction of the light-emitting element L causes the first drive node P1 and the second drive node P2 of the pixel circuit 1 to be turned off. Then, when the pixel circuit 1 is in the light emitting phase, the potential of the signal of the gate of the driving transistor is the first potential, the driving transistor is turned on, and the first power signal is input to the first driving node P1. Since the first driving node P1 is disconnected from the second driving node P2, the third power terminal VSS can input a third power signal to the second driving node P2.
  • the compensation circuit 20 is turned on under the control of the third power signal, and the second power signal can be input to the first driving node P1 in the other pixel circuit, so that when the light-emitting element L to which the pixel circuit 1 is connected cannot normally emit light,
  • the second power signal may be input to the first driving node P1 of the other pixel circuit, thereby enhancing the light emitting luminance of the light emitting element connected to the other pixel circuit to compensate the light emitting brightness of the malfunctioning light emitting element L, thereby ensuring the display device Or the display of the second power signal to the other of the current pixel circuits connected to the output terminal OUT when the light-emitting element L to which the pixel circuit 1 is connected is not normally illuminated, thereby replacing the The normally illuminated light-emitting element emits light, which improves the display quality of the display device.
  • the pixel circuit provided by the embodiment of the present disclosure includes a compensation circuit that can be turned on under the control of the voltage signal of the control node N and the level of the second driving node to the other pixel circuit.
  • a driving node P1 inputs a second power signal from the second power terminal VDD', so that the first driving node of the other pixel circuit can be turned on in the case where the light-emitting element L to which the pixel circuit 1 is connected fails to emit light normally.
  • P1 inputs a second power signal to enhance the brightness of the light-emitting elements connected to the other pixel circuit, thereby ensuring the display effect of the display device and improving the display quality of the display device.
  • another pixel circuit connected to the compensation circuit of the pixel circuit may be in the same row or the same column as the pixel circuit, and another pixel connected to the compensation circuit of the pixel circuit
  • the circuit can be closest to the pixel circuit and the pixel units to which they belong are the same color.
  • FIG. 2B is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure.
  • the compensation circuit 20 can include a compensation sub-circuit 201 and a switch sub-circuit 202.
  • the compensation sub-circuit 201 can be respectively connected to the second power terminal VDD', the control node N (the gate of the driving transistor (not shown in FIG. 2B)), and the switch sub-circuit 202, and the compensation sub-circuit 201 can A second power signal is input to the switch sub-circuit 202 in response to the voltage signal of the control node N.
  • the potential of the signal of the gate of the driving transistor is the first potential
  • the compensating sub-circuit 201 is turned on in response to the first potential, so that the switching sub-circuit 202 and the second voltage terminal VDD 'Connected to input a second power signal to the switch sub-circuit 202.
  • the potential of the second power signal can be a second potential.
  • the switch sub-circuit 202 can be respectively connected to the third power supply terminal VSS, the second drive node P2, and the first drive node P1 (ie, the output terminal OUT) of another pixel circuit, and the switch sub-circuit 202 is configured to respond to The signal of the second driving node P2 connects the compensation sub-circuit 201 with the first driving node P1 of the other pixel circuit to input the second power signal to the first driving node P1 of the other pixel circuit.
  • the third power terminal VSS may input a third power signal to the second driving node P2, the switch The sub-circuit 202 is connected to the first driving node P1 of another pixel circuit in response to the signal of the second driving node P2 being turned on to input the second power signal to the first driving node P1 of the other pixel circuit.
  • the potential of the third power signal may be a first potential, and the first potential may be an effective potential.
  • the first driving node P1, the second driving node P2, and the control node N do not represent actual components, but represent the convergence points of related circuit connections in the circuit diagram, so that For description.
  • FIG. 3 is a schematic diagram of a specific implementation example of the pixel circuit shown in FIG. 2B.
  • the pixel circuit 1 includes a driving transistor M0 and first to third transistors M1, M2, M3 and includes a capacitor C, a resistor R, and a light emitting element L (for example, a MicroLED).
  • the first to third transistors M1, M2, M3 are used as switching transistors.
  • the light-emitting elements may be of various types, such as top emission, bottom emission, etc., and may emit red, green, blue, or white light, etc., which is not limited by the embodiments of the present disclosure.
  • each of the switching transistors may employ a P-type transistor
  • the driving transistor M0 may employ a P-type transistor.
  • the P-type transistor is turned on in response to the low-level signal, and is turned off in response to the high-level signal.
  • the compensation sub-circuit 201 may include a first transistor M1.
  • the gate of the first transistor M1 may be connected to the gate of the driving transistor M0 (ie, the control node N), and the first electrode of the first transistor M1 may be connected to the second power terminal VDD' to receive the second The power supply signal, the second pole of the first transistor M1 may be connected to the first pole of the second transistor M2.
  • the switch sub-circuit 202 can include a second transistor M2.
  • the gate of the second transistor M2 may be connected to the second driving node P2, and the second pole of the second transistor M2 may be coupled to the first driving node P1 of the other pixel circuit (ie, the output terminal OUT shown in FIG. 2A). connection.
  • the switch subcircuit 202 can also include a resistor R. One end of the resistor R may be connected to the second driving node P2, and the other end of the resistor R may be connected to the third power terminal VSS to receive the third power signal.
  • the resistor R can divide the third power signal provided by the third power terminal VSS, that is, the voltage on the second driving node P2 is smaller than the voltage of the third power signal, so that When the light-emitting element L connected to the pixel circuit 1 can normally emit light, the first driving node P1 can input the first power signal to the second driving node P2 through the light-emitting element L, and the second transistor M2 can be The second driving node P2 is kept turned off under the control of the second driving node P2, so that the compensation circuit 20 in the pixel circuit 1 inputs the second power signal to the first driving node P1 of the other pixel circuit when the light emitting element L is normally illuminated.
  • the problem that the brightness of the light emitted from the different pixel circuits connected to the light-emitting elements is different in the display device further ensures the display effect of the display device.
  • the driving circuit 10 may include a switching transistor M3, a driving transistor M0, and a capacitor C.
  • the data writing sub-circuit 12 includes a switching transistor M3.
  • the gate of the switching transistor M3 can be connected to the gate line G to receive the gate driving signal.
  • the first pole of the switching transistor M3 can be connected to the data line D to receive the data signal.
  • the second pole of the switching transistor M3 can be controlled.
  • the node N ie, the gate of the driving transistor M0 is connected.
  • the driving sub-circuit 11 includes a driving transistor M0.
  • the first pole of the driving transistor M0 can be connected to the first power terminal VDD to receive the first power signal, and the second pole of the driving transistor M0 can be connected to the first driving node P1.
  • the storage subcircuit 13 includes a capacitor C.
  • One end of the capacitor C may be connected to the first power terminal VDD (ie, the first pole of the driving transistor M0) to receive the first power signal, and the other end of the capacitor C may be connected to the control node N (ie, the gate of the driving transistor M0). Extremely connected.
  • the driving circuit 10 of the above 2T1C structure is merely an example, and the driving circuit may of course be any other circuit capable of driving the light emitting element to emit light, such as 4T2C, 5T1C, 7T1C, etc., and the embodiment of the present disclosure does not limit.
  • the first power terminal VDD and the second power terminal VDD' may be the same power terminal VDD.
  • the wiring space occupied by the pixel circuit can be reduced, and the wiring cost can be reduced.
  • the gate of the first transistor M1 is connected to the gate of the driving transistor M0, when the switching transistor M3 is turned on, the data line D can simultaneously provide the gate of the driving transistor M0 and the gate of the first transistor M1. Data signal.
  • the first power terminal VDD and the second power terminal VDD' are disposed at the same power terminal, so that the voltage applied to the first electrode of the driving transistor M0 is equal to the voltage applied to the first electrode of the first transistor M1, so When the light-emitting element L connected to the pixel circuit is unable to emit light normally, the size of the compensation current supplied by the first transistor M1 to the light-emitting element connected to the other pixel circuit and the driving transistor are driven by the data signal supplied from the data line D.
  • the driving currents of the M0 output are equal in magnitude.
  • the light-emitting luminance of the light-emitting elements connected to the other pixel circuit can accurately compensate the brightness loss caused by the light-emitting elements connected to the current pixel circuit that cannot be normally illuminated, thereby realizing the display.
  • the accurate compensation of the display brightness of the device ensures the display effect of the display device more effectively.
  • the driving circuit may also include a larger number of transistors.
  • Other configurations of the present disclosure are not limited thereto.
  • the first transistor, the second transistor, the switching transistor, and the driving transistor are P-type transistors, and the first potential is lower than the second potential.
  • the first transistor, the second transistor, the switching transistor, and the driving transistor may further adopt an N-type transistor.
  • the first potential is opposite to The second potential is high, and the embodiment of the present disclosure does not limit this.
  • the pixel circuit provided by the embodiment of the present disclosure includes a compensation circuit that can control the first driving node in another pixel circuit under the control of the voltage signal of the control node and the level of the second driving node.
  • a compensation circuit that can control the first driving node in another pixel circuit under the control of the voltage signal of the control node and the level of the second driving node.
  • FIG. 5 is a flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure. As shown in FIG. 5, the method may be used to drive a pixel circuit as described in any one of FIG. 2A to FIG. Can include:
  • Step S501 the gate line provides a gate driving signal of a first potential, the data line provides a data signal, and the driving circuit inputs the first power signal from the first power terminal to the first driving node in response to the gate driving signal and the data signal;
  • the first driving node is turned on with the second driving node, and the compensation circuit is turned off under the control of the second driving node.
  • the first driving node P1 and the second driving node P2 may pass through the light-emitting element L. connection.
  • the first driving node P1 can input the first power signal to the second driving node P2 through the light emitting element L, and the compensation circuit 20 can be turned off under the control of the second driving node P2, thereby ensuring the pixel.
  • Step S502 when the light-emitting element is not working normally, the first driving node is disconnected from the second driving node, and the third power terminal inputs a third power signal to the second driving node, and the compensation circuit is at the level of the second driving node. Under control, a second power signal from the second power terminal is input to the output terminal.
  • the potential of the first power signal and the potential of the second power signal may both be the second potential, and the potential of the third power signal may be the first potential.
  • the first driving node P1 and the second driving node P2 of the pixel circuit 1 are disconnected due to the failure of the light-emitting element L (the first power terminal VDD)
  • the circuit is disconnected from the third power terminal VSS (as shown in FIG.
  • the first driving node P1 cannot input the first power signal to the second driving node P2 through the light emitting element L, and the third power terminal VSS
  • the third power signal may be input to the second driving node P2, and the compensation circuit 20 may be under the control of the level of the second driving node P2 to the first driving node P1 in the other pixel circuit (ie, the output end)
  • the second power signal from the second power terminal VDD' is input.
  • the compensation circuit 20 includes the compensation sub-circuit 201 and the switch sub-circuit 202
  • the compensation sub-circuit 201 when the light-emitting element L is not operating normally, the compensation sub-circuit 201 is turned on in response to the voltage signal of the control node N, and the switch sub-circuit 202 is
  • the second driving node P2 is turned on under the control of the level of the second driving node P2, so that the second power supply terminal VSS is connected to the first driving node P1 in the other pixel circuit to receive the second power supply signal of the second power supply terminal VDD'.
  • the drive circuit 10 includes a drive sub-circuit 11, a data write sub-circuit 12, and a storage sub-circuit 13, and the drive method further includes a data writing phase and an illumination phase.
  • the gate drive signal and the data signal are input, the data write sub-circuit 12 is turned on, and the data write sub-circuit 12 writes the data signal to the control node N and the memory circuit 13.
  • the driving sub-circuit 11 is turned on under the control of the voltage signal of the control node N, and the driving current is applied to the first driving node P1.
  • the driving circuit 10 can input the first power signal to the first driving node P1 in response to the gate driving signal and the data signal.
  • the third power terminal VSS may input a third power signal to the second driving node, and the compensation circuit may be in another pixel circuit under the control of the level of the second driving node P2 and the data signal.
  • the first driving node P1 inputs a second power signal, so that when the light-emitting element connected to the pixel circuit fails to emit light normally, the second power signal is input to the first driving node P1 of the other pixel circuit to enhance the
  • the light-emitting luminance of the light-emitting element L connected to the other pixel circuit ensures the display effect of the display device and improves the display quality of the display device.
  • the driving principle of the pixel circuit provided by the embodiment of the present disclosure is described in detail by taking the pixel circuit 1 shown in FIG. 3 as an example and taking each transistor in the pixel circuit 1 as a P-type transistor as an example.
  • the switching transistor M3 when the gate line G provides the gate driving signal of the first potential, the switching transistor M3 is turned on, and the data line D inputs the data signal to the gate of the driving transistor M0 through the switching transistor M3.
  • the driving transistor M0 and the first transistor M1 are turned on.
  • the driving transistor M0 can input a first power signal from the first power terminal VDD to the first driving node P1 under the control of the data signal.
  • the data signal can determine the magnitude of the driving current output by the driving transistor M0, that is, the data signal can determine the luminance (ie, gray scale) of the light emitting element L connected to the pixel circuit; the first transistor M1 can be Under the control of the data signal, a second power signal from the second power terminal VDD' is input to the second transistor M2. Therefore, the data signal can control the light-emitting luminance of the light-emitting elements in the other pixel circuit through the first transistor M1 and the second transistor M2.
  • the first drive node P1 and the second drive node P2 are connected.
  • the pixel circuit 1 can input the first power signal of the first driving node P1 to the second driving node P2 through the light emitting element L, and the second transistor M2 can be turned off under the control of the second driving node P2.
  • the first driving node P1 and the second driving node P2 are disconnected, that is, the first power terminal VDD and the third power terminal VSS.
  • the third power supply terminal VSS can input a third power signal to the second driving node P2, and the second transistor M2 can be turned on under the control of the second driving node P2.
  • the second power terminal VDD' can input the second power signal to the first driving node P1 of the other pixel circuit through the second transistor M2, thereby enhancing the brightness of the light emitting element connected to the other pixel circuit to compensate
  • the light-emitting luminance of the malfunctioning light-emitting element ensures the display effect of the display device.
  • the first transistor, the second transistor, the switching transistor, and the driving transistor are P-type transistors, and the first potential is lower than the second potential.
  • the first transistor, the second transistor, the switching transistor, and the driving transistor may further adopt an N-type transistor.
  • the first potential is opposite to The second potential is high.
  • the driving circuit 10 can input the first power signal to the first driving node P1 in response to the gate driving signal and the data signal.
  • the third power terminal VDD may input a third power signal to the second driving node
  • the compensation circuit 20 may be under the control of the level of the second driving node P2 and the data signal to another pixel.
  • the first driving node P1 in the circuit inputs the second power signal, so that when the light-emitting element L connected to the pixel circuit 1 fails to emit light normally, the second power signal is input to the first driving node P1 of the other pixel circuit.
  • the display effect of the display device is ensured, and the display quality of the display device is improved.
  • FIG. 6 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of another display substrate according to at least one embodiment of the present disclosure.
  • the display substrate 310 may include a plurality of pixel units arranged in an array, and each of the pixel units may include the pixel circuit 1 as shown in FIG. 3 or 4.
  • Figure 6 shows a total of three pixel units.
  • the compensation circuit 20 of the pixel circuit 1 in each pixel unit may be connected to the first driving node P1 of another pixel circuit 1.
  • another pixel circuit 1 to which the compensation circuit 20 of each pixel circuit 1 is connected may be in the same column or the same row as the pixel circuit 1.
  • the other pixel circuit 1 to which the compensation circuit 20 of each pixel circuit 1 is connected may be closest to the pixel circuit 1, and the color of the pixel unit to which the two belong is the same.
  • another pixel circuit 1 connected to the compensation circuit 20 of each pixel circuit 1 may be located in the same row as the pixel circuit 1. Moreover, the other pixel circuit 1 to which the compensation circuit 20 of each pixel circuit 1 is connected may be closest to the pixel circuit 1, and the color of the pixel unit to which the two belong is the same.
  • each pixel unit may refer to one sub-pixel (also referred to as a sub-pixel), and a plurality of pixels may be arrayed on the display substrate, and each pixel may include a pixel unit including a plurality of different colors.
  • each pixel may include a red pixel unit, a green pixel unit, and a blue pixel unit.
  • the compensation circuit of the pixel circuit in the red pixel unit may be connected to the first driving node of the pixel circuit in the same row and the closest red pixel unit, and the compensation of the pixel circuit in the green pixel unit
  • the circuit may be connected to the first driving node of the pixel circuit in the same row and closest to the green pixel unit, and the compensation circuit of the pixel circuit in the blue pixel unit may be the same pixel in the same row and closest to the blue pixel unit
  • the first drive node of the circuit is connected.
  • the third power terminal VSS can input a third power signal to the second driving node, and the compensation circuit 20 can input the first driving node P1 in the other pixel circuit under the control of the level and the data signal of the second driving node P2. a power signal, so that when the light-emitting element L to which the pixel circuit 1 is connected fails to emit light, the second power signal is input to the first driving node P1 of the other pixel circuit to enhance the connection of the other pixel circuit.
  • the light-emitting luminance of the light-emitting element L ensures the display effect of the display device and improves the display quality of the display device.
  • At least one embodiment of the present disclosure also provides a display device, which may include a display substrate 310 as shown in FIG.
  • the display device 300 includes a plurality of pixel units P including any of the pixel circuits 1 and the light-emitting elements L provided in the above embodiments.
  • the pixel circuit 1 shown in FIG. 3 or FIG. 4 is included.
  • the connection mode of the pixel circuit 1 is as shown in FIG. 6.
  • the display device 1 further includes a plurality of gate lines G and a plurality of data lines D. It should be noted that only a part of the pixel unit P, the gate line G, and the data line D are shown in FIG.
  • the plurality of pixel units P are arranged in a plurality of rows, and the control terminals of the data writing sub-circuit 12 (shown in FIG. 2C) of the pixel circuits 1 of the row of pixel units P are connected to the same gate line G.
  • a gate drive signal is provided to write the sub-circuit 12 to the data.
  • the data line D of each column is coupled to the input of the data write sub-circuit 200 in the column of pixel circuits 10 to provide a data signal.
  • the driving sub-circuit 11 (shown in FIG. 2C) includes a control terminal 130, a first terminal 110, and a second terminal 120, and the first end of the driving sub-circuit 11 is connected to the first power terminal VDD to receive the first power signal.
  • the compensation circuit 20 (shown in FIG. 2A or FIG. 2B) and the second power supply terminal VDD' and the third power supply terminal VSS are connected to receive the second power supply signal and the third power supply signal, respectively.
  • the display device 1 shown in FIG. 8 may further include a plurality of first voltage lines, second voltage lines, and third voltage lines to respectively provide the first voltage, the second voltage, and the third voltage.
  • the display device 1 may further include a display panel 310, a gate driver 320, a data driver 340, and a timing controller 330.
  • the display panel 310 includes a plurality of pixel units P defined according to a plurality of gate lines G and a plurality of data lines D; a gate driver 320 for driving a plurality of gate lines G; and a data driver 340 for driving a plurality of data lines a line D; and a timing controller 330 for processing image data RGB input from outside the display device 1, supplying processed image data RGB to the data driver 340, and outputting scan control signals GCS and data to the gate driver 320 and the data driver 340
  • the signal DCS is controlled to control the gate driver 320 and the data driver 340.
  • the display panel 310 includes a plurality of intersecting gate lines G and a plurality of data lines D.
  • the pixel unit P is disposed at an intersection area of the gate line G and the data line D.
  • each pixel unit P is connected to a gate line G (for providing a gate driving signal), a data line D, a first voltage line for supplying a first power signal, and a second power supply signal A second voltage line and a third voltage line for providing a third power signal.
  • the first voltage line, the second voltage line, or the third voltage line herein may be replaced with a corresponding plate-like common electrode (for example, a common anode or a common cathode).
  • the gate driver 320 supplies a plurality of gate signals to the plurality of gate lines G in accordance with the plurality of scan control signals GCS derived from the timing controller 330.
  • the plurality of strobe signals includes a gate drive signal. These signals are supplied to each of the pixel units P through a plurality of gate lines G.
  • the data driver 340 converts the digital image data RGB input from the timing controller 330 into a data signal according to a plurality of data control signals DCS derived from the timing controller 330 using the reference gamma voltage.
  • the data driver 340 provides the converted data signals to the plurality of data lines D.
  • the timing controller 330 sets the externally input image data RGB to match the size and resolution of the display panel 310, and then supplies the set image data to the data driver 340.
  • the timing controller 330 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using a synchronization signal (for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device.
  • the timing controller 330 supplies the generated scan control signal GCS and data control signal DCS to the gate driver 320 and the data driver 340, respectively, for control of the gate driver 320 and the data driver 340.
  • the data driver 340 may be connected to the plurality of data lines D to provide the data signal Vdata; and may also be connected to the plurality of first voltage lines, the plurality of second voltage lines, and the plurality of third voltage lines to respectively provide the first The power signal, the second power signal, and the third power signal.
  • the gate driver 320 and the data driver 340 can be implemented as a semiconductor chip.
  • the display device 300 may also include other components, such as signal decoding circuits, voltage conversion circuits, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • the display device 300 can be: a MicroLED display substrate, a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any display product or component. .

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Abstract

一种像素电路（1）及其驱动方法、显示基板、显示装置，该像素电路（1）包括驱动电路（10）和补偿电路（20），该补偿电路（20）可以在控制节点（N）的电压信号和第二驱动节点（P2）的电平的控制下，将输出端（OUT）与第二电源端（VDD'）连接以接收第二电源信号。该像素电路（1）可以在该像素电路（1）所连接的发光元件出现故障无法正常发光时，向输出端（OUT）输入第二电源信号，从而可以通过增强该另一像素电路所连接的发光元件的发光亮度或驱动替补发光元件发光，保证了显示装置的显示效果，提高了显示装置的显示质量。

Description

像素电路及其驱动方法、显示基板、显示装置
本申请要求于2018年5月10日递交的中国专利申请第201810445154.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种像素电路及其驱动方法、显示基板、显示装置。
背景技术
微型发光二极管(Micro Light-Emitting Doide，MicroLED)是一种采用无机材料作为发光材料的发光器件。采用MicroLED作为发光器件的显示装置具有亮度高、响应速度快以及稳定性高等优点。
发明内容
本公开至少一实施例提供一种像素电路，包括：驱动电路和补偿电路；所述驱动电路分别与栅线、数据线、第一电源端、控制节点以及第一驱动节点连接，所述驱动电路配置为响应于所述栅线的栅极驱动信号将所述数据线的数据信号写入至所述控制节点，并在所述控制节点的电压信号的控制下将所述第一驱动节点与所述第一电源端连接以接收第一电源信号，所述第一驱动节点与发光元件的一极连接；所述补偿电路分别与第二电源端、第三电源端、所述控制节点、第二驱动节点以及输出端连接，所述补偿电路配置为响应于所述控制节点的电压信号和所述第二驱动节点的信号，将所述另一像素电路中的第一驱动节点与所述第二电源端连接以接收第二电源信号，所述第二驱动节点与所述发光元件的另一极连接。
例如，在本公开至少一实施例提供的像素电路中，所述输出端与另一像素电路中的第一驱动节点或所述输出端所在的当前像素电路包括的另一发光元件连接。
例如，在本公开至少一实施例提供的像素电路中，所述补偿电路包括补 偿子电路和开关子电路；所述补偿子电路分别与所述第二电源端、所述控制节点以及所述开关子电路连接，所述补偿子电路配置为响应于所述控制节点的电压信号，向所述开关子电路输入所述第二电源信号；所述开关子电路分别与所述第三电源端、所述第二驱动节点以及所述输出端连接，所述开关子电路配置为在所述第二驱动节点的电平的控制下，将所述补偿子电路与所述输出端连接，以向所述输出端输入所述第二电源信号。
例如，在本公开至少一实施例提供的像素电路中，所述补偿子电路包括：第一晶体管；所述第一晶体管的栅极与所述控制节点连接，所述第一晶体管的第一极与所述第二电源端连接以接收所述第二电源信号，所述第一晶体管的第二极与所述开关子电路连接。
例如，在本公开至少一实施例提供的像素电路中，所述开关子电路包括：第二晶体管；所述第二晶体管的栅极与所述第二驱动节点连接，所述第二晶体管的第一极和所述第一晶体管的第二极连接，所述第二晶体管的第二极与所述输出端连接。
例如，在本公开至少一实施例提供的像素电路中，所述开关子电路还包括电阻；所述电阻的一端与所述第二驱动节点连接，所述电阻的另一端与所述第三电源端连接以接收第三电源信号。
例如，在本公开至少一实施例提供的像素电路中，所述驱动电路包括：驱动子电路、数据写入子电路和存储子电路；所述驱动子电路包括控制端、第一端和第二端，且配置为响应于所述控制节点的电压信号控制驱动所述发光元件发光的驱动电流，所述驱动子电路的第一端配置为从第一电源端接收所述第一电源信号；所述数据写入子电路与所述存储电路、所述栅线、所述数据线和所述控制节点连接，且配置为响应于所述栅线的栅极驱动信号将所述数据线的数据信号写入至所述控制节点和所述存储子电路；所述存储子电路与所述控制节点和所述第一电源端连接，且配置为存储所述数据写入子电路写入的所述数据信号。
例如，在本公开至少一实施例提供的像素电路中，所述数据写入子电路包括开关晶体管；所述开关晶体管的栅极与所述栅线连接以接收所述栅极驱动信号，所述开关晶体管的第一极与所述数据线连接以接收所述数据信号，所述开关晶体管的第二极与所述控制节点连接。
例如，在本公开至少一实施例提供的像素电路中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的栅极与所述控制节点连接，所述驱动晶体管的第一极与所述第一电源端连接以接收所述第一电源信号，所述驱动晶体管的第二极与所述第一驱动节点连接。
例如，在本公开至少一实施例提供的像素电路中，所述存储子电路包括电容器，所述电容器的一端与所述第一电源端连接以接收所述第一电源信号，所述电容器的另一端与所述控制节点连接。
例如，在本公开至少一实施例提供的像素电路中，所述第一电源端与所述第二电源端为同一个电源端或不同的电源端。
本公开至少一实施例还提供一种像素电路的驱动方法，用于驱动本公开任一实施例提供的像素电路，所述驱动方法包括：所述栅线提供第一电位的栅极驱动信号，所述数据线提供所述数据信号，所述驱动电路响应于所述栅极驱动信号和所述数据信号，向所述第一驱动节点输入来自所述第一电源端的所述第一电源信号；当所述发光元件正常工作时，所述第一驱动节点与所述第二驱动节点连接，所述补偿电路在所述第二驱动节点的电平的控制下关断；当所述发光元件非正常工作时，所述第一驱动节点与所述第二驱动节点断开连接，第三电源端向所述第二驱动节点输入第三电源信号，所述补偿电路在所述第二驱动节点的电平的控制下，向所述输出端输入来自所述第二电源端的第二电源信号。
例如，在本公开至少一实施例提供的像素电路的驱动方法中，所述第一电源信号的电位和所述第二电源信号的电位均为第二电位，所述第三电源信号的电位为第一电位。
例如，在本公开至少一实施例提供的像素电路的驱动方法中，所述补偿电路包括补偿子电路和开关子电路，当所述发光元件非正常工作时，所述补偿子电路响应于所述控制节点的电压信号而导通，所述开关子电路在所述第二驱动节点的电平的控制下导通，使得所述第二电源端与所述输出端连接以接收所述第二电源端的第二电源信号。
例如，在本公开至少一实施例提供的像素电路的驱动方法中，所述驱动电路包括：驱动子电路、数据写入子电路和存储子电路，所述驱动方法还包括数据写入阶段和发光阶段：在数据写入阶段，输入所述栅极驱动信号和所 述数据信号，开启所述数据写入子电路，所述数据写入子电路将所述数据信号写入所述控制节点和所述存储电路；在发光阶段，所述驱动子电路在所述控制节点的电压信号的控制下导通，将驱动电流施加至所述第一驱动节点。
本公开至少一实施例还提供一种显示基板，包括阵列布置的多个像素单元，其中，每个所述像素单元包括本公开至少一实施例提供的像素电路和发光元件；每个所述像素电路的输出端均与另一像素电路的第一驱动节点或当前像素电路的另一发光元件连接。
例如，在本公开至少一实施例提供的显示基板中，每个所述像素电路的输出端所连接的另一像素电路，与所述像素电路位于同一行或同一列；每个所述像素电路的输出端所连接的另一像素电路与所述像素电路的距离最近，且二者所属的像素单元的颜色相同。
例如，在本公开至少一实施例提供的显示基板中，所述发光元件为微型发光二极管。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种2T1C像素电路的示意图；
图1B为另一种2T1C像素电路的示意图；
图2A是本公开至少一实施例提供的一种像素电路的示意框图；
图2B是本公开至少一实施例提供的另一种像素电路的示意框图；
图2C为图2A或图2B所示的驱动电路的示意框图；
图3为图2B中所示的像素电路的一种具体实现示例的电路示意图；
图4为图2B中所示的像素电路的另一种具体实现示例的电路示意图；
图5是本公开至少一实施例提供的一种像素电路的驱动方法的流程图；
图6是本公开至少一实施例提供的一种显示基板的示意框图；
图7是本公开至少一实施例提供的另一种显示基板的示意框图；以及
图8为本公开至少一实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的实施例的限制。
在制造MicroLED显示装置时，一般会先在电路基板上形成阵列排布的薄膜晶体管(例如，图1A或图1B中所示的开关晶体管T0和驱动晶体管N0)，也即进行背板制作；然后再在另一基板上形成阵列排布的多个MicroLED，例如，该基板的材料可以为单晶硅或者砷化镓等无机材料；最后再将基板上形成的多个MicroLED批量转印至形成有薄膜晶体管的电路基板上。从而可以形成例如图1A或图1B所示的像素电路结构。
但是，通过相关技术在批量转印MicroLED的过程中，由于MicroLED的数量较多且尺寸较小，一些MicroLED可能会转印失败，从而影响显示装置的显示效果，降低显示装置的显示质量。例如，MicroLED的尺寸(例如， 长方形的长边或正方形的边长)小于100微米，例如，小于50微米。
图1A和图1B分别为示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cs。例如，该开关晶体管T0的栅极连接扫描线以接收栅极驱动信号Scan1，例如源极连接到数据线以接收数据信号Vdata，漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电压端以接收第一电压Vdd(高电压)，漏极连接到MicroLED的正极端；存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电压端以接收第一电压Vdd；MicroLED的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过扫描线施加栅极驱动信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据线送入的数据信号Vdata将经由开关晶体管T0对存储电容Cs充电，由此将数据信号Vdata存储在存储电容Cs中，且此存储的数据信号Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管以驱动MicroLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：MicroLED的正极端连接到第一电压端以接收第一电压Vdd(高电压)，而负极端连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式基本上与图1A所示的像素电路基本相同，这里不再赘述。
例如，在图2A所示的示例的基础上，还可以包括补偿电路(例如，可以实现为补偿晶体管，图中未示出)，以补偿驱动晶体管N0的阈值电压或电源线(例如，提供第一电压Vdd)的压降。例如，该补偿电路包括第一端、 第二端和控制端，其分别与驱动晶体管N0的栅极、驱动晶体管N0的漏极以及补偿信号线(图中未示出，例如，可以是扫描线)连接。例如在补偿阶段，补偿电路响应于补偿信号线提供的补偿信号导通，可以将驱动晶体管N0的栅极和漏极电连接，从而可以使驱动晶体管N0的阈值电压的相关信息相应地存储在存储电容Cs中，从而使得驱动晶体管N0的阈值电压得到补偿，以在发光阶段，使得流经MicroLED的驱动电流仅与数据信号等有关，不再与驱动晶体管N0的阈值电压有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管N0由于工艺制程及长时间的操作等原因造成阈值电压漂移的问题，消除了该阈值电压对驱动电流的影响导致的显示不均匀，而且在某些示例中，流经MicroLED的驱动电流也不再与第一电压Vdd有关，从而解决了电源线的压降导致的第一电压Vdd出现偏差而导致的显示面板的显示不均匀问题。例如，图2B中未示出的补偿电路的工作方式与图2A类似，在此不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，根据需要也可以为P型晶体管，由此控制其导通或截止的栅极驱动信号Scan1的极性进行相应地改变即可。
例如，当图1A或图1B所示的像素电路中的MicroLED转印失败时，图1A或图1B所示的像素电路中没有MicroLED，从而影响显示装置的显示效果，降低显示装置的显示质量。
本公开至少一实施例提供一种像素电路，包括：驱动电路和补偿电路。驱动电路分别与栅线、数据线、第一电源端、控制节点以及第一驱动节点连接，驱动电路配置为响应于栅线的栅极驱动信号将数据线的数据信号写入至控制节点，并在控制节点的电压信号的控制下将第一驱动节点与第一电源端连接以接收第一电源信号，第一驱动节点与发光元件的一极连接；补偿电路分别与第二电源端、第三电源端、控制节点、第二驱动节点以及输出端连接，补偿电路配置为响应于控制节点的电压信号和第二驱动节点的信号，将输出端与第二电源端连接以接收第二电源信号，第二驱动节点与发光元件的另一极连接。
本公开至少一实施例还提供一种对应于上述像素电路的驱动方法、显示基板和显示装置。
本公开上述实施例提供的像素电路可以在该像素电路所连接的发光元件出现故障无法正常发光时，向输出端输入第二电源信号，从而可以通过增强该另一像素电路所连接的发光元件的发光亮度或驱动替补发光元件发光，保证了显示装置的显示效果，提高了该显示装置的显示质量。
为了使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施例作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用，本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以为P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极的电平为低电平时导通，在栅极的电平为高电平时截止，N型开关晶体管在栅极的电平为高电平时导通，在栅极的电平为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位，第一电位和第二电位仅代表该信号的电位有2个不同的状态量，不代表全文中第一电位或第二电位具有特定的数值。例如，在本公开一些实施例中，第一电位为低电平，第二电位为高电平。需要注意的是，第一电位和第二电位的电平的高低根据实际情况设置，本公开的实施例对此不作限制。
图2A是本公开至少一实施例提供的一种像素电路的示意框图。该像素电路1例如用于驱动显示面板的子像素中的发光元件发光。在本公开的至少一个实施例中，显示面板例如通过玻璃衬底制备，具体结构与制备工艺可以采用本领域中的方法，这里不再详述，且本公开的实施例对此不作限制。例如，发光元件可为MicroLED，也可为OLED(Organic Light Emitting Diode，有机发光二极管)或QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)等，相应的显示面板为MicroLED显示面板，或OLED显示面板或QLED显示面板等。下面以发光元件为或MicroLED显示面板为例进行说明，本公开的实施例对此不作限制。
如图2A所示，该像素电路1可以包括：驱动电路10和补偿电路20，该 驱动电路10可以包括驱动晶体管(图2A中未示出)。
参考图2A，该驱动电路10可以分别与栅线G、数据线D、第一电源端VDD、控制节点N以及第一驱动节点P1连接。该驱动电路10配置为响应于栅线G的栅极驱动信号将数据线D的数据信号写入至控制节点N，并在所述控制节点的电压信号的控制下将第一驱动节点P1与第一电源端VDD连接以接收第一电源信号。例如，该第一驱动节点P1与发光元件L的一极连接。例如，该第一驱动节点P1可以与发光元件L的阳极连接。
图2C为图2A所示的驱动电路的示意框图。例如，在图2C所示的示例中，驱动电路10可以包括驱动子电路11、数据写入子电路12以及存储子电路13。驱动电路10例如用于控制驱动发光元件L发光的驱动电流。
例如，驱动子电路11包括控制端130(例如，图3中所示的驱动晶体管M0的栅极)、第一端110(例如，图3中所示的驱动晶体管M0的第一极)和第二端120(例如，图3中所示的驱动晶体管M0的第二极)，且配置为响应于控制节点N的电压信号控制驱动发光元件L发光的驱动电流，驱动子电路11的第一端110配置为从第一电源端VDD接收第一电源信号。
数据写入子电路12与存储电路13、栅线G、数据线D和控制节点N连接，且配置为响应于栅线G的栅极驱动信号将数据线D的数据信号写入至控制节点N和存储子电路13。例如，在数据写入阶段，数据写入子电路12可以响应于栅极驱动信号而开启，从而可以将数据信号写入驱动子电路11的控制端130(即控制节点N和存储电路13)，然后可将数据信号存储在存储子电路13中，该存储的数据信号将用于控制驱动子电路11的打开程度，从而控制生成驱动发光器件发光的驱动电流。
存储子电路13与控制节点N和驱动子电路11的第一电源端VDD连接，配置为存储数据写入子电路12写入的数据信号。
例如，当该栅线G提供的栅极驱动信号的电位为第一电位，且该数据线D提供的数据信号的电位为第一电位时，数据子电路12导通，并将数据信号写入控制节点N和存储电路13。该驱动子电路11在控制节点N的控制下导通，可以向第一驱动节点P1输入来自第一电源端VDD的第一电源信号，该第一电源信号的电位可以为第二电位，且该第二电位可以为无效电位。例如，第二电位高于第一电位。
参考图2A，该补偿电路20可以分别与第二电源端VDD'、第三电源端VSS、控制节点N(例如，驱动晶体管的栅极(图2A中未示出))、第二驱动节点P2以及输出端OUT连接，该补偿电路20可以配置为响应于控制节点N的电压信号和第二驱动节点P2的信号，将输出端OUT与第二电源端VDD'连接以接收第二电源信号。例如，该第二驱动节点P2与发光元件L的另一极连接。例如，该第二驱动节点P2可以与发光元件L的阴极连接。
例如，该输出端OUT可以与另一像素电路中的第一驱动节点(图中未示出)或当前像素电路的另一发光元件(图中未示出)连接。例如，该另一发光元件(图中未示出)属于当前像素电路，且与该补偿电路20连接。例如，该另一发光元件作为替补发光元件，在发光元件L出现故障或转印失败时，可替代发光元件L进行发光。需要注意的是，下面以输出端OUT与另一像素电路中的第一驱动节点为例进行说明，该电路连接和驱动方法同样适用于输出端OUT与当前像素电路的另一发光元件连接的情形，本公开的实施例对此不再赘述。
例如，该第一电源端VDD与第二电源端VDD'可以是不同的电源端，也可以是相同的电源端(如图4所示)，本公开的实施例对此不作限制。
在本公开实施例中，该像素电路1中的发光元件L可以为MicroLED发光器件，或者也可以为LED或者OLED等发光器件，本公开实施例对此不做限定。
例如，假设发光元件L出现故障(例如MicroLED转印过程中丢失或者转印后连接不良)造成该像素电路1的第一驱动节点P1和第二驱动节点P2断开。则当该像素电路1处于发光阶段时，驱动晶体管的栅极的信号的电位为第一电位，该驱动晶体管开启，并向第一驱动节点P1输入第一电源信号。由于该第一驱动节点P1与第二驱动节点P2断开，故此时第三电源端VSS可以向第二驱动节点P2输入第三电源信号。补偿电路20在第三电源信号的控制下开启，可以向另一像素电路中的第一驱动节点P1输入第二电源信号，从而使得在该像素电路1所连接的发光元件L无法正常发光时，可以向另一像素电路的第一驱动节点P1输入第二电源信号，从而增强另一像素电路所连接的发光元件的发光亮度，以补偿该出现故障的发光元件L的发光亮度，保证了显示装置的显示效果；或使得在该像素电路1所连接的发光元件L无 法正常发光时，可以向与输出端OUT连接的当前像素电路中的另一发光元件输入第二电源信号，从而可替代该无法正常发光的发光元件发光，提高了显示装置的显示质量。
综上所述，本公开实施例提供的像素电路包括补偿电路，该补偿电路可以在控制节点N的电压信号和第二驱动节点的电平的控制下导通，向另一像素电路中的第一驱动节点P1输入来自第二电源端VDD’的第二电源信号，从而可以在该像素电路1所连接的发光元件L出现故障无法正常发光的情形下，向另一像素电路的第一驱动节点P1输入第二电源信号，以增强该另一像素电路所连接的发光元件的发光亮度，保证了显示装置的显示效果，提高了该显示装置的显示质量。
例如，为了进一步保证显示装置的显示效果，该像素电路的补偿电路所连接的另一像素电路，与该像素电路可以位于同一行或同一列，且该像素电路的补偿电路所连接的另一像素电路可以与该像素电路的距离最近，且二者所属的像素单元的颜色相同。
图2B是本公开至少一实施例提供的另一种像素电路的示意框图。如图2B所示，该补偿电路20可以包括补偿子电路201和开关子电路202。
参考图2B，该补偿子电路201可以分别与第二电源端VDD'、控制节点N(驱动晶体管的栅极(图2B中未示出))以及开关子电路202连接，该补偿子电路201可以响应于控制节点N的电压信号，向开关子电路202输入第二电源信号。
例如，当该像素电路处于发光阶段时，驱动晶体管的栅极的信号的电位为第一电位，该补偿子电路201响应于该第一电位而开启，使得开关子电路202与第二电压端VDD’连接以向开关子电路202输入第二电源信号。例如，该第二电源信号的电位可以为第二电位。
参考图2B，该开关子电路202可以分别与第三电源端VSS、第二驱动节点P2以及另一像素电路的第一驱动节点P1(即输出端OUT)连接，开关子电路202配置为响应于第二驱动节点P2的信号，将补偿子电路201与另一像素电路的第一驱动节点P1连接，以向另一像素电路的第一驱动节点P1输入第二电源信号。
例如，假设发光元件L出现故障造成该像素电路的第一驱动节点P1和 第二驱动节点P2断开时，该第三电源端VSS可以向该第二驱动节点P2输入第三电源信号，该开关子电路202响应于该第二驱动节点P2的信号开启，将补偿子电路201与另一像素电路的第一驱动节点P1连接，以向另一像素电路的第一驱动节点P1输入第二电源信号。例如，该第三电源信号的电位可以为第一电位，该第一电位可以为有效电位。
需要注意的是，在本公开各个实施例的说明中，第一驱动节点P1、第二驱动节点P2以及控制节点N并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点，以便于描述。
图3是图2B所示的像素电路的一种具体实现示例的示意图。如图3所示，该像素电路1包括驱动晶体管M0和第一至第三晶体管M1、M2、M3以及包括电容器C、电阻R和发光元件L(例如，MicroLED)。例如，第一至第三晶体管M1、M2、M3被用作开关晶体管。例如，发光元件可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。例如，在本公开实施例中，各个开关晶体管可以采用P型晶体管，驱动晶体管M0采用P型晶体管。例如P型晶体管响应于低电平信号而开启，响应于高电平信号而截止，以下实施例与此相同，不再赘述。
如图3所示，该补偿子电路201可以包括：第一晶体管M1。参考图3，该第一晶体管M1的栅极可以与驱动晶体管M0的栅极(即控制节点N)连接，该第一晶体管M1的第一极可以与第二电源端VDD'连接以接收第二电源信号，该第一晶体管M1的第二极可以与第二晶体管M2的第一极连接。
例如，如图3所示，该开关子电路202可以包括：第二晶体管M2。
该第二晶体管M2的栅极可以与第二驱动节点P2连接，该第二晶体管M2的第二极可以与另一个像素电路的第一驱动节点P1(即图2A中所示的输出端OUT)连接。
该开关子电路202还可以包括电阻R。该电阻R的一端可以与第二驱动节点P2连接，该电阻R的另一端可以与第三电源端VSS连接以接收第三电源信号。
在本公开实施例中，该电阻R可以对第三电源端VSS提供的第三电源信号进行分压，也即，该第二驱动节点P2上的电压小于该第三电源信号的 电压，从而可以使得当像素电路1所连接的发光元件L能够正常发光时，该第一驱动节点P1可以通过该发光元件L将第一电源信号输入至第二驱动节点P2，该第二晶体管M2即可以在该第二驱动节点P2的控制下保持关断，避免了在该发光元件L正常发光时，该像素电路1中的补偿电路20向另一像素电路的第一驱动节点P1输入第二电源信号，造成该显示装置中不同像素电路所连接到发光元件的发光亮度不同的问题，进一步保证了该显示装置的显示效果。
例如，如图3所示，该驱动电路10可以包括：开关晶体管M3、驱动晶体管M0和电容器C。
参考图2C和图3，数据写入子电路12包括开关晶体管M3。该开关晶体管M3的栅极可以与栅线G连接以接收栅极驱动信号，该开关晶体管M3的第一极可以与数据线D连接以接收数据信号，该开关晶体管M3的第二极可以与控制节点N(即驱动晶体管M0的栅极)连接。
例如，驱动子电路11包括驱动晶体管M0。该驱动晶体管M0的第一极可以与第一电源端VDD连接以接收第一电源信号，该驱动晶体管M0的第二极可以与第一驱动节点P1连接。
存储子电路13包括电容器C。该电容器C的一端可以与第一电源端VDD(即，驱动晶体管M0的第一极)连接以接收第一电源信号，该电容器C的另一端可以与控制节点N(即，驱动晶体管M0的栅极)连接。
需要注意的是，上述2T1C结构的驱动电路10仅仅是示例，该驱动电路当然还可以是其它任何可以驱动发光元件发光的电路，如4T2C、5T1C、7T1C等结构，本公开的实施例对此不作限制。
在本公开至少一实施例中，如图4所示，该第一电源端VDD与第二电源端VDD'可以为同一个电源端VDD。通过将该第一电源端VDD与该第二电源端VDD'设置为同一个电源端，可以减小由该像素电路所占用的布线空间，降低布线成本。并且，由于该第一晶体管M1的栅极连接的是驱动晶体管M0的栅极，因此当开关晶体管M3开启时，数据线D可以同时为驱动晶体管M0的栅极以及第一晶体管M1的栅极提供数据信号。第一电源端VDD与该第二电源端VDD'设置为同一个电源端，可以使得加载至驱动晶体管M0的第一极的电压等于加载至该第一晶体管M1的第一极的电压，因此当该像 素电路所连接的发光元件L无法正常发光时，在数据线D提供的数据信号的驱动下，该第一晶体管M1为另一像素电路所连接的发光元件提供的补偿电流的大小与驱动晶体管M0输出的驱动电流的大小相等，此时该另一像素电路所连接的发光元件的发光亮度可以精准补偿当前像素电路所连接的发光元件无法正常发光而造成的亮度损失，从而实现了对该显示装置的显示亮度的精准补偿，更加有效的保证该显示装置的显示效果。
需要说明的是，在本公开实施例中，该驱动电路除了可以为图3或图4所示的2T1C(即两个晶体管和一个电容器)的结构之外，也可以为包括更多数量的晶体管的其他结构，本公开实施例对此不做限定。
还需要说明的是，在上述各实施例中，均是以第一晶体管、第二晶体管、开关晶体管以及驱动晶体管为P型晶体管，且第一电位相对于第二电位为低电位为例进行的说明。当然，第一晶体管、第二晶体管、开关晶体管以及驱动晶体管还可以采用N型晶体管，当该第一晶体管、第二晶体管、开关晶体管以及驱动晶体管均采用N型晶体管时，该第一电位相对于第二电位为高电位，本公开的实施例对此不作限制。
综上所述，本公开实施例提供的像素电路包括补偿电路，该补偿电路可以在控制节点的电压信号和第二驱动节点的电平的控制下，向另一像素电路中的第一驱动节点输入来自第二电源端的第二电源信号，从而可以在该像素电路所连接的发光元件出现故障无法正常发光的情形下，向另一像素电路的第一驱动节点输入第二电源信号，以增强该另一像素电路所连接的发光元件的发光亮度，保证了显示装置的显示效果，提高了该显示装置的显示质量。
图5是本公开至少一实施例提供的一种像素电路的驱动方法的流程图，如图5所示，该方法可以用于驱动如图2A至图4任一所述的像素电路，该方法可以包括：
步骤S501：栅线提供第一电位的栅极驱动信号，数据线提供数据信号，驱动电路响应于栅极驱动信号和数据信号，向第一驱动节点输入来自第一电源端的第一电源信号；当发光元件正常工作时，第一驱动节点与第二驱动节点导通，补偿电路在第二驱动节点的控制下关断。
在本公开实施例中，当像素电路1所连接的发光元件L正常发光时，也即是该发光元件L未出现故障时，该第一驱动节点P1和第二驱动节点P2可 以通过发光元件L连接。此时，该第一驱动节点P1可以将第一电源信号通过发光元件L输入至第二驱动节点P2，该补偿电路20即可以在该第二驱动节点P2的控制下关断，从而保证了像素电路1所连接的发光元件L在正常工作时的显示效果。
步骤S502：当发光元件非正常工作时，第一驱动节点与第二驱动节点断开连接，第三电源端向第二驱动节点输入第三电源信号，补偿电路在第二驱动节点的电平的控制下，向输出端输入来自第二电源端的第二电源信号。
例如，该第一电源信号的电位和第二电源信号的电位均可以为第二电位，第三电源信号的电位可以为第一电位。
在本公开实施例中，当发光元件L非正常工作时，也即是由于发光元件L出现故障造成该像素电路1的第一驱动节点P1和第二驱动节点P2断开(第一电源端VDD和第三电源端VSS之间断路)时(如图7所示)，该第一驱动节点P1无法将第一电源信号通过发光元件L输入至第二驱动节点P2，且该第三电源端VSS可以将第三电源信号输入至第二驱动节点P2，该补偿电路20即可以在该第二驱动节点P2的电平的控制下，向另一像素电路中的第一驱动节点P1(即输出端)输入来自第二电源端VDD’的第二电源信号。
例如，在补偿电路20包括补偿子电路201和开关子电路202的情形下，当发光元件L非正常工作时，补偿子电路201响应于控制节点N的电压信号而导通，开关子电路202在第二驱动节点P2的电平的控制下导通，使得第二电源端VSS与另一像素电路中的第一驱动节点P1连接以接收第二电源端VDD’的第二电源信号。
例如，驱动电路10包括驱动子电路11、数据写入子电路12和存储子电路13，驱动方法还包括数据写入阶段和发光阶段。
在数据写入阶段，输入栅极驱动信号和数据信号，开启数据写入子电路12，数据写入子电路12将数据信号写入控制节点N和存储电路13。
在发光阶段，驱动子电路11在控制节点N的电压信号的控制下导通，将驱动电流施加至第一驱动节点P1。
综上所述，本公开实施例提供的像素电路的驱动方法，驱动电路10可以响应于栅极驱动信号和数据信号，向第一驱动节点P1输入第一电源信号。在发光元件非正常工作时，第三电源端VSS可以向第二驱动节点输入第三电 源信号，补偿电路可以在该第二驱动节点P2的电平和数据信号的控制下，向另一像素电路中的第一驱动节点P1输入第二电源信号，从而可以在该像素电路所连接的发光元件出现故障无法正常发光时，向另一像素电路的第一驱动节点P1输入第二电源信号，以增强该另一像素电路所连接的发光元件L的发光亮度，保证了显示装置的显示效果，提高了该显示装置的显示质量。
在本公开实施例中，以图3所示的像素电路1为例，并以像素电路1中各个晶体管为P型晶体管为例，详细介绍本公开实施例提供的像素电路的驱动原理。
在本公开实施例中，参考图3，当栅线G提供第一电位的栅极驱动信号时，该开关晶体管M3开启，数据线D通过该开关晶体管M3向驱动晶体管M0的栅极输入数据信号，该驱动晶体管M0和该第一晶体管M1开启。该驱动晶体管M0可以在该数据信号的控制下，向第一驱动节点P1输入来自第一电源端VDD的第一电源信号。并且，该数据信号可以决定该驱动晶体管M0输出的驱动电流的大小，也即是该数据信号可以决定该像素电路连接的发光元件L的发光亮度(即灰度)；该第一晶体管M1可以在该数据信号的控制下，向第二晶体管M2输入来自第二电源端VDD'的第二电源信号。因此，该数据信号可以通过第一晶体管M1和第二晶体管M2控制另一像素电路中的发光元件的发光亮度。
例如，如图3所示，当该像素电路1所连接的发光元件L正常工作时，该第一驱动节点P1和第二驱动节点P2连接。此时，该像素电路1可以将该第一驱动节点P1的第一电源信号通过发光元件L输入至第二驱动节点P2，该第二晶体管M2即可以在该第二驱动节点P2的控制下关断；当该像素电路所连接的发光元件L由于出现故障无法正常工作时，该第一驱动节点P1和第二驱动节点P2断开，也即是该第一电源端VDD和第三电源端VSS之间断路，该第三电源端VSS可以向该第二驱动节点P2输入第三电源信号，该第二晶体管M2即可以在该第二驱动节点P2的控制下开启。此时，第二电源端VDD'可以通过该第二晶体管M2向另一像素电路的第一驱动节点P1输入第二电源信号，从而增强另一像素电路所连接的发光元件的发光亮度，以补偿该出现故障的发光元件的发光亮度，保证了显示装置的显示效果。
需要说明的是，在上述各实施例中，均是以第一晶体管、第二晶体管、 开关晶体管以及驱动晶体管为P型晶体管，且第一电位相对于第二电位为低电位为例进行的说明。当然，第一晶体管、第二晶体管、开关晶体管以及驱动晶体管还可以采用N型晶体管，当该第一晶体管、第二晶体管、开关晶体管以及驱动晶体管均采用N型晶体管时，该第一电位相对于第二电位为高电位。
综上所述，本公开实施例提供的像素电路的驱动方法，驱动电路10可以响应于栅极驱动信号和数据信号，向第一驱动节点P1输入第一电源信号。在发光元件L非正常工作时，第三电源端VDD可以向第二驱动节点输入第三电源信号，补偿电路20可以在该第二驱动节点P2的电平和数据信号的控制下，向另一像素电路中的第一驱动节点P1输入第二电源信号，从而可以在该像素电路1所连接的发光元件L出现故障无法正常发光时，向另一像素电路的第一驱动节点P1输入第二电源信号，以增强该另一像素电路所连接的发光元件L的发光亮度，保证了显示装置的显示效果，提高了该显示装置的显示质量。
图6是本公开至少一实施例提供的一种显示基板的结构示意图，图7是本公开至少一实施例提供的另一种显示基板的结构示意图。该显示基板310可以包括阵列布置的多个像素单元，每个像素单元可以包括如图3或图4所示的像素电路1。例如，图6共示出了三个像素单元。参考图6，该每个像素单元中的像素电路1的补偿电路20可以均与另一像素电路1的第一驱动节点P1连接。
例如，该每个像素电路1的补偿电路20所连接的另一像素电路1，可以与该像素电路1位于同一列或同一行。并且，该每个像素电路1的补偿电路20所连接的另一像素电路1可以与该像素电路1的距离最近，且二者所属的像素单元的颜色相同。
在本公开实施例中，为了更好的提升显示装置的显示效果，每个像素电路1的补偿电路20所连接的另一像素电路1，可以与该像素电路1位于同一行。并且，该每个像素电路1的补偿电路20所连接的另一像素电路1可以与像素电路1的距离最近，且二者所属的像素单元的颜色相同。
例如，该每个像素单元可以是指一个子像素(也称为亚像素)，显示基板上可以阵列设置有多个像素，每个像素可以包括包括多个不同颜色的像素单 元。例如，每个像素可以包括红色像素单元、绿色像素单元和蓝色像素单元。在本公开实施例中，该红色像素单元中的像素电路的补偿电路可以与同一行且距离最近的红色像素单元中的像素电路的第一驱动节点连接，该绿色像素单元中的像素电路的补偿电路可以与同一行且距离最近的绿色像素单元中的像素电路的第一驱动节点连接，该蓝色像素单元中的像素电路的补偿电路可以与同一行且距离最近的蓝色像素单元中的像素电路的第一驱动节点连接。
因此，在发光元件L非正常工作(例如，如图7所示，第一个像素电路1中的发光元件L缺失(例如，图7中虚线表示的发光元件L表示不存在))时，第三电源端VSS可以向第二驱动节点输入第三电源信号，补偿电路20可以在该第二驱动节点P2的电平和数据信号的控制下，向另一像素电路中的第一驱动节点P1输入第二电源信号，从而可以在该像素电路1所连接的发光元件L出现故障无法正常发光时，向另一像素电路的第一驱动节点P1输入第二电源信号，以增强该另一像素电路所连接的发光元件L的发光亮度，保证了显示装置的显示效果，提高了该显示装置的显示质量。
本公开至少一实施例还提供一种显示装置，该显示装置可以包括如图6所示的显示基板310。如图8所示，该显示装置300包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路1和发光元件L。例如，包括图3或图4所示像素电路1。例如，该像素电路1的连接方式如图6所示。如图8所示，该显示装置1还包括多条栅线G和多条数据线D。需要说明的是，在图8中仅示出了部分的像素单元P、栅线G和数据线D。
例如，在一些示例中，该多个像素单元P排列为多行，一行像素单元P的像素电路1的数据写入子电路12(如图2C所示)的控制端连接到同一条栅线G以向该数据写入子电路12提供栅极驱动信号。例如，每一列的数据线D和本列像素电路10中的数据写入子电路200的输入端连接以提供数据信号。
例如，驱动子电路11(如图2C所示)包括控制端130、第一端110和第二端120，且驱动子电路11的第一端和第一电源端VDD连接以接收第一电源信号，补偿电路20(如图2A或图2B所示)和第二电源端VDD’和第三电源端VSS连接以分别接受第二电源信号和第三电源信号。
需要说明的是，图8所示的显示装置1还可以包括多条第一电压线、第 二电压线和第三电压线以分别提供第一电压、第二电压和第三电压。
例如，如图8所示，该显示装置1还可以包括显示面板310、栅极驱动器320、数据驱动器340和定时控制器330。该显示面板310包括根据多条栅线G和多条数据线D交叉限定的多个像素单元P；栅极驱动器320，用于驱动多条栅线G；数据驱动器340，用于驱动多条数据线D；以及定时控制器330，用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器340提供处理的图像数据RGB以及向栅极驱动器320和数据驱动器340输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器320和数据驱动器340进行控制。
如图8所示，显示面板310包括交叉的多条栅线G和多条数据线D。像素单元P设置在栅线G和数据线D的交叉区域。例如，每个像素单元P连接到一条栅线G(用于提供栅极驱动信号)、一条数据线D、用于提供第一电源信号的第一电压线、用于提供第二电源信号的第二电压线以及用于提供第三电源信号的第三电压线。并且，这里的第一电压线、第二电压线或第三电压线可以用相应的板状公共电极(例如公共阳极或公共阴极)替代。
例如，栅极驱动器320根据源自定时控制器330的多个扫描控制信号GCS向多个栅线G提供多个选通信号。多个选通信号包括栅极驱动信号。这些信号通过多个栅线G提供给每个像素单元P。
例如，数据驱动器340使用参考伽玛电压根据源自定时控制器330的多个数据控制信号DCS将从定时控制器330输入的数字图像数据RGB转换成数据信号。数据驱动器340向多条数据线D提供转换的数据信号。
例如，定时控制器330设置外部输入的图像数据RGB以匹配显示面板310的大小和分辨率，然后向数据驱动器340提供设置的图像数据。定时控制器330使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器330分别向栅极驱动器320和数据驱动器340提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器320和数据驱动器340的控制。
例如，数据驱动器340可以与多条数据线D连接，以提供数据信号Vdata；同时还可以与多条第一电压线、多条第二电压线和多条第三电压线连接以分 别提供第一电源信号、第二电源信号和第三电源信号。
例如，栅极驱动器320和数据驱动器340可以实现为半导体芯片。该显示装置300还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
该显示装置300可以为：MicroLED显示基板、液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的像素电路1和显示装置300的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种像素电路，包括：驱动电路和补偿电路；其中，
    所述驱动电路分别与栅线、数据线、第一电源端、控制节点以及第一驱动节点连接，所述驱动电路配置为响应于所述栅线的栅极驱动信号将所述数据线的数据信号写入至所述控制节点，并在所述控制节点的电压信号的控制下将所述第一驱动节点与所述第一电源端连接以接收第一电源信号，所述第一驱动节点与发光元件的一极连接；
    所述补偿电路分别与第二电源端、第三电源端、所述控制节点、第二驱动节点以及输出端连接，所述补偿电路配置为响应于所述控制节点的电压信号和所述第二驱动节点的信号，将所述另一像素电路中的第一驱动节点与所述第二电源端连接以接收第二电源信号，所述第二驱动节点与所述发光元件的另一极连接。
  2. 根据权利要求1所述的像素电路，其中，所述输出端与另一像素电路中的第一驱动节点或所述输出端所在的当前像素电路包括的另一发光元件连接。
  3. 根据权利要求2所述的像素电路，其中，所述补偿电路包括补偿子电路和开关子电路；其中，
    所述补偿子电路分别与所述第二电源端、所述控制节点以及所述开关子电路连接，所述补偿子电路配置为响应于所述控制节点的电压信号，向所述开关子电路输入所述第二电源信号；
    所述开关子电路分别与所述第三电源端、所述第二驱动节点以及所述输出端连接，所述开关子电路配置为在所述第二驱动节点的电平的控制下，将所述补偿子电路与所述输出端连接，以向所述输出端输入所述第二电源信号。
  4. 根据权利要求3所述的像素电路，其中，所述补偿子电路包括：第一晶体管，
    其中，所述第一晶体管的栅极与所述控制节点连接，所述第一晶体管的第一极与所述第二电源端连接以接收所述第二电源信号，所述第一晶体管的第二极与所述开关子电路连接。
  5. 根据权利要求4所述的像素电路，其中，所述开关子电路包括：第二 晶体管，
    其中，所述第二晶体管的栅极与所述第二驱动节点连接，所述第二晶体管的第一极和所述第一晶体管的第二极连接，所述第二晶体管的第二极与所述输出端连接。
  6. 根据权利要求4或5所述的像素电路，其中，所述开关子电路还包括电阻，
    其中，所述电阻的一端与所述第二驱动节点连接，所述电阻的另一端与所述第三电源端连接以接收第三电源信号。
  7. 根据权利要求1至6任一所述的像素电路，其中，所述驱动电路包括：驱动子电路、数据写入子电路和存储子电路；其中，
    所述驱动子电路包括控制端、第一端和第二端，且配置为响应于所述控制节点的电压信号控制驱动所述发光元件发光的驱动电流，所述驱动子电路的第一端配置为从第一电源端接收所述第一电源信号；
    所述数据写入子电路与所述存储电路、所述栅线、所述数据线和所述控制节点连接，且配置为响应于所述栅线的栅极驱动信号将所述数据线的数据信号写入至所述控制节点和所述存储子电路；
    所述存储子电路与所述控制节点和所述第一电源端连接，且配置为存储所述数据写入子电路写入的所述数据信号。
  8. 根据权利要求7所述的像素电路，其中，所述数据写入子电路包括开关晶体管；
    其中，所述开关晶体管的栅极与所述栅线连接以接收所述栅极驱动信号，所述开关晶体管的第一极与所述数据线连接以接收所述数据信号，所述开关晶体管的第二极与所述控制节点连接。
  9. 根据权利要求7或8所述的像素电路，其中，所述驱动子电路包括驱动晶体管，
    其中，所述驱动晶体管的栅极与所述控制节点连接，所述驱动晶体管的第一极与所述第一电源端连接以接收所述第一电源信号，所述驱动晶体管的第二极与所述第一驱动节点连接。
  10. 根据权利要求7-9任一所述的像素电路，其中，所述存储子电路包括电容器，
    其中，所述电容器的一端与所述第一电源端连接以接收所述第一电源信号，所述电容器的另一端与所述控制节点连接。
  11. 根据权利要求1至10任一所述的像素电路，其中，所述第一电源端与所述第二电源端为同一个电源端或不同的电源端。
  12. 一种像素电路的驱动方法，用于驱动如权利要求1至11任一所述的像素电路，所述驱动方法包括：
    所述栅线提供第一电位的栅极驱动信号，所述数据线提供所述数据信号，所述驱动电路响应于所述栅极驱动信号和所述数据信号，向所述第一驱动节点输入来自所述第一电源端的所述第一电源信号；
    当所述发光元件正常工作时，所述第一驱动节点与所述第二驱动节点连接，所述补偿电路在所述第二驱动节点的电平的控制下关断；
    当所述发光元件非正常工作时，所述第一驱动节点与所述第二驱动节点断开连接，第三电源端向所述第二驱动节点输入第三电源信号，所述补偿电路在所述第二驱动节点的电平的控制下，向所述输出端输入来自所述第二电源端的第二电源信号。
  13. 根据权利要求12所述的像素电路的驱动方法，其中，所述第一电源信号的电位和所述第二电源信号的电位均为第二电位，所述第三电源信号的电位为第一电位。
  14. 根据权利要求12或13所述的像素电路的驱动方法，其中，所述补偿电路包括补偿子电路和开关子电路，
    当所述发光元件非正常工作时，所述补偿子电路响应于所述控制节点的电压信号而导通，所述开关子电路在所述第二驱动节点的电平的控制下导通，使得所述第二电源端与所述输出端连接以接收所述第二电源端的第二电源信号。
  15. 根据权利要求12-14任一所述的像素电路的驱动方法，其中，所述驱动电路包括：驱动子电路、数据写入子电路和存储子电路，所述驱动方法还包括数据写入阶段和发光阶段：
    在数据写入阶段，输入所述栅极驱动信号和所述数据信号，开启所述数据写入子电路，所述数据写入子电路将所述数据信号写入所述控制节点和所述存储电路；
    在发光阶段，所述驱动子电路在所述控制节点的电压信号的控制下导通，将驱动电流施加至所述第一驱动节点。
  16. 一种显示基板，包括阵列布置的多个像素单元，其中，每个所述像素单元包括如权利要求1至11任一所述的像素电路和发光元件；
    其中，每个所述像素电路的输出端均与另一像素电路的第一驱动节点或当前像素电路的另一发光元件连接。
  17. 根据权利要求16所述的显示基板，其中，
    每个所述像素电路的输出端所连接的另一像素电路，与所述像素电路位于同一行或同一列；
    每个所述像素电路的输出端所连接的另一像素电路与所述像素电路的距离最近，且二者所属的像素单元的颜色相同。
  18. 根据权利要求16或17所述的显示基板，其中，所述发光元件为微型发光二极管。
  19. 一种显示装置，包括如权利要求16-18任一所述的显示基板。
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