WO2019205740A1 - 一种输出零纹波变换器 - Google Patents

一种输出零纹波变换器 Download PDF

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Publication number
WO2019205740A1
WO2019205740A1 PCT/CN2019/070643 CN2019070643W WO2019205740A1 WO 2019205740 A1 WO2019205740 A1 WO 2019205740A1 CN 2019070643 W CN2019070643 W CN 2019070643W WO 2019205740 A1 WO2019205740 A1 WO 2019205740A1
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Prior art keywords
winding
capacitor
output
switching transistor
circuit
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PCT/CN2019/070643
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English (en)
French (fr)
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王志燊
钟年发
郭启利
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广州金升阳科技有限公司
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Publication of WO2019205740A1 publication Critical patent/WO2019205740A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output

Definitions

  • the invention relates to an output zero ripple converter.
  • the above scheme has a deficiency.
  • the scheme has different output voltage ripples under different input voltages, and zero ripple cannot be realized in the full input voltage range.
  • the technical problem solved by the present invention is to overcome the deficiencies of the prior methods, and an output zero ripple converter is proposed to realize output zero ripple in a wide input voltage range.
  • An output zero ripple converter includes a main power stage circuit, and the main power stage circuit includes a transformer, a switch tube Q1, a switch tube Q2, a switch tube SR1, a switch tube SR2, a capacitor Cr, and an output rectification filter circuit;
  • the transformer has four magnetic columns, which are a first magnetic column, a second magnetic column, a third magnetic column and a fourth magnetic column; the first magnetic column is wound on the winding p and the winding s, and the second magnetic column is Winding winding a, there is no winding on the third magnetic column, winding winding L on the fourth magnetic column;
  • the positive end of the input voltage Vin is connected to the same end of the winding p and the negative end of the capacitor Cr.
  • the different ends of the winding p are respectively connected to the drain of the switching transistor Q1 and the source of the switching transistor Q2, and the source of the switching transistor Q1.
  • the drain of the switch Q2 is connected to the positive terminal of the capacitor Cr; the same-name terminal of the winding s is respectively connected to the same-name terminal of the winding L and the drain of the switching transistor SR1, and the different-name end of the winding L is The positive end of the output rectification and filtering circuit is connected, the source of the switching tube SR2 and the source of the switching tube SR1 are connected to the negative end of the output rectifying and filtering circuit, and the drain of the switch SR2 is connected to the different end of the winding s;
  • an auxiliary voltage circuit that outputs an auxiliary voltage to the winding a such that the effect of the magnetic flux generated by the auxiliary voltage on the current on the winding L counteracts the effect of the change in the flux of the winding p on the current on the winding L.
  • the output rectification and filtering circuit comprises a resistor R and a capacitor Co.
  • the positive terminal of the capacitor Co is connected to one end of the resistor R and serves as a positive terminal of the output rectifying and filtering circuit; the negative terminal of the capacitor Co is connected to the other end of the resistor R and serves as The negative terminal of the output rectification filter circuit.
  • the auxiliary voltage circuit comprises a sampling/operation circuit U1, a capacitor Ca, a switch tube G1 and a switch tube G2; the first input end of the sampling/operation circuit U1 is connected to the positive end of the capacitor Cr, and the sampling/operation circuit U1 The second input end is connected to the negative end of the capacitor Cr, the third input end of the sampling/operation circuit U1 is connected to the positive end of the capacitor Co, and the fourth input end of the sampling/operation circuit U1 is connected to the negative end of the capacitor Co; the sampling/operation circuit U1 The forward output end is connected to the same end of the winding a and the negative end of the capacitor Ca.
  • the positive end of the capacitor Ca is connected to the drain of the switch G1; the source of the switch G1 is respectively connected to the drain and winding of the switch G2.
  • the different name ends of a are connected; the source of the switching transistor G2 is connected to the negative phase output terminal of the sampling/operation circuit U1, and is connected to the negative terminal of the input voltage Vin.
  • the auxiliary voltage circuit comprises a sampling/operation circuit U1, a capacitor Ca, a switch tube G1 and a switch tube G2; the first input end of the sampling/operation circuit U1 is connected to the gate of the switch tube Q1, and the sampling/operation circuit U1 The second input end is connected to the source of the switch tube Q1, the third input end of the sampling/operation circuit U1 is connected to the positive end of the input voltage Vin, and the fourth input end of the sampling/operation circuit U1 is connected to the negative end of the input voltage Vin; sampling The forward output end of the /operation circuit U1 is connected to the same end of the winding a and the negative end of the capacitor Ca, and the positive end of the capacitor Ca is connected to the drain of the switch G1; the source of the switch G1 is respectively connected to the switch G2 The drain and the abbreviated end of the winding a are connected; the source of the switching transistor G2 is connected to the negative phase output terminal of the sampling/operation circuit U1, and is connected to the negative terminal of the input voltage Vin.
  • the driving of the switch tube Q1 and the switch tube Q2 is complementary, and the driving of the switch tube Q1, the switch tube G1 and the switch tube SR2 is the same, and the driving of the switch tube Q2, the switch tube G2 and the switch tube SR1 is identical.
  • the solution proposed by the invention overcomes the shortcomings of the prior art switching converter, and when the input voltage range is wide, the output zero ripple can be realized in the full input voltage range.
  • FIG. 1 is a schematic circuit diagram of a conventional magnetic integration to realize single voltage zero ripple
  • FIG. 2 is a schematic diagram of a power stage of the present invention
  • FIG. 3 is a schematic diagram of an auxiliary voltage according to a first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an auxiliary voltage according to a second embodiment of the present invention.
  • the inventive concept of the present invention is to increase the magnetic circuit, construct a new magnetic flux by using a voltage, and cancel the influence of the magnetic flux in the original transformer on the output current by the newly added magnetic flux, thereby realizing zero ripple.
  • the converter of the present invention is composed of a power stage circuit and an auxiliary voltage circuit.
  • the power stage circuits of both embodiments are identical except that the auxiliary voltage is implemented differently.
  • FIG. 2 is a schematic diagram of a power stage of a first embodiment of a zero ripple circuit of the present invention.
  • the transformer structure of the zero ripple circuit of the present invention is as follows:
  • the transformer has four magnetic columns, which are a first magnetic column 1, a second magnetic column 2, a third magnetic column 3, and a fourth magnetic column 4.
  • the winding p is wound on the magnetic column 1 of the transformer, the number of turns is Np
  • the winding s is wound on the magnetic column 1 of the transformer, the number of turns is Ns
  • the winding a is wound on the transformer magnetic column 2
  • the number of turns is Na
  • There is no winding on the 3 and the winding L is wound on the transformer magnetic column 4, and the number of turns is N L .
  • connection relationship of the power stage circuit of the zero ripple circuit of the present invention is as follows:
  • the positive terminal of the input voltage Vin is connected to the same end of the winding p
  • the different name of the winding p is connected to the drain of the switch Q1
  • the source of the switch Q1 is connected to the negative terminal of the input voltage Vin.
  • the drain of the switch Q1 is connected to the source of the switch Q2
  • the drain of the switch Q2 is connected to the positive terminal of the capacitor Cr
  • the negative terminal of the capacitor Cr is connected to the positive terminal of the input voltage Vin.
  • the same name end of the winding s is connected to the same end of the winding L.
  • the different name end of the winding L is connected to the positive end of the output capacitor Co.
  • the negative end of the output capacitor Co is connected to the source of the switch SR2, and the drain and winding s of the switch SR2
  • the synonyms are connected.
  • the same name end of the winding s is connected to the drain of the switch SR1, and the source of the switch SR1 is connected to the negative end of the output capacitor Co.
  • One end of the load resistor R is connected to the positive terminal of the output capacitor Co, and the other end is connected to the negative terminal of the output capacitor Co.
  • FIG. 3 is a schematic diagram of a first embodiment of an auxiliary voltage circuit of a zero ripple circuit of the present invention.
  • connection relationship of the auxiliary voltage circuit of the zero ripple circuit of the present invention is as follows:
  • the positive end of the capacitor Cr is connected to the first input end of the sampling/operation circuit U1
  • the negative end of the capacitor Cr is connected to the second input end of the sampling/operation circuit U1
  • the positive end of the output capacitor Co and the first of the sampling/operation circuit U1 The three input terminals are connected, and the negative end of the output capacitor Co is connected to the fourth input end of the sampling/operation circuit U1.
  • the forward output end of the sampling/operation circuit U1 is connected to the same name end of the power stage winding a, and the different name end of the winding a
  • the source of the switch G2 and the negative phase output of the sampling/operation circuit U1 the forward output of the sampling/operation circuit U1 is connected to the negative terminal of the capacitor Ca, and the positive terminal of the capacitor Ca and the switch
  • the drain of G1 is connected, the source of switch G1 is connected to the drain of switch G2, and the negative output of sampling/operation circuit U1 is connected to the negative terminal of input voltage Vin.
  • the process of generating the auxiliary voltage Vax is as follows.
  • the voltage Vcr of the sampling capacitor Cr and the sampling output voltage Vo are used to obtain the auxiliary voltage according to the proportional difference circuit. Since the number of turns Na of the winding a, the number of turns N L of the winding L , the number of turns Np of the winding p, the magnetic resistance R m3 of the magnetic column 3, and the magnetic resistance R m4 of the magnetic column 4 are known, the voltage Vax is known. It is obtained by multiplying the clamp capacitor voltage Vcr and the output voltage Vo by a fixed proportional coefficient and then finding the difference. Since the proportional circuit and the difference circuit are common knowledge in the industry, no specific circuit is given here.
  • the auxiliary voltage Vax can be generated by the control chip or by using discrete components to build the circuit.
  • the gates of the switching transistors Q1, Q2, SR1, SR2, G1, and G2 of this embodiment are respectively connected to an external driving signal, wherein the driving of the switch Q1 and the switch Q2 are complementary, and the driving of the switch Q1, the switch G1, and the switch SR2 are the same.
  • the driving of the switch Q2, the switch G2, and the switch SR1 is the same.
  • the amount of change of the current on the winding L in one cycle must be zero. Therefore, the amount of change of the current of the winding L in the turn-on phase of the switch G2 is equal to the amount of change in the turn-off phase of the switch G2. In the opposite direction.
  • the magnetic flux generated by the auxiliary voltage Vax on the magnetic core through the winding a affects the magnetic flux on the magnetic column 4, and the magnetic flux cancels the influence of the magnetic flux generated by the winding p on the current of the winding L
  • the current on the winding L is kept constant, that is, the phase of the switch G2 is turned on, and the current on the winding L does not change. Since the amount of change in the turn-on phase and the turn-off phase of the switch G2 is equal, the current change amount of the winding L does not change in the phase in which the switch G2 is turned off. In summary, the current of the winding L is constant throughout the period, and the output voltage Vo does not fluctuate.
  • the air gap on the four magnetic columns of the transformer is processed according to the magnitude of the magnetic resistance.
  • the output voltage also has a certain small ripple.
  • the input voltage of a switching converter is 9 ⁇ 36V, the output voltage is 5V, the output maximum current is 10A, the switching frequency is 330kHz, the output capacitance is 1uF, and the parasitic resistance of the output capacitor is 10m ⁇ .
  • the original scheme is used when the input voltage is 10.7V.
  • the output voltage ripple obtained by the simulation is 2.5mV.
  • the input voltage is 36V
  • the output voltage ripple is 60mV.
  • the output voltage ripple is 1.3mV.
  • the output voltage ripple is 2.5mV, which achieves zero ripple output in the full voltage range.
  • FIG. 4 is a schematic diagram of a second embodiment of an auxiliary voltage of a zero ripple circuit of the present invention.
  • connection relationship of the auxiliary voltage circuit of the zero ripple circuit of the present invention is as follows:
  • the gate of the switch Q1 is connected to the first input end of the sampling/operation circuit U2, the source of the switch Q1 is connected to the second input end of the sampling/operation circuit U2, and the positive end of the input voltage Vin and the first end of the sampling/operation circuit U2
  • the three input terminals are connected, the negative end of the input voltage Vin is connected to the fourth input end of the sampling/operation circuit U2, and the forward output end of the sampling/operation circuit U2 is connected to the same name end of the power stage winding a, and the different name end of the winding a
  • the source of the switch G2 and the negative phase output of the sampling/operation circuit U2 the forward output of the sampling/operation circuit U2 is connected to the negative terminal of the capacitor Ca, and the positive terminal of the capacitor Ca and the switch
  • the drain of G1 is connected, the source of switch G1 is connected to the drain of switch G2, and the negative output of sampling/operation circuit U1 is connected to the negative terminal of input voltage Vin.
  • the power stage schematic diagram of the second embodiment is the same as the first embodiment except that the implementation of the auxiliary voltage Vax is different.
  • the calculation formula in this embodiment is The clamp voltage Vax is obtained by sampling the input voltage Vin and the duty ratio D of the drive signal drvQ1 of the switch Q1, and then performing a mathematical operation. Since conventional mathematical operations on a given voltage are common knowledge in the industry, they are not given here. Specific circuit.
  • the auxiliary voltage Vax can be generated by the control chip or by using discrete components to build the circuit.

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Abstract

一种输出零纹波变换器，改变变压器的磁芯形状，在原来的变压器结构基础上增加一磁柱，将三磁柱的磁芯变为四磁柱的磁芯。然后，在增加的磁柱上添加一绕组，在绕组中上加入合适的电压，让添加的电压产生的磁通抵消原来磁通的对输出电流纹波的影响，使得可以实现输出零纹波。克服了现有开关变换器的不足，当输入电压范围较宽时，可在全输入电压范围内实现输出零纹波。

Description

一种输出零纹波变换器 技术领域
本发明涉及一种输出零纹波变换器。
背景技术
在传统的开关变换器中，由于电压在输出端磁性元器件上的跳变，往往会引起电流波动，这会使得输出电压存在纹波。由于纹波的存在，要选择容量大一点的电容，使输出电压的波动在可接受范围内。
若变换器能实现输出零纹波，则可以减小输出电容，而且纹波降为零，开关电源传输到负载的噪声也会相应减小。陈乾宏在论文《输出纹波最小化有源箝位正激磁集成变换器》中提出了磁集成ACF变换器，将正激变换器中的电感与变压器集成到一个磁芯上，该集成方案对固定的输入电压和输出电压，可以实现输出零纹波。
上述方案存在不足，当输入电压范围较宽时，该方案在不同的输入电压下有不同的输出电压纹波，不能在全输入电压范围内实现零纹波。在上述方案后，有不少方案改进了变压器绕组的绕制位置以及电路，改善了变换器的整体性能，但都未能在全输入电压范围内实现零纹波输出。
发明内容
有鉴于此，本发明解决的技术问题是克服现有方法的不足，提出一种输出零纹波变换器，在较宽的输入电压范围内实现输出零纹波。
本发明解决上述技术问题的技术方案如下：
首先，改变变压器的磁芯形状，在原来的变压器结构基础上增加一磁柱，将三磁柱的磁芯变为四磁柱的磁芯。然后，在增加的磁柱上添加一绕组，在绕组中上加入合适的电压，让添加的电压产生的磁通抵消原来磁通的对输出电流纹波的影响，使得可以实现输出零纹波。
一种输出零纹波变换器，包括主功率级电路，所述的主功率级电路包括一变压器、开关管Q1、开关管Q2、开关管SR1、开关管SR2、电容Cr和输出整流滤波电路；
所述的变压器有四根磁柱，分别为第一磁柱、第二磁柱、第三磁柱和第四磁柱；第一磁柱上绕制绕组p和绕组s，第二磁柱上绕制绕组a，第三磁柱上没有绕组，第四磁柱上绕制绕组L；
输入电压Vin的正端分别与绕组p的同名端和电容Cr的负端相连，绕组p的异名端分别与开关管Q1的漏极和开关管Q2的源极相连，开关管Q1的源极与输入电压Vin的负端相连；开关Q2的漏极与电容Cr的正端相连；绕组s的同名端分别与绕组L的同名端和开关管SR1的漏极相连，绕组L的异名端与输出整流滤波电路的正端相连，开关管SR2的源极和开关管SR1的源极与输出整流滤波电路的负端相连，开关SR2的漏极与绕组s的异名端相连；
还包括一个辅助电压电路，所述的辅助电压电路输出辅助电压给绕组a，使辅助电压产生的磁通对绕组L上电流的影响抵消了绕组p磁通的变化对绕组L上电流的影响。
优选的，所述的输出整流滤波电路包括电阻R和电容Co，电容Co的正端连接电阻R的一端并作为输出整流滤波电路的正端；电容Co的负端连接电阻R的另一端并作为输出整流滤波电路的负端。
优选的，所述的辅助电压电路包括采样/运算电路U1、电容Ca、开关管G1和开关管G2；采样/运算电路U1的第一输入端连接电容Cr的正端，采样/运算电路U1的第二输入端连接电容Cr的负端，采样/运算电路U1的第三输入端连接电容Co的正端，采样/运算电路U1的第四输入端连接电容Co的负端；采样/运算电路U1的正向输出端分别与绕组a的同名端、电容Ca的负端相连，电容Ca的正端与开关管G1的漏极相连；开关管G1的源极分别与开关管G2的漏极、绕组a的异名端相连；开关管G2的源极与采样/运算电路U1的负相输出端相连，并且连接到输入电压Vin的负端。
优选的，所述的辅助电压电路包括采样/运算电路U1、电容Ca、开关管G1和开关管G2；采样/运算电路U1的第一输入端连接开关管Q1的栅极，采样/运算电路U1的第二输入端连接开关管Q1的源极，采样/运算电路U1的第三输入端连接输入电压Vin的正端，采样/运算电路U1的第四输入端连接输入电压Vin的负端；采样/运算电路U1的正向输出端分别与绕组a的同名端、电容Ca的负端相连，电容Ca的正端与开关管G1的漏极相连；开关管G1的源极分别与开关管G2的漏极、绕组a的异名端相连；开关管G2的源极与采样/运算电路U1的负相输出端相连，并且连接到输入电压Vin的负端。
优选的，所述的开关管Q1和开关管Q2的驱动是互补的，开关管Q1、开关管G1以及开关管SR2的驱动是相同的，开关管Q2、开关管G2以及开关管SR1的驱动是相同的。
本发明所提的方案，克服了现有开关变换器的不足，当输入电压范围较宽时，可在全输入电压范围内实现输出零纹波。
附图说明
图1为现有磁集成实现单电压零纹波的电路原理图；
图2为本发明的功率级原理图；
图3为本发明第一实施例辅助电压原理图；
图4为本发明第二实施例辅助电压原理图。
具体实施方式
本发明的发明构思为增加磁路，利用电压构造新磁通，将新添加的磁通抵消原来变压器中磁通对输出电流的影响，从而实现零纹波。
本发明的变换器由功率级电路以及辅助电压电路构成。本发明有两个实施例，两个实施例的功率级电路都是相同的，只是辅助电压的实现方式不一样。
第一实施例
图2为本发明零纹波电路的第一实施例功率级原理图。
本发明零纹波电路的变压器结构如下：
变压器有四根磁柱，分别为第一磁柱1、第二磁柱2、第三磁柱3和第四磁柱4。变压器的磁柱1上绕制绕组p，匝数为Np，变压器的磁柱1上绕制绕组s，匝数为Ns，变压器磁柱2上绕制绕组a，匝数为Na，变压器磁柱3上没有绕组，变压器磁柱4上绕制绕组L，匝数为N L。
本发明零纹波电路的功率级电路的连接关系如下：
输入电压Vin的正端与绕组p的同名端相连，绕组p的异名端与开关Q1的漏极相连，开关Q1的源极与输入电压Vin的负端相连。开关Q1的漏极与开关Q2的源极相连，开关Q2的漏极与电容Cr的正端相连，电容Cr的负端与输入电压Vin的正端相连。绕组s的同名端与绕组L的同名端相连，绕组L的异名端与输出电容Co的正端相连，输出电容Co的负端与开关SR2的源极相连，开关SR2的漏极与绕组s的异名端相连。绕组s的同名端与开关SR1的漏极相连，开关SR1的源极与输出电容Co的负端相连。负载电阻R一端接在输出电容Co的正端，另一端接在输出电容Co的负端。
图3为本发明零纹波电路的辅助电压电路第一实施例原理图。
本发明零纹波电路的辅助电压电路的连接关系如下：
电容Cr的正端与采样/运算电路U1的第一输入端相连，电容Cr的负端与采样/运算电路U1的第二输入端相连，输出电容Co的正端与采样/运算电路U1的第三输入端相连，输 出电容Co的负端与采样/运算电路U1的第四输入端相连，采样/运算电路U1的正向输出端与功率级绕组a的同名端相连，绕组a的异名端与开关G2的漏极相关，开关G2的源极与采样/运算电路U1的负相输出端，采样/运算电路U1的正向输出端与电容Ca的负端相连，电容Ca的正端与开关G1的漏极相连，开关G1的源极与开关G2的漏极相连；采样/运算电路U1的负相输出端连接到输入电压Vin的负端。
辅助电压Vax的产生过程如下，通过采样电容Cr的电压Vcr，以及采样输出电压Vo，根据比例求差电路，得到辅助电压
Figure PCTCN2019070643-appb-000001
由于绕组a的匝数Na、绕组L的匝数N L、绕组p的匝数Np、磁柱3的磁阻R m3、磁柱4的磁阻R m4都是已知的，因此，电压Vax是通过箝位电容电压Vcr和输出电压Vo乘以一固定比例系数后求差求出来的，由于比例电路以及求差电路都是业界公知常识，因此这里不给出具体的电路。辅助电压Vax可以由控制芯片产生，也可以用分立元器件搭建电路产生。
该实施例的开关管Q1、Q2、SR1、SR2、G1、G2的栅极分别连接外部驱动信号，其中开关Q1和开关Q2的驱动是互补的，开关Q1、开关G1以及开关SR2的驱动是相同的，开关Q2、开关G2以及开关SR1的驱动是相同的。本发明实现零纹波的过程如下：
达到稳定状态后，绕组L上的电流在一个周期内的变化量一定为零，因此，绕组L的电流在开关G2开通阶段的变化量，与开关G2关断阶段的变化量相比，大小相等，方向相反。
在开关G2开通的阶段，辅助电压Vax通过绕组a在磁芯上产生的磁通会影响磁柱4上的磁通，该磁通抵消了绕组p产生的磁通对绕组L的电流的影响，使得绕组L上的电流维持不变，即开关G2开通的阶段，绕组L上的电流不变。由于开关G2开通阶段和关断阶段的变化量大小相等，因此开关G2关断的阶段，绕组L的电流变化量也不变。综上所述可知，绕组L的电流在整个周期里是不变的，输出电压Vo不会产生波动。
变压器四根磁柱上的气隙根据磁阻的大小进行加工。
实际过程中，由于参数偏差，辅助绕组a产生的磁通不一定能完全抵消绕组p对绕组L的电流的影响，因此，实际过程中，输出电压也会存在着一定的小纹波。
某开关变换器输入电压为9～36V，输出电压为5V，输出最大电流为10A，开关频率330kHz，输出电容1uF，输出电容的寄生电阻为10mΩ，采用原方案，在输入电压为10.7V时，仿真得到的输出电压纹波为2.5mV，当输入电压为36V时，输出电压纹波为60mV，采 用本发明所提方案后，当输入电压为10.7V时，输出电压纹波为1.3mV，当输入电压为36V时，输出电压纹波为2.5mV，近似在全电压范围内实现零纹波输出。
第二实施例
图4为本发明零纹波电路的辅助电压第二实施例原理图。
本发明零纹波电路的辅助电压电路的连接关系如下：
开关Q1的栅极与采样/运算电路U2的第一输入端相连，开关Q1的源极与采样/运算电路U2的第二输入端相连，输入电压Vin的正端与采样/运算电路U2的第三输入端相连，输入电压Vin的负端与采样/运算电路U2的第四输入端相连，采样/运算电路U2的正向输出端与功率级绕组a的同名端相连，绕组a的异名端与开关G2的漏极相关，开关G2的源极与采样/运算电路U2的负相输出端，采样/运算电路U2的正向输出端与电容Ca的负端相连，电容Ca的正端与开关G1的漏极相连，开关G1的源极与开关G2的漏极相连；采样/运算电路U1的负相输出端连接到输入电压Vin的负端。
第二实施例的功率级原理图与第一实施例相同，只是辅助电压Vax的实施方式不同，本实施例中的计算公式为
Figure PCTCN2019070643-appb-000002
钳位电压Vax是通过采样输入电压Vin和开关Q1的驱动信号drvQ1的占空比D，然后进行数学运算得到的，由于对给定电压进行常规的数学运算是业界公知常识，因此这里不给出具体的电路。辅助电压Vax可以由控制芯片产生，也可以用分立元器件搭建电路产生。
以上仅是本发明优选的实施方式，本发明所属领域的技术人员还可以对上述具体实施方式进行变更和修改。因此，本发明并不局限于上面揭示和描述的具体控制方式，对本发明的一些修改和变更也应当落入本发明的权利要求的保护范围内。此外，尽管本说明书中使用了一些特定的术语，但这些术语只是为了方便说明，并不对本发明构成任何限制。

Claims (6)

  1. 一种输出零纹波变换器，包括主功率级电路，所述的主功率级电路包括一变压器、开关管Q1、开关管Q2、开关管SR1、开关管SR2、电容Cr和输出整流滤波电路；
    所述的变压器有四根磁柱，分别为第一磁柱、第二磁柱、第三磁柱和第四磁柱；第一磁柱上绕制绕组p和绕组s，第二磁柱上绕制绕组a，第三磁柱上没有绕组，第四磁柱上绕制绕组L；
    输入电压Vin的正端分别与绕组p的同名端和电容Cr的负端相连，绕组p的异名端分别与开关管Q1的漏极和开关管Q2的源极相连，开关管Q1的源极与输入电压Vin的负端相连；开关Q2的漏极与电容Cr的正端相连；绕组s的同名端分别与绕组L的同名端和开关管SR1的漏极相连，绕组L的异名端与输出整流滤波电路的正端相连，开关管SR2的源极和开关管SR1的源极与输出整流滤波电路的负端相连，开关SR2的漏极与绕组s的异名端相连；
    其特征在于：还包括一个辅助电压电路，所述的辅助电压电路输出辅助电压给绕组a，使辅助电压产生的磁通对绕组L上电流的影响抵消了绕组p磁通的变化对绕组L上电流的影响。
  2. 根据权利要求1所述的一种输出零纹波变换器，其特征在于：所述的输出整流滤波电路包括电阻R和电容Co，电容Co的正端连接电阻R的一端并作为输出整流滤波电路的正端；电容Co的负端连接电阻R的另一端并作为输出整流滤波电路的负端。
  3. 根据权利要求2所述的一种输出零纹波变换器，其特征在于：所述的辅助电压电路包括采样/运算电路U1、电容Ca、开关管G1和开关管G2；采样/运算电路U1的第一输入端连接电容Cr的正端，采样/运算电路U1的第二输入端连接电容Cr的负端，采样/运算电路U1的第三输入端连接电容Co的正端，采样/运算电路U1的第四输入端连接电容Co的负端；采样/运算电路U1的正向输出端分别与绕组a的同名端、电容Ca的负端相连，电容Ca的正端与开关管G1的漏极相连；开关管G1的源极分别与开关管G2的漏极、绕组a的异名端相连；开关管G2的源极与采样/运算电路U1的负相输出端相连，并且连接到输入电压Vin的负端。
  4. 根据权利要求2所述的一种输出零纹波变换器，其特征在于：所述的辅助电压电路包括采样/运算电路U1、电容Ca、开关管G1和开关管G2；采样/运算电路U1的第一输入端连接开关管Q1的栅极，采样/运算电路U1的第二输入端连接开关管Q1的源极，采样/运算 电路U1的第三输入端连接输入电压Vin的正端，采样/运算电路U1的第四输入端连接输入电压Vin的负端；采样/运算电路U1的正向输出端分别与绕组a的同名端、电容Ca的负端相连，电容Ca的正端与开关管G1的漏极相连；开关管G1的源极分别与开关管G2的漏极、绕组a的异名端相连；开关管G2的源极与采样/运算电路U1的负相输出端相连，并且连接到输入电压Vin的负端。
  5. 根据权利要求2或3所述的一种输出零纹波变换器，其特征在于：所述的开关管Q1和开关管Q2的驱动是互补的，开关管Q1、开关管G1以及开关管SR1的驱动是相同的，开关管Q2、开关管G2以及开关管SR2的驱动是相同的。
  6. 一种变换器输出零纹波的方法，其特征在于：在原有三磁柱的磁芯的变压器结构基础上增加一磁柱，变为四磁柱的磁芯；在增加的磁柱上添加一绕组；在绕组中上添加辅助电压，通过添加的电压产生的磁通抵消原有磁通的对输出电流纹波的影响，实现输出零纹波。
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