WO2019205198A1 - 液晶面板驱动电路及液晶面板 - Google Patents

液晶面板驱动电路及液晶面板 Download PDF

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Publication number
WO2019205198A1
WO2019205198A1 PCT/CN2018/086899 CN2018086899W WO2019205198A1 WO 2019205198 A1 WO2019205198 A1 WO 2019205198A1 CN 2018086899 W CN2018086899 W CN 2018086899W WO 2019205198 A1 WO2019205198 A1 WO 2019205198A1
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Prior art keywords
resistor
liquid crystal
crystal panel
transistor
driving circuit
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PCT/CN2018/086899
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English (en)
French (fr)
Inventor
张先明
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/072,665 priority Critical patent/US11087704B2/en
Publication of WO2019205198A1 publication Critical patent/WO2019205198A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present invention relates to the field of electronic circuits, and in particular, to a liquid crystal panel driving circuit and a liquid crystal panel.
  • the liquid crystal panel driving circuit for driving the operation of the liquid crystal panel includes a pulse width modulation integrated circuit (PWM IC), and the commonly used PWMIC has an under voltage lockout (UVLO) voltage, that is, the input voltage is high. At this value, the PWMIC starts to work. When the input voltage is lower than this value, the PWMIC turns off and there is no more output.
  • PWM IC pulse width modulation integrated circuit
  • UVLO under voltage lockout
  • An object of the present invention is to provide a liquid crystal panel driving circuit with good reliability and excellent customer experience.
  • the present invention provides a liquid crystal panel driving circuit including a pulse width modulation integrated circuit, the pulse width modulation integrated circuit including an input terminal, a first resistor, a second resistor, a comparator, a light emitting diode, and a latch Device, RC circuit and power supply voltage;
  • the input end is connected to the ground end via the first resistor and the second resistor connected in series with each other;
  • a positive input terminal of the comparator is connected to a reference voltage, and a negative input terminal of the comparator is connected between the first resistor and the second resistor;
  • the anode of the light emitting diode is connected to the output of the comparator, and the cathode of the light emitting diode is connected to the latch;
  • the RC circuit input and output are coupled to the supply voltage and the latch, respectively.
  • the RC circuit includes a third resistor and a capacitor, a first end of the third resistor is connected to the power voltage, and a second end of the third resistor is connected to the first end of the capacitor; The second end of the third resistor and the second end of the capacitor are electrically connected to the latch, respectively.
  • the latch includes a first transistor, a second transistor, a fourth resistor, and a fifth resistor;
  • a base of the first transistor is coupled to a collector of the second transistor, an emitter of the first transistor is coupled to a second end of the third resistor of the RC circuit, the first transistor a collector is connected to the ground via the fifth resistor and a collector of the first transistor is connected to a cathode of the diode;
  • a base of the second transistor is coupled to a collector of the first transistor and serves as an output, an emitter of the second transistor is coupled to a second end of the capacitor of the RC circuit and simultaneously connected to a ground And a first end of the fourth resistor is connected to a base of the first transistor, and a second end of the fourth resistor is connected to an emitter of the first transistor.
  • the liquid crystal panel driving circuit further includes a logic gate and a logic AND gate, the output terminal is connected to the input of the logic gate; the first input of the logic AND gate is connected to the logic gate Output, the logic and the second input of the gate are connected to a low level voltage signal, and the output of the logic AND gate is used as an output of the liquid crystal panel driving circuit.
  • the liquid crystal panel driving circuit adjusts its discharge time by adjusting the size of the third resistor and the capacitor.
  • the first transistor and the second transistor are both PNP type transistors.
  • the power supply voltage is 3.3V.
  • the present invention also provides a liquid crystal panel having the above liquid crystal panel driving circuit.
  • the liquid crystal panel driving circuit of the present invention realizes the RC circuit by using the power supply voltage, and fully charges the capacitor in the RC circuit during normal operation of the liquid crystal panel driving circuit. Causing the output terminal to a high level, and when the output terminal voltage drops suddenly and falls below the undervoltage lockout voltage, through the latch and the logic gate and the logic AND gate, Turning off the output of the liquid crystal panel driving circuit, and enabling the power to be turned on again only when the power supply voltage falls below a safe point, ensuring that the liquid crystal panel driving circuit works normally and its output timing is not Disorder, thereby improving the reliability and user experience of the liquid crystal panel driving circuit.
  • FIG. 1 is a schematic diagram showing the circuit structure of a liquid crystal panel driving circuit of the present invention
  • FIG. 2 is a schematic view showing the circuit structure of an output end portion of a liquid crystal panel driving circuit of the present invention.
  • FIG. 1 is a circuit diagram of a liquid crystal panel driving circuit of the present invention.
  • the invention provides a liquid crystal panel driving circuit, comprising a pulse width modulation integrated circuit 10, wherein the pulse width modulation integrated circuit 10 comprises an input terminal VIN, a first resistor R1, a second resistor R2, a comparator A, a light emitting diode D, and a lock.
  • the input terminal VIN is connected to the ground terminal via the first resistor R1 and the second resistor R2 which are sequentially connected in series with each other.
  • the positive input terminal of the comparator A is connected to the reference voltage Vref1, and the negative input terminal of the comparator A is connected between the first resistor R1 and the second resistor R2.
  • the anode of the light emitting diode D is connected to the output of the comparator A, and the cathode of the light emitting diode D is connected to the latch 1.
  • the working principle of the liquid crystal panel driving circuit is: when the signal of the input terminal VIN is powered off, the liquid crystal panel driving circuit detects the main output voltage and determines whether the output voltage has dropped to a safe point. The next restart can be started to ensure that the output timing of the voltage is not disordered and normal operation is guaranteed.
  • the liquid crystal panel driving circuit may specifically include a pulse width modulation integrated circuit 10, and the specific circuit is as follows:
  • the input and output of the RC circuit 2 are connected to the power supply voltage VDD and the latch 1, respectively.
  • the power supply voltage VDD is 3.3V.
  • the latch 1 includes a first transistor T1, a second transistor, a fourth resistor R4, and a fifth resistor R5. More preferably, the first transistor T1 and the second transistor T2 are both PNP type transistors.
  • the RC circuit 2 includes a third resistor R3 and a capacitor C, that is, the third resistor R3 and the capacitor C together constitute the RC circuit 2.
  • the structure of the RC circuit 2 is not limited to this.
  • the first end of the third resistor R3 is connected to the power supply voltage VDD
  • the second end of the third resistor R3 is connected to the first end of the capacitor C
  • the second end of the third resistor R3 is The second end of the capacitor C is electrically connected to the latch 1 respectively.
  • a base of the first transistor T1 is connected to a collector of the second transistor T2, and an emitter of the first transistor T1 is connected to a second end of the third resistor R3 of the RC circuit 2,
  • the collector of the first transistor T1 is connected to the ground via the fifth resistor R5 and the collector of the first transistor T1 is connected to the cathode of the diode D.
  • a base of the second transistor T2 is connected to a collector of the first transistor T1 and serves as an output terminal EN1 of the liquid crystal panel driving circuit, and an emitter of the second transistor T2 is connected to the RC circuit 2
  • the second end of the capacitor C is connected to the ground end
  • the first end of the fourth resistor R4 is connected to the base of the first transistor T1
  • the second end of the fourth resistor R4 is connected to the ground
  • the emitter of the first transistor T1 is described.
  • the liquid crystal panel driving circuit further includes a logic gate 3 and a logic AND gate 4, the output terminal EN1 is connected to the input of the logic gate 3; the first input of the logic AND gate 4 is connected to The output of the logic gate 3 is connected to the second input of the gate 4 by a low level voltage signal VL, and the output of the logic AND gate 4 is used as an output of the liquid crystal panel driving circuit.
  • the above circuit structure causes the output signal of the output terminal EN1 to pass through the logic NOT gate 3 and then output the signal through the logic AND gate 4 together with the low-level voltage signal VL.
  • the liquid crystal panel driving circuit can adjust the discharge time by adjusting the size of the third resistor R3 and the capacitor C.
  • the liquid crystal panel driving circuit of the present invention fully charges the capacitor C in the RC circuit 2 during the normal operation of the liquid crystal panel driving circuit by using the power supply voltage VDD and implementing the RC circuit 2, At this time, the comparator A outputs a low level, the latch 1 composed of the first transistor T1 and the second transistor T2 does not operate, and the output terminal EN1 is at a high level.
  • the output terminal EN1 When the liquid crystal panel driving circuit is turned on again, the output terminal EN1 outputs the same as 0, the latch 1 does not work, and the power supply voltage VDD voltage is 0. At this time, the output EN1 of the VDD starts to be High level, the entire liquid crystal panel driving circuit starts to work normally.
  • the liquid crystal panel driving circuit of the present invention By using the liquid crystal panel driving circuit of the present invention, if the input terminal VIN voltage suddenly drops below UVLO, all the liquid crystal panel driving circuits are turned off by the latch 1, and the logic NOT gate 3 and the logic AND gate 4. (ie, PWMIC) output, the liquid crystal panel driving circuit has the ability to be turned on again only when the voltage of the power supply voltage VDD falls below a safe point, regardless of whether the input terminal VIN voltage exceeds UVLO or Below UVLO, you can restart the boot only if you exceed UVLO again.
  • the liquid crystal panel driving circuit can ensure that all output voltages are reduced to a safe point before the next power-on, so that the output timing is not disordered and the normal operation is ensured.
  • the liquid crystal panel driving circuit can adjust the discharge time of the third resistor R3 and the capacitor C to ensure that the output voltage has been discharged when the power is turned on again.
  • the liquid crystal panel driving circuit of the present invention realizes the RC circuit by using the power supply voltage, and fully charges the capacitor in the RC circuit during normal operation of the liquid crystal panel driving circuit. Causing the output terminal to a high level, and when the output terminal voltage drops suddenly and falls below the undervoltage lockout voltage, through the latch and the logic gate and the logic AND gate, Turning off the output of the liquid crystal panel driving circuit, and enabling the power to be turned on again only when the power supply voltage falls below a safe point, ensuring that the liquid crystal panel driving circuit works normally and its output timing is not Disorder, thereby improving the reliability and user experience of the liquid crystal panel driving circuit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶面板驱动电路，包括输入端(VIN)、第一电阻(R1)、第二电阻(R2)、比较器(A)、发光二极管(D)、锁存器(1)、RC电路(2)以及电源电压(VDD)；该输入端(VIN)经依次相互串联的第一电阻(R1)和第二电阻(R2)连接至接地端；该比较器(A)的正输入端连接至参考电压(Vref1)，该比较器的负输入端连接至第一电阻(R1)与第二电阻(R2)之间；该发光二极管(D)的正极连接至比较器(A)的输出，该发光二极管(D)的负极连接至锁存器(1)；该RC电路(2)输入和输出分别连接至电源电压(VDD)和锁存器(1)。该液晶面板驱动电路可靠性好且使用户体验效果优。

Description

液晶面板驱动电路及液晶面板 技术领域
本发明涉及一种电子电路领域，尤其涉及一种液晶面板驱动电路及液晶面板。
背景技术
随着显示技术的发展，对于电视、电影等，人们越来越多的追求立体显示的逼真体验效果，而液晶面板则是实现立体显示的主要部件。用于驱动液晶面板工作的液晶面板驱动电路中包括脉宽调制集成电路(PWM IC)，常使用的PWMIC来说，其有一个欠压锁定(Under Voltage Lock Out，UVLO)电压，即输入电压高于此值时，PWMIC开始工作，输入电压低于此值时，PWMIC关闭，不再有输出。
然而，我们使用电视的过程中会遇到市电不稳的状况，导致电压有突降然后恢复，由于这个电压突降的时间太短，PWMIC只是瞬间关闭而后重新启动，这个时候各个输出的电压都不能放电完全。特别是针对于屏驱动板(Timing Controller，TCON)，如果电源电压VDD3.3V，以及核心电压Vcore没有放电完全，再重新开机，就有可能会引发时序紊乱，导致输出异常，出现画异，甚至导致液晶面板出现不可逆的损伤，严重影响用户体验。
因此，有必要提供一种新的液晶面板驱动电路以解决上述问题。
发明内容
本发明的目的在于提供一种可靠性好，客户体验效果优的液晶面板驱动电路。
为了达到上述目的，本发明提供了一种液晶面板驱动电路，包括脉宽 调制集成电路，所述脉宽调制集成电路包括输入端、第一电阻、第二电阻、比较器、发光二极管、锁存器、RC电路以及电源电压；
所述输入端经依次相互串联的所述第一电阻和所述第二电阻连接至接地端；
所述比较器的正输入端连接至参考电压，所述比较器的负输入端连接至所述第一电阻与所述第二电阻之间；
所述发光二极管的正极连接至所述比较器的输出，所述发光二极管的负极连接至所述锁存器；
所述RC电路输入和输出分别连接至所述电源电压和所述锁存器。
优选的，所述RC电路包括第三电阻和电容，所述第三电阻的第一端与所述电源电压连接，所述第三电阻的第二端与所述电容的第一端连接；所述第三电阻的第二端及所述电容的第二端分别与所述锁存器电连接。
优选的，所述锁存器包括第一晶体管、第二晶体管、第四电阻及第五电阻；
所述第一晶体管的基极连接至所述第二晶体管的集电极，所述第一晶体管的发射极连接至所述RC电路的所述第三电阻的第二端，所述第一晶体管的集电极经所述第五电阻连接至接地端且所述第一晶体管的集电极连接至所述二极管的负极；
所述第二晶体管的基极连接至所述第一晶体管的集电极并作为输出端，所述第二晶体管的发射极连接至所述RC电路的所述电容的第二端且同时连接至接地端，所述第四电阻的第一端连接至所述第一晶体管的基极，所述第四电阻的第二端连接至所述第一晶体管的发射极。
优选的，所述液晶面板驱动电路还包括逻辑非门和逻辑与门，所述输出端连接至所述逻辑非门的输入；所述逻辑与门的第一输入连接至所述逻辑非门的输出，所述逻辑与门的第二输入连接低电平电压信号，所述逻辑 与门的输出作为所述液晶面板驱动电路的输出。
优选的，所述液晶面板驱动电路通过调节所述第三电阻和所述电容的大小实现调整其放电时间。
优选的，所述第一晶体管和所述第二晶体管均为PNP型三极管。
优选的，所述电源电压为3.3V。
本发明还提供了一种具有上述液晶面板驱动电路的液晶面板。
与相关技术相比，本发明的液晶面板驱动电路通过使用所述电源电压实现一所述RC电路，在所述液晶面板驱动电路正常工作过程中给所述RC电路中的所述电容进行充满电，使所述输出端为高电平，当所述输出端电压突然下降且降至欠压锁定电压以下时，通过所述锁存器和所述逻辑非门与所述逻辑与门的作用，关闭所述液晶面板驱动电路的所述输出，且使得只有当所述电源电压降至安全点以下后，才具备再次开启的能力，保证了所述液晶面板驱动电路正常工作且其输出时序不会紊乱，从而提高了所述液晶面板驱动电路的可靠性和用户体验感。
附图说明
图1为本发明液晶面板驱动电路的电路结构示意图；
图2为本发明液晶面板驱动电路的输出端部分电路结构示意图。
具体实施方式
下面结合附图和实施方式对本发明作进一步说明。
请参阅图1，为本发明液晶面板驱动电路的电路结构示意图。本发明提供一种液晶面板驱动电路，包括脉宽调制集成电路10，所述脉宽调制集成电路10包括输入端VIN、第一电阻R1、第二电阻R2、比较器A、发光二极管D、锁存器1、RC电路2以及电源电压VDD。
所述输入端VIN经依次相互串联的所述第一电阻R1和所述第二电阻 R2连接至接地端。所述比较器A的正输入端连接至参考电压Vref1，所述比较器A的负输入端连接至所述第一电阻R1与所述第二电阻R2之间。所述发光二极管D的正极连接至所述比较器A的输出，所述发光二极管D的负极连接至所述锁存器1。
所述液晶面板驱动电路的工作原理为：在所述输入端VIN的信号掉电的时候，该液晶面板驱动电路对主要的输出电压进行侦测，判断其输出电压是否已经降至安全点，才可进行下一次的重启开机，从而保证电压的输出时序不会紊乱，保证正常工作。本实施方式中，所述液晶面板驱动电路可具体包括脉宽调制集成电路10，具体电路如下：
所述RC电路2输入和输出分别连接至所述电源电压VDD和所述锁存器1。具体的，所述电源电压VDD为3.3V。
本实施方式中，所述锁存器1包括第一晶体管T1、第二晶体管、第四电阻R4及第五电阻R5。更优的，所述第一晶体管T1和所述第二晶体管T2均为PNP型三极管。
本实施方式中，所述RC电路2包括第三电阻R3和电容C，即所述第三电阻R3和所述电容C共同构成所述RC电路2。当然，所述RC电路2的结构不限于此。所述第三电阻R3的第一端与所述电源电压VDD连接，所述第三电阻R3的第二端与所述电容C的第一端连接；所述第三电阻R3的第二端及所述电容C的第二端分别与所述锁存器1电连接。所述第一晶体管T1的基极连接至所述第二晶体管T2的集电极，所述第一晶体管T1的发射极连接至所述RC电路2的所述第三电阻R3的第二端，所述第一晶体管T1的集电极经所述第五电阻R5连接至接地端且所述第一晶体管T1的集电极连接至所述二极管D的负极。
所述第二晶体管T2的基极连接至所述第一晶体管T1的集电极并作为所述液晶面板驱动电路的输出端EN1，所述第二晶体管T2的发射极连接至所述RC电路2的所述电容C的第二端且同时连接至接地端，所述第四电阻R4的第一端连接至所述第一晶体管T1的基极，所述第四电阻R4 的第二端连接至所述第一晶体管T1的发射极。
更优的，所述液晶面板驱动电路还包括逻辑非门3和逻辑与门4，所述输出端EN1连接至所述逻辑非门3的输入；所述逻辑与门4的第一输入连接至所述逻辑非门3的输出，所述逻辑与门4的第二输入连接低电平电压信号VL，所述逻辑与门4的输出作为所述液晶面板驱动电路的输出。上述电路结构使得所述输出端EN1的输出信号经过所述逻辑非门3后再与低电平电压信号VL共同经所述逻辑与门4实现信号输出。
本实施方式中，所述液晶面板驱动电路可通过调节所述第三电阻R3和所述电容C的大小实现调整其放电时间。
本发明的液晶面板驱动电路通过使用所述电源电压VDD并实现一所述RC电路2，在所述液晶面板驱动电路正常工作过程中给所述RC电路2中的所述电容C进行充满电，此时所述比较器A输出为低电平，所述第一晶体管T1和所述第二晶体管T2组成的所述锁存器1不工作，所述输出端EN1为高电平。
当遇到所述输出端VIN电压突然下降，并降至欠压锁定(Under Voltage Lock Out，UVLO)电压以下的时候，其电压低于所述参考电压Vref1，所述比较器A输出为高电平，所有电压会关闭，此时所述第二晶体管T2导通，然后所述第一晶体管T1导通，所述锁存器1开始工作，直到所述电源电压VDD的电压掉至不能支持所述锁存器1的工作，此时，所述输出端EN1的电压逐渐趋近于0。
所述液晶面板驱动电路再次开机的时候，所述输出端EN1一样输出为0，所述锁存器1不工作，所述电源电压VDD电压为0，此时，所述VDD的输出EN1开始为高电平，整个所述液晶面板驱动电路开始正常工作。
通过使用本发明的液晶面板驱动电路，如果所述输入端VIN电压突然降低至UVLO以下，通过所述锁存器1，以及所述逻辑非门3和逻辑与 门4，关闭所有液晶面板驱动电路(也即PWMIC)的输出，只有当所述电源电压VDD的电压降至安全点以下后，所述液晶面板驱动电路才具备再次开启的能力，不管当时所述输入端VIN电压是超过UVLO或者在UVLO以下，只有再次超出UVLO则可重启开机。通过该液晶面板驱动电路可保证其所有输出电压降至安全点后才进行下一次开机，从而保证其输出时序不会紊乱，并保证其正常的工作。
为了进一步提高其可靠性，所述液晶面板驱动电路可通过调节所述第三电阻R3和所述电容C的大小实现调整其放电时间，以保证再次开机时输出电压都已放电完成。
与相关技术相比，本发明的液晶面板驱动电路通过使用所述电源电压实现一所述RC电路，在所述液晶面板驱动电路正常工作过程中给所述RC电路中的所述电容进行充满电，使所述输出端为高电平，当所述输出端电压突然下降且降至欠压锁定电压以下时，通过所述锁存器和所述逻辑非门与所述逻辑与门的作用，关闭所述液晶面板驱动电路的所述输出，且使得只有当所述电源电压降至安全点以下后，才具备再次开启的能力，保证了所述液晶面板驱动电路正常工作且其输出时序不会紊乱，从而提高了所述液晶面板驱动电路的可靠性和用户体验感。
以上所述的仅是本发明的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本发明创造构思的前提下，还可以做出改进，但这些均属于本发明的保护范围。

Claims (10)

  1. 一种液晶面板驱动电路，包括脉宽调制集成电路，其中，所述脉宽调制集成电路包括：输入端、第一电阻、第二电阻、比较器、发光二极管、锁存器、RC电路以及电源电压；
    所述输入端经依次相互串联的所述第一电阻和所述第二电阻连接至接地端；
    所述比较器的正输入端连接至参考电压，所述比较器的负输入端连接至所述第一电阻与所述第二电阻之间；
    所述发光二极管的正极连接至所述比较器的输出，所述发光二极管的负极连接至所述锁存器；
    所述RC电路输入和输出分别连接至所述电源电压和所述锁存器。
  2. 根据权利要求1所述的液晶面板驱动电路，其中，所述RC电路包括第三电阻和电容，所述第三电阻的第一端与所述电源电压连接，所述第三电阻的第二端与所述电容的第一端连接；所述第三电阻的第二端及所述电容的第二端分别与所述锁存器电连接。
  3. 根据权利要求2所述的液晶面板驱动电路，其中，所述锁存器包括第一晶体管、第二晶体管、第四电阻及第五电阻；
    所述第一晶体管的基极连接至所述第二晶体管的集电极，所述第一晶体管的发射极连接至所述RC电路的所述第三电阻的第二端，所述第一晶体管的集电极经所述第五电阻连接至接地端且所述第一晶体管的集电极连接至所述二极管的负极；
    所述第二晶体管的基极连接至所述第一晶体管的集电极并作为输出端，所述第二晶体管的发射极连接至所述RC电路的所述电容的第二端且 同时连接至接地端，所述第四电阻的第一端连接至所述第一晶体管的基极，所述第四电阻的第二端连接至所述第一晶体管的发射极。
  4. 根据权利要求3所述的液晶面板驱动电路，其中，所述液晶面板驱动电路还包括逻辑非门和逻辑与门，所述输出端连接至所述逻辑非门的输入；所述逻辑与门的第一输入连接至所述逻辑非门的输出，所述逻辑与门的第二输入连接低电平电压信号，所述逻辑与门的输出作为所述液晶面板驱动电路的输出。
  5. 根据权利要求3所述的液晶面板驱动电路，其中，所述液晶面板驱动电路通过调节所述第三电阻和所述电容的大小实现调整其放电时间。
  6. 根据权利要求4所述的液晶面板驱动电路，其中，所述液晶面板驱动电路通过调节所述第三电阻和所述电容的大小实现调整其放电时间。
  7. 根据权利要求3所述的液晶面板驱动电路，其中，所述第一晶体管和所述第二晶体管均为PNP型三极管。
  8. 根据权利要求4所述的液晶面板驱动电路，其中，所述第一晶体管和所述第二晶体管均为PNP型三极管。
  9. 根据权利要求1所述的液晶面板驱动电路，其中，所述电源电压为3.3V。
  10. 一种液晶面板，其中，包括权利要求1所述的液晶面板驱动电路的。
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