WO2019200693A1 - Oled显示面板以及显示装置 - Google Patents
Oled显示面板以及显示装置 Download PDFInfo
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- WO2019200693A1 WO2019200693A1 PCT/CN2018/092072 CN2018092072W WO2019200693A1 WO 2019200693 A1 WO2019200693 A1 WO 2019200693A1 CN 2018092072 W CN2018092072 W CN 2018092072W WO 2019200693 A1 WO2019200693 A1 WO 2019200693A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- the embodiments of the present application relate to the field of OLED display technologies, and in particular, to an OLED display panel and a display device.
- OLED has many advantages such as wide color gamut, high contrast, energy saving, foldability, etc., and has strong competitiveness in new generation displays. There are many parameters that characterize the quality of an OLED display panel, such as color gamut, power consumption, uniformity, and so on.
- the technical problem to be solved by the present application is to provide an OLED display panel and an OLED display panel, which can improve the uniformity of display of the OLED display panel.
- an embodiment of the present application provides an OLED display panel, including an array substrate, a reset signal line, and a power signal line.
- the reset signal line and the power signal line are respectively connected to the pixel unit of the array substrate.
- the power signal line is configured to transmit a power voltage to the pixel unit of the array substrate for the pixel unit to operate.
- the reset signal line is configured to transmit a reset voltage to a pixel unit of the array substrate to reset the pixel unit.
- the reset signal line includes a connection line connected to the pixel unit of the array substrate, and a current flowing in the power signal line is the same as a current flow in the connection line.
- the embodiment of the present application further provides an OLED display panel, which includes the OLED display panel provided by the embodiment of the present application.
- the application has the beneficial effects that the connection line of the reset signal line is connected to the pixel unit of the array substrate, and the current flow in the power signal line is the same as the current flow in the connection line, so along the power signal line.
- the brightness is getting higher and higher.
- the current flow in the power signal line to be the same as the current flow in the connection line, the brightness unevenness generated by the power signal line is neutralized and the brightness unevenness generated in the connection line is neutralized, so that the uneven brightness of the two portions partially cancel each other. , effectively improving the uneven brightness of the display panel.
- FIG. 1 is a schematic structural diagram of an embodiment of an OLED display panel of the present application.
- FIG. 2 is a schematic structural view of another embodiment of an OLED display panel of the present application.
- FIG. 3 is a schematic circuit diagram of a pixel unit in an embodiment of an OLED display panel of the present application.
- FIG. 4 is a schematic structural view of an embodiment of a display device of the present application.
- an embodiment of an OLED display panel of the present application includes an array substrate 11, a reset signal line 12, and a power signal line 13.
- the reset signal line 12 and the power signal line 13 are respectively connected to the pixel unit 111 of the array substrate 11.
- the reset signal line 12 is disposed in the same direction as the power signal line 13, that is, the pixel unit 111 is extended in the same direction.
- the power signal line 13 is used to transmit the power voltage V DD to the pixel unit 111 of the array substrate 11 for the pixel unit 111 to operate.
- the power source voltage V DD transmitted by the power signal line 13 is mainly used to illuminate the OLED to emit light.
- the reset signal line 12 is for transmitting a reset voltage V I to the pixel unit 111 of the array substrate 11 to reset the data voltage of the pixel unit 111.
- the pixel unit 111 of the array substrate 11 resets the data voltage already existing on the pixel unit 11 before rewriting the data signal or the data voltage, and transmits the reset voltage V I through the reset signal line 12. That is to say, it is necessary to reset the data voltage written on the pixel unit 11 at a time to facilitate the next re-writing, otherwise the display panel cannot be displayed or the gray scale, color and the like cannot be adjusted.
- the so-called reset voltage V I can be regarded as a reset signal, for example, by resetting the signal line 12 to the pixel unit 111 with a low level signal, so that the data voltage of the pixel unit 11 is greater than the reset signal line 12
- the potential is such that the current reciprocating bit signal line 12 of the pixel unit 11 flows out, that is, the data voltage of the pixel unit 11 is pulled down to the reset voltage V I level to reset the pixel unit 111, so that the data voltage or data signal can be rewritten next time.
- the reset signal line 12 is to reset the data voltage of the pixel unit 111, and the data signal of the array substrate 11 is generally transmitted by the column electrode line 113, so when the connection line 121 of the reset signal line 12 is along the column When the direction of the pixel unit 111 is connected, the power signal line 13 can also be connected to the pixel unit 111 in the direction of the column.
- the reset signal line 12 includes a connection line 121 that is connected to the pixel unit 111 of the array substrate 11, and the current in the power supply signal line 13 flows in the same direction as the current flow in the connection line 121.
- the reset signal line 12 is connected to the gate of the driving transistor of the pixel unit 111 (such as the second transistor T2 of FIG. 3), and the data voltage is also written to the gate of the driving transistor, and the reset signal line 12 is also pressed.
- the falling phenomenon affects the starting potential of the gate of the driving transistor, resulting in different gate voltages of different pixel units 111 during the writing of the data voltage, the direction of the current along the reset signal line 12, the start of the driving transistor
- connection line 121 of the reset signal line 12 is connected to the unit of the array substrate 11, and the current in the power supply signal line 13 flows in the same direction as the current in the connection line 121, that is, along the power supply signal line 13.
- the current flows inside, the brightness of the display panel is getting lower and lower, and as the current flows in the connection line 121 of the reset signal line 12, the reset voltage V I of the connected pixel unit 111 becomes lower and lower, and the brightness becomes more and more
- the connection line 121 of the reset signal line 12 by setting the current flow in the power supply signal line 13 to be the same as the current flow in the connection line 121, the luminance unevenness generated by the power supply signal line 13 and the luminance unevenness generated in the connection line 121 are neutralized.
- the uneven brightness of the two parts is partially offset, which effectively improves the uneven brightness of the OLED display panel.
- the reset signal line 12 further includes an extension line 122.
- the connection line 121 extends from one end of the array substrate 11 toward the other end and is connected to the pixel unit 111 of the array substrate 11, and the connection line 121 is connected to one end of the extension line 122 at a position adjacent to the other end of the array substrate 11, the extension line
- the other end of 122 is used to input a reset voltage V I such as a low level signal.
- the current in the reset signal line 12 first flows through the connection line 121 in the direction of the other end of the array substrate 11 toward the other end of the array substrate 11, and then flows through the extension line in the direction of the other end of the array substrate 11 toward the end of the array substrate 11. 122.
- the current in the power signal line 13 flows from one end of the array substrate 11 to the other end of the array substrate 11.
- the array substrate 11 includes a plurality of pixel units 111 extending from one end of the array substrate 11 toward the other end (for example, a column direction) and connecting the plurality of pixel units 111, and the connection lines 121 are adjacent to the array.
- the other end of the substrate 11 is connected to one end of the extension line 122, and the other end of the extension line 122 is used to input a reset voltage V I .
- the pattern formed by the connecting line 121 and the extension line 122 is, for example, an n-shape, and the top of the n-shape is the junction.
- the current in the power signal line 13 flows from one end of the array substrate 11 to the other end of the array substrate 11, that is, the power is supplied from one end of the array substrate 11 to the other end of the array substrate 11, and the pixel unit 111 to which the power signal line 13 is connected Since the power supply voltage V DD gradually becomes lower due to the effect of the voltage drop, the luminance of one end of the array substrate 11 gradually decreases toward the other end.
- the width a of the connecting line 121 is less than or equal to the width b of the extended line 122.
- the width a of the connection line 121 is less than or equal to the width b of the extension line 122, such that the cross-sectional area of the connection line 121 is greater than or equal to the width of the extension line 122.
- Cross-sectional area according to The resistance of the connecting line 121 is greater than or equal to the extension line 122, so that the voltage drop effect on the connecting line 121 is greater, so that the effect of uneven display due to the voltage drop of the power signal line 13 can be more effective. Neutralization or improvement further makes the display of the display panel more uniform.
- the width c at the junction of the connecting line 121 and the extension line 122 is smaller than the width a of the connecting line 121 and the width b of the extension line 122 .
- the width c of the joint may be less than one of the connecting line 121 and the extension line 122, or both, or both.
- the display panel further includes a power drive chip 14.
- the power driving chip 14 includes at least a reset voltage interface 141 and a power voltage interface 142.
- the reset voltage interface 141 is connected to the extension line 122 to transfer the reset voltage V I to the pixel unit 111 of the array substrate 11 through the reset signal line 12.
- the power supply voltage interface 142 is connected to the power supply signal line 13 to supply the power supply voltage V DD to the pixel unit 111 through the power supply signal line 13.
- the power driving chip 14 is disposed at one end of the array substrate 11, and the power voltage interface 142 is connected to the power signal line 13. Therefore, the current in the power signal line 13 flows from one end of the array substrate 11 to the other end of the array substrate 11, and the reset voltage interface 141 passes.
- the reset signal line 12 gives the pixel unit 111 a low level signal, and thus the current in the reset signal line 12 flows from the pixel unit 111 to the direction of the external reciprocating voltage interface 141, that is, the current flows from one end of the array substrate 11 to the other end of the array substrate 11.
- the direction flows through the connection line 121, and then flows from the other end of the array substrate 11 to the end of the array substrate 11 through the extension line 122 to reach the reset voltage interface 141. Therefore, the current of the connection line 121 flows to the same direction as the current of the power source signal line 13, so that the brightness display uniformity of the display panel can be improved.
- the reset voltage interface 241 may be disposed at the other end of the array substrate 21, and the extension line 222 is connected between the connection line 221 and the reset voltage interface 241, whereby the current is on the array substrate.
- One end of 21 flows directly through the connecting line 221 and the extension line 222 in the direction of the other end.
- the main difference from the embodiment of the OLED display panel of the present application is that the reset voltage interfaces 141 and 241 are disposed at different positions, but the current flows in the connection lines 121 and 221 are the same, and the current flow in the power supply signal line 23 is also the same.
- the reset voltage interface 241 and the power supply voltage interface 242 may not be disposed on the same power drive chip 14 at the same time.
- the array substrate 11 further includes a plurality of row electrode lines 112, a plurality of column electrode lines 113, and a plurality of pixel units 111.
- Each pixel unit 111 is connected to a row electrode line. 112 and a column electrode line 113, each pixel unit 111 includes a first transistor T1, a second transistor T2, and a light emitting unit 1111.
- the gate of the first transistor T1 is connected to the row electrode line 112, and the drain of the first transistor T1 is connected.
- the column electrode line 113, the source of the first transistor T1 is connected to the gate of the second transistor T2, the source of the second transistor T2 is connected to the power supply voltage interface 142 through the power signal line 13, and the drain of the second transistor T2 is grounded and illuminated.
- the unit 1111 is connected to the source or the drain of the second transistor T2.
- the connection line 121 is connected to the gate of the second transistor T2 to transmit the reset voltage V I to the pixel unit 111 before writing the data voltage V Data to the pixel unit 111.
- a plurality of row electrode lines 112 are used to transmit a scan signal scan1 to the array substrate 11, and the scanned pixel unit 111 is gated.
- the plurality of column electrode lines 113 are used to input data signals to the selected pixel unit 111. That is, the data voltage is written to the pixel unit 111.
- the gate of the first transistor T1 is turned on, that is, the drain and the source of the first transistor T1 are turned on, and at this time, the data voltage of the column electrode line 113 is connected to the second.
- the gate of the transistor T2, the second transistor T2 is turned on, and the light-emitting unit 1111 (OLED light-emitting unit) emits light under the power supply voltage V DD .
- the light emitting unit 1111 is connected to the source or the drain of the second transistor T2, which means that one end of the light emitting unit 1111 is connected to the source of the second transistor T2, and the other end is connected to the power signal line 13. Or it means that one end of the light emitting unit 1111 is connected to the drain of the second transistor T2, and the other end is grounded.
- V g is the gate voltage of the second transistor T2
- V s is the source voltage of the second transistor T2
- V th is the threshold voltage of the second transistor T2.
- V g is mainly provided by the data voltage V Data provided by the column electrode lines 113, but the reset voltage V I Effect of initial voltage of the second transistor T2, V s is supplied by the power supply voltage V DD.
- V g ⁇ V s so the smaller the V g , the larger the illuminating current of the OLED and the brighter the OLED. That is different as between different reset voltage V I of pixel units 111, during a write voltage, the second transistor V g T2 are different, the lower the reset voltage V I, the lower V g Therefore, the OLED illuminating current is larger.
- the pixel unit 111 connected to the connection line 121 is viewed from the end of the array substrate 11 to the other end, and the reset voltage V I is respectively due to the left and right of the voltage drop.
- 1V, -2V, -3V, and these pixel units 111 are to write a data voltage V Data of 5V, so the gate voltage V of the pixel units 111 is within 1S, for example, at the same write speed of 1V/S.
- g is 4V, 3V, 2V respectively.
- the gate voltage V g of the pixel units 111 is not equal to 5V, but is 4V, 3V, 2V, respectively.
- V g the larger the OLED illuminating current is, that is, the illuminating brightness of one end of the array substrate 11 is low, and the illuminating brightness of the other end is high, just
- the phenomenon of voltage drop with the power signal line 13 is opposite to the display effect produced by the display panel.
- connection line 121 flows from one end of the array substrate 11 to the other end, that is, V g gradually becomes smaller, and the luminance of the OLED is gradually increased.
- the current flowing in the connection line 121 flows in the same direction as the current in the power supply signal line 13, so that the display panel display unevenness due to the voltage drop of the power supply signal line 13 can be reduced.
- the display panel further includes a third transistor T3, and the reset signal line 12 is connected to the gate of the second transistor T2 through the third transistor T3.
- the gate of the third transistor T3 is used to input the strobe signal scan2, and the third The drain of the transistor T3 is connected to the reset signal line 12, and the source of the third transistor T3 is connected to the source of the second transistor T2.
- the gate of the third transistor T3 receives the strobe signal scan2, the source and the drain of the third transistor T3 are turned on, and the reset signal line 12 is The gate of the second transistor T2 is turned on and transmits a low level signal to reset the gate of the second transistor T2.
- the pixel unit 111 further includes a storage capacitor C1 connected between the source of the first transistor T1 and the source of the second transistor T2.
- the display panel further includes a row driver and a column driver (not shown).
- the row driver is configured to scan and select the row electrode line 112 of the array substrate 11 by sending the scan signal scan1, and the column driver is used to pass the column electrode line.
- 113 inputs a data voltage V Data to the pixel unit 111 corresponding to the selected row electrode line 112.
- the display panel includes at least two reset signal lines 12 disposed on opposite sides of the array substrate 11 and respectively connected to different pixel units 111 .
- the reset efficiency of the pixel unit 111 can be improved, the delay can be reduced, and the uniformity of the display panel can be improved.
- the present application shows an apparatus embodiment, including the OLED display panel as set forth in the embodiment of the OLED display panel of the present application.
- the display device can be considered a display screen, such as an OLED display.
- the display device can also be considered as a device including a display screen, such as a mobile phone, a tablet computer, a notebook computer, a television, etc., wherein the display screen includes the display panel.
- connection line 121 of the reset signal line 12 is connected to the pixel unit 111 of the array substrate 11, and the current in the power signal line 13 flows into the connection line 121.
- the current flow is the same.
- the current in the power signal line 13 flows, the brightness of the display panel becomes lower and lower, and as the current flows in the connection line 121 of the reset signal line 12, the connected pixel unit 111 resets the voltage V I more and more.
- the current flowing in the power signal line 13 is set to be the same as the current flowing in the connection line 121, so that the luminance unevenness generated by the power signal line 13 and the generated in the connection line 121 are generated.
- the uneven brightness is neutralized, so that the uneven brightness of the two cancels each other, which effectively improves the uneven brightness of the OLED display panel.
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Abstract
本申请实施例提供OLED显示面板以及显示装置，其中显示面板包括阵列基板、复位信号线以及电源信号线。所述复位信号线与所述电源信号线分别连接阵列基板的像素单元。其中所述电源信号线用于向所述阵列基板的像素单元传输电源电压供所述像素单元工作。所述复位信号线用于向所述阵列基板的像素单元传输复位电压，以对所述像素单元进行复位。其中所述复位信号线包括连接线，所述连接线与所述阵列基板的像素单元连接，所述电源信号线内的电流流向与所述连接线内的电流流向相同。通过上述方式，本申请能够有效地提高显示面板的显示亮度的均匀性。
Description
本申请实施例涉及OLED显示技术领域，特别是涉及OLED显示面板以及显示装置。
OLED具有色域广、对比度高、节能、可折叠等诸多优点，在新世代显示器中具有强的竞争力。表征一个OLED显示面板的品质高低的参数很多，比如色域、功耗、均匀度等。
众所周知，电流在导体中流动时由于导体中的电阻作用会产生压降，在对显示面板进行供电使其工作时，显示面板上下供电电压大小不一，进而导致显示面板显示不均，也就是大家常说的IR drop，这种情况使得显示面板的显示效果大打折扣。
【发明内容】
本申请主要解决的技术问题是提供OLED显示面板以及OLED显示屏，能够提高OLED显示面板显示的均匀性。
为解决上述技术问题，本申请实施例提供一种OLED显示面板，包括阵列基板、复位信号线以及电源信号线。所述复位信号线与所述电源信号线分别连接阵列基板的像素单元。其中所述电源信号线用于向所述阵列基板的像素单元传输电源电压供所述像素单元工作。所述复位信号线用于向所述阵列基板的像素单元传输复位电压，以对所述像素单元进行复位。
其中所述复位信号线包括连接线，所述连接线与所述阵列基板的像素单元连接，所述电源信号线内的电流流向与所述连接线内的电流流向相同。
本申请实施例还提供一种OLED显示屏，包括本申请实施例提供的OLED显示面板。
与现有技术相比，本申请的有益效果是：复位信号线的连接线与阵列基板的像素单元连接，电源信号线内的电流流向与连接线内的电流流向相同，如此沿着电源信号线内的电流流向，显示面板的亮度越来越低，而随着复位信号线的连接线内的电流流向，所连接的像素单元复位电压越来越低，根据OLED发 光电流的公式I＝k(V
g-V
s-V
th)
2，复位电压越低，V
g越低，由于V
g＜V
s，因此V
g越小，OLED的发光电流就越大。则亮度越来越高。通过设置电源信号线内的电流流向与连接线内的电流流向相同，使得电源信号线产生的亮度不均与连接线内的产生的亮度不均进行中和，使得两者亮度不均相互部分抵消，有效改善了显示面板的亮度不均的现象。
图1是本申请OLED显示面板实施例的结构示意图；
图2是本申请OLED显示面板另一实施例结构示意图；
图3是本申请OLED显示面板实施例中像素单元的电路结构示意图；
图4是本申请显示装置实施例的结构示意图。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参阅图1，本申请OLED显示面板实施例包括阵列基板11、复位信号线12以及电源信号线13。复位信号线12与电源信号线13分别连接阵列基板11的像素单元111，例如复位信号线12与电源信号线13同向设置，也即同一方向延伸连接像素单元111。其中电源信号线13用于向阵列基板11的像素单元111传输电源电压V
DD供像素单元111工作，例如电源信号线13传输的电源电压V
DD主要用于点亮OLED，使其发光。复位信号线12用于向阵列基板11的像素单元111传输复位电压V
I，以对像素单元111的数据电压进行复位。在本实施例中，阵列基板11的像素单元111在重新写入数据信号或者数据电压之前，要对已经存在于像素单元11上的数据电压进行复位，通过复位信号线12传输复位电压V
I，也就是说要对像素单元11上一次写入数据电压进行复位，以方便下一次重新写入，要不然显示面板无法显示或者无法调节灰度、色彩等问题。
在本实施例中，所谓的复位电压V
I，可以认为是复位信号，例如通过复位信号线12给像素单元111一个低电平信号，使得像素单元11的数据电压大于复位信号线12各处的电位，使得像素单元11的电流往复位信号线12外流，即拉 低像素单元11的数据电压至复位电压V
I水平，以对像素单元111进行复位，便于下一次重新写入数据电压或者数据信号。在本实施例中，复位信号线12要对像素单元111的数据电压进行复位，而阵列基板11的数据信号，一般由列电极线113进行传输，因此当复位信号线12的连接线121沿列的方向连接像素单元111时，电源信号线13也可以沿列的方向连接像素单元111。
其中复位信号线12包括连接线121，连接线121与阵列基板11的像素单元111连接，电源信号线13内的电流流向与连接线121内的电流流向相同。
在本实施例中，电源信号线13内由于导体的关系存在压降(IR Drop)，在传输电流的过程中，使得显示面板的显示亮度随着压降会出现显示不均的现象，在电源电压V
DD高的地方亮度越亮，电源电压V
DD低的部分亮度越暗。一般，复位信号线12连接的是像素单元111的驱动晶体管(如图3的第二晶体管T2)的栅极，而数据电压也是写入到驱动晶体管的栅极，复位信号线12也由于存在压降的现象影响了驱动晶体管栅极的起始电位，导致在写入数据电压的过程中，不同的像素单元111栅极电压的不同，沿着复位信号线12的电流方向，驱动晶体管的起始电位越来越低，根据OLED发光电流的公式I＝k(V
g-V
s-V
th)
2，V
g＜V
s，因此V
g越小，OLED的发光电流就越大，因此沿着复位信号线12的连接线121的电流方向，V
g越来越小，而亮度越来越大，跟电源信号线13压降所引起的亮暗不均的现象刚好相反。
在本实施例中，复位信号线12的连接线121与阵列基板11的单元连接，电源信号线13内的电流流向与连接线121内的电流流向相同，也就是说，沿着电源信号线13内的电流流向，显示面板的亮度越来越低，而随着复位信号线12的连接线121内的电流流向，所连接的像素单元111复位电压V
I越来越低，而亮度越来越高，本实施例通过设置电源信号线13内的电流流向与连接线121内的电流流向相同，使得电源信号线13产生的亮度不均与连接线121内的产生的亮度不均进行中和，使得两者亮度不均相互部分抵消，有效改善了OLED显示面板的亮度不均的现象。
请继续参阅图1，可选的是，复位信号线12进一步包括延长线122。连接线121在阵列基板11一端向另一端的方向上延伸并与阵列基板11的像素单元111连接，且连接线121在邻近阵列基板11的另一端的位置与延长线122的一端连接，延长线122的另一端用于输入复位电压V
I例如是低电平信号。其中， 复位信号线12内的电流先在阵列基板11的一端往阵列基板11的另一端的方向上流经连接线121，再在阵列基板11的另一端往阵列基板11一端的方向上流经延长线122。电源信号线13内的电流从阵列基板11一端流向阵列基板11的另一端。
在本实施中，例如阵列基板11包括多个像素单元111，连接线121从阵列基板11的一端向另一端(例如列方向)延伸并连接该多个像素单元111，而连接线121在邻近阵列基板11的另一端的位置与延长线122的一端连接，延长线122的另一端用于输入复位电压V
I。连接线121与延长线122所构成的图形例如n形，n形的顶部即为连接处。
具体地，电源信号线13内的电流从阵列基板11一端流向阵列基板11的另一端，也即电源从阵列基板11一端向阵列基板11另一端供电，电源信号线13所连接的像素单元111的电源电压V
DD由于压降的作用逐渐变低，因此，阵列基板11的一端向另一端亮度逐渐减暗。而这些像素单元111在连接线121的复位信号线12的复位电压V
I的影响下，阵列基板11的一端向另一端的像素单元111的驱动晶体管栅极电压降低，因此阵列基板11的另一端亮度大，而阵列基板11一端的亮度低，与电源信号线13所产生的亮度效果进行中和，能够有效降低显示面板显示不均的现象。
继续参阅图1，可选的是，连接线121的宽度a小于或等于延长线122的宽度b。例如，连接线121与延长线122线厚与长度相差不大时，连接线121的宽度a小于或等于延长线122的宽度b，使得连接线121的横截面积大于或等于延长线122的横截面积，根据
连接线121的电阻会大于等于延长线122的，因此在连接线121上的压降作用会更大，如此能够对电源信号线13的压降所产生的显示不均的效果进行更有效的部分中和或者改善，进一步使得显示面板的显示更均匀。
继续参阅图1，可选的是，连接线121与延长线122连接处的宽度c小于连接线121的宽度a以及延长线122的宽度b。通过设置连接处的宽度c小于连接线121的宽度a以及延长线122的宽度b，一方面能够减少复位信号线12所占用的空间以简化线路设置，另一方面有利于复位信号的传输，减少耗损。
当然，在其他实施例中，连接处的宽度c可以只小于连接线121以及延长线122中的一者，或者，同时大于其中一者或者两者。
继续参阅图1，可选的是，显示面板进一步包括电源驱动芯片14。电源驱动芯片14至少包括复位电压接口141以及电源电压接口142。复位电压接口141连接延长线122，以通过复位信号线12向阵列基板11的像素单元111传输复位电压V
I。电源电压接口142连接电源信号线13，以通过电源信号线13向像素单元111提供电源电压V
DD。
例如电源驱动芯片14设置于阵列基板11的一端，电源电压接口142连接电源信号线13，因此电源信号线13内的电流从阵列基板11一端流向阵列基板11的另一端，而复位电压接口141通过复位信号线12给像素单元111低电平信号，因此复位信号线12内的电流从像素单元111向外往复位电压接口141的方向流，也即电流从阵列基板11一端到阵列基板11另一端的方向流经连接线121，再从阵列基板11的另一端到阵列基板11一端的方向流经延长线122，到达复位电压接口141。因此，连接线121的电流流向与电源信号线13的电流流向相同，如此能够提高显示面板的亮度显示均匀性。
请参阅图1与图2，在其他实施例中，复位电压接口241可以设置在阵列基板21的另一端，延长线222连接在连接线221与复位电压接口241之间，由此电流在阵列基板21的一端往另一端的方向上直接流经连接线221、以及延长线222。与本申请OLED显示面板实施例主要不同在于：复位电压接口141、241设置位置不同，但是连接线121、221内的电流流向是相同的，跟电源信号线23内的电流流向也相同。例如复位电压接口241和电源电压接口242可以不同时设置在同一个电源驱动芯片14上。
请参阅图1与图3，可选的是，阵列基板11进一步包括多根行电极线112、多根列电极线113以及多个像素单元111，每个像素单元111对应连接一根行电极线112与一根列电极线113，每个像素单元111包括第一晶体管T1、第二晶体管T2以及发光单元1111，第一晶体管T1的栅极连接行电极线112，第一晶体管T1的漏极连接列电极线113，第一晶体管T1的源极连接第二晶体管T2的栅极，第二晶体管T2的源极通过电源信号线13与电源电压接口142连接，第二晶体管T2的漏极接地，发光单元1111连接第二晶体管T2的源极或者漏极上。其中，连接线121连接第二晶体管T2的栅极，以对像素单元111在写入数据电压V
Data前向像素单元111传输复位电压V
I。
参阅图3，多根行电极线112用于向阵列基板11传输扫描信号scan1，对扫描的像素单元111进行选通，多根列电极线113用于向所选通的像素单元111 输入数据信号，也即对像素单元111写入数据电压。在当行电极线112输入高平扫描信号scan1时，第一晶体管T1的栅极打开，也即第一晶体管T1的漏极和源极导通，此时列电极线113的数据电压接入到第二晶体管T2的栅极，第二晶体管T2导通，在电源电压V
DD供电下，发光单元1111(OLED发光单元)发光。
在行电极线112扫描之间，行电极线112对所在行的像素单元111进行选通之前，需要在第二晶体管T2的栅极写入数据电压之前通过复位信号线12对第二晶体管T2的栅极电压进行复位，以使得在数据电压能够正常写入第二晶体管T2的栅极，使得发光单元1111正常发光。
在本实施例中，发光单元1111连接第二晶体管T2的源极或者漏极上，是指发光单元1111一端连接第二晶体管T2的源极，另一端连接电源信号线13。或者是指发光单元1111一端连接第二晶体管T2的漏极，另一端接地。
为了进一步说明本申请的技术方案，下面通过公式结合图1与图3进行阐述，根据OLED发光电流的公式I＝k(V
g-V
s-V
th)
2，其中k＝μCox W/2L，Cox为单位面积绝缘栅的电容大小，μ为薄膜晶体管的饱和迁移率，W/L为薄膜晶体管的沟道宽长比，也即k本身与薄膜晶体管(第二晶体管T2)的性质有关。V
g是第二晶体管T2的栅极电压，V
s是第二晶体管T2的源极电压，V
th是第二晶体管T2的阈值电压。在本实施例中，V
g主要是由列电极线113提供的数据电压V
Data提供，但是复位电压V
I影响第二晶体管T2的起始电压，V
s是由电源电压V
DD提供。一般而言，V
g＜V
s，因此V
g越小，OLED的发光电流就越大，OLED就越亮。也就是说像不同的素单元111之间不同的复位电压V
I，在写入数据电压的过程中，第二晶体管T2的V
g也是不同的，复位电压V
I越低，V
g就越低，因此OLED发光电流就越大。
例如，在连接线121传输了低电平之后，连接线121连接的像素单元111，从阵列基板的11一端往另一端的方向上看，其由于压降的左右后复位电压V
I分别是-1V、-2V、-3V，而这些像素单元111将要写入5V的数据电压V
Data，因此在例如同样的写入速度1V/S，在1S之内，该些像素单元111的栅极电压V
g分别为4V，3V，2V，如果时间充足，写入过程中V
g≠V
Data，但是像素单元111最后依然是V
g＝V
Data，同样都是5V，但是在行电极线112扫描时间短暂时，比如只有1S，那么该些像素单元111的栅极电压V
g，都不会等于5V，而是分别为4V，3V，2V。或者在像素单元111的栅极电压V
g＝V
Data之前，各像素单元111 的栅极电压V
g都是不相同的，且沿电流方向逐渐减小。根据公式I＝k(V
g-V
s-V
th)
2，V
g就越低，因此OLED发光电流就越大，就是阵列基板11一端的发光亮度低，而另一端的发光亮度高，刚好跟电源信号线13压降现象对显示面板产生的显示作用相反。
因此连接线121内的电流流向从阵列基板11一端往另一端流，也即V
g逐渐变小，OLED发光亮度逐渐大。连接线121内的电流流向与电源信号线13内的电流流向相同如此能够减少由于电源信号线13的压降所带来的显示面板显示不均匀的问题。
进一步地，显示面板进一步包括第三晶体管T3，复位信号线12通过第三晶体管T3连接第二晶体管T2的栅极，具体地，第三晶体管T3的栅极用于输入选通信号scan2，第三晶体管T3的漏极连接复位信号线12，第三晶体管T3的源极连接第二晶体管T2的源极。
具体地，在行电极线112未选通某一部分像素单元111时，第三晶体管T3的栅极接收到选通信号scan2，第三晶体管T3的源极和漏极导通，复位信号线12与第二晶体管T2的栅极导通并传输低电平信号，对第二晶体管T2的栅极进行复位。
可选的是，像素单元111进一步包括存储电容C1，连接于第一晶体管T1的源极与第二晶体管T2源极之间。
可选的是，显示面板进一步包括行驱动器以及列驱动器(图未示)，行驱动器用于发送扫描信号scan1对阵列基板11的行电极线112进行扫描并选择，列驱动器用于通过列电极线113对所选择的行电极线112所对应的像素单元111输入数据电压V
Data。
请继续参阅图1，可选的是，显示面板包括至少两条复位信号线12，设置于阵列基板11两侧，分别连接不同的像素单元111。通过在两侧同时设置至少两条复位信号线12，能够提高像素单元111的复位效率，减少延迟，有利于提高显示面板的均匀性。
请参阅图4，本申请显示装置实施例，包括本申请OLED显示面板实施例中所阐述的OLED显示面板。显示装置可以认为是显示屏，例如OLED显示屏。显示装置也可以认为是包含显示屏的装置，例如手机、平板电脑、笔记本电脑、电视等，其中显示屏包括该显示面板。
综上，在本申请OLED显示面板实施例以及显示装置实施例中，复位信号线12的连接线121与阵列基板11的像素单元111连接，电源信号线13内的电流流向与连接线121内的电流流向相同。如此沿着电源信号线13内的电流流向，显示面板的亮度越来越低，而随着复位信号线12的连接线121内的电流流向，所连接的像素单元111复位电压V
I越来越低，而亮度越来越高，本实施例通过设置电源信号线13内的电流流向与连接线121内的电流流向相同，使得电源信号线13产生的亮度不均与连接线121内的产生的亮度不均进行中和，使得两者亮度不均相互抵消，有效改善了OLED显示面板的亮度不均的现象。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。
Claims (19)
- 一种OLED显示面板，包括：阵列基板；复位信号线以及电源信号线，分别与所述阵列基板的像素单元连接，其中电源信号线用于向所述像素单元传输电源电压供所述像素单元工作，所述复位信号线用于向所述像素单元传输复位电压，以对所述像素单元的数据电压进行复位；其中所述复位信号线包括连接线，所述连接线与所述阵列基板的像素单元连接，所述电源信号线内的电流流向与所述连接线的电流流向相同。
- 根据权利要求1所述的显示面板，其中，所述复位信号线进一步包括延长线，所述连接线在所述阵列基板一端向另一端的方向上延伸并与所述阵列基板的像素单元连接，且所述连接线在邻近所述阵列基板的另一端的位置与所述延长线的一端连接，所述延长线的另一端用于输入所述复位电压；其中，所述复位信号线内的电流先在所述阵列基板的一端往所述阵列基板的另一端的方向上流经所述连接线，所述电源信号线内的电流从所述阵列基板一端流向所述阵列基板的另一端。
- 根据权利要求2所述的显示面板，其中，所述复位信号线内的电流先在所述阵列基板的一端往所述阵列基板的另一端的方向上流经所述连接线，再在所述阵列基板的另一端往所述阵列基板一端的方向上流经所述延长线，所述延长线内的电流流向与所述连接线内的电流流向相反。
- 根据权利要求2所述的显示面板，其中，所述复位信号线内的电流先在所述阵列基板的一端往所述阵列基板的另一端的方向上流经所述连接线，再在相同方向流经所述延长线，所述延长线内的电流流向与所述连接线内的电流流向相同。
- 根据权利要求3所述的显示面板，其中，所述连接线的宽度小于或等于延长线的宽度。
- 根据权利要求5所述的显示面板，其中，所述连接线与所述延长线连接处的宽度小于所述连接线的宽度。
- 根据权利要求5所述的显示面板，其特征在于：所述连接线与所述延长线的连接处的宽度小于所述延长线的宽度。
- 根据权利要求2所述的显示面板，其中，所述显示面板进一步包括电源驱 动芯片，所述电源驱动芯片至少包括复位电压接口以及电源电压接口，所述复位电压接口连接所述延长线，以通过所述复位信号线向所述阵列基板的所述像素单元传输复位电压；所述电源电压接口连接所述电源信号线，以通过所述电源信号线向所述像素单元提供电源电压。
- 根据权利要求8所述的显示面板，其中，所述阵列基板进一步包括多根行电极线、多根列电极线以及多个所述像素单元，每个像素单元对应连接一根所述行电极线与一根所述列电极线，每个所述像素单元包括第一晶体管、第二晶体管以及发光单元，所述第一晶体管的栅极连接所述行电极线，所述第一晶体管的漏极连接所述列电极线，所述第一晶体管的源极连接所述第二晶体管的栅极，所述第二晶体管的源极通过所述电源信号线与所述电源电压接口连接，所述第二晶体管的漏极接地，所述发光单元连接所述第二晶体管的源极或者漏极上；其中，所述连接线连接所述第二晶体管的栅极，以对所述像素单元在写入数据电压前向所述像素单元传输复位电压。
- 根据权利要求9所述的显示面板，其中，所述像素单元进一步包括存储电容，连接于所述第一晶体管的源极与所述第二晶体管源极之间。
- 根据权利要求9所述的显示面板，其中，所述显示面板进一步包括第三晶体管，第三晶体管的栅极用于输入选通信号，第三晶体管的漏极连接复位信号线，第三晶体管的源极连接第二晶体管的源极。
- 根据权利要求9所述的显示面板，其中，所述显示面板进一步包括行驱动器以及列驱动器，所述行驱动器用于发送扫描信号对所述阵列基板的所述行电极线进行扫描并选择，所述列驱动器用于通过所述列电极线对所选择的行电极线所对应的所述像素单元输入所述数据电压。
- 根据权利要求1所述的显示面板，其中，所述显示面板包括至少两条复位信号线，设置于所述阵列基板两侧，分别连接不同的所述像素单元。
- 一种显示装置，包括显示面板，其中所述显示面板包括：阵列基板；复位信号线以及电源信号线，分别与所述阵列基板的像素单元连接，其中电源信号线用于向所述像素单元传输电源电压供所述像素单元工作，所述复位信号线用于向所述像素单元传输复位电压，以对所述像素单元的数据电压进行复位；其中所述复位信号线包括连接线，所述连接线与所述阵列基板的像素单元 连接，所述电源信号线内的电流流向与所述连接线的电流流向相同。
- 根据权利要求14所述的显示装置，其中，所述复位信号线进一步包括延长线，所述连接线在所述阵列基板一端向另一端的方向上延伸并与所述阵列基板的像素单元连接，且所述连接线在邻近所述阵列基板的另一端的位置与所述延长线的一端连接，所述延长线的另一端用于输入所述复位电压；其中，所述复位信号线内的电流先在所述阵列基板的一端往所述阵列基板的另一端的方向上流经所述连接线，所述电源信号线内的电流从所述阵列基板一端流向所述阵列基板的另一端。
- 根据权利要求15所述的显示装置，其中，所述复位信号线内的电流先在所述阵列基板的一端往所述阵列基板的另一端的方向上流经所述连接线，再在所述阵列基板的另一端往所述阵列基板一端的方向上流经所述延长线，所述延长线内的电流流向与所述连接线内的电流流向相反。
- 根据权利要求15所述的显示装置，其中，所述复位信号线内的电流先在所述阵列基板的一端往所述阵列基板的另一端的方向上流经所述连接线，再在相同方向流经所述延长线，所述延长线内的电流流向与所述连接线内的电流流向相同。
- 根据权利要求15所述的显示装置，其中，所述显示面板进一步包括电源驱动芯片，所述电源驱动芯片至少包括复位电压接口以及电源电压接口，所述复位电压接口连接所述延长线，以通过所述复位信号线向所述阵列基板的像素单元传输复位电压；所述电源电压接口连接所述电源信号线，以通过所述电源信号线向所述像素单元提供电源电压。
- 根据权利要求18所述的显示装置，其中，所述阵列基板进一步包括多根行电极线、多根列电极线以及多个所述像素单元，每个像素单元对应连接一根所述行电极线与一根所述列电极线，每个所述像素单元包括第一晶体管、第二晶体管以及发光单元，所述第一晶体管的栅极连接所述行电极线，所述第一晶体管的漏极连接所述列电极线，所述第一晶体管的源极连接所述第二晶体管的栅极，所述第二晶体管的源极通过所述电源信号线与所述电源电压接口连接，所述第二晶体管的漏极接地，所述发光单元连接所述第二晶体管的源极或者漏极上；其中，所述连接线连接所述第二晶体管的栅极，以对所述像素单元在写入数据电压前向所述像素单元传输复位电压。
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| CN109345990B (zh) * | 2018-12-14 | 2020-10-13 | 武汉华星光电半导体显示技术有限公司 | 显示面板测试电路及显示面板 |
| CN111862891B (zh) * | 2019-04-25 | 2021-10-01 | 上海和辉光电股份有限公司 | 一种有机发光显示器 |
| WO2021046717A1 (zh) * | 2019-09-10 | 2021-03-18 | 京东方科技集团股份有限公司 | 显示面板及显示装置 |
| CN110676298B (zh) * | 2019-09-30 | 2022-06-03 | 昆山国显光电有限公司 | 阵列基板及oled显示面板 |
| CN110992897B (zh) * | 2019-12-31 | 2021-03-16 | 深圳市华星光电半导体显示技术有限公司 | 显示面板驱动方法、显示驱动电路和显示面板 |
| CN112596300A (zh) | 2020-12-16 | 2021-04-02 | Tcl华星光电技术有限公司 | 一种背光模组及显示装置 |
| CN112863438A (zh) * | 2021-01-19 | 2021-05-28 | 武汉华星光电半导体显示技术有限公司 | 一种显示面板和显示装置 |
| CN113160745A (zh) * | 2021-03-31 | 2021-07-23 | 合肥维信诺科技有限公司 | 显示面板及显示装置 |
| CN113488448B (zh) * | 2021-06-24 | 2022-11-01 | 厦门天马微电子有限公司 | 显示面板和显示装置 |
| WO2023039842A1 (en) * | 2021-09-17 | 2023-03-23 | Boe Technology Group Co., Ltd. | Array substrate and display apparatus |
| CN114743505B (zh) * | 2022-04-29 | 2023-06-27 | 武汉华星光电半导体显示技术有限公司 | 显示装置 |
| CN115240586B (zh) * | 2022-06-27 | 2023-07-14 | 惠科股份有限公司 | 显示驱动电路及显示装置 |
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