WO2019196008A1 - Structure de tranche de diode à effet tunnel résonnant ayant un rapport de courant de crête à vallée élevé, et son procédé de préparation - Google Patents

Structure de tranche de diode à effet tunnel résonnant ayant un rapport de courant de crête à vallée élevé, et son procédé de préparation Download PDF

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Publication number
WO2019196008A1
WO2019196008A1 PCT/CN2018/082494 CN2018082494W WO2019196008A1 WO 2019196008 A1 WO2019196008 A1 WO 2019196008A1 CN 2018082494 W CN2018082494 W CN 2018082494W WO 2019196008 A1 WO2019196008 A1 WO 2019196008A1
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WO
WIPO (PCT)
Prior art keywords
layer
ingaas
resonant tunneling
tunneling diode
diode wafer
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Application number
PCT/CN2018/082494
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English (en)
Chinese (zh)
Inventor
张翠
丁庆
冯军正
杨旻蔚
刘荣跃
孙竹
许奔
Original Assignee
雄安华讯方舟科技有限公司
深圳市太赫兹科技创新研究院
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Priority to PCT/CN2018/082494 priority Critical patent/WO2019196008A1/fr
Publication of WO2019196008A1 publication Critical patent/WO2019196008A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/88—Tunnel-effect diodes

Definitions

  • the present invention belongs to the technical field of nanoelectronic devices, and in particular, to a resonance tunneling diode wafer structure of a peak-to-valley current ratio and a preparation method thereof.
  • Terahertz waves can be used for detection, imaging, and integration due to their unique properties, such as narrow pulse width, high bandwidth, low photon energy, and the ability to penetrate most dry, non-metallic, non-polar, and dielectric materials.
  • High-bandwidth wireless communication systems are widely used in various fields (aerospace, offshore equipment, security, medical, cultural heritage, etc.).
  • electromagnetic waves in the Terahertz band have not been fully studied and applied.
  • high-power radiation sources are needed to illuminate the target object for applications such as detection and imaging. Therefore, effective high-power terahertz radiation sources have become the top priority of technology.
  • TMIC monolithic terahertz integrated circuit
  • RTD resonant tunneling diode
  • the double barrier quantum well structure of the indium phosphide-based wafer material used to fabricate the device has a direct effect on the peak-to-valley voltage ratio (AV) and peak-to-valley current ratio (AI) of the resonant tunneling diode.
  • the commonly used InP-based is used to prepare RTD devices.
  • the change of the conduction band position of this structure under different working biases and the corresponding IV of the RTD device The increase in line response current is limited.
  • An object of the present invention is to provide a resonant tunneling diode wafer structure and a corresponding preparation method for peak-to-valley current ratio, aiming at solving the change of the conduction band position and the response current of the existing RTD under different working biases. Increased limited technical issues.
  • the present invention provides a resonant tunneling diode wafer structure including a stacked collector layer, a double barrier quantum well structure, and an emission layer, the double barrier quantum well structure including first AlAs stacked in sequence a barrier layer, a first InGaAs well layer, a second InGaAs well layer, and a second AlAs barrier layer, and an InAs sub-layer is disposed between the first I nGaAs well layer and the second InGaAs well layer Potential well layer
  • the first AlAs barrier layer is adjacent to the collection layer, the second AlAs barrier layer is adjacent to the emission layer; or the first AlAs barrier layer is adjacent to the emission layer, The second AlAs barrier layer is adjacent to the collection layer.
  • the present invention also provides a method for fabricating the above resonant tunneling diode wafer structure, comprising the following steps:
  • the collection layer of the resonant tunneling diode wafer structure, the double barrier quantum well structure, and the emissive layer are formed on the substrate using a micro-nano processing technique.
  • an InAs sub-well layer is disposed between the first InGaAs well layer and the second InGaAs well layer, and InAs is narrower than InGaAs.
  • the effective mass increases the energy spacing between the quantum constrained bound states and also reduces the ground state energy of the quantum well.
  • the method for preparing the above resonant tunneling diode wafer structure generates the above-mentioned resonant tunneling diode wafer structure on the substrate by using a micro-nano processing technique, and the method is simple and easy, and the cost is low.
  • the resonant tunneling diode wafer structure has more electrons to migrate under the same operating bias, and the current response is larger, increasing the peak-to-valley current ratio (AI) and increasing the resonance in the sub-well layer.
  • the energy level also increases the bias operating voltage of the device and increases the peak-to-valley voltage ratio (AV).
  • FIG. 1 is a double barrier quantum well structure diagram; wherein (a) is a double barrier quantum well structure of a prior art resonant tunneling diode, (b) is a resonant tunneling diode wafer structure of the present invention; a double barrier quantum well structure having an InAs sub-well layer;
  • FIG. 2 is a schematic diagram showing changes in the energy band of a double-barrier quantum well structure of a resonant tunneling diode under different bias operating voltages; [0016] FIG.
  • FIG. 3 is a diagram showing changes in the energy band of a double-barrier quantum well structure having an InAs sub-well layer at different bias operating voltages in the resonant tunneling diode of Embodiment 1 of the present invention
  • FIG. 4 is a cross-sectional layer structural view of a resonant tunneling diode according to Embodiment 1 of the present invention.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the indicated technical features. quantity. Thus, features defining “first” and “second” may include one or more of the features, either explicitly or implicitly. In the description of the present invention, the meaning of "a plurality" is two or more, unless specifically defined otherwise.
  • an embodiment of the present invention provides a resonant tunneling diode wafer structure, including a stacked collector layer, a double barrier quantum well structure, and an emission layer, wherein the double barrier quantum well structure includes a stacking arrangement in sequence. a first AlAs barrier layer, a first InGaAs well layer, a second InGaAs well layer, and a second AlAs barrier layer, and disposed between the first InGaAs well layer and the second InGaAs well layer InAs sub-well layer
  • the first AlAs barrier layer is adjacent to the collection layer, the second AlAs barrier layer is adjacent to the emission layer; or the first AlAs barrier layer is adjacent to the emission layer, The second AlAs barrier layer is adjacent to the collection layer.
  • the effective mass of the electron is reduced, thereby increasing the energy separation between the quantum confinement bound states and also reducing the ground state energy of the quantum well. Therefore, under the same operating bias, more electrons are transferred, the current response is larger, and the peak-to-valley current ratio (AI) is increased. At the same time, the increased resonance level in the sub-well layer also increases the bias of the device. Set the operating voltage to increase the peak-to-valley voltage ratio (AV).
  • the compressive strain of the InAs sub-well layer counteracts the tensile strain of AlAs, which may be an important consideration in the development of multilayer RTD heterostructures.
  • the first AlAs barrier layer is adjacent to the emission layer
  • the second AlAs barrier layer is adjacent to the Collection layer.
  • FIG. 2 A simplified representation of the variation of the energy band of a double-barrier quantum well structure for an RTD device.
  • Figure 2 (a) - (e) shows the change of the energy band of the double-barrier quantum well structure of the RTD device under different bias voltages.
  • the IV DC response of each stage corresponds one-to-one in the last Figure 2 (f).
  • the position of the peak current in Fig. 2(f) can be changed from the c position to the c' position.
  • FIG. 2(d) When the bias voltage is further increased, the first resonance level (Erl) drops to the emission band of the emission region.
  • FIG. 2(e) When the bias voltage is further increased, the second resonance level (Er2) continues to move down, thereby forming another electron tunneling process, and the increase of the heat emission electrons causes the current in the barrier layer. The rapid increase.
  • the bias current at this point where the current begins to increase again is the peak-to-valley voltage (Vv).
  • an additional layer of InAs sub-well layer is additionally added to the existing double-barrier quantum well structure (shown in FIG. 1) of InGaAs as a well layer (FIG. 1b).
  • Eg 0.36 eV, at room temperature
  • the thickness of the InAs sub-well layer is 10 -45 A.
  • the thickness of the first 11 8 8 well layer is 10-25 A; the thickness of the second InGaAs well layer is 10-25 A, and when the thickness of the well layer is too thick, the peak voltage Vp will be left Movement, while in the thickness range of embodiments of the present invention, is more beneficial to maintain Vp in a suitable range.
  • the thickness of the first AlAs barrier layer is 10-25 people; the thickness of the second AlAs barrier layer is 10-25 people, and when the thickness of the barrier layer is too thick, the peak current density It will be reduced, and it is more beneficial to maintain the peak current density at a higher level within the thickness range of embodiments of the present invention.
  • the emission layer includes a Si doping concentration of 2-3 ⁇ 10 19 cm 1
  • the collection layer comprising a third InGaAs doping having a Si doping concentration of 2-3 ⁇ 10 19 cm 1 a fourth InGaAs doped layer having a layer and a Si doping concentration of 2-3 x 10 18 cm -1 ; wherein the second InGaAs doped layer and the fourth InGaAs doped layer are adjacent to the double barrier quantum well structure.
  • the second InGaAs doped layer has a thickness of 800 to 1000 A
  • the fourth InGaAs doped layer has a thickness of 800 to 1000 A and/or
  • the first AlAs barrier layer is adjacent to the emission layer
  • the second AlAs barrier layer is adjacent to the collection layer
  • the first InGaAs doped layer has a thickness of 2000 ⁇ 4000
  • the thickness of the third InGaAs doped layer is 350-450, and the thickness of the above four layers can meet the requirement of high doping concentration in the collecting/emission region, which is favorable for the electron tunneling and current conduction.
  • the first AlAs barrier layer is adjacent to the emission layer
  • the second AlAs barrier layer is adjacent to the collection layer
  • the emission layer is disposed between the double barrier quantum well structure
  • the first spacer layer and the second spacer layer function mainly to isolate the emitter/receiver layer from the undoped double barrier region.
  • the first spacer layer includes a Si doping concentration of 2-5 ⁇ 10 16 cm 1
  • the second spacer layer comprising a sixth InGaAs doped layer having a Si doping concentration of 2-5 ⁇ 10 16 cm 1 and an undoped second An InGaAs spacer layer; wherein the first InGaAs spacer layer and the second InGaAs spacer layer are adjacent to the double barrier quantum well structure. More preferably, the first InGaAs spacer layer has a thickness of 20-50 people, and the second InGaAs spacer layer has a thickness of 20-50 A.
  • the fifth InGaAs doped layer has a thickness of 500-1200 ⁇
  • the sixth InGaAs doped layer has a thickness of 500-1200 A, a first InGaAs spacer layer and a fifth InGaAs doped layer
  • the first spacer layer composed of the thickness is sufficient to reduce the penetration of the fourth InGaAs doped layer into the second AlAs barrier layer, and the diffusion of the doping concentration of the barrier layer by the high doping layer can be prevented.
  • the second spacer layer composed of the thickness of the second InGaAs spacer layer and the sixth InGaA s doped layer is sufficient to reduce the penetration of the second InGaAs doped layer into the first A1 As barrier layer, and also prevent high doping concentration The diffusion of the layer to the doping concentration of the barrier layer.
  • the first AlAs barrier layer is adjacent to the emission layer
  • the second AlAs barrier layer is adjacent to the collection layer, and the opposite surface of the emission layer and the double barrier quantum well structure An InP substrate is provided.
  • a buffer layer is further disposed between the InP substrate and the emission layer.
  • the buffer layer is an undoped InP layer or an undoped I nAlAs layer.
  • the buffer layer has a thickness of 2,000 people, which is sufficient to prevent diffusion of the doping concentration of the upper layer of the high concentration doping layer.
  • an embodiment of the present invention further provides a method for fabricating the resonant tunneling diode wafer structure, including the following steps:
  • S02 generating the collection layer of the resonant tunneling diode wafer structure, the double barrier quantum well structure, and the emission layer on the substrate by using a micro-nano processing technique.
  • the method for preparing the resonant tunneling diode wafer structure generateds the resonant tunneling diode wafer structure on a substrate by using a micro-nano processing technique, which is simple and easy, low in cost, and finally
  • the resulting resonant tunneling diode wafer structure has more electrons to migrate under the same operating bias, greater current response, increased peak-to-valley current ratio (AI), and increased in the sub-well layer
  • the resonant level also increases the bias operating voltage of the device and increases the peak-to-valley voltage ratio (AV).
  • Embodiments of the present invention further provide a resonant tunneling diode including the resonant tunneling diode wafer structure of the present invention; the resonant tunneling diode includes a double-barrier quantum well structure of a three-layer structure of InGaAs-InAs-InGaAs.
  • the effective mass of the electron can be reduced, thereby increasing the energy interval between the quantum confinement bound states, and also reducing the ground state energy of the quantum well, so that the resonant tunneling diode has a peak-to-valley current ratio.
  • Embodiments of the present invention also provide a single-chip terahertz integrated circuit radiation source, the single-chip terahertz integrated circuit radiation source including the above-described resonant tunneling diode of the embodiment of the present invention.
  • the single piece provided by the embodiment of the present invention is too Hertz integrated circuit radiation source, because of the unique resonant tunneling diode of the present invention, the resonant tunneling diode has more electrons to migrate under the same working bias, and the current response is larger, and the peak-to-valley current ratio is increased (AI).
  • the increased resonant level in the sub-well layer also increases the bias operating voltage of the device and increases the peak-to-valley voltage ratio (AV), so the monolithic terahertz integrated circuit radiation source has Less power and cost.
  • AV peak-to-valley voltage ratio
  • FIG. 4 is a cross-sectional layer structure of an RTD device formed by preparing an indium phosphide wafer having a double-barrier quantum well structure of a sub-well layer, and each layer is as shown in Table 1.
  • the preparation method comprises: firstly, using MBE (molecular beam epitaxy) to grow an indium phosphide-based wafer from bottom to top according to the layer thickness and the doping concentration and the order provided in Table 1, and the InP lining from bottom to top respectively.
  • MBE molecular beam epitaxy
  • an InP buffer layer or an InGaAs buffer layer a heavily doped n ++ -InGaAs layer and a lightly doped n + -InGaAs layer (as an emissive layer Afe collector layer, this embodiment is preferably an emissive layer, n - Depositing metal on the InGaAs layer to form a metal contact to place the working bias electrode), lighter doped InGaAs layer and undoped InGaAs layer
  • a double-barrier quantum well structure including two layers of u-AlAs barrier layers, two layers of u-InGaAs well layers, one layer of u-InAs sub-well layers), and four of the double-barrier quantum well structures
  • the layer structure forms a symmetrical structure with the lower four layers, and has the same parameters and functions. On the uppermost layer, it is heavily doped n.
  • the structure of the RTD device shown in Fig. 4 is formed using a micro-nano process.
  • the specific micro-nano process is to first deposit metal on a specific area of the first layer of n-InGaAs layer to form a metal ohmic contact.
  • etching is performed by acid wet etching until the uppermost n + MnGaAs layer, and metal is deposited on a specific area on the surface thereof to form a metal ohmic contact.
  • a second wet etch etch is performed to the undoped InP substrate, thereby isolating adjacent devices, insulating the effects of interconnection between the devices due to the interconnection of the conductive layers.
  • FIG. 3 is a diagram showing the variation of the energy level of a double-barrier quantum well structure having an Asian well layer under different operating bias voltages of the RTD device of this embodiment.
  • Vp bias voltage of peak voltage
  • the compressive strain of the InAs layer counteracts the tensile strain of AlAs, which may be an important consideration for the development of multi-layer RTD heterostructures.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

L'invention concerne une structure de tranche de diode à effet tunnel résonant et un procédé de préparation. La structure de tranche de diode à effet tunnel résonant comprend une couche de collecte, une structure de puits quantique de barrière à double potentiel, et une couche de transmission qui sont agencées de manière empilée ; la structure de puits quantique à double barrière de potentiel comprend une première couche barrière de potentiel d'AlAs, une première couche de puits de potentiel d'InGaAs, une seconde couche de puits de potentiel d'InGaAs, et une seconde couche barrière de potentiel d'InGaAs qui sont agencées de manière empilée ; et une couche de puits de sous-potentiel d'InAs est disposée entre la première couche de puits de potentiel d'InGaAs et la seconde couche de puits de potentiel d'InGaAs. La première couche barrière de potentiel d'AlAs est proche de la couche de collecte, et la seconde couche barrière de potentiel AlAs est proche de la couche de transmission ; ou la première couche barrière de potentiel d'AlAs est proche de la couche de transmission, et la seconde couche barrière de potentiel d'AlAs est proche de la couche de collecte. Dans une même polarisation de fonctionnement, la structure de tranche de diode à effet tunnel résonnant réalise une migration de plus d'électrons, rend la réponse en courant supérieure, et augmente un rapport de courant de crête à vallée.
PCT/CN2018/082494 2018-04-10 2018-04-10 Structure de tranche de diode à effet tunnel résonnant ayant un rapport de courant de crête à vallée élevé, et son procédé de préparation WO2019196008A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070145347A1 (en) * 2005-12-22 2007-06-28 International Business Machines Corporation Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same
CN104752524A (zh) * 2015-02-17 2015-07-01 天津大学 一种超窄双阱的共振隧穿二极管器件
CN105047725A (zh) * 2015-06-08 2015-11-11 中国科学院半导体研究所 基于共振隧穿效应的近红外探测器
CN106653863A (zh) * 2016-10-19 2017-05-10 四川大学 一种带GaN子阱的RTD发射区新设计

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070145347A1 (en) * 2005-12-22 2007-06-28 International Business Machines Corporation Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same
CN104752524A (zh) * 2015-02-17 2015-07-01 天津大学 一种超窄双阱的共振隧穿二极管器件
CN105047725A (zh) * 2015-06-08 2015-11-11 中国科学院半导体研究所 基于共振隧穿效应的近红外探测器
CN106653863A (zh) * 2016-10-19 2017-05-10 四川大学 一种带GaN子阱的RTD发射区新设计

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