WO2019178748A1 - 频率产生器 - Google Patents

频率产生器 Download PDF

Info

Publication number
WO2019178748A1
WO2019178748A1 PCT/CN2018/079632 CN2018079632W WO2019178748A1 WO 2019178748 A1 WO2019178748 A1 WO 2019178748A1 CN 2018079632 W CN2018079632 W CN 2018079632W WO 2019178748 A1 WO2019178748 A1 WO 2019178748A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
signal
phase
output
coupled
Prior art date
Application number
PCT/CN2018/079632
Other languages
English (en)
French (fr)
Inventor
黄彦颖
张镕谕
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2018/079632 priority Critical patent/WO2019178748A1/zh
Priority to CN201880000473.8A priority patent/CN110506394B/zh
Priority to EP18782865.2A priority patent/EP3567727A4/en
Priority to US16/158,312 priority patent/US11086353B2/en
Publication of WO2019178748A1 publication Critical patent/WO2019178748A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation

Definitions

  • the present application relates to a frequency generator, and more particularly to a fractional frequency generator that reduces power consumption.
  • Electronic systems require frequency signals of different frequencies to accommodate different operations or applications. Based on design and cost considerations, electronic systems typically generate signals of various frequencies based on reference frequency signals.
  • FIG. 1 is a schematic diagram of a phase locked loop 10.
  • the phase locked loop 10 includes a frequency phase detector 100, a charge pump 102, a low pass filter 104, a voltage controlled oscillator 106, and a frequency divider 108.
  • the frequency divider 108 can perform an integer divisor division operation on the output signal CKOUT.
  • the frequency phase detector 100 is configured to receive the divided output signal CKOUT and the reference frequency signal CKIN, and compare the frequency and phase of the two to generate a comparison result.
  • the charge pump 102 is coupled to the frequency phase detector 100 for charging or discharging according to the comparison result generated by the frequency phase detector 100 to generate different voltage signals, and filtering the frequency phase detector 100 through the low pass filter 104. After the generated high frequency noise, the voltage controlled oscillator 106 is adjusted to generate a corresponding oscillation frequency. As a result, the output frequency signal CKOUT generated by the phase locked loop 10 and the reference frequency signal CKIN are in an integer divisor relationship.
  • the bandwidth of the phase-locked loop 10 can be reduced to suppress the noise in the frequency band, so that the bandwidth of the loop filter needs to be reduced to reduce the noise.
  • the noise of the voltage-controlled oscillator 106 is also increased due to the bandwidth, resulting in a decrease in the quality of the frequency signal.
  • FIG. 2 is a schematic diagram of a frequency synthesizer 20.
  • the frequency synthesizer 20 includes a frequency phase detector 200, a charge pump 202, a low pass filter 204, a voltage controlled oscillator 206, a programmable frequency divider 208, and a delta-sigma modulator 210.
  • the frequency synthesizer 20 replaces the frequency divider with a programmable frequency divider 208, and additionally includes a delta-sigma modulator 210. Therefore, the frequency synthesizer 20 can receive the divided output signal CKOUT by the delta-sigma modulator 210, thereby adjusting the divisor of the programmable frequency divider 208.
  • the average of the output signal CKOUT generated by the frequency synthesizer 20 is in a fractional divisor relationship with the reference frequency signal CKIN.
  • the delta-sigma modulator 208 in the frequency synthesizer 20 generates additional quantization noise, it is necessary to reduce the loop bandwidth or increase the resolution of the programmable demultiplexer 208 to suppress quantization noise, wherein The loop bandwidth requires an increase in circuit area, and increasing the resolution requires an increase in the number of output phases of the voltage controlled oscillator 206, thus generating additional power consumption.
  • the embodiment of the present application provides a frequency generator
  • the frequency generator includes a delta-sigma modulator for generating a divisor control signal and a phase control signal, and an oscillator for generating an oscillating signal.
  • the oscillating signal has a first frequency;
  • the tunable frequency divider is configured to perform a frequency dividing operation on the first signal according to the divisor control signal to generate a first frequency dividing signal and a second frequency dividing signal, where The first frequency-divided signal and the second frequency-divided signal have a second frequency; and a phase interpolator for the first frequency-divided signal and the second frequency-divided signal according to the phase control signal
  • a phase interpolation operation is performed to generate an output signal having an output frequency; wherein the first frequency is greater than the second frequency.
  • the first frequency is an integer multiple of the second frequency.
  • the second frequency division signal is delayed by one time period than the first frequency division signal, and the time period is a period of the oscillation signal.
  • the output signal is delayed compared to the first divided signal, and the second divided signal is delayed from the output signal.
  • the phase interpolator includes a first interpolation module, and includes a plurality of buffers coupled between the first frequency division signal and the interpolation node; and a second interpolation module including a plurality of buffer couplings And between the second frequency dividing signal and the interpolation node; and an output buffer coupled to the interpolation node for generating the output signal.
  • the delta-sigma modulator further receives a ratio signal to generate the divisor control signal and the phase control signal.
  • the frequency generator further includes a frequency detector coupled to the phase interpolator for receiving a ratio signal and a reference signal, comparing the reference signal and the output signal to generate a comparison signal, wherein The reference signal has a reference frequency; and a low pass filter coupled between the frequency detector and the delta-sigma modulator to filter high frequency noise of the comparison signal.
  • the delta-sigma modulator receives the comparison signal after filtering high frequency noise to generate the divisor control signal and the phase control signal, instructing the adjustable frequency divider to perform a frequency division operation and an indication
  • the phase interpolator performs a phase interpolation operation such that a ratio of the output frequency to the reference frequency is a fraction.
  • the phase frequency detector includes a first D-type flip-flop, including a D data input end coupled to the system supply power source, a frequency input end coupled to the output signal, and a data output end configured to generate the first a comparison signal, and a reset terminal;
  • the second D-type flip-flop includes a D data input end coupled to the ground, the frequency input end coupled to the reference signal, and the data output end configured to generate a second comparison signal, and a reset circuit; a digital circuit configured to receive a ratio signal, the first comparison signal and the second comparison signal to compare the output frequency and the reference frequency, and generate the comparison signal; and a NAND gate
  • the first data input terminal includes the first comparison signal
  • the second data input terminal receives the second comparison signal
  • the data output end is coupled to the reset end of the first D-type flip-flop, and The reset end of the second D-type flip-flop.
  • the frequency generator further includes a phase-locked loop coupled to the phase interpolator for filtering high frequency noise generated by the delta-sigma modulator.
  • Figure 1 is a schematic diagram of a phase locked loop.
  • FIG. 2 is a schematic diagram of a frequency synthesizer.
  • FIG. 3 is a schematic diagram of a frequency generator according to an embodiment of the present application.
  • phase interpolator 4 is a schematic diagram of a phase interpolator according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another frequency generator according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a frequency detector according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another frequency generator according to an embodiment of the present application.
  • embodiments of the present application provide a low noise fractional frequency generator.
  • the oscillator in the frequency generator In order to generate a low-noise output signal, the oscillator in the frequency generator generates a single-frequency and low-noise high-frequency signal, and the operating frequency is reduced by the frequency divider, so that the circuit performs phase interpolation at a low frequency, thereby reducing the frequency.
  • the power consumption of the generator increases the linearity of the signal.
  • FIG. 3 is a schematic diagram of a frequency generator 30 according to an embodiment of the present application.
  • the frequency generator 30 includes an oscillator 300, an adjustable frequency divider 302, a phase interpolator 304, and a delta-sigma modulator 306.
  • the oscillator 300 can oscillate at a first frequency to generate an oscillating signal CK_OSC having a first frequency.
  • the adjustable frequency divider 302 is coupled to the oscillator 300 for performing an integer frequency division operation on the first signal to generate a first frequency-divided signal CK_DIV and a second frequency-divided signal CK_DIV_D delayed by one cycle.
  • the phase interpolator 304 is coupled to the adjustable frequency divider 302 for phase interpolating the first frequency divided signal CK_DIV and the second frequency divided signal CK_DIV_D to generate a phase between the first frequency divided signal CK_DIV and the first The output signal CKOUT between the two divided signals CK_DIV_D.
  • the triangular integral modulator 306 is configured to receive a control code to control the adjustable frequency divider 302 and the phase interpolator 304. In other words, the triangular integral modulator 306 can generate a divisor control signal and a phase control signal. The divisor between the first frequency and the second frequency is respectively adjusted, and the delay between the first divided signal CK_DIV and the output signal CKOUT is adjusted.
  • the oscillator 300 of the present application can generate a low-noise high-frequency frequency signal and oscillate in a high-frequency frequency band.
  • the adjustable frequency divider 302 can perform frequency division operations of different divisors, and according to the indication of the triangular integral modulator 306 to determine the divisor of the frequency division operation, to generate the first frequency division signal CK_DIV in the low frequency band, the adjustable frequency divider 302 also delays the first frequency-divided signal CK_DIV by one cycle of the oscillating signal CK_OSC to generate a second frequency-divided signal CK_DIV_D.
  • the phase interpolator 304 can perform a phase interpolation operation on the first frequency divided signal CK_DIV and the second frequency divided signal CK_DIV_D, and according to the indication of the triangular integral modulator 306 to determine the phase of the output signal CKOUT, providing the required delay to the A frequency dividing signal CK_DIV is used to adjust the period of the output signal CKOUT, in other words, to adjust the frequency of the output signal CKOUT.
  • the adjustable frequency divider 302 provides an integer frequency divisor and the phase interpolator 304 provides a fractional frequency divisor such that the frequency generator 30 utilizes a delta-sigma modulator 306 to indicate an adjustable divide frequency.
  • the converter 302 and the phase interpolator 304 can perform a fractional type of frequency division operation.
  • the delta-sigma modulator 306 can receive a divisor signal and a phase control signal by receiving a ratio signal Ratio.
  • the frequency generator 30 first performs the frequency division operation through the adjustable frequency divider 302 to reduce the frequency of the signal, and then transmits the first frequency division.
  • the signal CK_DIV to the phase interpolator 304 performs a phase internal difference operation, such that, in the case where the operating frequency is low and the time per unit period is long, the phase interpolator 304 can be implemented by a simple digital circuit. Reducing power consumption, there is ample time for phase interpolation to generate a linearity better output signal CKOUT, and no additional driver circuit (such as level shifter) is required to drive the oscillator 300.
  • the signal is applied to the phase interpolator 304, whereby the present application can reduce the power consumption of the output drive circuit and improve the quality of the output signal CKOUT. Furthermore, since the frequency generator 30 of the present application does not need to generate the output signal CKOUT by a reference frequency signal, the frequency generator 30 uses the oscillator 300 to generate a high frequency frequency signal of a single frequency, in which case The oscillator 300 does not need to be applied to wideband operation, thus reducing the design complexity of the oscillator 300 and improving the signal quality produced by the oscillator 300. Finally, the present application reduces the operating frequency through the adjustable frequency divider 302 so that the phase interpolator 304 of the frequency generator 30 can process the signal at a low frequency, reducing its power consumption.
  • the frequency generator 30 of the present application can utilize the oscillator 300, the adjustable frequency divider 302, the phase interpolator 304, and the delta-sigma modulator 306 to generate a low-noise signal path with adjustable frequency division.
  • the device 302 reduces the operating frequency to reduce power consumption to achieve a low power, low noise, fractional frequency generator.
  • FIG. 4 is a schematic diagram of a phase interpolator 404 according to an embodiment of the present application.
  • the phase interpolator 404 includes an interpolation module 4040 , 4042 and a buffer BUF_OUT.
  • the interpolation module 4040 is coupled between the first frequency division signal CK_DIV and an interpolation node 404N, wherein the interpolation module includes N buffers BUF_1 BB BUF_N connected in parallel to the first frequency division signal CK_DIV and the interpolation node 404N.
  • the interpolating module 4042 is coupled between the second frequency dividing signal CK_DIV_D and the interpolation node 404N, wherein the interpolation module 4042 includes a plurality of buffers BUF_N+1 ⁇ BUF_2N connected in parallel to the second frequency dividing signal CK_DIV_D and Between the nodes 404N.
  • the phase of the signal on the interpolation node 404N is determined according to the phase of the first frequency-divided signal CK_DIV, the second frequency-divided signal CK_DIV_D, and the driving capability of the interpolation modules 4040 and 4042, and the interpolation node 404N is driven via the buffer BUF_OUT.
  • the upper signal produces an output signal CKOUT.
  • the interpolation module 4040 controls the opening or closing of the buffers BUF_1 to BUF_N through the interpolation weight signals S_1 to S_N, respectively; the interpolation module 4042 controls the buffer BUF_N+ through the interpolation weight signals S_N+1 to S_2N, respectively.
  • 1 ⁇ BUF_2N is turned on or off. For example, when the interpolation weight signals S_1 to S_N indicate that only one buffer is turned on in the buffers BUF_1 to BUF_N, and the interpolation weight signals S_N+1 to S_2N indicate that N-1 buffers are turned on in the buffers BUF_N+1 to BUF_2N.
  • the phase weight of the first frequency-divided signal CK_DIV representing the interpolation node 404N is 1/N
  • the phase weight of the second frequency-divided signal CK_DIV_D is N-1/N
  • the interpolation node 404N A signal phase having a phase weight of the first frequency-divided signal CK_DIV of 1/N and a phase weight of the second frequency-divided signal CK_DIV_D of N-1/N is generated, and is driven via the buffer BUF_OUT to generate an output signal CKOUT.
  • the phase interpolator 404 has 2N interpolated weight signals S_1 S S_2N to perform phase interpolation operations on the first divided signal CK_DIV and the second divided signal CK_DIV_D.
  • the number of output phases can be increased by increasing the number of oscillator stages or by interpolating the oscillator output, in addition to increasing the oscillator. In addition to power consumption, additional power is also required to drive the signal.
  • the present invention produces an output signal by reducing the number of oscillator signal phases and reducing the operating frequency of the phase interpolator, thereby achieving a low power frequency generator.
  • the frequency generator may further include a frequency detector and a low pass filter, wherein the frequency detector is coupled to the phase interpolator for receiving a ratio signal Ratio and comparing the output signal with a The reference signal CKIN; the low-pass filter is coupled between the frequency detector and the delta-sigma modulator to filter the high-frequency noise signal of the frequency detector.
  • FIG. 5 is a schematic diagram of another frequency generator 50 according to an embodiment of the present application.
  • the frequency generator 50 is derived from the frequency generator 30, and thus the same components are denoted by the same symbols.
  • the frequency generator 50 includes an oscillator 300, an adjustable frequency divider 302, a phase interpolator 304, a delta-sigma modulator 306, a frequency detector 508, and a low pass filter 510.
  • the delta-sigma modulator 306 can generate the divisor control signal by using the indication of the frequency detector 508, in addition to directly receiving the ratio signal to generate the divisor control signal and the phase control signal. Phase control signal.
  • the frequency detector 508 is coupled to the phase interpolator 304 for receiving the ratio signal Ratio, and comparing the output signal CKOUT with the reference signal CKIN to generate the comparison signal Comp and transmitting to the low pass filter 510, and the low pass filter 510 filters In addition to the high frequency noise signal in the comparison signal Comp, it is passed to the delta-sigma modulator 306 to further instruct the adjustable frequency divider 302 to adjust the divisor of the divisor operation and the phase interpolator 304 to adjust the phase of the output signal CKOUT.
  • the frequency detector 508 is based on the ratio signal Ratio to compare whether the ratio of the output frequency of the output signal CKOUT to the reference frequency of the reference signal CKIN matches the ratio indicated by the ratio signal Ratio, and generates a corresponding comparison signal Comp.
  • the frequency generator 50 can use the frequency detector 508 to compare the reference signal CKIN with the output signal CKOUT to generate a comparison signal Comp, which is fed back to the delta-sigma modulator 306 through the low-pass filter 510.
  • the adjustable frequency divider 302 and the phase interpolator 304 are controlled such that when the first signal generated by the oscillator 300 has an error, the frequency generator 50 can pass the frequency detector 508 and low pass filtering.
  • the feedback loop generated by the 510 is used to adjust the frequency division operation of the frequency generator 50.
  • the frequency detector 508 receives the reference signal CKIN to compare the frequency of the reference signal CKIN and the output signal CKOUT, thereby dynamically adjusting the divisor of the frequency division operation of the adjustable frequency divider 302, and adjusting the phase interpolator 304.
  • the phase interpolation operation causes the frequency generator 50 to generate an output signal CKOUT required by the electronic system.
  • the frequency of the output signal CKOUT and the frequency of the reference signal CKIN can maintain a fixed fractional relationship according to the ratio signal Ratio for the oscillator 300.
  • the average frequency is generated as the output signal CKOUT required by the system.
  • the frequency generator 50 of the present application utilizes an externally input reference signal CKIN in the signal path, wherein the reference signal CKIN may have a large in-band noise, however, the present application utilizes a frequency detector. 508 only takes out the characteristic of the frequency information of the reference signal CKIN, and can effectively block the noise of the reference signal CKIN in the generation path of the output signal CKOUT, and achieve a low-power low-noise fractional frequency generator.
  • FIG. 6 is a schematic diagram of a frequency detector 608 according to an embodiment of the present application.
  • the frequency detector 608 includes a D-Flip-flop (DFF) DFF1, DFF2, a NAND gate 6080, and a digital unit 6082.
  • DFF D-Flip-flop
  • the D-type flip-flop DFF1 includes a data input end coupled to the system supply power supply VDD, a frequency input end coupled to the output signal CKOUT, a data output end for generating the first comparison signal C1, and a reset terminal;
  • the flip-flop DFF2 includes a data input end coupled to a ground GND, a frequency input end coupled to the reference signal CKIN, a data output end for generating a second comparison signal C2, and a reset terminal;
  • the NAND gate 6080 is coupled Connected between the first output terminal, the second output terminal, and the D-type flip-flops DFF1 and DFF2, the NAND gate 6080 includes a first data input terminal to receive the first comparison signal C1, and a second data input terminal to receive the second data input terminal.
  • the comparison signal C2 and a data output end are coupled to the reset ends of the D-type flip-flops DFF1 and DFF2.
  • the digital unit 6082 is coupled to the D-type flip-flops DFF1 and DFF2 for receiving the ratio signal Ratio between the first comparison signal C1 and the second comparison signal C2 to determine the output frequency of the output signal CKOUT and the reference frequency of the reference signal CKIN. Whether the ratio corresponds to the indication of the ratio signal Ratio, thereby generating the comparison signal Comp.
  • the frequency detector 608 can use the D-type flip-flops DFF1 and DFF2 to obtain the frequency information of the comparison output signal CKOUT and the reference signal CKIN, and pass the NAND gate 6080 to reset the D-type flip-flops DFF1 and DFF2.
  • the digital unit 6082 can determine the ratio between the frequency of the output signal CKOUT and the frequency of the reference signal CKIN according to the ratio signal Ratio to generate the comparison signal Comp, and the comparison signal Comp generated by the frequency detector 608 is filtered through the low-pass filter 510. After the noise is passed to the delta-sigma modulator, the divisor operation of the adjustable demultiplexer 302 and the phase interpolation of the phase interpolator 304 are adjusted by adjusting the divisor control signal and the phase control signal.
  • the frequency generator may further comprise a phase-locked loop, wherein the phase-locked loop is coupled to the phase interpolator for filtering out quantization noise generated by the delta-sigma modulator.
  • FIG. 7 is a schematic diagram of another frequency generator 70 according to an embodiment of the present application.
  • the frequency generator 70 is derived from the frequency generator 50, and thus the same components are denoted by the same symbols.
  • the frequency generator 70 includes an oscillator 300, an adjustable frequency divider 302, a phase interpolator 304, a delta-sigma modulator 306, a frequency detector 508, a low pass filter 510, and a phase locked loop 712.
  • the phase-locked loop 712 is coupled to the phase interpolator 304 for filtering out the high-frequency quantization noise generated by the delta-sigma modulator 306 and further reducing the noise of the output signal CKOUT.
  • the frequency generator 70 of the present invention since the frequency generator 70 of the present invention generates a signal path of the output frequency through the oscillator 300, it has greatly reduced the noise in the bandwidth in the reference signal path and the high frequency quantization noise generated by the triangular integral modulator 306, if desired Further reducing the high frequency quantization noise of the delta-sigma modulator 306, the present invention can filter the quantization noise through the phase-locked loop 712 to meet system requirements.
  • phase locked loop 712 since the high frequency quantization noise has been reduced by the system architecture of the frequency generator 70, the phase locked loop 712 only needs to be optimized for the high frequency quantization noise generated by the triangular integral modulator 306, and does not need to be designed as The low bandwidth phase-locked loop, in this way, greatly reduces the design complexity, circuit area and power consumption of the phase-locked loop 712.
  • the frequency of the present application when the input signal and the output signal are in a multiple of the fractional type, in order to obtain a good output signal quality, it is often achieved by increasing manufacturing cost and power consumption, in contrast, the frequency of the present application.
  • the generator generates a clean high frequency signal through the oscillator.
  • the adjustable frequency divider first reduces the operating frequency, and then adjusts the required output phase by the phase interpolator to achieve the desired output frequency.
  • the applied frequency generator can achieve a low power and low noise fractional frequency generator.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

一种频率产生器，所述频率产生器包括三角积分调变器，用来产生除数控制信号以及相位控制信号；振荡器，用来产生振荡信号，其中所述振荡信号具有第一频率；可调式除频器，用来根据所述除数控制信号对所述振荡信号进行除频操作，以产生第一除频信号以及第二除频信号，其中所述第一除频信号以及所述第二除频信号具有第二频率；以及相位内插器，用来根据所述相位控制信号对所述第一除频信号以及所述第二除频信号进行相位内插操作，以产生输出信号，所述输出信号具有输出频率；其中，所述第一频率大于所述第二频率。

Description

频率产生器 技术领域
本申请涉及一种频率产生器，尤其涉及一种降低功率消耗的分数型频率产生器。
背景技术
电子系统需要不同频率的频率信号以适应不同的操作或应用，基于设计与成本考虑，电子系统通常是根据参考频率信号产生各种不同频率的信号。
一般来说，若所需要的频率信号与参考频率信号之间为整数的倍数关系，电子系统可藉由锁相回路(Phase-Locked Loop，PLL)取得所需要的频率；若所需要的频率信号与参考频率信号之间的倍数关系为分数的倍数关系，电子系统可藉由频率合成器(Frequency Synthesizer)取得。请参考图1，图1为一锁相回路10的示意图。锁相回路10包括频率相位侦测器100、充电泵102、低通滤波器104、压控振荡器106以及除频器108。首先，除频器108可对输出信号CKOUT进行整数除数的除频操作。频率相位侦测器100用来接收除频后的输出信号CKOUT以及参考频率信号CKIN，且比较两者的频率以及相位以产生比较结果。充电泵102耦接于频率相位侦测器100，用来根据频率相位侦测器100产生的比较结果进行充电或放电以产生不同电压信号，通过低通滤波器104滤除频率相位侦测器100产生的高频噪声后，调整压控振荡器106产生相对应的振荡频率。如此一来，锁相回路10产生的输出频率信号CKOUT与参考频率信 号CKIN之间为整数除数的关系。值得注意的是，若锁相回路10中的参考频率信号CKIN带宽内噪声很大时，可降低锁相回路10的带宽以抑制频带内噪声，如此一来需降低回路滤波器的带宽以降低噪声，却也伴随着回路滤波器的面积增加，造成锁相回路10的生产成本增加，除此之外，压控振荡器106的噪声也会因为带宽的缘故而提高，造成频率信号质量降低。
另外，请参考图2，图2为一频率合成器20的示意图。频率合成器20包括频率相位侦测器200、充电泵202、低通滤波器204、压控振荡器206、可程序化除频器208以及三角积分调变器210。相较于锁相回路10，频率合成器20以可程序化除频器208代替除频器，另包括三角积分调变器210。因此，频率合成器20可利用三角积分调变器210接收除频后的输出信号CKOUT，进而调整可程序化除频器208的除数。如此一来，频率合成器20产生的输出信号CKOUT的平均与参考频率信号CKIN之间为分数除数的关系。然而，由于频率合成器20中的三角积分调变器208会产生额外的量化噪声(Quantization Noise)，需降低回路带宽或提高可程序化除频器208的分辨率以抑制量化噪声，其中，降低回路带宽需要增加电路面积，提高分辨率需要增加压控振荡器206的输出相位数量，因而产生额外的功率消耗。
简单而言，不论透过锁相回路或是频率合成器，皆无法排除参考频率信号带宽内噪声，且在系统需求高分辨率的时候，更需透过增加输出信号的相位数量，如此一来，即增加系统的制造成本以及功率消耗。因此，现有技术实有改善的必要。
发明内容
因此，本申请部分实施例的目的即在于提供一种低功率且低噪声的分数型除数频率产生器，以改善现有技术的缺点。
为了解决上述技术问题，本申请实施例提供了一种频率产生器，所述频率产生器包括三角积分调变器，用来产生除数控制信号以及相位控制信号；振荡器，用来产生振荡信号，其中所述振荡信号具有第一频率；可调式除频器，用来根据所述除数控制信号对所述第一信号进行除频操作，以产生第一除频信号以及第二除频信号，其中所述第一除频信号以及所述第二除频信号具有第二频率；以及相位内插器，用来根据所述相位控制信号对所述第一除频信号以及所述第二除频信号进行相位内插操作，以产生输出信号，所述输出信号具有输出频率；其中，所述第一频率大于所述第二频率。
例如，所述第一频率为所述第二频率的整数倍。
例如，所述第二除频信号比所述第一除频信号延迟一个时间周期，所述时间周期为所述振荡信号的周期。
例如，所述输出信号比所述第一除频信号延迟，且所述第二除频信号比所述输出信号延迟。
例如，所述相位内插器包括第一内插模块，包括复数个缓冲器耦接于所述第一除频信号及内插节点之间；第二内插模块，包括复数个缓冲器耦接于所述第二除频信号及所述内插节点之间；以及输出缓冲器，耦接于所述内插节点，用来产生所述输出信号。
例如，所述三角积分调变器另接收一比值信号以产生所述除数控制信号以及所述相位控制信号。
例如，所述频率产生器，另包括频率侦测器，耦接于所述相位内插器，用来接收比值信号和参考信号，比较参考信号以及所述输出信号以产生比较信号，其中所述参考信号具有参考频率；以及低通滤波器，耦接于所述频率侦测器以及所述三角积分调变器之间，用来滤除所述比较信号的高频噪声。
例如，所述三角积分调变器接收滤除高频噪声后的所述比较信号，以产生所述除数控制信号以及所述相位控制信号，指示所述可调式除频器进行除频操作以及指示所述相位内插器进行相位内插操作，使所述输出频率与所述参考频率的比值为分数。
例如，所述相位频率侦测器包括一第一D型正反器，包括D数据输入端，耦接于系统供应电源，频率输入端耦接于所述输出信号，数据输出端用来产生第一比较信号，以及复位端；第二D型正反器，包括D数据输入端，耦接于地，频率输入端耦接于所述参考信号，数据输出端用来产生第二比较信号，以及复 位端；数字电路，用来接收比值信号，所述第一比较信号以及所述第二比较信号，以比较所述输出频率以及所述参考频率，且产生所述比较信号；以及与非门，包括第一数据输入端接收所述第一比较信号，第二数据输入端接收所述第二比较信号，以及数据输出端耦接于所述第一D型正反器的所述复位端、以及所述第二D型正反器的所述复位端。
例如，所述频率产生器还包括锁相回路，耦接于所述相位内插器，用来滤除所述三角积分调变器产生的高频噪声。
附图说明
图1为一锁相回路的示意图。
图2为一频率合成器的示意图。
图3为本申请实施例一频率产生器的示意图。
图4为本申请实施例一相位内插器的示意图。
图5为本申请实施例另一频率产生器的示意图。
图6为本申请实施例一频率侦测器的示意图。
图7为本申请实施例另一频率产生器的示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅 仅用以解释本发明，并不用于限定本发明。此外，本发明用来描述两组件之间的链接关系所使用的文字，例如「耦接」以及「连接」，不应用来限制两组件之间的连接关系为直接连结或间接连结。
在以下说明中，本申请实施例提供了一种低噪声的分数型频率产生器。为了产生低噪声的输出信号，频率产生器中的振荡器产生单一频率且低噪声的高频信号，以及藉由除频器降低操作频率，使电路于低频下进行相位内插操作，因而降低频率产生器的功率消耗且提升信号的线性度。
请参考图3，图3为本申请实施例一频率产生器30的示意图。频率产生器30包括振荡器300、可调式除频器302、相位内插器304以及三角积分调变器306。振荡器300可于第一频率振荡而产生具第一频率的一振荡信号CK_OSC。可调式除频器302耦接于振荡器300，用来对第一信号进行整数的除频操作，以产生第一除频信号CK_DIV，及延迟一周期的一第二除频信号CK_DIV_D。相位内插器304耦接于可调式除频器302，用来对第一除频信号CK_DIV以及第二除频信号CK_DIV_D进行相位内插操作，以产生相位介于第一除频信号CK_DIV以及第二除频信号CK_DIV_D之间的输出信号CKOUT。三角积分调变器306则用来接收一控制码以控制可调式除频器302以及相位内插器304，换句话说，三角积分调变器306可产生一除数控制信号以及一相位控制信号，分别调整第一频率以及第二频率之间的除数，以及调整第一除频信号CK_DIV与输出信号CKOUT之间的延迟。
本申请的振荡器300可产生低噪声的高频频率信号，于高频的频段进行振荡。可调式除频器302可进行不同除数的除频操作，根据三角积分调变器306的指示以决定除频操作的除数，以于低频的频段产生第一除频信号CK_DIV，可调式除频器302亦将第一除频信号CK_DIV延迟振荡信号CK_OSC的一周期以产生第二除频信号CK_DIV_D。相位内插器304可对第一除频信号CK_DIV以及第二除频信号CK_DIV_D进行相位内插操作，根据三角积分调变器306的指示以决定输出信号CKOUT的相位，提供所需要的延迟至第一除频信号CK_DIV以调整输出信号CKOUT的周期，换句话说，即调整输出信号CKOUT的频率。值得注意的是，可调式除频器302提供整数的频率除数，而相位内插器304提供分数的频率除数，如此一来，频率产生器30利用三角积分调变器306以指示可调式除频器302以及相位内插器304可进行分数型的除频操作。值得注意的是，三角积分调变器306可透过接收一比值信号Ratio以产生除数控制信号以及相位控制信号。
值得注意的是，透过本申请的本申请频率产生器30的架构，由频率产生器30先透过可调式除频器302进行除频操作将信号的频率降低后，再传递第一除频信号CK_DIV至相位内插器304进行相位内差操作，如此一来，在操作频率较低且每单位周期的时间较长的情况下，相位内插器304可利用简单的数字电路实现，藉此降低功率消耗，有较充裕的时间进行相位内插操作以产生线性度较佳的输出信号CKOUT外，且不需要额外的驱动电路(如位准偏移器(Level Shifter))以驱动振荡器300信号至相位内插器304，据此，本申请可降低输出驱动电路的功率消耗且改善输出信号CKOUT的质量。再者，由于本申请的 频率产生器30不需藉由一参考频率信号以产生输出信号CKOUT，取而代之，频率产生器30利用了振荡器300产生单一频率的高频频率信号，在这样的情况下，振荡器300不需要应用于宽带操作，因而降低振荡器300的设计复杂度且提升了振荡器300所产生的信号质量。最后，本申请透过可调式除频器302将操作频率降低，使频率产生器30的相位内插器304可于低频进行信号的处理，降低其功率消耗。简单来说，本申请的频率产生器30可利用振荡器300、可调式除频器302、相位内插器304以及三角积分调变器306产生低噪声的信号路径，并藉由可调式除频器302降低操作频率以降低功率消耗，以达到低功率低噪声的分数型频率产生器。
请参考图4，其为本申请实施例一相位内插器404的示意图，相位内插器404包括内插模块4040、4042以及缓冲器BUF_OUT。内插模块4040耦接于第一除频信号CK_DIV及一内插节点404N之间，其中内插模块包括N个缓冲器BUF_1～BUF_N，并联连接于第一除频信号CK_DIV以及内插节点404N之间；内插模块4042耦接于第二除频信号CK_DIV_D以及内插节点404N之间，其中内插模块4042包括复数个缓冲器BUF_N+1～BUF_2N，并联连接于第二除频信号CK_DIV_D以及内插节点404N之间。在内插节点404N上的信号相位会根据第一除频信号CK_DIV、第二除频信号CK_DIV_D的相位，以及内插模块4040、4042的驱动能力而决定，再经由缓冲器BUF_OUT驱动内插节点404N上的信号以产生输出信号CKOUT。详细而言，内插模块4040透过内插权重信号S_1～S_N分别控制缓冲器BUF_1～BUF_N的开启或关闭；内插模块4042透过内插权重信号S_N+1～S_2N分别控制缓冲器BUF_N+1～BUF_2N的开启 或关闭。举例来说，当内插权重信号S_1～S_N指示缓冲器BUF_1～BUF_N中仅开启一个缓冲器，且内插权重信号S_N+1～S_2N指示缓冲器BUF_N+1～BUF_2N中开启N-1个缓冲器时，代表在内插节点404N的第一除频信号CK_DIV的相位权重为1/N，且第二除频信号CK_DIV_D的相位权重为N-1/N，如此一来，于内插节点404N会产生第一除频信号CK_DIV的相位权重为1/N且第二除频信号CK_DIV_D的相位权重为N-1/N的信号相位，经由缓冲器BUF_OUT驱动以产生输出信号CKOUT。值得注意的是，在此实施例中，相位内插器404具有2N个内插权重信号S_1～S_2N，以对第一除频信号CK_DIV以及第二除频信号CK_DIV_D进行相位内插操作。
值得注意的是，在习知技术中，若要提高输出信号的分辨率，可以透过增加振荡器级数或是将振荡器输出加以内插以增加输出相位的数量，除了提高了振荡器的功率消耗外，亦需消耗额外的功率以驱动信号。因此，本发明透过较少的振荡器信号相位数量以及降低相位内插器的操作频率产生输出信号，可以因此达到低功率的频率产生器。
在一实施例中，频率产生器可另包括一频率侦测器以及一低通滤波器，其中频率侦测器耦接于相位内插器，用来接收一比值信号Ratio且比较输出信号与一参考信号CKIN；低通滤波器耦接于频率侦测器以及三角积分调变器之间，用来滤除频率侦测器的高频噪声信号。
请参考图5，其为本申请实施例另一频率产生器50的示意图。频率产生器 50由频率产生器30所衍生，因此相同组件以相同符号表示。频率产生器50包括振荡器300、可调式除频器302、相位内插器304、三角积分调变器306、频率侦测器508以及低通滤波器510。图5所示的实施例中，三角积分调变器306除了通过直接接收比值信号以产生除数控制信号以及相位控制信号之外，更可藉由频率侦测器508的指示以产生除数控制信号以及相位控制信号。频率侦测器508耦接于相位内插器304，用来接收比值信号Ratio，且比较输出信号CKOUT与参考信号CKIN以产生比较信号Comp并传递至低通滤波器510，低通滤波器510滤除比较信号Comp中的高频噪声信号后传递至三角积分调变器306以进一步指示可调式除频器302调整除频操作的除数以及相位内插器304调整输出信号CKOUT的相位。值得注意的是，频率侦测器508是根据比值信号Ratio以比较输出信号CKOUT的输出频率与参考信号CKIN的参考频率的比值是否符合比值信号Ratio所指示的比值，且产生相对应的比较信号Comp至三角积分调变器306。相较于频率产生器30，频率产生器50可利用频率侦测器508比较参考信号CKIN与输出信号CKOUT以产生比较信号Comp，透过低通滤波器510回授至三角积分调变器306，以控制可调式除频器302以及相位内插器304，如此一来，当振荡器300产生的第一信号有误差的情况下，频率产生器50可透过频率侦测器508与低通滤波器510产生的回授回路以调整频率产生器50的除频操作。详细而言，频率侦测器508接收参考信号CKIN以比较参考信号CKIN以及输出信号CKOUT的频率，藉此动态调整可调式除频器302的除频操作的除数，以及调整相位内插器304的相位内插操作，使频率产生器50产生电子系统所需的输出信号CKOUT。值得注意的是，藉由频率侦测器508与低通滤波器510的回授回路，输出信号CKOUT的频率与参考信号CKIN的 频率可根据比值信号Ratio维持固定的分数关系，以于振荡器300产生误差时产生平均频率为系统所需的输出信号CKOUT。除此之外，本申请的频率产生器50虽然于信号路径中利用了外部输入的参考信号CKIN，其中参考信号CKIN可能具有较大的in-band噪声，然而，本申请利用了频率侦测器508只取出参考信号CKIN的频率资讯的特性，可在输出信号CKOUT的产生路径上有效的阻隔参考信号CKIN的噪声，且达到低功率低噪声的分数型频率产生器。
此外，请参考图6，其为本申请实施例一频率侦测器608的示意图。其中，频率侦测器608包括D型正反器(D Flip-flop，DFF)DFF1、DFF2，一与非门6080以及一数字单元6082。D型正反器DFF1包括一数据输入端耦接于系统供应电源VDD、一频率输入端耦接于输出信号CKOUT、一数据输出端用来产生第一比较信号C1，以及一复位端；D型正反器DFF2包括一数据输入端耦接于一接地GND、一频率输入端耦接于参考信号CKIN、一数据输出端用来产生第二比较信号C2，以及一复位端；与非门6080耦接于第一输出端、第二输出端以及D型正反器DFF1、DFF2之间，与非门6080包括一第一数据输入端接收第一比较信号C1，一第二数据输入端接收第二比较信号C2、以及一数据输出端耦接于D型正反器DFF1、DFF2的复位端。数字单元6082耦接于D型正反器DFF1、DFF2，用来接收比值信号Ratio以第一比较信号C1以及第二比较信号C2，判断输出信号CKOUT的输出频率与参考信号CKIN的参考频率之间的比值是否符合比值信号Ratio的指示，进而产生比较信号Comp。如此一来，频率侦测器608可利用D型正反器DFF1、DFF2以取得比较输出信号CKOUT以及参考信号CKIN的频率信息，且透过与非门6080以复位D型正反器DFF1、 DFF2，数字单元6082可根据比值信号Ratio判断输出信号CKOUT的频率与参考信号CKIN的频率之间的比值以产生比较信号Comp，而频率侦测器608产生的比较信号Comp透过低通滤波器510滤除噪声后传递至三角积分调变器，藉由调整除数控制信号以及相位控制信号以调整可调式除频器302的除频操作以及相位内插器304的相位内插操作。
在一实施例中，频率产生器可另包括一锁相回路，其中锁相回路耦接于相位内插器，用来滤除三角积分调变器所产生的量化噪声(Quantization Noise)。
请参考图7，其为本申请实施例另一频率产生器70的示意图。频率产生器70由频率产生器50所衍生，因此相同组件以相同符号表示。频率产生器70包括振荡器300、可调式除频器302、相位内插器304、三角积分调变器306、频率侦测器508、低通滤波器510以及锁相回路712。在图7所示的实施例中，锁相回路712耦接于相位内插器304，用来滤除三角积分调变器306所产生的高频量化噪声，并进一步降低输出信号CKOUT的噪声。另外，由于本发明的频率产生器70透过振荡器300产生输出频率的信号路径，其已大幅降低参考信号路径中的带宽内噪声以及三角积分调变器306产生的高频量化噪声，若欲更进一步降低三角积分调变器306的高频量化噪声，本发明可透过锁相回路712针对量化噪声进行滤波，以符合系统需求。值得注意的是，由于此高频量化噪声已透过频率产生器70系统架构降低，因此，锁相回路712仅需针对三角积分调变器306产生的高频量化噪声进行优化，不须设计为低带宽的锁相回路，如此一来，可大幅地降低锁相回路712的设计复杂度、电路面积以及功率消耗。
习知技术中，当输入信号与输出信号为分数型的倍数关系的情况下，为取得良好的输出信号质量往往需透过增加制造成本以及功率消耗以达成，相较之下，本申请的频率产生器透过振荡器产生干净的高频信号，可调式除频器先将操作频率降低，再藉由相位内插器调整所需要的输出相位以达到所需要的输出频率，如此一来，本申请的频率产生器可达到低功率低噪声的分数型频率产生器。

Claims (10)

  1. 一种频率产生器，所述频率产生器包括：
    三角积分调变器，用来产生除数控制信号以及相位控制信号；
    振荡器，用来产生振荡信号，其中所述振荡信号具有第一频率；
    可调式除频器，用来根据所述除数控制信号对所述振荡信号进行除频操作，以产生第一除频信号以及第二除频信号，其中所述第一除频信号以及所述第二除频信号具有第二频率；以及
    相位内插器，用来根据所述相位控制信号对所述第一除频信号以及所述第二除频信号进行相位内插操作，以产生输出信号，所述输出信号具有输出频率；
    其中，所述第一频率大于所述第二频率。
  2. 如权利要求1所述的频率产生器，其中所述第一频率为所述第二频率的整数倍。
  3. 如权利要求1所述的频率产生器，其中所述第二除频信号比所述第一除频信号延迟一个时间周期，所述时间周期为所述振荡信号的周期。
  4. 如权利要求3所述的频率产生器，其中所述输出信号比所述第一除频信号延迟，且所述第二除频信号比所述输出信号延迟。
  5. 如权利要求1所述的频率产生器，其中所述相位内插器包括：
    第一内插模块，包括复数个缓冲器耦接于所述第一除频信号及内插节点之间；
    第二内插模块，包括复数个缓冲器耦接于所述第二除频信号及所述内插节点之间；以及
    输出缓冲器，耦接于所述内插节点，用来产生所述输出信号。
  6. 如权利要求1所述的频率产生器，所述三角积分调变器另接收一比值信号以产生所述除数控制信号以及所述相位控制信号。
  7. 如权利要求1所述的频率产生器，另包括：
    频率侦测器，耦接于所述相位内插器，用来接收比值信号和参考信号，比较参考信号以及所述输出信号以产生比较信号，其中所述参考信号具有参考频率；以及
    低通滤波器，耦接于所述频率侦测器以及所述三角积分调变器之间，用来滤除所述比较信号的高频噪声。
  8. 如权利要求7所述的频率产生器，其中所述三角积分调变器接收滤除高频噪声后的所述比较信号，以产生所述除数控制信号以及所述相位控制信号，指示所述可调式除频器进行除频操作以及指示所述相位内插器进行相位内插操作，使所述输出频率与所述参考频率的比值为分数。
  9. 如权利要求7所述的频率产生器，其中所述频率侦测器包括：
    第一D型正反器，包括D数据输入端，耦接于系统供应电源，频率输入端耦接于所述输出信号，数据输出端用来产生第一比较信号，以及复位端；
    第二D型正反器，包括D数据输入端，耦接于地，频率输入端耦接于所述参考信号，数据输出端用来产生第二比较信号，以及复位端；
    数字电路，用来接收比值信号，所述第一比较信号以及所述第二比较信号，以比较所述输出频率以及所述参考频率，且产生所述比较信号；以及
    与非门，包括第一数据输入端接收所述第一比较信号，第二数据输入端接收所述第二比较信号，以及数据输出端耦接于所述第一D型正反器的所述复位端、以及所述第二D型正反器的所述复位端。
  10. 如权利要求7所述的频率产生器，还包括：
    锁相回路，耦接于所述相位内插器，用来滤除所述三角积分调变器产生的高频噪声。
PCT/CN2018/079632 2018-03-20 2018-03-20 频率产生器 WO2019178748A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2018/079632 WO2019178748A1 (zh) 2018-03-20 2018-03-20 频率产生器
CN201880000473.8A CN110506394B (zh) 2018-03-20 2018-03-20 频率产生器
EP18782865.2A EP3567727A4 (en) 2018-03-20 2018-03-20 FREQUENCY GENERATOR
US16/158,312 US11086353B2 (en) 2018-03-20 2018-10-12 Fractional clock generator with low power and low noise

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/079632 WO2019178748A1 (zh) 2018-03-20 2018-03-20 频率产生器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/158,312 Continuation US11086353B2 (en) 2018-03-20 2018-10-12 Fractional clock generator with low power and low noise

Publications (1)

Publication Number Publication Date
WO2019178748A1 true WO2019178748A1 (zh) 2019-09-26

Family

ID=67985190

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/079632 WO2019178748A1 (zh) 2018-03-20 2018-03-20 频率产生器

Country Status (4)

Country Link
US (1) US11086353B2 (zh)
EP (1) EP3567727A4 (zh)
CN (1) CN110506394B (zh)
WO (1) WO2019178748A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112350694B (zh) * 2020-10-30 2022-09-06 上海兆芯集成电路有限公司 相位插值器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417510B2 (en) * 2006-09-28 2008-08-26 Silicon Laboratories Inc. Direct digital interpolative synthesis
CN103023495A (zh) * 2011-09-23 2013-04-03 硅谷实验室公司 将内插分频器用作数控振荡器的pll
CN103117746A (zh) * 2011-10-20 2013-05-22 联发科技（新加坡）私人有限公司 分数倍锁相环及其操作方法
CN103124175A (zh) * 2011-08-22 2013-05-29 英飞凌科技股份有限公司 小数分频器
CN103780252A (zh) * 2012-10-22 2014-05-07 联发科技股份有限公司 时钟产生装置、用于时钟产生装置的方法以及分数型分频器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426662B1 (en) * 2001-11-12 2002-07-30 Pericom Semiconductor Corp. Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays
US20110031906A1 (en) * 2008-04-15 2011-02-10 Panasonic Corporation Motor driving device, integrated circuit device, motor device, and motor driving system
JP5106330B2 (ja) * 2008-09-16 2012-12-26 パナソニック株式会社 ディジタル制御発振回路、周波数シンセサイザ及び無線通信機器
US7733151B1 (en) * 2008-12-08 2010-06-08 Texas Instruments Incorporated Operating clock generation system and method for audio applications
TWI502308B (zh) * 2009-07-09 2015-10-01 Univ Nat Taiwan 全數位展頻時脈產生器
JP2012010308A (ja) * 2010-05-24 2012-01-12 Panasonic Corp リファレンスリークの発生や位相ノイズを低減できるｐｌｌ回路
US8248175B2 (en) * 2010-12-30 2012-08-21 Silicon Laboratories Inc. Oscillator with external voltage control and interpolative divider in the output path
US8692599B2 (en) * 2012-08-22 2014-04-08 Silicon Laboratories Inc. Interpolative divider linearity enhancement techniques
US8791734B1 (en) * 2013-02-13 2014-07-29 Silicon Laboratories Inc. Cascaded PLL for reducing low-frequency drift in holdover mode
US9244484B2 (en) * 2013-12-11 2016-01-26 International Business Machines Corporation Fractional-N spread spectrum state machine
CN106775143B (zh) * 2015-12-31 2020-01-03 深圳市汇顶科技股份有限公司 积分电路及电容感测电路
US10678294B2 (en) * 2016-10-14 2020-06-09 Sound Devices, LLC Clock for recording devices
US10534025B2 (en) * 2017-06-12 2020-01-14 Qualcomm Incorporated Phase frequency detector linearization using switching supply
WO2019006588A1 (zh) * 2017-07-03 2019-01-10 深圳市汇顶科技股份有限公司 音频系统及耳机

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417510B2 (en) * 2006-09-28 2008-08-26 Silicon Laboratories Inc. Direct digital interpolative synthesis
CN103124175A (zh) * 2011-08-22 2013-05-29 英飞凌科技股份有限公司 小数分频器
CN103023495A (zh) * 2011-09-23 2013-04-03 硅谷实验室公司 将内插分频器用作数控振荡器的pll
CN103117746A (zh) * 2011-10-20 2013-05-22 联发科技（新加坡）私人有限公司 分数倍锁相环及其操作方法
CN103780252A (zh) * 2012-10-22 2014-05-07 联发科技股份有限公司 时钟产生装置、用于时钟产生装置的方法以及分数型分频器

Also Published As

Publication number Publication date
EP3567727A1 (en) 2019-11-13
EP3567727A4 (en) 2019-11-13
US11086353B2 (en) 2021-08-10
US20190294201A1 (en) 2019-09-26
CN110506394A (zh) 2019-11-26
CN110506394B (zh) 2023-05-05

Similar Documents

Publication Publication Date Title
CN103001631B (zh) 小数n锁相环路
US8368435B2 (en) Method and apparatus for jitter reduction
EP1148648B1 (en) Frequency synthesizer
US20020136341A1 (en) Fractional-N frequency synthesizer with fractional compensation method
US7636018B2 (en) Phase locked loop with phase shifted input
US7973606B2 (en) Fractional-N frequency synthesizer and method thereof
US6642800B2 (en) Spurious-free fractional-N frequency synthesizer with multi-phase network circuit
WO2019183866A1 (zh) 频率产生器以及频率产生方法
US7145367B2 (en) Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector
US8565368B1 (en) Wide range multi-modulus divider in fractional-N frequency synthesizer
EP2571165B1 (en) Accumulator type fractional-n pll synthesizer and control method thereof
WO2019178748A1 (zh) 频率产生器
WO2012093424A1 (ja) デルタシグマ変調型分数分周ｐｌｌ周波数シンセサイザおよびそれを備えた無線通信装置
US9742414B2 (en) Reducing errors due to non-linearities caused by a phase frequency detector of a phase locked loop
US8669795B2 (en) Noise filtering fractional-N frequency synthesizer and operating method thereof
US8502574B2 (en) Device and method for generating a signal of parametrizable frequency
US11909409B1 (en) Low jitter PLL
JP2005033581A (ja) フラクショナル−ｎ方式の位相同期ループ形周波数シンセサイザ
WO2007104176A1 (fr) Procédé de construction et de commande d'une boucle à phase asservie fractionnelle n comprenant un diviseur de fréquence fractionnelle
Thirunarayanan et al. An injection-locking based programmable fractional frequency divider with 0.2 division step for quantization noise reduction
US9948308B2 (en) Multi-modulus prescaler with improved noise performance
JP2006186576A (ja) 位相同期ループ形周波数シンセサイザ
CN118074711A (zh) 一种车载SerDes芯片、包括其的汽车配件及汽车
Wang New strategies for low noise, agile PLL frequency synthesis
JPH10224218A (ja) 信号発生器

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2018782865

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2018782865

Country of ref document: EP

Effective date: 20181018

ENP Entry into the national phase

Ref document number: 2018782865

Country of ref document: EP

Effective date: 20181018

NENP Non-entry into the national phase

Ref country code: DE