WO2019177287A1 - Dispositif de mémoire de cellule dram - Google Patents

Dispositif de mémoire de cellule dram Download PDF

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Publication number
WO2019177287A1
WO2019177287A1 PCT/KR2019/002379 KR2019002379W WO2019177287A1 WO 2019177287 A1 WO2019177287 A1 WO 2019177287A1 KR 2019002379 W KR2019002379 W KR 2019002379W WO 2019177287 A1 WO2019177287 A1 WO 2019177287A1
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Prior art keywords
region
body region
drain region
gate
concentration
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PCT/KR2019/002379
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English (en)
Korean (ko)
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강인만
윤영준
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경북대학교 산학협력단
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Publication of WO2019177287A1 publication Critical patent/WO2019177287A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • a silicon on insulator (SOI) substrate is used as a data storage for storing holes in a P-type body by using a body floating effect.
  • the capacitorless 1T DRAM using the body floating effect not only has poor data retention capability but also has a high manufacturing cost due to the use of expensive SOI substrates.
  • An object of the present disclosure is to solve an integration problem through a nanowire structure, improve memory retention time by providing a distance between a gate region and a source / drain region, and implement a program operation using a tunneling phenomenon between a body region and a drain region. It is to provide a memory device that performs the.
  • a hole is stored, the source region is formed on one side of the body region, the impurity of the first type is doped to a concentration higher than the predetermined concentration, and the drain region is formed on the other side of the body region;
  • the dopant of the first type is doped to a concentration higher than the predetermined concentration.
  • the entire body region may be depleted to secure a data storage, and thus it may be manufactured on a bulk silicon substrate.
  • existing semiconductor process equipment and manufacturing methods can be used as it is, resulting in excellent process compatibility, and thus can be used for embedded systems.
  • 2A and 2B are views and graphs for explaining the operation of writing '1' of a memory device
  • 4A and 4B are views and graphs for explaining a hold operation of a memory device
  • 5A to 5C are diagrams and graphs for explaining a read operation of a memory device.
  • ordinal numbers such as “first”, “second”, and the like may be used to distinguish between components. These ordinal numbers are used to distinguish the same or similar components from each other, and the meaning of the terms should not be construed as limited by the use of these ordinal numbers. For example, the components combined with these ordinal numbers should not be limited in order of use or arrangement by the number. If necessary, the ordinal numbers may be used interchangeably.
  • modules such as “module”, “unit”, “part”, and the like are terms for referring to a component that performs at least one function or operation, and such components are referred to as hardware or software. It may be implemented or a combination of hardware and software.
  • a plurality of "modules”, “units”, “parts”, etc. are integrated into at least one module or chip, except that each needs to be implemented with a particular specific hardware, and is at least one processor. It can be implemented as.
  • a part when a part is connected to another part, this includes not only a direct connection but also an indirect connection through another medium.
  • the meaning that a part includes a certain component means that it may further include other components, without excluding other components, unless specifically stated otherwise.
  • 1A and 1B are examples of a three-dimensional structure and a cross-sectional view of a memory device according to the present disclosure.
  • a memory device 100 includes a nanowire-shaped columnar semiconductor including a source region 10, a body region 20, and a drain region 30.
  • the gate insulating layer 40 may include a gate insulating layer 40 formed to surround the surface of the columnar semiconductor, and a gate 50 formed on the surface of the gate insulating layer so that at least a portion of the region is positioned in a region corresponding to the body region.
  • a gate insulating layer 40 surrounds a cylindrical semiconductor including a drain region 30, and a portion of the gate insulating layer 40 is again gated 50. You can see that surround).
  • the gate 50 is formed so as to surround at least a portion of the gate insulating layer 40 surrounding the body region 20 from the outside.
  • the body region 20 may be doped with a predetermined concentration of impurities of the first type to store holes by tunneling with the drain region 30.
  • the body region 20 may be used as a hole storage, and a memory value '1' or '0' of the memory device 100 may be determined according to the amount of holes stored in the body region 20.
  • the gate 50 is formed to cover only a portion of the gate insulating layer 40 that surrounds the body region 20, and surrounds the source region 10 and the drain region 30. It can be seen that can be formed so as not to wrap.
  • the gate 50 may be formed so as not to cover the portion close to the portion surrounding the source region 10 and the drain region 30, even if the portion of the gate insulating layer 40 surrounds the body region 20. have.
  • the first type of impurities doped with the source region 10, the body region 20, and the drain region 30 may be N-type impurities.
  • the doping concentration of the body region 20 may be lower than that of the source region 10 and the drain region 30.
  • the writing (1) operation generates holes in which data can be distinguished and stores the holes in the body region 20, specifically, in the region of the body region 20 adjacent to the gate insulating layer 40. Means.
  • 2A and 2B are diagrams and graphs for describing an operation of writing '1' of the memory device 100.
  • 2A and 2B assume a case in which a predetermined negative voltage is applied to the gate 50 and a predetermined positive voltage is applied to the drain region 30.
  • the energy level is substantially the same or rather reversed, so that the tunneling phenomenon occurs largely, and the electrons of the body region 20 move to the drain region 30. Done.
  • the amount of holes stored in the body region 20 increases as the electrons move, so that a program (writing '1') operation may be performed.
  • an impact generation phenomenon may occur as a result of applying a higher voltage to the drain region 30 than the gate 50.
  • a high electric field value is formed in the vicinity of the drain region 30, and electrons that have flowed from the source region 10 to the drain region 30 are accelerated to collide with the lattice.
  • the electron-hole pair is generated in the body region 20 due to the collision, and the generated electrons are discharged to the drain region 30 by the high voltage of the drain region 30, so that the generated holes are generated in the body region 20.
  • the resultant program (writing '1') operation may be performed.
  • the amount of holes stored in the body region 20 may be reduced by drift. As a result, the writing '0' operation on the memory device 100 may be performed.
  • the writing '0' operation refers to an operation of reducing the amount of holes stored in the body region 20.
  • 3A and 3B are diagrams and graphs for describing an operation of writing '0' of the memory device 100.
  • 3A and 3B assume a case in which a predetermined positive voltage is applied to the gate 50 and a predetermined negative voltage is applied to the drain region 30.
  • FIG. 3A it can be seen that holes stored in the body region 20 exit to the drain region 30 through drift and diffusion. The reason is explained through FIG. 3B.
  • FIG. 3B is a graph showing an approximate energy level for each position sequentially leading to the source region 10, the body region 20, and the drain region 30.
  • the energy level of the body region 20 is lowered and the energy level of the drain region 30 is increased, so that an energy barrier between the body region 20 and the drain region 30 is lowered to the body region 20. It can be seen that the stored holes move to the drain region 30.
  • the hold operation is an operation in which the amount of holes stored in the body region 20 is maintained.
  • 4A and 4B are diagrams and graphs for describing a hold operation of a memory device. 4A and 4B assume that gate 50 and drain region 30 are grounded or floating (0 V voltage).
  • FIG. 4A it can be seen that holes stored in the body region 20 are maintained without moving to the drain region 30 or the source region 10. The reason is explained through FIG. 4B.
  • FIG. 4B is a graph showing an approximate energy level for each position sequentially leading to the source region 10, the body region 20, and the drain region 30.
  • the body region 20 is depleted in a state where the voltage of the gate 50 is 0 V, and thus the energy level of the body region 20 is determined by the drain region 30 and the source region 10. It is higher than the energy level.
  • a high energy barrier between the body region 20 and the drain region 30 and a high energy barrier between the body region 20 and the source region 10 exist, such that holes stored in the body region 20 are drained. 30 or move to the source region 10.
  • a hold operation may be performed by maintaining the amount of holes stored in the body region 20.
  • the read operation forms a channel through which current (holes) can flow in the body region 20 to allow holes stored in the body region 20 to move, and the movement is performed by the drain region 30 and the source region ( 10) by sensing as the inter-current, it refers to the operation of checking how much the amount of holes previously stored in the body region 20.
  • the current value between the drain region 30 and the source region 10 varies according to the amount of holes stored in the body region 20, and the memory device 100 according to the difference. It can be distinguished whether the memory state of '1' or '0'.
  • 5A through 5C are diagrams and graphs for describing a read operation of a memory device.
  • 5A through 5C assume a case in which a predetermined amount of voltage in which a channel is formed between the drain region 30 and the source region 10 is applied to the gate 50.
  • FIG. 5A assumes that the hole storage state of the body region 20, that is, the memory state is '1' before the predetermined amount of voltage is applied to the gate 50. That is, it corresponds to read '1' operation.
  • FIG. 5C is a graph showing an approximate energy level for each position sequentially leading to the source region 10, the body region 20, and the drain region 30.
  • the read '0' operation (FIG. 5B) is larger than that of the read '0' operation. It can be seen that the energy level of the body region 20 is lowered.
  • the energy barrier between the body region 20 and the drain region 30 and the energy barrier between the body region 20 and the source region 10 are lower in the case of read '1' operation than in the case of read '0' operation.
  • the current value flowing between the drain region 30 and the source region 10 becomes larger in the read '1' operation than in the read '0' operation.
  • FIG. 6 shows the values of the drain region 30 and the source region 10 current I ds according to the gate 50 and source region 10 voltages V gs , and the memory states state '1' and state '0. This is the result of each measurement.
  • the voltage V ds between the drain region 30 and the source region 10 is 0.1V .
  • the difference between I ds when the memory state is '1' and '0' is defined as a sensing current margin value.
  • the sensing current margin value is influenced by the electron mobility and the dielectric constant of the material constituting the body region 20. Therefore, by configuring the body region 20 using SiGe having a higher electron mobility and dielectric constant than Si, it is possible to secure a higher sensing current margin.
  • the constituent material of the body region 20 may be applied to a Ge, Group 3/5 compound in consideration of a semiconductor process.
  • the heterojunction structure between the source region 10 and the drain region 30 composed of Si and the body region 20 composed of SiGe is a staggered bandgap heterojunction, a high potential barrier to holes is formed to improve hole retention. Can be.
  • FIG. 7 illustrates a sensing current margin value between a read '1' operation and a read '0' operation in performing the above-described operations in the memory device 100.
  • the hold time means the minimum time required for the state change to be accurately recognized. That is, in performing a read '1' or a read '0' operation, it may mean a minimum time at which a specific current value corresponding to '1' or '0' should be measured.
  • a read result I ds value should be measured as a current value corresponding to '1'.
  • the I ds value that is maintained for at least 10 ns may be referred to as a current value corresponding to the memory state '1'. That is, the sensing current margin ( ⁇ I ds ) can be measured as a result of comparing the I ds value of the read '1' operation by 10 ns (Transient Time: 40 ns) with the I ds value of the read '0' operation. have.
  • the sensing current margin value is about 0.4 ⁇ A / ⁇ m, and the memory state can be clearly determined through this.
  • 8 is a graph illustrating I ds values of the memory device 100 for each read operation read '1' or read '0' according to a hold time. 8 illustrates the case where the absolute temperature is 300K and the case where it is 358K.
  • the sensing current margin is maintained to some extent even when the hold time is 100 ms or more at room temperature (300K). In addition, even if the absolute temperature increases to 358K (85 ° C), it can be confirmed that the holding current margin is valid until the hold time 64 ms.
  • Table 1 below may be applied to the gate 50, the drain region 30 and the source region 10 to perform each operation (program, erase, read, hold) in consideration of the characteristics of the memory device 100.
  • An example of a voltage value is shown.
  • the above-described embodiments are related to cases in which the first type of impurities are N-type impurities.
  • the first type of impurities may be P-type impurities. That is, the body region 20 may be doped to a predetermined concentration by the P-type impurity, and the drain region 30 and the source region 10 may be doped to a concentration higher than the predetermined concentration by the P-type impurity.
  • the source region 10 and the drain region 30 may be doped with a P + concentration, and the body region 20 may be doped with a P ⁇ concentration.
  • the memory state '1' or '0' may be determined according to the amount of electrons stored in the body region 20.
  • the memory device 100 is not limited to the above-described embodiments, and the present invention may be made without departing from the spirit of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un dispositif de mémoire. Le dispositif de mémoire comprend : un semi-conducteur en colonne comprenant une région de source, une région de corps et une région de drain; une couche d'isolation de grille formée de façon à entourer la surface du semi-conducteur en colonne; et une grille formée sur une surface de la couche d'isolation de grille de telle sorte qu'au moins une partie de la région est située dans une région correspondant à la région de corps, la région de corps étant dopée avec un premier type de dopant à une concentration prédéterminée pour stocker des trous par effet tunnel avec la région de drain, la région de source étant formée sur un côté de la région de corps de telle sorte que le premier type de dopant est dopé à une concentration supérieure à la concentration prédéterminée, et la région de drain étant formée sur l'autre côté de la région de corps de telle sorte que le premier type de dopant est dopé à une concentration supérieure à la concentration prédéterminée.
PCT/KR2019/002379 2018-03-14 2019-02-27 Dispositif de mémoire de cellule dram WO2019177287A1 (fr)

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KR1020180029940A KR102029196B1 (ko) 2018-03-14 2018-03-14 디램 셀 메모리 소자
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060114991A (ko) * 2005-05-03 2006-11-08 삼성전자주식회사 수직 채널 트랜지스터 구조를 갖는 단일 트랜지스터 플로팅바디 디램 소자들 및 그 제조방법들
KR20100094732A (ko) * 2009-02-19 2010-08-27 서울대학교산학협력단 고성능 단일 트랜지스터 플로팅 바디 ｄｒａｍ 소자 및 그 제조 방법
KR101085155B1 (ko) * 2010-11-16 2011-11-18 서강대학교산학협력단 터널링 전계효과 트랜지스터를 이용한 1ｔ 디램 셀 소자
KR101091010B1 (ko) * 2010-12-17 2011-12-08 서울대학교산학협력단 2비트 저장 가능한 단일 트랜지스터 구조를 갖는 디램 소자

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Publication number Priority date Publication date Assignee Title
KR20060114991A (ko) * 2005-05-03 2006-11-08 삼성전자주식회사 수직 채널 트랜지스터 구조를 갖는 단일 트랜지스터 플로팅바디 디램 소자들 및 그 제조방법들
KR20100094732A (ko) * 2009-02-19 2010-08-27 서울대학교산학협력단 고성능 단일 트랜지스터 플로팅 바디 ｄｒａｍ 소자 및 그 제조 방법
KR101085155B1 (ko) * 2010-11-16 2011-11-18 서강대학교산학협력단 터널링 전계효과 트랜지스터를 이용한 1ｔ 디램 셀 소자
KR101091010B1 (ko) * 2010-12-17 2011-12-08 서울대학교산학협력단 2비트 저장 가능한 단일 트랜지스터 구조를 갖는 디램 소자

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANSARI, HASAN RAZA ET AL.: "Doping Dependent Assessment of Accumulation Mode and Junctioniess FET for IT DRAM", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 65, no. 3, 23 January 2018 (2018-01-23), pages 1205 - 1210, XP055641186 *

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KR20190108433A (ko) 2019-09-24

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