WO2019169877A1 - 一种双bios的控制方法及相关装置 - Google Patents

一种双bios的控制方法及相关装置 Download PDF

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Publication number
WO2019169877A1
WO2019169877A1 PCT/CN2018/112054 CN2018112054W WO2019169877A1 WO 2019169877 A1 WO2019169877 A1 WO 2019169877A1 CN 2018112054 W CN2018112054 W CN 2018112054W WO 2019169877 A1 WO2019169877 A1 WO 2019169877A1
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bios
chip
startup
main
cpld
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PCT/CN2018/112054
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English (en)
French (fr)
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邱星萍
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郑州云海信息技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1612—Error detection by comparing the output signals of redundant hardware where the redundant component is persistent storage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44536—Selecting among different versions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • the present application relates to the field of computer technology, and in particular, to a dual BIOS control method, a control device, and a control system.
  • BIOS Basic Input/Output System
  • BIOS program for saving basic input and output of a computer system (or computer), system setting information, self-test after power-on, and system self-starting program.
  • BIOS is responsible for initializing the hardware, detecting hardware functions, and booting the operating system.
  • BIOS is the bridge between computer software and hardware. The computer realizes the coordination between software and hardware through BIOS. If the BIOS is damaged due to an upgrade or virus intrusion, the computer will not work properly or even start.
  • the conventional dual BIOS implementation method is to use the original BIOS as the main BIOS chip on the basis of the original system, and to increase the chip selection chip for switching BIOS, a spare BIOS chip, and the main and backup BIOS switching circuits, through the chip selection chip in two Make a selection in the BIOS chip.
  • the system first checks the status of the main BIOS chip after power-on. If the main BIOS chip is found to be damaged, it will automatically switch to the standby BIOS chip boot system and then repair the main BIOS chip.
  • the southmost chipset and the chip select chip are mainly selected between the primary BIOS and the standby BIOS, and the chip select chip determines the state of the BIOS chip, and then selects a certain BIOS chip as the currently booted BIOS.
  • the selection process only involves the communication between the chip selection chip and the south bridge chipset.
  • the BIOS itself does not output the corresponding signal during the startup selection process. Therefore, in the process of judging, there will be a signal error received by the chip selection chip, and the standby BIOS chip will be used.
  • the main BIOS chip As the main BIOS chip is booted, it will affect the stability of the dual BIOS structure and make the dual BIOS structure lose its meaning in the computer device.
  • each BIOS chip needs to be connected to the chip select chip and the south bridge chipset, and the design structure is complicated.
  • the purpose of the application is to provide a dual BIOS control method, a control device, and a control system, which determine whether the BIOS fails to be booted by the boot state sent by the BIOS, and use the SPI register to record the BIOS startup failure information, so that the processor, the CPLD, and the like
  • the BIOS forms a communication flow that interacts with each other, improves the stability of the BIOS switch, and avoids the situation that the BIOS determines that the error is caused by the port detection.
  • the present application provides a dual BIOS control method, including:
  • the CPLD determines whether the primary BIOS startup fails according to the startup status signal sent by the primary BIOS.
  • the startup state of the BIOS sends a switching instruction to the CPLD;
  • the CPLD determines, according to the startup status signal sent by the primary BIOS, whether the primary BIOS fails to start, including:
  • the primary BIOS sends the startup status signal through the GPIO; wherein the startup status signal is a high voltage when the primary BIOS is successfully booted;
  • the CPLD determines whether the primary BIOS startup fails according to the voltage of the startup state signal.
  • it also includes:
  • the processor When the SPI bus switches to the primary BIOS, the processor performs a maintenance operation or an upgrade operation on the primary BIOS.
  • it also includes:
  • the SPI bus is switched to the primary BIOS.
  • the application also provides a dual BIOS control device, including:
  • a startup state determining module configured to determine, according to a startup status signal sent by the primary BIOS, whether the primary BIOS startup fails
  • An alternate BIOS switching module configured to: when the primary BIOS fails to boot, switch the SPI bus to the standby BIOS, and write the startup state of the primary BIOS to the SPI register, so that the processor acquires the SPI register through the SPI register Determining a startup state of the primary BIOS, and sending a switching instruction to the CPLD according to the startup state of the primary BIOS;
  • a main BIOS switching module configured to switch the SPI bus to the main BIOS according to the received switching instruction.
  • the startup state determining module includes:
  • a signal sending unit configured to send the startup status signal by using a GPIO; wherein the startup status signal is a high voltage when the primary BIOS is successfully booted;
  • the determining unit is configured to determine, according to the voltage of the startup state signal, whether the primary BIOS startup fails.
  • the device further includes:
  • the BIOS maintenance module is configured to perform a maintenance operation or an upgrade operation on the primary BIOS when the SPI bus is switched to the primary BIOS.
  • the device further includes:
  • the power-off switching module is configured to switch the SPI bus to the main BIOS after the power-off restart.
  • the present application further provides a dual BIOS control system, including: a processor, a south bridge chipset, a CPLD, a primary BIOS, and a standby BIOS, the processor being connected to the south bridge chipset, the CPLD and the The south bridge chipset is connected, and the primary BIOS and the standby BIOS are both connected to the CPLD;
  • the CPLD is configured to determine, according to the startup status signal sent by the primary BIOS, whether the primary BIOS startup fails; if yes, switch the SPI bus to the standby BIOS, and write the startup state of the primary BIOS to the SPI register, according to Receiving the switching instruction to switch the SPI bus to the primary BIOS;
  • the processor is configured to acquire an activation state of the primary BIOS through the SPI register, and send a switching instruction to the CPLD according to the startup state of the primary BIOS;
  • the primary BIOS is configured to send a startup status signal to the CPLD.
  • the primary BIOS is configured to send the startup status signal by using a GPIO, where the startup status signal is a high voltage when the primary BIOS is successfully booted;
  • the CPLD is specifically configured to determine, according to the voltage of the startup status signal, whether the primary BIOS startup fails.
  • the dual BIOS control method provided by the present application includes: the CPLD determines whether the primary BIOS startup fails according to the startup status signal sent by the primary BIOS; if yes, switches the SPI bus to the standby BIOS, and Writing a boot status of the primary BIOS to the SPI register, so that the processor acquires the startup state of the primary BIOS through the SPI register, and sends a switching instruction to the CPLD according to the startup state of the primary BIOS;
  • the primary BIOS and the standby BIOS are both connected to the CPLD through the SPI bus; and the SPI bus is switched to the primary BIOS according to the received switching instruction.
  • the startup state of the BIOS is used to determine whether the BIOS fails to start, and the SPI register is used to record the information of the BIOS startup failure, so that the communication flow between the processor, the CPLD, and the BIOS is formed, thereby improving the stability of the BIOS switching and avoiding the stability.
  • the BIOS determines the error due to port detection.
  • the present application further provides a dual BIOS control device and a control system, which have the above-mentioned beneficial effects, and are not described herein.
  • FIG. 1 is a flowchart of a dual BIOS control method according to an embodiment of the present application
  • FIG. 2 is a flowchart of signal determination of a dual BIOS control method according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a dual BIOS control apparatus according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a dual BIOS control system according to an embodiment of the present application.
  • the chip select chip judges the boot state of the BIOS chip through the signals of some ports, but the signal of the port is not a signal used by the BIOS chip to determine the startup state, therefore, the chip select chip judges The BIOS chip startup status will be biased. Moreover, since the BIOS chip itself cannot control itself as the main BIOS chip or the standby BIOS chip, the standby BIOS chip is determined to be the main BIOS chip.
  • the core of the application is to provide a dual BIOS control method, a control device and a control system, and determine whether the BIOS fails to be booted through the boot status actively sent by the BIOS, and use the SPI register to record the BIOS startup failure information, so that the processor, the CPLD, and the like
  • the BIOS forms a communication flow that interacts with each other, improves the stability of the BIOS switch, and avoids the situation that the BIOS determines that the error is caused by the port detection.
  • FIG. 1 is a flowchart of a dual BIOS control method according to an embodiment of the present application.
  • This embodiment provides a dual BIOS control method, which can improve stability when dual BIOS is switched.
  • the method may include:
  • the CPLD determines, according to the startup status signal sent by the primary BIOS chip, whether the startup of the primary BIOS chip fails. If yes, step S102 is performed.
  • This step is for the Complex Programmable Logic Device (CPLD) to determine whether the main BIOS chip fails to start according to the startup status signal sent by the main BIOS chip.
  • CPLD Complex Programmable Logic Device
  • the CPLD mainly determines whether the main BIOS chip fails to be started by the startup status signal sent by the BIOS chip itself.
  • the startup status signal sent by the main BIOS chip is a status signal obtained by the main BIOS chip to determine its own state.
  • the manner of acquiring the status signal is different from that obtained by some BIOS chips in the prior art.
  • the main BIOS chip can output signals according to its own control program or judgment program, so that the main BIOS chip knows its own state and can control.
  • the manner in which the main BIOS chip sends signals and obtains signals may be selected according to actual conditions, and is not specifically limited herein.
  • this step is to achieve the interaction between the CPLD and the BIOS chip, and each part can control its signal state.
  • S102 Switch a Serial Peripheral Interface (SPI) bus to the standby BIOS chip, and write the startup state of the main BIOS chip to the SPI register, so that the processor acquires the startup state of the main BIOS chip through the SPI register. And sending a switching instruction to the CPLD according to the startup state of the main BIOS chip; wherein, the main BIOS chip and the standby BIOS chip are connected to the CPLD through the SPI bus;
  • SPI Serial Peripheral Interface
  • this step is to switch the SPI bus to the standby BIOS chip when the primary BIOS chip fails to boot, and write the corresponding startup state to the SPI register.
  • the main purpose is to make the backup BIOS chip take over the work after the main BIOS chip fails to start, and complete the system startup. And causing the processor to acquire the startup state of the main BIOS chip through the SPI register, and send a switching instruction to the CPLD according to the startup state.
  • the processor starts to acquire the startup state of the BIOS chip after the system is started. If the startup fails, the BIOS chip is switched according to the startup state, and maintenance and the like are performed.
  • the main BIOS chip and the standby BIOS chip are only connected to the CPLD chip through the SPI bus.
  • the difference between the two BIOS chips and the chip select chip in the prior art is also connected with the south bridge chipset. Reduces the number of connections and makes the structure simpler.
  • the purpose of switching the BIOS chip by switching the SPI bus is to complete the switching hardware circuit, and the stability of the connection between the SPI bus and the BIOS chip after switching and after switching can be improved.
  • this step is to switch the SPI bus to the main BIOS chip according to the received switching instruction. After switching to the main BIOS chip, you can directly perform maintenance and upgrade operations on the BIOS chip.
  • the switching of the CPLD by the switching instruction is different from the manner of switching the system process in the prior art, and the stability of the switching between the dual BIOS in the dual BIOS chip structure can be improved.
  • the CPLD of step S102 communicates with the processor through the SPI register, and the mutual communication by the switching instruction in step S103.
  • the dual BIOS structure is switched between the BIOS chips, mutual communication between the three is formed, that is, there is a certain interaction between the three, which can improve the stability of the dual BIOS structure.
  • the embodiment may further include:
  • the processor When the SPI bus switches to the main BIOS chip, the processor performs a maintenance operation or an upgrade operation on the main BIOS chip.
  • the embodiment may further include:
  • the SPI bus is switched to the main BIOS chip.
  • the BIOS chip can be used as the boot BIOS chip after each power-off and restart, and the standby BIOS chip is kept in a silent state to protect its BIOS information.
  • this embodiment mainly determines whether the BIOS chip fails to be booted by the boot state of the BIOS chip, and uses the SPI register to record the information that the BIOS chip fails to start, so that a communication flow between the processor, the CPLD, and the BIOS chip is formed. It improves the stability of the BIOS chip switch and avoids the situation that the BIOS chip determines the error caused by the port detection.
  • FIG. 2 is a flowchart of signal determination of a dual BIOS control method according to an embodiment of the present application.
  • this embodiment is mainly directed to a specific description of how to perform signal judgment in the previous embodiment.
  • the other parts are substantially the same as the previous embodiment, and the same part can refer to the previous embodiment.
  • the main BIOS chip sends a startup status signal through the GPIO; wherein, when the main BIOS chip is successfully booted, the startup status signal is a high voltage;
  • the CPLD determines, according to the voltage of the startup state signal, whether the startup of the main BIOS chip fails.
  • the main BIOS chip transmits the startup status signal through GPIO (General Purpose Input Output).
  • the startup status signal is mainly represented by the voltage level.
  • the startup status signal changes to a high voltage state. That is, if the startup status signal is still low voltage within a specified period of time or at a specified time point, it can be determined that the main BIOS chip fails to boot. According to this, the CPLD can be made to determine whether the startup of the main BIOS chip fails according to the voltage of the startup state signal.
  • the voltage of the GPIO x port can be used for the voltage rise and fall operation.
  • the high and low voltages mentioned in this embodiment are high and low voltages as stipulated in the technical field, and are a conventional definition that can be clearly known by a skilled person.
  • the startup state signal sent by the BIOS chip in this embodiment can determine the startup state of the BIOS chip, and execute the subsequent operation flow according to the startup state.
  • the embodiment of the present application provides a dual BIOS control method, which can determine whether the BIOS chip fails to be booted by the startup state of the BIOS chip, and records the BIOS startup failure information by using the SPI register, so that the processor, the CPLD, and the BIOS chip are Forming mutually interactive communication processes improves the stability of BIOS chip switching and avoids the situation in which the BIOS chip determines errors due to port detection.
  • a dual BIOS control device provided by the embodiment of the present application is described below.
  • a dual BIOS control device described below and a dual BIOS control method described above may be mutually referenced.
  • FIG. 3 is a schematic structural diagram of a dual BIOS control apparatus according to an embodiment of the present application.
  • the embodiment provides a dual BIOS control device, which may include:
  • the startup state determining module 100 is configured to determine, according to the startup status signal sent by the primary BIOS chip, whether the startup of the primary BIOS chip fails;
  • the standby BIOS switching module 200 is configured to: when the primary BIOS chip fails to boot, switch the SPI bus to the standby BIOS chip, and write the startup state of the primary BIOS chip to the SPI register, so that the processor obtains the primary use through the SPI register.
  • the startup state of the BIOS chip and sending a switching instruction to the CPLD according to the startup state of the main BIOS chip; wherein, the main BIOS chip and the standby BIOS chip are connected to the CPLD through the SPI bus;
  • the main BIOS switching module 300 is configured to switch the SPI bus to the main BIOS chip according to the received switching instruction.
  • the startup state determining module 100 may include:
  • a signal sending unit configured to send a startup status signal by using the GPIO; wherein, when the primary BIOS chip is successfully booted, the startup status signal is a high voltage;
  • the determining unit is configured to determine, according to the voltage of the startup state signal, whether the startup of the main BIOS chip fails.
  • the device may further include:
  • the BIOS maintenance module is configured to perform a maintenance operation or an upgrade operation on the main BIOS chip when the SPI bus is switched to the main BIOS chip.
  • the device may further include:
  • the power-off switching module is used to switch the SPI bus to the main BIOS chip after the power-off is restarted.
  • FIG. 4 is a schematic structural diagram of a dual BIOS control system according to an embodiment of the present application.
  • the embodiment of the present application further provides a dual BIOS control system, which may include: a processor, a south bridge chipset, a CPLD, a main BIOS chip and a backup BIOS chip, a processor and a south bridge chipset, a CPLD and a south bridge chip.
  • the group connection, the main BIOS chip and the backup BIOS chip are all connected with the CPLD;
  • the CPLD is configured to determine whether the startup of the primary BIOS chip fails according to the startup status signal sent by the primary BIOS chip; if yes, switch the SPI bus to the standby BIOS chip, and write the startup state of the primary BIOS chip to the SPI register. Switching the SPI bus to the main BIOS chip according to the received switching instruction;
  • the processor is configured to obtain a startup state of the main BIOS chip through the SPI register, and send a switching instruction to the CPLD according to the startup state of the main BIOS chip;
  • the main BIOS chip is used to send a startup status signal to the CPLD.
  • the main BIOS chip and the standby BIOS chip are not connected, but are connected through the CPLD, and are connected through the SPI bus, and the structure is simpler, easy to implement, and convenient for maintenance.
  • the main BIOS chip is specifically configured to send a startup status signal by using the GPIO; wherein, when the main BIOS chip is successfully booted, the startup status signal is a high voltage;
  • the CPLD is specifically configured to determine whether the startup of the primary BIOS chip fails according to the voltage of the startup state signal.
  • the steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented directly in hardware, a software module executed by a processor, or a combination of both.
  • the software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

Abstract

一种双BIOS的控制方法、装置以及控制系统，包括：CPLD根据主用BIOS发送的启动状态信号判断主用BIOS启动是否失败（S101）；若是，则切换SPI总线至备用BIOS，并将所述主用BIOS的启动状态写入SPI寄存器，以使处理器通过SPI寄存器获取主用BIOS的启动状态（S102）。通过BIOS主动发送的启动状态判断BIOS是否启动失败，并使用SPI寄存器记录BIOS启动失败的信息，使处理器、CPLD以及BIOS之间形成相互交互的通信流程，提高了BIOS切换的稳定性，避免了因端口检测导致BIOS判断错误的情况。

Description

一种双BIOS的控制方法及相关装置
本申请要求于2018年03月07日提交中国专利局、申请号为201810185591.2、发明名称为“一种双BIOS的控制方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及一种双BIOS的控制方法、控制装置以及控制系统。
背景技术
随着计算机技术的出现，在计算机内出现了基本输入输出系统(Basic Input/Output System，BIOS)的设计。BIOS，用于保存计算机系统(或称为计算机)的基本输入输出的程序、系统设置信息、开机后自检程序和系统自启动程序。在计算机启动的过程中，BIOS担负着初始化硬件，检测硬件功能，以及引导操作系统的责任。BIOS是计算机软件与硬件之间的桥梁，计算机通过BIOS实现软件和硬件之间的协调工作。如果BIOS由于升级或者病毒入侵损坏，计算机将不能正常工作，甚至不能启动。
为了解决上述问题，很多主板采用双BIOS的机制，以确保系统正常启动。目前常规的双BIOS实现方法是在原有系统的基础上将原有BIOS作为主用BIOS芯片，增加切换BIOS的片选芯片、一片备用BIOS芯片以及主备BIOS切换电路，通过片选芯片在两个BIOS芯片中进行选择。在实际使用过程中，系统上电以后首先检测主用BIOS芯片的状态，如果发现主用BIOS芯片损坏， 就会自动切换到备用BIOS芯片启动系统，然后修复主用BIOS芯片。
但是现有技术中，主要是通过南桥芯片组和片选芯片在主用BIOS和备用BIOS之间进行选择，片选芯片判断BIOS芯片的状态，再选择某个BIOS芯片作为目前启动的BIOS。该选择过程只涉及到片选芯片与南桥芯片组的通信，BIOS本身在启动选择的过程中不输出相应的信号，因此在判断过程中会出现片选芯片接收的信号出错，将备用BIOS芯片当作主用BIOS芯片启动的情况，会影响双BIOS结构的稳定性，使双BIOS结构失去在计算机设备中的意义。此外，现有技术在结构上，还需要将每个BIOS芯片均和片选芯片、南桥芯片组相连，设计结构复杂。
发明内容
本申请的目的是提供一种双BIOS的控制方法、控制装置以及控制系统，通过BIOS主动发送的启动状态判断BIOS是否启动失败，并使用SPI寄存器记录BIOS启动失败的信息，使处理器、CPLD以及BIOS之间形成相互交互的通信流程，提高了BIOS切换的稳定性，避免了因端口检测导致BIOS判断错误的情况。
为解决上述技术问题，本申请提供一种双BIOS的控制方法，包括：
CPLD根据主用BIOS发送的启动状态信号判断主用BIOS启动是否失败；
若是，则切换SPI总线至备用BIOS，并将所述主用BIOS的启动状态写入SPI寄存器，以使处理器通过所述SPI寄存器获取所述主用BIOS的启动状态，并根据所述主用BIOS的启动状态向所述CPLD发送切换指令；
根据接收到的所述切换指令将所述SPI总线切换至所述主用BIOS。
可选的，CPLD根据主用BIOS发送的启动状态信号判断主用BIOS启动是否失败，包括：
所述主用BIOS通过GPIO发送所述启动状态信号；其中，当所述主用BIOS启动成功时所述启动状态信号为高电压；
所述CPLD根据所述启动状态信号的电压判断所述主用BIOS启动是否失败。
可选的，还包括：
当所述SPI总线切换至所述主用BIOS时，所述处理器对所述主用BIOS执行维护操作或升级操作。
可选的，还包括：
当所述CPLD断电重启后，将所述SPI总线切换至主用BIOS。
本申请还提供一种双BIOS的控制装置，包括：
启动状态判断模块，用于根据主用BIOS发送的启动状态信号判断主用BIOS启动是否失败；
备用BIOS切换模块，用于当所述主用BIOS启动失败时，切换SPI总线至备用BIOS，并将所述主用BIOS的启动状态写入SPI寄存器，以使处理器通过所述SPI寄存器获取所述主用BIOS的启动状态，并根据所述主用BIOS的启动状态向所述CPLD发送切换指令；
主用BIOS切换模块，用于根据接收到的所述切换指令将所述SPI总线切换至所述主用BIOS。
可选的，所述启动状态判断模块包括：
信号发送单元，用于通过GPIO发送所述启动状态信号；其中，当所述主 用BIOS启动成功时所述启动状态信号为高电压；
判断单元，用于根据所述启动状态信号的电压判断所述主用BIOS启动是否失败。
可选的，该装置还包括：
BIOS维护模块，用于当所述SPI总线切换至所述主用BIOS时，对所述主用BIOS执行维护操作或升级操作。
可选的，该装置还包括：
断电切换模块，用于当断电重启后，将所述SPI总线切换至主用BIOS。
本申请还提供一种双BIOS的控制系统，包括：处理器、南桥芯片组、CPLD、主用BIOS与备用BIOS，所述处理器与所述南桥芯片组连接，所述CPLD与所述南桥芯片组连接，所述主用BIOS和备用BIOS均与所述CPLD连接；
其中，所述CPLD用于根据主用BIOS发送的启动状态信号判断主用BIOS启动是否失败；若是，则切换SPI总线至备用BIOS，并将所述主用BIOS的启动状态写入SPI寄存器，根据接收到的所述切换指令将所述SPI总线切换至所述主用BIOS；
所述处理器用于通过所述SPI寄存器获取所述主用BIOS的启动状态，并根据所述主用BIOS的启动状态向所述CPLD发送切换指令；
所述主用BIOS，用于向所述CPLD发送启动状态信号。
可选的，所述主用BIOS，具体用于通过GPIO发送所述启动状态信号；其中，当所述主用BIOS启动成功时所述启动状态信号为高电压；
所述CPLD，具体用于根据所述启动状态信号的电压判断所述主用BIOS启动是否失败。
本申请所提供的一种双BIOS的控制方法，其特征在于，包括：CPLD根据主用BIOS发送的启动状态信号判断主用BIOS启动是否失败；若是，则切换SPI总线至备用BIOS，并将所述主用BIOS的启动状态写入SPI寄存器，以使处理器通过所述SPI寄存器获取所述主用BIOS的启动状态，并根据所述主用BIOS的启动状态向所述CPLD发送切换指令；其中，所述主用BIOS与所述备用BIOS均通过所述SPI总线与所述CPLD相连；根据接收到的所述切换指令将所述SPI总线切换至所述主用BIOS。
通过BIOS主动发送的启动状态判断BIOS是否启动失败，并使用SPI寄存器记录BIOS启动失败的信息，使处理器、CPLD以及BIOS之间形成相互交互的通信流程，提高了BIOS切换的稳定性，避免了因端口检测导致BIOS判断错误的情况。
本申请还提供一种双BIOS的控制装置以及控制系统，具有上述有益效果，在此不做赘述。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请实施例所提供的一种双BIOS的控制方法的流程图；
图2为本申请实施例所提供的一种双BIOS的控制方法的信号判断的流程图；
图3为本申请实施例所提供的一种双BIOS的控制装置的结构示意图；
图4为本申请实施例所提供的一种双BIOS的控制系统的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在现有技术中，片选芯片会通过一些端口的信号判断BIOS芯片的启动状态，但是该端口的信号并不是由BIOS芯片所控制的用来判断启动状态的信号，因此，片选芯片判断的BIOS芯片启动状态会出现偏差。并且，由于BIOS芯片本身无法控制自身为主用BIOS芯片或备用BIOS芯片，会导致将备用BIOS芯片判断为主用BIOS芯片。
本申请的核心是提供一种双BIOS的控制方法、控制装置以及控制系统，通过BIOS主动发送的启动状态判断BIOS是否启动失败，并使用SPI寄存器记录BIOS启动失败的信息，使处理器、CPLD以及BIOS之间形成相互交互的通信流程，提高了BIOS切换的稳定性，避免了因端口检测导致BIOS判断错误的情况。
请参考图1，图1为本申请实施例所提供的一种双BIOS的控制方法的流程图。
本实施例提供一种双BIOS的控制方法，可以提高双BIOS切换时的稳定 性，该方法可以包括：
S101，CPLD根据主用BIOS芯片发送的启动状态信号判断主用BIOS芯片启动是否失败；若是，则执行步骤S102。
本步骤旨在复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)根据主用BIOS芯片发送的启动状态信号判断主用BIOS芯片启动是否失败。
因此，本步骤中CPLD主要通过BIOS芯片自身发送的启动状态信号来判断该主用BIOS芯片是否启动失败。其中，主用BIOS芯片所发送的启动状态信号是主用BIOS芯片对自身状态进行判断得到的状态信号，该状态信号获取的方式就区别于现有技术中通过一些BIOS芯片无法控制端口信号获取的方式，该过程中主用BIOS芯片可以根据自身的控制程序或判断程序输出信号，做到主用BIOS芯片知道自己的状态，并且可以进行控制。
具体的，主用BIOS芯片发送信号以及获取信号的方式可以根据实际情况做选择，在此不做具体限定。
总的来说，本步骤也就是实现了CPLD与BIOS芯片之间的交互，并且每个部分都可以控制其信号状态。
S102，切换串行外设接口(Serial Peripheral Interface，SPI)总线至备用BIOS芯片，并且将主用BIOS芯片的启动状态写入SPI寄存器，以使处理器通过SPI寄存器获取主用BIOS芯片的启动状态，并根据主用BIOS芯片的启动状态向CPLD发送切换指令；其中，主用BIOS芯片与备用BIOS芯片均通过SPI总线与CPLD相连；
在步骤S101的基础上，本步骤旨在当判定主用BIOS芯片启动失败时， 将SPI总线切换至备用BIOS芯片，并且将对应的启动状态写入SPI寄存器中。主要目的就是当主用BIOS芯片启动失败后使备用BIOS芯片接替其工作，完成系统的启动。并且使处理器通过所述SPI寄存器获取主用BIOS芯片的启动状态，根据启动状态向CPLD发送切换指令。
其中，通常情况下处理器是在系统启动后开始获取BIOS芯片的启动状态，如果发生启动失败的情况，根据启动状态切换BIOS芯片，并进行维护等操作。
需要知道的是，本步骤中主用BIOS芯片与备用BIOS芯片通过SPI总线只与CPLD芯片进行连接，区别于现有技术中两个BIOS芯片与片选芯片连接后还与南桥芯片组连接。减少了连接次数，使结构上更为简单。
并且，通过切换SPI总线达到切换BIOS芯片的目的，是通过切换硬件电路完成，可以提高切换时和切换后SPI总线与BIOS芯片连接的稳定性。
S103，根据接收到的切换指令将SPI总线切换至主用BIOS芯片。
在步骤S102的基础上，本步骤旨在根据接收的切换指令将SPI总线切换至主用BIOS芯片。切换至主用BIOS芯片后就可以直接对BIOS芯片进行维护升级等操作。
需要说明的是，本步骤中通过切换指令使CPLD进行切换区别于现有技术中通过切换系统进程的方式，可以提高双BIOS芯片结构中双BIOS之间切换的稳定性。
本实施例中，通过步骤S101的CPLD与主用BIOS芯片之间的相互通信,步骤S102的CPLD通过SPI寄存器与处理器进行相互的通信，以及步骤S103中通过切换指令进行的相互的通信。使双BIOS结构在切换BIOS芯片时，形成三者之间的相互通信，即这三者之间存在一定的交互，可以提高双BIOS结 构的稳定性。
可选的，本实施例还可以包括：
当SPI总线切换至主用BIOS芯片时，处理器对主用BIOS芯片执行维护操作或升级操作。
当SPI总线切换至主用BIOS芯片时，在通常情况是当系统启动后，因此需要对主用BIOS芯片进行相应的维护操作，升级操作。
可选的，本实施例还可以包括：
当CPLD断电重启后，将SPI总线切换至主用BIOS芯片。
通过本可选方案可以使每次断电重启后都以主用BIOS芯片作为启动的BIOS芯片，保持了备用BIOS芯片处在静默状态，保护其BIOS信息。
综上，本实施例主要通过BIOS芯片主动发送的启动状态判断BIOS芯片是否启动失败，并使用SPI寄存器记录BIOS芯片启动失败的信息，使处理器、CPLD以及BIOS芯片之间形成相互交互的通信流程，提高了BIOS芯片切换的稳定性，避免了应端口检测导致BIOS芯片判断错误的情况。
请参考图2，图2为本申请实施例所提供的一种双BIOS的控制方法的信号判断的流程图。
基于上一实施例，本实施例主要针对上一实施例中如何进行信号判断做的一个具体说明，其他部分与上一实施例大体相同，相同部分可以参考上一实施例。
本实施例可以包括：
S201，主用BIOS芯片通过GPIO发送启动状态信号；其中，当主用BIOS 芯片启动成功时启动状态信号为高电压；
S202，CPLD根据启动状态信号的电压判断主用BIOS芯片启动是否失败。
本实施例中主要是使主用BIOS芯片通过GPIO(General Purpose Input Output通用输入/输出)发送启动状态信号。启动状态信号主要是通过电压高低来表现，当主用BIOS芯片启动成功时启动状态信号变为高电压状态。也就是如果在规定的时间段内或规定的时间点启动状态信号仍为低电压就可以判定主用BIOS芯片启动失败。据此，就可以使CPLD根据启动状态信号的电压判断主用BIOS芯片启动是否失败。
具体的，在实际操作中可以通过GPIO x端口的电压进行升降电压操作。
需要注意的是，本实施例中所提到的高低电压为本技术领域中所规定的高低电压，是技术人员可以清楚的知道的常规定义。
综上，通过本实施例中BIOS芯片所发送的启动状态信号就可以判断出BIOS芯片的启动状态，并根据该启动状态执行后续的操作流程。
本申请实施例提供了一种双BIOS的控制方法，可以通过BIOS芯片主动发送的启动状态判断BIOS芯片是否启动失败，并使用SPI寄存器记录BIOS启动失败的信息，使处理器、CPLD以及BIOS芯片之间形成相互交互的通信流程，提高了BIOS芯片切换的稳定性，避免了因端口检测导致BIOS芯片判断错误的情况。
下面对本申请实施例提供的一种双BIOS的控制装置进行介绍，下文描述的一种双BIOS的控制装置与上文描述的一种双BIOS的控制方法可相互对应参照。
请参考图3，图3为本申请实施例所提供的一种双BIOS的控制装置的结构示意图。
本实施例提供一种双BIOS的控制装置，可以包括：
启动状态判断模块100，用于根据主用BIOS芯片发送的启动状态信号判断主用BIOS芯片启动是否失败；
备用BIOS切换模块200，用于当主用BIOS芯片启动失败时，切换SPI总线至备用BIOS芯片，并将所述主用BIOS芯片的启动状态写入SPI寄存器，以使处理器通过SPI寄存器获取主用BIOS芯片的启动状态，并根据主用BIOS芯片的启动状态向CPLD发送切换指令；其中，主用BIOS芯片与备用BIOS芯片均通过SPI总线与CPLD相连；
主用BIOS切换模块300，用于根据接收到的切换指令将SPI总线切换至主用BIOS芯片。
可选的，该启动状态判断模块100可以包括：
信号发送单元，用于通过GPIO发送启动状态信号；其中，当主用BIOS芯片启动成功时启动状态信号为高电压；
判断单元，用于根据启动状态信号的电压判断主用BIOS芯片启动是否失败。
可选的，该装置还可以包括：
BIOS维护模块，用于当SPI总线切换至主用BIOS芯片时，对主用BIOS芯片执行维护操作或升级操作。
可选的，该装置还可以包括：
断电切换模块，用于当断电重启后，将SPI总线切换至主用BIOS芯片。
请参考图4，图4为本申请实施例所提供的一种双BIOS的控制系统的结构示意图。
本申请实施例还提供一种双BIOS的控制系统，可以包括：处理器、南桥芯片组、CPLD、主用BIOS芯片与备用BIOS芯片，处理器与南桥芯片组连接，CPLD与南桥芯片组连接，主用BIOS芯片和备用BIOS芯片均与CPLD连接；
其中，CPLD用于根据主用BIOS芯片发送的启动状态信号判断主用BIOS芯片启动是否失败；若是，则切换SPI总线至备用BIOS芯片，并将所述主用BIOS芯片的启动状态写入SPI寄存器，根据接收到的切换指令将SPI总线切换至主用BIOS芯片；
处理器用于通过SPI寄存器获取主用BIOS芯片的启动状态，并根据主用BIOS芯片的启动状态向CPLD发送切换指令；
主用BIOS芯片，用于向CPLD发送启动状态信号。
本实施例中主用BIOS芯片与备用BIOS芯片之间不相连，而是通过CPLD进行连接，并且是通过SPI总线进行连接，结构更加简单，易于实施，方便维护。
可选的，主用BIOS芯片，具体用于通过GPIO发送启动状态信号；其中，当主用BIOS芯片启动成功时启动状态信号为高电压；
CPLD，具体用于根据启动状态信号的电压判断主用BIOS芯片启动是否失败。
说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与 其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上对本申请所提供的一种双BIOS的控制方法、控制装置以及控制系统进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。
Figure PCTCN2018112054-appb-000001
Figure PCTCN2018112054-appb-000002

Claims (2)

  1. 启动状态写入SPI寄存器，根据接收到的所述切换指令将所述SPI总线切换至所述主用BIOS；
    所述处理器用于通过所述SPI寄存器获取所述主用BIOS的启动状态，并根据所述主用BIOS的启动状态向所述CPLD发送切换指令；
    所述主用BIOS，用于向所述CPLD发送启动状态信号。
  2. 根据权利要求9所述的控制系统，其特征在于，所述主用BIOS，具体用于通过GPIO发送所述启动状态信号；其中，当所述主用BIOS启动成功时所述启动状态信号为高电压；
    所述CPLD，具体用于根据所述启动状态信号的电压判断所述主用BIOS启动是否失败。
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