WO2019169705A1 - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

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Publication number
WO2019169705A1
WO2019169705A1 PCT/CN2018/084054 CN2018084054W WO2019169705A1 WO 2019169705 A1 WO2019169705 A1 WO 2019169705A1 CN 2018084054 W CN2018084054 W CN 2018084054W WO 2019169705 A1 WO2019169705 A1 WO 2019169705A1
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WIPO (PCT)
Prior art keywords
cathode
display panel
layer
power supply
auxiliary power
Prior art date
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Ceased
Application number
PCT/CN2018/084054
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English (en)
French (fr)
Inventor
刘兆松
任章淳
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/074,649 priority Critical patent/US11139364B2/en
Publication of WO2019169705A1 publication Critical patent/WO2019169705A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a method of fabricating the same.
  • the transparent cathode in a conventional large-size display panel (for example, an OLED display panel) adopting a top emission mode has a large impedance, which results in the conventional display panel having a more serious IR.
  • the Drop phenomenon causes the conventional display panel to emit unevenly.
  • the display effect of the above-described conventional large-sized display panel is not ideal because the transparent cathode has a large impedance.
  • An object of the present invention is to provide a display panel and a method of manufacturing the same that can improve the display quality of the display panel.
  • a display panel the display area of the display panel is divided into at least two sub-display areas, and a portion of the display panel corresponding to the sub-display area is provided with at least one pixel unit and at least one auxiliary power supply unit, the pixel unit
  • the auxiliary power supply unit is configured to supply power to a cathode layer of the display panel such that voltages applied by the cathode layer in each of the sub-display regions are equal or substantially equal; wherein
  • the cathode layer includes a first cathode located at a position corresponding to the auxiliary power supply unit and a second cathode located at a position corresponding to the pixel unit, the first cathode being connected to the second cathode;
  • the auxiliary power supply unit The power supply electrode and the auxiliary power supply electrode are connected, the auxiliary power supply electrode is connected to the power transmission line and the first cathode;
  • the pixel unit includes a thin film transistor, an anode, an organic light emitting device, and the second
  • the display panel includes a thin film transistor array device board and a display device board, the display device board and the thin film transistor array device board are superimposed and integrated; the power transmission line is disposed on the thin film transistor array a planarization layer disposed on the thin film transistor array device panel, and the planarization layer covers the power transmission line; the pixel definition layer is disposed on the planarization layer.
  • the thin film transistor array device board further includes a substrate, a light shielding member, a buffer layer, the thin film transistor, a first insulating layer, a second insulating layer, a scan line, and a data line
  • the thin film transistor includes a gate a semiconductor, a source, and the drain, wherein the first insulating layer is disposed between the gate and the semiconductor member, the data line, at least a portion of the source, and the At least a portion of the drain is disposed on the second insulating layer.
  • the auxiliary power supply unit is evenly distributed in the display area of the display panel.
  • a display panel the display area of the display panel is divided into at least two sub-display areas, and a portion of the display panel corresponding to the sub-display area is provided with at least one pixel unit and at least one auxiliary power supply unit, the pixel unit
  • the auxiliary power supply unit is configured to supply power to a cathode layer of the display panel such that voltages applied by the cathode layer in each of the sub-display regions are equal or substantially equal; wherein
  • the cathode layer includes a first cathode located at a position corresponding to the auxiliary power supply unit and a second cathode located at a position corresponding to the pixel unit, the first cathode being connected to the second cathode;
  • the auxiliary power supply unit The power supply electrode and the auxiliary power supply electrode are connected, the auxiliary power supply electrode is connected to the power transmission line and the first cathode;
  • the pixel unit includes a thin film transistor, an anode, an organic light emitting device, and the second
  • the display panel further includes a pixel defining layer; the pixel defining layer is provided with a first recessed portion and a second recessed portion, and the first recessed portion and the second recessed portion are both penetrated a pixel defining layer, wherein a position of the first recess portion corresponds to a position where the auxiliary power supply electrode is located, a position where the second recess portion is located corresponds to a position where the anode is located; and at least the organic light emitting device a portion is disposed on the second recess, a portion of the organic light emitting device located on the second recess is in contact with the anode; at least a portion of the first cathode is disposed on the first recess a portion of the first cathode located on the first recess portion is connected to the auxiliary power supply electrode, at least a portion of the second cathode is disposed on the second recess portion, and the second cathode is located at the A portion on the
  • the display panel further includes a planarization layer; the planarization layer is provided with a first via hole and a second via hole; at least a portion of the auxiliary power supply electrode is disposed on the planarization layer Another portion of the auxiliary power supply electrode is connected to the power line through the first through hole; at least a portion of the anode is disposed on the planarization layer, and another portion of the anode passes through the second pass A hole is connected to the drain.
  • the display panel includes a thin film transistor array device board and a display device board, the display device board and the thin film transistor array device board are superimposed and integrated; the power transmission line is disposed on the thin film transistor array a planarization layer disposed on the thin film transistor array device panel, and the planarization layer covers the power transmission line; the pixel definition layer is disposed on the planarization layer.
  • the thin film transistor array device board further includes a substrate, a light shielding member, a buffer layer, the thin film transistor, a first insulating layer, a second insulating layer, a scan line, and a data line
  • the thin film transistor includes a gate a semiconductor, a source, and the drain, wherein the first insulating layer is disposed between the gate and the semiconductor member, the data line, at least a portion of the source, and the At least a portion of the drain is disposed on the second insulating layer.
  • the auxiliary power supply unit is evenly distributed in the display area of the display panel.
  • the distance between any two of the auxiliary power supply units adjacent in the first direction or the second direction is equal or substantially equal, wherein the first direction is the length of the display panel
  • the direction corresponding to the edge is the direction corresponding to the short side of the display panel.
  • At least two of the auxiliary power supply units are used to collectively supply power to the cathode layer of the display panel.
  • the second cathode is configured to receive power from the auxiliary power supply unit through the first cathode, and apply a voltage to the organic light emitting device together with the anode, thereby causing the organic light emitting device Glowing.
  • a manufacturing method of a display panel comprising the steps of: step A, preparing a thin film transistor array device board; and step B, preparing a display device board on the thin film transistor array device board, wherein the display device board and The thin film transistor array device board is superimposed and integrated, and the display device board includes at least one of the pixel unit and at least one of the auxiliary power supply units.
  • the step B includes: step b1, forming an auxiliary power supply electrode and the anode; and step b2, forming a pixel defining layer having a first recessed portion and a second recessed portion, wherein The first recessed portion and the second recessed portion each penetrate the pixel defining layer, the first recessed portion is located at a position corresponding to a position where the auxiliary power supply electrode is located, and the second recessed portion is located at a position Corresponding to the position where the anode is located; step b3, the organic light emitting device is disposed on the pixel defining layer, wherein at least a portion of the organic light emitting device is disposed on the second recess, and the organic light emitting device is located a portion of the second recess is in contact with the anode; step b4, providing the cathode layer at the first recess and the organic light emitting device, wherein the cathode layer comprises the first a cathode and the second ca
  • the step B further includes: step b5, forming a planarization layer; step b6, providing a first via hole and a second on the planarization layer
  • the step b1 includes: step b11, forming the auxiliary power supply electrode on the planarization layer and the first via hole, wherein at least a portion of the auxiliary power supply electrode is disposed on the planarization a layer, the other portion of the auxiliary power supply electrode is connected to the power line through the first through hole; in step b12, the anode is formed on the planarization layer and the second through hole, wherein At least a portion of the anode is disposed on the planarization layer, and another portion of the anode is connected to the drain through the second via; the step b2 is: forming a layer on the planarization layer The pixel definition layer.
  • step B further includes: b7, removing a portion of the organic light emitting device corresponding to the first recess portion by using a laser beam, Forming a third through hole at a position corresponding to the first recessed portion of the organic light emitting device, wherein the auxiliary power supply electrode is exposed to the first recessed portion and the third through hole.
  • the step B further includes: step b8, forming the power line.
  • the step A includes: step a1, sequentially providing a light shielding member and a buffer layer on the substrate; step a2, providing a semiconductor member on the buffer layer; and step a3, in the semiconductor member Providing a first insulating layer thereon; step a4, providing a gate on the first insulating layer; step a5, providing a second insulating layer on the buffer layer, wherein the second insulating layer covers the semiconductor member a first insulating layer and the gate; a step a6, forming a fourth via hole and a fifth via hole on the second insulating layer; step a7, providing a source on the second insulating layer, The drain.
  • the step A further includes a step a8 of implanting N+ ions in both end edges of the semiconductor member.
  • the auxiliary power supply electrode is disposed in each sub-display area of the display panel, the auxiliary power supply electrode is evenly distributed, and the plurality of auxiliary power supply electrodes are collectively directed to the display panel including the plurality of sub-display areas.
  • the cathode layer is powered, so it can effectively reduce IR in large-size display panels.
  • the Drop phenomenon helps to improve the display quality of the display panel.
  • FIG. 1 is a schematic view of a display panel of the present invention in a plan view.
  • FIG. 2 is a cross-sectional view of a region B in the display panel shown in FIG. 1.
  • FIG. 3 is a cross-sectional view of a region C in the display panel shown in FIG. 1.
  • 4 to 15 are schematic views showing a method of manufacturing a display panel of the present invention.
  • Figure 16 is a flow chart showing a method of manufacturing a display panel of the present invention.
  • Figure 17 is a flow chart showing the steps of preparing a display device board on the thin film transistor array device board of Figure 16.
  • Figure 18 is a flow chart showing the steps of preparing the thin film transistor array device board of Figure 16.
  • the display panel 10 of the present invention is an OLED (Organic Light Emitting Diode) or the like.
  • FIG. 1 is a schematic view of a display panel 10 according to the present invention in a plan view angle
  • FIG. 2 is a cross-sectional view of a region B in the display panel 10 illustrated in FIG. 1
  • FIG. A cross-sectional view of a region C in the display panel 10 is shown.
  • the display panel 10 includes a thin film transistor array device board 101 and a display device board 102, and the display device board 102 and the thin film transistor array device board 101 are superimposed and integrated.
  • the display area of the display panel 10 of the present invention is divided into at least two sub-display areas A, and the portion of the display panel 10 corresponding to the sub-display area A is provided with at least one pixel unit and at least one auxiliary power supply unit, the pixel unit For displaying an image, the auxiliary power supply unit is configured to supply power to the cathode layer 1027 of the display panel 10 such that the voltage applied by the cathode layer 1027 in each of the sub-display areas A is equal or substantially equal.
  • the auxiliary power supply unit is uniformly distributed in the display area of the display panel 10, specifically, the distance between any two auxiliary power supply units adjacent in the first direction or the second direction is equal or Almost equal.
  • the first direction is a direction corresponding to a long side of the display panel 10
  • the second direction is a direction corresponding to a short side of the display panel 10.
  • At least two of the auxiliary power supply units are used to collectively supply power to the cathode layer 1027 of the display panel 10, so that the distance to the cathode layer 1027 can be shortened, so that the charge obtained by the cathode layer 1027 is at the cathode layer.
  • the distribution on the surface of 1027 is uniform or substantially uniform, so that the display panel 10 can be effectively prevented from exhibiting a decrease in display effect at a portion of the cathode layer 1027 remote from the voltage receiving end.
  • the cathode layer 1027 includes a first cathode 10271 at a position corresponding to the auxiliary power supply unit and a second cathode 10272 located at a position corresponding to the pixel unit, the first cathode 10271 and the second The cathode 10272 is connected.
  • the auxiliary power supply unit includes a power transmission line 1021 and an auxiliary power supply electrode 1023 that connects the power transmission line 1021 and the first cathode 10271.
  • the power line 1021 is disposed on the thin film transistor array device board 101.
  • the pixel unit includes a thin film transistor, an anode 1024, an organic light emitting device 1026, and the second cathode 10272.
  • the organic light emitting device 1026 is disposed between the anode 1024 and the second cathode 10272, and the anode 1024 is The drain 1019 of the thin film transistor is connected.
  • the second cathode 10272 is configured to receive a power source (voltage/current) from the auxiliary power supply unit through the first cathode 10271, and apply a voltage to the organic light emitting device 1026 together with the anode 1024, thereby causing the The organic light emitting device 1026 emits light.
  • a power source voltage/current
  • the display panel 10 also includes a pixel definition layer 1025.
  • the pixel defining layer 1025 is disposed on the planarization layer 1022.
  • the pixel defining layer 1025 is provided with a first recessed portion 10251 and a second recessed portion 10252, and the first recessed portion 10251 and the second recessed portion 10252 both penetrate the pixel defining layer 1025, the first recessed portion
  • the position of the portion 10251 corresponds to the position where the auxiliary power supply electrode 1023 is located
  • the position of the second recess portion 10252 corresponds to the position where the anode 1024 is located.
  • the first recessed portion 10251 and the second recessed portion 10252 are formed by performing a third mask process and a third etching process on the material layer corresponding to the pixel defining layer 1025.
  • At least a portion of the organic light emitting device 1026 is disposed on the second recess portion 10252, and a portion of the organic light emitting device 1026 located on the second recess portion 10252 is in contact with the anode 1024.
  • At least a portion of the first cathode 10271 is disposed on the first recessed portion 10251, and a portion of the first cathode 10271 located on the first recessed portion 10251 is connected (contacted) to the auxiliary power supply electrode 1023.
  • At least a portion of the second cathode 10272 is disposed on the second recess portion 10252, and a portion of the second cathode 10272 located on the second recess portion 10252 is disposed on the organic light emitting device 1026.
  • a portion of the first cathode 10271 that is connected (contacted) to the auxiliary power supply electrode 1023 on the first recessed portion 10251 is disposed on the pixel defining layer 1025 (including the portion)
  • the portion of the organic light emitting device 1026 located on the first recessed portion 10251 is removed by laser to be used in the organic light emitting device 1026 and the Forming a third through hole at a position corresponding to the first recessed portion 10251, thereby exposing the auxiliary power supply electrode 1023 in the first recessed portion 10251 and the third through hole, and then setting the cathode layer 1027 Formed on the organic light emitting device 1026 and on the auxiliary power supply electrode 1023 exposed to the first recess portion 10251 and the third via hole.
  • the display panel 10 further includes a planarization layer 1022.
  • the planarization layer 1022 is disposed on the thin film transistor array device board 101, and the planarization layer 1022 covers the power transmission line 1021.
  • the planarization layer 1022 is provided with a first through hole 1001 and a second through hole 1002.
  • the first through hole 1001 and the second through hole 1002 each penetrate the planarization layer 1022.
  • the first via hole 1001 and the second via hole 1002 are formed by performing a second mask process and a third etching process on the planarization layer 1022.
  • At least a portion of the auxiliary power supply electrode 1023 is disposed on the planarization layer 1022, and another portion of the auxiliary power supply electrode 1023 is connected to the power transmission line 1021 through the first through hole 1001.
  • At least a portion of the anode 1024 is disposed on the planarization layer 1022, and another portion of the anode 1024 is coupled to the drain 1019 through the second via 1002.
  • the thin film transistor array device board 101 further includes a substrate 1011, a light shielding member 1012, a buffer layer 1013, the thin film transistor, a first insulating layer 1015, a second insulating layer 1017, a scan line, and a data line, the thin film transistor including a gate a pole 1016, a semiconductor member 1014, a source 1018, and the drain 1019, wherein the first insulating layer 1015 is disposed between the gate 1016 and the semiconductor member 1014, the data line, the source At least a portion of the pole 1018 and at least a portion of the drain 1019 are disposed on the second insulating layer 1017.
  • the structure of the thin film transistor in the thin film transistor array device board 101 is any one of a top gate structure, a bottom gate structure, and a flat gate structure.
  • auxiliary power supply electrode 1023 is provided in the display panel 10 of the present invention, it is possible to apply a voltage to the cathode in a plurality of regions by the auxiliary power supply electrode 1023, thereby effectively reducing the IR. Drop prevents the cathode layer 1027 from deteriorating the display quality of the display panel 10 due to its large impedance.
  • FIG. 4 to FIG. 18 are schematic diagrams showing a method of fabricating a display panel of the present invention
  • FIG. 16 is a flowchart of a method of fabricating the display panel of the present invention
  • FIG. 17 is a diagram of the thin film transistor of FIG.
  • FIG. 18 is a flow chart showing the steps of the thin film transistor array device board 101 of FIG.
  • a method of manufacturing a display panel of the present invention is used to manufacture the display panel 10 of the present invention, the method comprising the steps of:
  • Step A a thin film transistor array device board 101 is prepared.
  • Step B (step 1602), preparing a display device board 102 on the thin film transistor array device board 101, wherein the display device board 102 and the thin film transistor array device board 101 are superimposed and integrated, the display device board 102 includes at least one of the pixel units and at least one of the auxiliary power supply units.
  • the step A (step 1601) includes:
  • step a1 the light shielding member 1012 and the buffer layer 1013 are sequentially disposed on the substrate 1011. Specifically, a light shielding metal layer is deposited on the substrate 1011, and the light shielding metal layer is patterned by a first mask process and a first etching process, thereby forming the light shielding member 1012, and then in the substrate 1011 and the The buffer layer 1013 is deposited on the light shielding member 1012.
  • a semiconductor member 1014 is provided on the buffer layer 1013. Specifically, a semiconductor layer is deposited on the buffer layer 1013, and the semiconductor layer is patterned by a second mask process and a second etching process, thereby forming the semiconductor member 1014.
  • step a3 (step 16013), a first insulating layer 1015 is provided on the semiconductor member 1014.
  • step a4 (step 16014), a gate 1016 is disposed on the first insulating layer 1015.
  • Step a5 (step 16015), providing a second insulating layer 1017 on the buffer layer 1013, wherein the second insulating layer 1017 covers the semiconductor member 1014, the first insulating layer 1015, and the gate 1016 .
  • step a6 a fourth via hole 801 and a fifth via hole 802 are formed on the second insulating layer 1017. Specifically, a fourth mask process is performed on the second insulating layer 1017 to form the fourth via hole 801 and the fifth via hole 802.
  • step a7 a source 1018 and a drain 1019 are disposed on the second insulating layer 1017.
  • a second metal layer is disposed on the second insulating layer 1017, and a fifth mask process and a fifth etching process are performed on the second metal layer to form the source 1018 and the drain 1019. .
  • the source 1018, the drain 1019 and the power line 1021 are simultaneously formed in the second metal layer by the fifth mask process and the fifth etching process.
  • steps a3 (steps 16013) and a4 (step 16014) specifically include sequentially depositing a first insulating material layer and a first metal layer on the semiconductor member 1014, and providing a photoresist (PR) on the first metal layer.
  • Photo Resist) block 601 performing a third mask process on the first insulating material layer and the first metal layer to pattern the first insulating material layer and the first metal layer, and to pattern
  • the first metal layer is subjected to a third etching process to form the gate electrode 1016, and then self-aligned by the gate electrode 1016 to etch the first insulating material layer such that both ends of the semiconductor component 1014 The edge is bare.
  • step A (step 1601) further includes:
  • Step a8 implanting N+ ions in both end edges of the semiconductor member 1014.
  • the step B includes:
  • Step b1 (step 16024), forming the auxiliary power supply electrode 1023 and the anode 1024.
  • a third metal layer is disposed on the planarization layer 1022 at a position corresponding to the first via hole 1001 and the second via hole 1002, and a seventh mask is performed on the third metal layer. The process and the seventh etching process are performed to form the auxiliary power supply electrode 1023 and the anode 1024.
  • Step b2 (step 16025), forming a pixel defining layer 1025 having a first recessed portion 10251 and a second recessed portion 10252, wherein the first recessed portion 10251 and the second recessed portion 10252 both penetrate the pixel defining layer 1025, a position where the first recessed portion 10251 is located corresponds to a position where the auxiliary power supply electrode 1023 is located, and a position where the second recessed portion 10252 is located corresponds to a position where the anode 1024 is located.
  • a material layer corresponding to the pixel defining layer 1025 is disposed on the planarization layer 1022, and an eighth mask process and an eighth etching process are performed on the material layer to form a material layer extending through the material layer.
  • Step b3 the organic light emitting device 1026 is disposed on the pixel defining layer 1025, wherein at least a portion of the organic light emitting device 1026 is disposed on the second recess portion 10252, the organic light emitting device A portion of the 1026 located on the second recess 10252 is in contact with the anode 1024.
  • an OLED material is vapor-deposited on the pixel defining layer 1025 to form the organic light emitting device 1026.
  • Step b4 (step 16027), providing the cathode layer 1027 at the first recess 10251 and the organic light emitting device 1026, wherein the cathode layer 1027 includes the first cathode 10271 and the second a cathode 10272, the first cathode 10271 is disposed at the first recess portion 10251, and the first cathode 10271 is connected to the auxiliary power supply electrode 1023, and the second cathode 10272 is disposed at the second recess portion 10252. And the second cathode 10272 is connected to the anode 1024.
  • step B further includes:
  • step b4 (step 16027) is:
  • the cathode layer 1027 is disposed on the auxiliary power supply electrode 1023 exposed on the first recessed portion 10251 and the third via hole and on the organic light emitting device 1026.
  • step B (step 1602) further includes:
  • step b5 (step 16022), a planarization layer 1022 is formed.
  • Step b6 (step 16223), a first via hole 1001 and a second via hole 1002 are disposed on the planarization layer 1022. Specifically, a sixth mask process and a seventh etching process are performed on the planarization layer 1022 to form the first via hole 1001 and the second via hole 1002.
  • the step b1 (step 16024) includes:
  • Step b11 forming the auxiliary power supply electrode 1023 on the planarization layer 1022 and the first via hole 1001, wherein at least a portion of the auxiliary power supply electrode 1023 is disposed on the planarization layer 1022. Another portion of the auxiliary power supply electrode 1023 is connected to the power line 1021 through the first through hole 1001.
  • Step b12 forming the anode 1024 on the planarization layer 1022 and the second via hole 1002, wherein at least a portion of the anode 1024 is disposed on the planarization layer 1022, the anode 1024 Another portion is connected to the drain 1019 through the second via 1002.
  • step b2 (step 16025) is:
  • the pixel defining layer 1025 is formed on the planarization layer 1022.
  • step B (step 1602) further includes:
  • step b8 step 16021
  • the power line 1021 is formed.
  • a metal having a thickness in the range of 500 angstroms to 2000 angstroms on the substrate 1011 as a TFT light shielding layer (light shielding metal layer), which may be Mo, Al, Cu, Ti, or the like, or an alloy, and patterned with the yellow light to form the light shielding member 1012.
  • a TFT light shielding layer which may be Mo, Al, Cu, Ti, or the like, or an alloy
  • a silicon oxide (SiOx) film is deposited on the substrate 1011 and the light shielding member 1012 as a buffer layer 1013 having a thickness in the range of 1000 angstroms to 5000 angstroms.
  • the metal oxide semiconductor material may be IGZO, IZTO, IGZTO, etc., and the thickness of the semiconductor layer is 100 angstroms to 1000 Within the range of angstroms, the semiconductor layer is patterned using yellow light to form the semiconductor component 1014.
  • a silicon oxide (SiOx) film on the buffer layer 1013 and the semiconductor member 1014 as a gate insulating layer (first insulating layer 1015), the gate insulating layer having a thickness of 1000 ⁇ Up to 3000 angstroms.
  • a metal on the gate insulating layer as a gate metal layer (first metal layer), and the gate metal layer may be Mo, Al, Cu, Cu, or an alloy, the gate
  • the thickness of the polar metal layer is in the range of 2000 angstroms to 8000 angstroms.
  • the gate insulating layer is such that the gate insulating layer exists only under the film layer of the gate metal pattern, and the gate insulating layer in other places is etched away.
  • the metal oxide semiconductor material has a significantly reduced resistance, forming an N+ conductor layer for contact with the source 1018 and the drain 1019 of the thin film transistor, and the metal oxide semiconductor material under the gate insulating layer is not processed.
  • TFT thin film transistor
  • an interlayer insulating layer that is, a second insulating layer 1017, on the buffer layer 1013, the semiconductor member 1014, and the gate electrode 1016, and the material of the second insulating layer 1017 may be a silicon oxide (SiOx), a silicon nitride (SiNx) or a sandwich structure, the second insulating layer 1017 having a thickness in the range of 3,000 angstroms to 10,000 angstroms, the source being formed on the second insulating layer 1017 1018.
  • the contact region of the drain electrode 1019 is opened (the fourth via hole 801 and the fifth via hole 802).
  • a SiOx film as a first planarization layer (passivation layer) on the second insulating layer 1017 and the source 1018, the drain 1019, and the power line 1021.
  • the thickness of the layer is in the range of 1000 angstroms to 5000 angstroms, and via holes are etched for the passivation layer (the first via hole 1001 and the second via hole 1002).
  • the second planarization layer may be a photoresist layer of different composition, and the thickness of the second planarization layer is in the range of 10,000 angstroms to 20,000 angstroms, Light makes a via for the second planarization layer (the first via 1001 and the second via 1002).
  • a transparent oxide such as ITO or a sandwich structure of ITO/Ag/ITO on the planarization layer 1022 including the first planarization layer and the second planarization layer, a transparent oxide such as ITO or ITO/Ag/
  • the sandwich structure of ITO has a thickness in the range of 500 angstroms to 2000 angstroms and is patterned using yellow light to form an anode 1024 and the auxiliary power supply electrode 1023.
  • a pixel defining layer 1025 (PDL layer) on the planarization layer 1022 and the anode 1024 and the auxiliary power supply electrode 1023, and the pixel defining layer 1025 may include a photoresist layer of different composition,
  • the pixel defining layer 1025 has a thickness in the range of 10,000 angstroms to 20,000 angstroms, and defines a light-emitting region for the pixel defining layer 1025 by yellow light to complete the back sheet fabrication.
  • a light-emitting layer is formed on the entire surface of the pixel defining layer 1025 by vapor deposition, and the light-emitting layer is placed in the auxiliary by laser beam irradiation in a nitrogen (N2) environment or a vacuum environment.
  • the portion at the power supply electrode 1023 is removed to ensure that the cathode can overlap the auxiliary electrode.
  • the diameter of the cross section of the laser beam (laser irradiation spot) needs to be smaller than the opening of the pixel electrode layer at the auxiliary power supply electrode 1023 to ensure that the luminescent layer material does not damage and contaminate the normal luminescent region.
  • a cathode metal is further formed on the auxiliary power supply electrode 1023 and the light-emitting layer, and the cathode is overlapped with the auxiliary electrode at a design position, that is, the fabrication of the OLED panel is completed.
  • the above technical solution can effectively improve the IR existing in the large-sized display panel 10. Drop problem. That is, since the auxiliary power supply electrode 1023 is provided in each of the sub-display areas A of the display panel 10, the auxiliary power supply electrodes 1023 are evenly distributed, and the plurality of auxiliary power supply electrodes 1023 collectively include the plurality of sub-display areas A. The cathode layer 1027 in the display panel is powered, so that the IR Drop phenomenon in the large-sized display panel 10 can be effectively reduced, thereby contributing to improvement in display quality of the display panel 10.
  • the OLED material at the auxiliary power supply electrode 1023 is processed by laser beam irradiation to overlap the cathode and the auxiliary power supply electrode 1023, the introduction of a yellow light process such as Pillar is avoided.
  • the process is simple.

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Abstract

提供一种显示面板及其制造方法。显示面板（10）与其子显示区（A）对应的部分设置有像素单元和辅助供电单元，辅助供电单元用于向阴极层（1027）供电，以使阴极层（1027）在每一子显示区（A）中所施加的电压相等或大致相等；阴极层（1027）包括第一阴极（10271）和第二阴极（10272）；辅助供电单元包括输电线（1021）和辅助供电电极（1023）。这能提高显示面板的显示质量。

Description

显示面板及其制造方法 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板及其制造方法。
 背景技术
传统的采用顶发光模式的大尺寸显示面板（例如，OLED显示面板）中的透明阴极具有较大的阻抗，这导致了该传统的显示面板具有较严重的IR Drop现象，从而导致了该传统的显示面板发光不均。
即，上述传统的大尺寸显示面板的显示效果因透明阴极具有较大阻抗而不够理想。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种显示面板及其制造方法，其能提高显示面板的显示质量。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种显示面板，所述显示面板的显示区划分有至少两个子显示区，所述显示面板与所述子显示区对应的部分设置有至少一像素单元和至少一辅助供电单元，所述像素单元用于显示图像，所述辅助供电单元用于向所述显示面板的阴极层供电，以使所述阴极层在每一所述子显示区中所施加的电压相等或大致相等；其中，所述阴极层包括位于与所述辅助供电单元对应的位置的第一阴极和位于与所述像素单元对应的位置的第二阴极，所述第一阴极与所述第二阴极连接；所述辅助供电单元包括输电线和辅助供电电极，所述辅助供电电极连接所述输电线和所述第一阴极；所述像素单元包括薄膜晶体管、阳极、有机发光器件和所述第二阴极，所述有机发光器件设置于所述阳极和所述第二阴极之间，所述阳极与所述薄膜晶体管的漏极连接；所述显示面板还包括像素定义层；所述像素定义层上设置有第一凹陷部和第二凹陷部，所述第一凹陷部和所述第二凹陷部均贯穿所述像素定义层，所述第一凹陷部所在的位置与所述辅助供电电极所在的位置对应，所述第二凹陷部所在的位置与所述阳极所在的位置对应；所述有机发光器件的至少一部分设置于所述第二凹陷部上，所述有机发光器件位于所述第二凹陷部上的部分与所述阳极接触；所述第一阴极的至少一部分设置于所述第一凹陷部上，所述第一阴极位于所述第一凹陷部上的部分与所述辅助供电电极相连接，所述第二阴极的至少一部分设置于所述第二凹陷部上，所述第二阴极位于所述第二凹陷部上的部分设置于所述有机发光器件上；所述显示面板还包括平坦化层；所述平坦化层上设置有第一通孔和第二通孔；所述辅助供电电极的至少一部分设置于所述平坦化层上，所述辅助供电电极的另一部分通过所述第一通孔与所述输电线连接；所述阳极的至少一部分设置于所述平坦化层上，所述阳极的另一部分通过所述第二通孔与所述漏极连接。
在上述显示面板中，所述显示面板包括薄膜晶体管阵列器件板和显示器件板，所述显示器件板与所述薄膜晶体管阵列器件板叠加组合为一体；所述输电线设置于所述薄膜晶体管阵列器件板上；所述平坦化层设置于所述薄膜晶体管阵列器件板上，并且所述平坦化层覆盖所述输电线；所述像素定义层设置于所述平坦化层上。
在上述显示面板中，所述薄膜晶体管阵列器件板还包括基板、遮光构件、缓冲层、所述薄膜晶体管、第一绝缘层、第二绝缘层、扫描线和数据线，所述薄膜晶体管包括栅极、半导体构件、源极和所述漏极，其中，所述第一绝缘层设置于所述栅极和所述半导体构件之间，所述数据线、所述源极的至少一部分和所述漏极的至少一部分设置于所述第二绝缘层上。
在上述显示面板中，所述辅助供电单元均匀分布于所述显示面板的所述显示区中。
一种显示面板，所述显示面板的显示区划分有至少两个子显示区，所述显示面板与所述子显示区对应的部分设置有至少一像素单元和至少一辅助供电单元，所述像素单元用于显示图像，所述辅助供电单元用于向所述显示面板的阴极层供电，以使所述阴极层在每一所述子显示区中所施加的电压相等或大致相等；其中，所述阴极层包括位于与所述辅助供电单元对应的位置的第一阴极和位于与所述像素单元对应的位置的第二阴极，所述第一阴极与所述第二阴极连接；所述辅助供电单元包括输电线和辅助供电电极，所述辅助供电电极连接所述输电线和所述第一阴极；所述像素单元包括薄膜晶体管、阳极、有机发光器件和所述第二阴极，所述有机发光器件设置于所述阳极和所述第二阴极之间，所述阳极与所述薄膜晶体管的漏极连接。
在上述显示面板中，所述显示面板还包括像素定义层；所述像素定义层上设置有第一凹陷部和第二凹陷部，所述第一凹陷部和所述第二凹陷部均贯穿所述像素定义层，所述第一凹陷部所在的位置与所述辅助供电电极所在的位置对应，所述第二凹陷部所在的位置与所述阳极所在的位置对应；所述有机发光器件的至少一部分设置于所述第二凹陷部上，所述有机发光器件位于所述第二凹陷部上的部分与所述阳极接触；所述第一阴极的至少一部分设置于所述第一凹陷部上，所述第一阴极位于所述第一凹陷部上的部分与所述辅助供电电极相连接，所述第二阴极的至少一部分设置于所述第二凹陷部上，所述第二阴极位于所述第二凹陷部上的部分设置于所述有机发光器件上。
在上述显示面板中，所述显示面板还包括平坦化层；所述平坦化层上设置有第一通孔和第二通孔；所述辅助供电电极的至少一部分设置于所述平坦化层上，所述辅助供电电极的另一部分通过所述第一通孔与所述输电线连接；所述阳极的至少一部分设置于所述平坦化层上，所述阳极的另一部分通过所述第二通孔与所述漏极连接。
在上述显示面板中，所述显示面板包括薄膜晶体管阵列器件板和显示器件板，所述显示器件板与所述薄膜晶体管阵列器件板叠加组合为一体；所述输电线设置于所述薄膜晶体管阵列器件板上；所述平坦化层设置于所述薄膜晶体管阵列器件板上，并且所述平坦化层覆盖所述输电线；所述像素定义层设置于所述平坦化层上。
在上述显示面板中，所述薄膜晶体管阵列器件板还包括基板、遮光构件、缓冲层、所述薄膜晶体管、第一绝缘层、第二绝缘层、扫描线和数据线，所述薄膜晶体管包括栅极、半导体构件、源极和所述漏极，其中，所述第一绝缘层设置于所述栅极和所述半导体构件之间，所述数据线、所述源极的至少一部分和所述漏极的至少一部分设置于所述第二绝缘层上。
在上述显示面板中，所述辅助供电单元均匀分布于所述显示面板的所述显示区中。
在上述显示面板中，任意两个在第一方向上或第二方向上相邻的所述辅助供电单元之间的距离相等或大致相等，其中，所述第一方向为所述显示面板的长边所对应的方向，所述第二方向为所述显示面板的短边所对应的方向。
在上述显示面板中，至少两所述辅助供电单元用于共同向所述显示面板的阴极层供电。
在上述显示面板中，所述第二阴极用于通过所述第一阴极从所述辅助供电单元接收电源，并与所述阳极共同向所述有机发光器件施加电压，从而使得所述有机发光器件发光。
一种显示面板的制造方法，所述方法包括以下步骤：步骤A、制备薄膜晶体管阵列器件板；步骤B、在所述薄膜晶体管阵列器件板上制备显示器件板，其中，所述显示器件板与所述薄膜晶体管阵列器件板叠加组合为一体，所述显示器件板包括至少一所述像素单元和至少一所述辅助供电单元。
在上述显示面板的制造方法中，所述步骤B包括：步骤b1、形成辅助供电电极和所述阳极；步骤b2、形成具有第一凹陷部和第二凹陷部的像素定义层，其中，所述第一凹陷部和所述第二凹陷部均贯穿所述像素定义层，所述第一凹陷部所在的位置与所述辅助供电电极所在的位置对应，所述第二凹陷部所在的位置与所述阳极所在的位置对应；步骤b3、在所述像素定义层上设置所述有机发光器件，其中，所述有机发光器件的至少一部分设置于所述第二凹陷部上，所述有机发光器件位于所述第二凹陷部上的部分与所述阳极接触；步骤b4、在所述第一凹陷部处和所述有机发光器件上设置所述阴极层，其中，所述阴极层包括所述第一阴极和所述第二阴极，所述第一阴极设置于所述第一凹陷部处，并且所述第一阴极与所述辅助供电电极连接，所述第二阴极设置于第二凹陷部处，并且所述第二阴极与所述阳极连接。
在上述显示面板的制造方法中，在所述步骤b1之前，所述步骤B还包括：步骤b5、形成平坦化层；步骤b6、在所述平坦化层上设置有第一通孔和第二通孔；所述步骤b1包括：步骤b11、在所述平坦化层上和所述第一通孔中形成所述辅助供电电极，其中，所述辅助供电电极的至少一部分设置于所述平坦化层上，所述辅助供电电极的另一部分通过所述第一通孔与所述输电线连接；步骤b12、在所述平坦化层上和所述第二通孔中形成所述阳极，其中，所述阳极的至少一部分设置于所述平坦化层上，所述阳极的另一部分通过所述第二通孔与所述漏极连接；所述步骤b2为：在所述平坦化层上形成所述像素定义层。
在上述显示面板的制造方法中，在步骤b3之后，以及在步骤b4之前，所述步骤B还包括：b7、利用激光束去除所述有机发光器件与所述第一凹陷部对应的部分，以在所述有机发光器件与所述第一凹陷部对应的位置处形成第三通孔，其中，所述辅助供电电极露出于所述第一凹陷部和所述第三通孔。
在上述显示面板的制造方法中，在所述步骤b5之前，所述步骤B还包括：步骤b8、形成所述输电线。
在上述显示面板的制造方法中，所述步骤A包括:步骤a1、在基板上依次设置遮光构件和缓冲层；步骤a2、在所述缓冲层上设置半导体构件；步骤a3、在所述半导体构件上设置第一绝缘层；步骤a4、在所述第一绝缘层上设置栅极；步骤a5、在所述缓冲层上设置第二绝缘层，其中，所述第二绝缘层覆盖所述半导体构件、所述第一绝缘层和所述栅极；步骤a6、在所述第二绝缘层上形成第四通孔和第五通孔；步骤a7、在所述第二绝缘层上设置源极、所述漏极。
在上述显示面板的制造方法中，在所述步骤a4之后，以及在所述步骤a5之前，所述步骤A还包括：步骤a8、在所述半导体构件的两端边缘部中植入N+离子。
 有益效果
相对现有技术，由于本发明在显示面板的每一个子显示区中均设置辅助供电电极，因此，辅助供电电极分布均匀，并且，多个辅助供电电极共同向包括多个子显示区的显示面板中的阴极层供电，因此可以有效降低大尺寸的显示面板中的IR Drop现象，从而有利于提高显示面板的显示质量。
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
 附图说明
图1为本发明的显示面板在俯视角度下的示意图。
图2为图1所示的显示面板中的区域B的剖视图。
图3为图1所示的显示面板中的区域C的剖视图。
图4至图15为本发明的显示面板的制造方法的示意图。
图16为本发明的显示面板的制造方法的流程图。
图17为图16中在所述薄膜晶体管阵列器件板上制备显示器件板的步骤的流程图。
图18为图16中制备薄膜晶体管阵列器件板的步骤的流程图。
 本发明的实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的显示面板10为OLED（Organic Light Emitting Diode，有机发光二极管显示面板）等。
参考图1、图2和图3，图1为本发明的显示面板10在俯视角度下的示意图，图2为图1所示的显示面板10中的区域B的剖视图，图3为图1所示的显示面板10中的区域C的剖视图。
所述显示面板10包括薄膜晶体管阵列器件板101和显示器件板102，所述显示器件板102与所述薄膜晶体管阵列器件板101叠加组合为一体。
本发明的显示面板10的显示区划分有至少两个子显示区A，所述显示面板10与所述子显示区A对应的部分设置有至少一像素单元和至少一辅助供电单元，所述像素单元用于显示图像，所述辅助供电单元用于向所述显示面板10的阴极层1027供电，以使所述阴极层1027在每一所述子显示区A中所施加的电压相等或大致相等。
所述辅助供电单元均匀分布于所述显示面板10的所述显示区中，具体地，任意两个在第一方向上或第二方向上相邻的所述辅助供电单元之间的距离相等或大致相等。其中，所述第一方向为所述显示面板10的长边所对应的方向，所述第二方向为所述显示面板10的短边所对应的方向。
至少两所述辅助供电单元用于共同向所述显示面板10的阴极层1027供电，因此可以缩短向所述阴极层1027供电的距离，从而使所述阴极层1027所获得电荷在所述阴极层1027的表面上的分布均匀或大致均匀，因此能够有效避免所述显示面板10在所述阴极层1027远离电压接收端的部分出现显示效果下降的现象。
其中，所述阴极层1027包括位于与所述辅助供电单元对应的位置的第一阴极10271和位于与所述像素单元对应的位置的第二阴极10272，所述第一阴极10271与所述第二阴极10272连接。
所述辅助供电单元包括输电线1021和辅助供电电极1023，所述辅助供电电极1023连接所述输电线1021和所述第一阴极10271。
所述输电线1021设置于所述薄膜晶体管阵列器件板101上。
所述像素单元包括薄膜晶体管、阳极1024、有机发光器件1026和所述第二阴极10272，所述有机发光器件1026设置于所述阳极1024和所述第二阴极10272之间，所述阳极1024与所述薄膜晶体管的漏极1019连接。
所述第二阴极10272用于通过所述第一阴极10271从所述辅助供电单元接收电源（电压/电流），并与所述阳极1024共同向所述有机发光器件1026施加电压，从而使得所述有机发光器件1026发光。
所述显示面板10还包括像素定义层1025。所述像素定义层1025设置于所述平坦化层1022上。
所述像素定义层1025上设置有第一凹陷部10251和第二凹陷部10252，所述第一凹陷部10251和所述第二凹陷部10252均贯穿所述像素定义层1025，所述第一凹陷部10251所在的位置与所述辅助供电电极1023所在的位置对应，所述第二凹陷部10252所在的位置与所述阳极1024所在的位置对应。
所述第一凹陷部10251和所述第二凹陷部10252是通过对所述像素定义层1025所对应的材料层实施第三光罩制程和第三蚀刻制程来形成的。
所述有机发光器件1026的至少一部分设置于所述第二凹陷部10252上，所述有机发光器件1026位于所述第二凹陷部10252上的部分与所述阳极1024接触。
所述第一阴极10271的至少一部分设置于所述第一凹陷部10251上，所述第一阴极10271位于所述第一凹陷部10251上的部分与所述辅助供电电极1023相连接（接触），所述第二阴极10272的至少一部分设置于所述第二凹陷部10252上，所述第二阴极10272位于所述第二凹陷部10252上的部分设置于所述有机发光器件1026上。
与所述辅助供电电极1023相连接（接触）的所述第一阴极10271位于所述第一凹陷部10251上的部分是在将所述有机发光器件1026设置于所述像素定义层1025（包括所述第一凹陷部10251和所述第二凹陷部10252）上后，将所述有机发光器件1026位于所述第一凹陷部10251上的部分用激光去除，以在所述有机发光器件1026与所述第一凹陷部10251对应的位置处形成第三通孔，从而使所述辅助供电电极1023在所述第一凹陷部10251和所述第三通孔中露出，然后将所述阴极层1027设置于所述有机发光器件1026上以及露出于所述第一凹陷部10251和所述第三通孔的所述辅助供电电极1023上来形成的。
所述显示面板10还包括平坦化层1022。所述平坦化层1022设置于所述薄膜晶体管阵列器件板101上，并且所述平坦化层1022覆盖所述输电线1021。
所述平坦化层1022上设置有第一通孔1001和第二通孔1002。所述第一通孔1001和所述第二通孔1002均贯穿所述平坦化层1022。所述第一通孔1001和所述第二通孔1002是通过对所述平坦化层1022实施第二光罩制程和第三蚀刻制程来形成的。
所述辅助供电电极1023的至少一部分设置于所述平坦化层1022上，所述辅助供电电极1023的另一部分通过所述第一通孔1001与所述输电线1021连接。
所述阳极1024的至少一部分设置于所述平坦化层1022上，所述阳极1024的另一部分通过所述第二通孔1002与所述漏极1019连接。
所述薄膜晶体管阵列器件板101还包括基板1011、遮光构件1012、缓冲层1013、所述薄膜晶体管、第一绝缘层1015、第二绝缘层1017、扫描线和数据线，所述薄膜晶体管包括栅极1016、半导体构件1014、源极1018和所述漏极1019，其中，所述第一绝缘层1015设置于所述栅极1016和所述半导体构件1014之间，所述数据线、所述源极1018的至少一部分和所述漏极1019的至少一部分设置于所述第二绝缘层1017上。
所述薄膜晶体管阵列器件板101中的所述薄膜晶体管的结构为顶栅结构、底栅结构、平栅结构中的任意一种。
由于本发明的显示面板10中设置有辅助供电电极1023，因此可以通过辅助供电电极1023在多个区域给阴极施加电压，有效减小IR drop，避免阴极层1027因具有较大的阻抗而导致显示面板10的显示质量下降。
参考图4至图18，图4至图15为本发明的显示面板的制造方法的示意图，图16为本发明的显示面板的制造方法的流程图，图17为图16中在所述薄膜晶体管阵列器件板101上制备显示器件板102的步骤的流程图，图18为图16中制备薄膜晶体管阵列器件板101的步骤的流程图。
本发明的显示面板的制造方法用于制造本发明的显示面板10，所述方法包括以下步骤：
步骤A（步骤1601）、制备薄膜晶体管阵列器件板101。
步骤B（步骤1602）、在所述薄膜晶体管阵列器件板101上制备显示器件板102，其中，所述显示器件板102与所述薄膜晶体管阵列器件板101叠加组合为一体，所述显示器件板102包括至少一所述像素单元和至少一所述辅助供电单元。
所述步骤A（步骤1601）包括：
步骤a1（步骤16011）、在基板1011上依次设置遮光构件1012和缓冲层1013。具体地，在基板1011上沉积遮光金属层，并通过第一光罩制程和第一蚀刻制程使得所述遮光金属层图案化，从而形成所述遮光构件1012，然后在所述基板1011和所述遮光构件1012上沉积所述缓冲层1013。
步骤a2（步骤16012）、在所述缓冲层1013上设置半导体构件1014。具体地，在所述缓冲层1013上沉积半导体层，并通过第二光罩制程和第二蚀刻制程对所述半导体层图案化，从而形成所述半导体构件1014。
步骤a3（步骤16013）、在所述半导体构件1014上设置第一绝缘层1015。
步骤a4（步骤16014）、在所述第一绝缘层1015上设置栅极1016。
步骤a5（步骤16015）、在所述缓冲层1013上设置第二绝缘层1017，其中，所述第二绝缘层1017覆盖所述半导体构件1014、所述第一绝缘层1015和所述栅极1016。
步骤a6（步骤16016）、在所述第二绝缘层1017上形成第四通孔801和第五通孔802。具体地，对所述第二绝缘层1017实施第四光罩制程，以形成所述第四通孔801和所述第五通孔802。
步骤a7（步骤16017）、在所述第二绝缘层1017上设置源极1018、所述漏极1019。具体地，在所述第二绝缘层1017上设置第二金属层，对所述第二金属层实施第五光罩制程和第五蚀刻制程，以形成所述源极1018和所述漏极1019。
进一步地，通过所述第五光罩制程和所述第五蚀刻制程在所述第二金属层中同时形成所述源极1018、所述漏极1019和所述输电线1021。
上述步骤a3（步骤16013）和a4（步骤16014）具体包括：在所述半导体构件1014上依次沉积第一绝缘材料层和第一金属层，并在所述第一金属层上设置光阻（PR，Photo Resist）块601，对所述第一绝缘材料层和所述第一金属层实施第三光罩制程，以使所述第一绝缘材料层和所述第一金属层图案化，对图案化后的所述第一金属层实施第三蚀刻制程，以形成所述栅极1016，然后利用栅极1016自对准，蚀刻所述第一绝缘材料层，使得所述半导体构件1014的两端边缘部裸露。
进一步地，在所述步骤a4（步骤16014）之后，以及在所述步骤a5（步骤16015）之前，所述步骤A（步骤1601）还包括：
步骤a8、在所述半导体构件1014的两端边缘部中植入N+离子。
所述步骤B（步骤1602）包括：
步骤b1（步骤16024）、形成所述辅助供电电极1023和所述阳极1024。具体地，在所述平坦化层1022上与所述第一通孔1001和所述第二通孔1002对应的位置处设置第三金属层，并对所述第三金属层进行第七光罩制程和第七蚀刻制程，以形成所述辅助供电电极1023和所述阳极1024。
步骤b2（步骤16025）、形成具有第一凹陷部10251和第二凹陷部10252的像素定义层1025，其中，所述第一凹陷部10251和所述第二凹陷部10252均贯穿所述像素定义层1025，所述第一凹陷部10251所在的位置与所述辅助供电电极1023所在的位置对应，所述第二凹陷部10252所在的位置与所述阳极1024所在的位置对应。具体地，在所述平坦化层1022上设置所述像素定义层1025所对应的材料层，并对所述材料层实施第八光罩制程和第八蚀刻制程，以形成贯穿所述材料层的所述第一凹陷部10251和所述第二凹陷部10252。
步骤b3（步骤16026）、在所述像素定义层1025上设置所述有机发光器件1026，其中，所述有机发光器件1026的至少一部分设置于所述第二凹陷部10252上，所述有机发光器件1026位于所述第二凹陷部10252上的部分与所述阳极1024接触。具体地，在所述像素定义层1025上整面蒸镀OLED材料，以形成所述有机发光器件1026。
步骤b4（步骤16027）、在所述第一凹陷部10251处和所述有机发光器件1026上设置所述阴极层1027，其中，所述阴极层1027包括所述第一阴极10271和所述第二阴极10272，所述第一阴极10271设置于所述第一凹陷部10251处，并且所述第一阴极10271与所述辅助供电电极1023连接，所述第二阴极10272设置于第二凹陷部10252处，并且所述第二阴极10272与所述阳极1024连接。
进一步地，在步骤b3（步骤16026）之后，以及在步骤b4（步骤16027）之前，所述步骤B（步骤1602）还包括：
b7、利用激光束去除所述有机发光器件1026与所述第一凹陷部10251对应的部分，以在所述有机发光器件1026与所述第一凹陷部10251对应的位置处形成第三通孔，其中，所述辅助供电电极1023露出于所述第一凹陷部10251和所述第三通孔。其中，所述激光束的横截面的直径小于所述第三通孔的直径。具体地，在氮气环境或真空环境中利用激光束去除所述有机发光器件1026与所述第一凹陷部10251对应的部分。
所述步骤b4（步骤16027）为：
在露出于所述第一凹陷部10251和所述第三通孔的所述辅助供电电极1023上以及所述有机发光器件1026上设置所述阴极层1027。
在所述步骤b1（步骤16024）之前，所述步骤B（步骤1602）还包括：
步骤b5（步骤16022）、形成平坦化层1022。
步骤b6（步骤16023）、在所述平坦化层1022上设置第一通孔1001和第二通孔1002。具体地，对所述平坦化层1022实施第六光罩制程和第七蚀刻制程，以形成所述第一通孔1001和所述第二通孔1002。
所述步骤b1（步骤16024）包括：
步骤b11、在所述平坦化层1022上和所述第一通孔1001中形成所述辅助供电电极1023，其中，所述辅助供电电极1023的至少一部分设置于所述平坦化层1022上，所述辅助供电电极1023的另一部分通过所述第一通孔1001与所述输电线1021连接。
步骤b12、在所述平坦化层1022上和所述第二通孔1002中形成所述阳极1024，其中，所述阳极1024的至少一部分设置于所述平坦化层1022上，所述阳极1024的另一部分通过所述第二通孔1002与所述漏极1019连接。
所述步骤b2（步骤16025）为：
在所述平坦化层1022上形成所述像素定义层1025。
在所述步骤b5（步骤16022）之前，所述步骤B（步骤1602）还包括：
步骤b8（步骤16021）、形成所述输电线1021。
本发明的显示面板的制造方法的技术方案为：
(1)清洗基板（玻璃基板）1011，并在基板1011上沉积一层厚度处于500埃至2000埃的范围内的金属作为TFT遮光层（遮光金属层），所述金属可以是Mo、Al、Cu、Ti等，或者是合金，并利用黄光针对该金属做出图形，以形成所述遮光构件1012。
(2)在所述基板1011和所述遮光构件1012上沉积一层氧化硅（SiOx）薄膜，作为缓冲层（Buffer）1013，该缓冲层1013的厚度处于1000埃至5000埃的范围内。
(3)在所述缓冲层1013上沉积一层金属氧化物半导体材料（Oxide）作为半导体层，该金属氧化物半导体材料可以是IGZO、IZTO、IGZTO等，该半导体层的厚度处于100埃至1000埃的范围内，并利用黄光针对该半导体层做出图形，以形成所述半导体构件1014。
(4)在所述缓冲层1013和所述半导体构件1014上沉积一层氧化硅（SiOx）薄膜，作为栅极绝缘层（第一绝缘层1015），所述栅极绝缘层的厚度处于1000埃至3000埃的范围内。
(5)在所述栅极绝缘层上沉积一层金属作为栅极金属层（第一金属层），所述栅极金属层可以是Mo、Al、Cu、Cu，或者是合金，所述栅极金属层的厚度处于2000埃至8000埃的范围内。
(6)利用一道黄光对所述栅极金属层进行图案化，先针对图案化后的所述栅极金属层蚀刻出栅极金属的图形，再利用栅极金属图形为自对准，蚀刻所述栅极绝缘层，使得栅极绝缘层仅存在于栅极金属图形的膜层下方，其余地方的栅极绝缘层均被蚀刻掉。
(7)对所述半导体构件1014进行的离子（Plasma）植入处理，使上方没有所述栅极绝缘层（所述第一绝缘层1015）和所述栅极金属（所述栅极）保护的金属氧化物半导体材料（Oxide）的电阻明显降低，形成N+导体层，用于与薄膜晶体管的源极1018和漏极1019接触，所述栅极绝缘层下方的金属氧化物半导体材料没有被处理到，保持半导体特性，作为薄膜晶体管（TFT）的电子迁移沟道（Channel）。
(8)在所述缓冲层1013、所述半导体构件1014、所述栅极1016上沉积层间绝缘层（ILD），即，第二绝缘层1017，所述第二绝缘层1017的材料可以是氧化硅（SiOx）、氮化硅（SiNx）或夹层结构，所述第二绝缘层1017的厚度处于3000埃至10000埃的范围内，在所述第二绝缘层1017上做出所述源极1018、所述漏极1019的接触区开孔（所述第四通孔801和所述第五通孔802）。
(9)在所述第二绝缘层1017上沉积一层金属作为源极1018/漏极1019金属层（第二金属层），源极1018/漏极1019金属层的材料可以是Mo、Al、Cu、Cu，或者是合金，源极1018/漏极1019金属层的厚度处于2000埃至8000埃的范围内，然后针对源极1018/漏极1019金属层定义出图形，以形成所述源极1018、所述漏极1019，并同时形成所述输电线1021。
(10)  在所述第二绝缘层1017以及所述源极1018、所述漏极1019和所述输电线1021上上沉积作为第一平坦化层（钝化层）的SiOx薄膜，该钝化层的厚度处于1000埃至5000埃的范围内，并针对该钝化层蚀刻出过孔（所述第一通孔1001和所述第二通孔1002）。
(11)  在所述钝化层上制作第二平坦化层，第二平坦化层可以是不同成分的光阻层，第二平坦化层的厚度处于10000埃至20000埃的范围内，通过黄光针对第二平坦化层做出过孔（所述第一通孔1001和所述第二通孔1002）。
(12)  在包括第一平坦化层和第二平坦化层的所述平坦化层1022上沉积ITO等透明氧化物或ITO/Ag/ITO的夹层结构，ITO等透明氧化物或ITO/Ag/ITO的夹层结构的厚度处于500埃至2000埃的范围内，并利用黄光做出图形，以形成阳极1024和所述辅助供电电极1023。
(13)  在所述平坦化层1022和所述阳极1024、所述辅助供电电极1023上制作像素定义层1025（PDL层），所述像素定义层1025可以包括不同成分的光阻层，所述像素定义层1025的厚度在10000埃至20000埃的范围内，通过黄光针对该像素定义层1025定义发光区，完成背板制作。
(14)  通过蒸镀的方式在像素定义层1025的整面上制作发光层，并在氮气（N2）环境或真空环境下利用激光束（Laser）照射的方式把所述发光层位于所述辅助供电电极1023处的部分去除，以确保阴极可以和辅助电极搭接。激光束的横截面（激光照射点）的直径需要小于所述像素电极层在所述辅助供电电极1023处的开孔，以确保不会损伤和污染到正常发光区的发光层材料。
(15)  在所述辅助供电电极1023和所述发光层上再制作阴极金属，阴极在制定设计位置与辅助电极搭接，即完成OLED面板的制作。
上述技术方案能有效改善大尺寸的显示面板10所存在的IR drop问题。即，由于本发明在显示面板10的每一个子显示区A中均设置辅助供电电极1023，因此，辅助供电电极1023分布均匀，并且，多个辅助供电电极1023共同向包括多个子显示区A的显示面板中的阴极层1027供电，因此可以有效降低大尺寸的显示面板10中的IR Drop现象，从而有利于提高显示面板10的显示质量。
此外，在本发明的显示面板的制造方法中，由于采用激光束照射的方式处理位于辅助供电电极1023处OLED材料，以使阴极与辅助供电电极1023的搭接，避免引入Pillar等黄光制程，制程简洁。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，所述显示面板的显示区划分有至少两个子显示区，所述显示面板与所述子显示区对应的部分设置有至少一像素单元和至少一辅助供电单元，所述像素单元用于显示图像，所述辅助供电单元用于向所述显示面板的阴极层供电，以使所述阴极层在每一所述子显示区中所施加的电压相等或大致相等；
    其中，所述阴极层包括位于与所述辅助供电单元对应的位置的第一阴极和位于与所述像素单元对应的位置的第二阴极，所述第一阴极与所述第二阴极连接；
    所述辅助供电单元包括输电线和辅助供电电极，所述辅助供电电极连接所述输电线和所述第一阴极；
    所述像素单元包括薄膜晶体管、阳极、有机发光器件和所述第二阴极，所述有机发光器件设置于所述阳极和所述第二阴极之间，所述阳极与所述薄膜晶体管的漏极连接；
    所述显示面板还包括像素定义层；
    所述像素定义层上设置有第一凹陷部和第二凹陷部，所述第一凹陷部和所述第二凹陷部均贯穿所述像素定义层，所述第一凹陷部所在的位置与所述辅助供电电极所在的位置对应，所述第二凹陷部所在的位置与所述阳极所在的位置对应；
    所述有机发光器件的至少一部分设置于所述第二凹陷部上，所述有机发光器件位于所述第二凹陷部上的部分与所述阳极接触；
    所述第一阴极的至少一部分设置于所述第一凹陷部上，所述第一阴极位于所述第一凹陷部上的部分与所述辅助供电电极相连接，所述第二阴极的至少一部分设置于所述第二凹陷部上，所述第二阴极位于所述第二凹陷部上的部分设置于所述有机发光器件上；
    所述显示面板还包括平坦化层；
    所述平坦化层上设置有第一通孔和第二通孔；
    所述辅助供电电极的至少一部分设置于所述平坦化层上，所述辅助供电电极的另一部分通过所述第一通孔与所述输电线连接；
    所述阳极的至少一部分设置于所述平坦化层上，所述阳极的另一部分通过所述第二通孔与所述漏极连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板包括薄膜晶体管阵列器件板和显示器件板，所述显示器件板与所述薄膜晶体管阵列器件板叠加组合为一体；
    所述输电线设置于所述薄膜晶体管阵列器件板上；
    所述平坦化层设置于所述薄膜晶体管阵列器件板上，并且所述平坦化层覆盖所述输电线；
    所述像素定义层设置于所述平坦化层上。
  3. 根据权利要求2所述的显示面板，其中，所述薄膜晶体管阵列器件板还包括基板、遮光构件、缓冲层、所述薄膜晶体管、第一绝缘层、第二绝缘层、扫描线和数据线，所述薄膜晶体管包括栅极、半导体构件、源极和所述漏极，其中，所述第一绝缘层设置于所述栅极和所述半导体构件之间，所述数据线、所述源极的至少一部分和所述漏极的至少一部分设置于所述第二绝缘层上。
  4. 根据权利要求1所述的显示面板，其中，所述辅助供电单元均匀分布于所述显示面板的所述显示区中。
  5. 一种显示面板，其中，所述显示面板的显示区划分有至少两个子显示区，所述显示面板与所述子显示区对应的部分设置有至少一像素单元和至少一辅助供电单元，所述像素单元用于显示图像，所述辅助供电单元用于向所述显示面板的阴极层供电，以使所述阴极层在每一所述子显示区中所施加的电压相等或大致相等；
    其中，所述阴极层包括位于与所述辅助供电单元对应的位置的第一阴极和位于与所述像素单元对应的位置的第二阴极，所述第一阴极与所述第二阴极连接；
    所述辅助供电单元包括输电线和辅助供电电极，所述辅助供电电极连接所述输电线和所述第一阴极；
    所述像素单元包括薄膜晶体管、阳极、有机发光器件和所述第二阴极，所述有机发光器件设置于所述阳极和所述第二阴极之间，所述阳极与所述薄膜晶体管的漏极连接。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板还包括像素定义层；
    所述像素定义层上设置有第一凹陷部和第二凹陷部，所述第一凹陷部和所述第二凹陷部均贯穿所述像素定义层，所述第一凹陷部所在的位置与所述辅助供电电极所在的位置对应，所述第二凹陷部所在的位置与所述阳极所在的位置对应；
    所述有机发光器件的至少一部分设置于所述第二凹陷部上，所述有机发光器件位于所述第二凹陷部上的部分与所述阳极接触；
    所述第一阴极的至少一部分设置于所述第一凹陷部上，所述第一阴极位于所述第一凹陷部上的部分与所述辅助供电电极相连接，所述第二阴极的至少一部分设置于所述第二凹陷部上，所述第二阴极位于所述第二凹陷部上的部分设置于所述有机发光器件上。
  7. 根据权利要求5所述的显示面板，其中，所述显示面板还包括平坦化层；
    所述平坦化层上设置有第一通孔和第二通孔；
    所述辅助供电电极的至少一部分设置于所述平坦化层上，所述辅助供电电极的另一部分通过所述第一通孔与所述输电线连接；
    所述阳极的至少一部分设置于所述平坦化层上，所述阳极的另一部分通过所述第二通孔与所述漏极连接。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板包括薄膜晶体管阵列器件板和显示器件板，所述显示器件板与所述薄膜晶体管阵列器件板叠加组合为一体；
    所述输电线设置于所述薄膜晶体管阵列器件板上；
    所述平坦化层设置于所述薄膜晶体管阵列器件板上，并且所述平坦化层覆盖所述输电线；
    所述像素定义层设置于所述平坦化层上。
  9. 根据权利要求8所述的显示面板，其中，所述薄膜晶体管阵列器件板还包括基板、遮光构件、缓冲层、所述薄膜晶体管、第一绝缘层、第二绝缘层、扫描线和数据线，所述薄膜晶体管包括栅极、半导体构件、源极和所述漏极，其中，所述第一绝缘层设置于所述栅极和所述半导体构件之间，所述数据线、所述源极的至少一部分和所述漏极的至少一部分设置于所述第二绝缘层上。
  10. 根据权利要求5所述的显示面板，其中，所述辅助供电单元均匀分布于所述显示面板的所述显示区中。
  11. 根据权利要求5所述的显示面板，其中，任意两个在第一方向上或第二方向上相邻的所述辅助供电单元之间的距离相等或大致相等，其中，所述第一方向为所述显示面板的长边所对应的方向，所述第二方向为所述显示面板的短边所对应的方向。
  12. 根据权利要求5所述的显示面板，其中，至少两所述辅助供电单元用于共同向所述显示面板的阴极层供电。
  13. 根据权利要求5所述的显示面板，其中，所述第二阴极用于通过所述第一阴极从所述辅助供电单元接收电源，并与所述阳极共同向所述有机发光器件施加电压，从而使得所述有机发光器件发光。
  14. 一种如权利要求5所述的显示面板的制造方法，其中，所述方法包括以下步骤：
    步骤A、制备薄膜晶体管阵列器件板；
    步骤B、在所述薄膜晶体管阵列器件板上制备显示器件板，其中，所述显示器件板与所述薄膜晶体管阵列器件板叠加组合为一体，所述显示器件板包括至少一所述像素单元和至少一所述辅助供电单元。
  15. 根据权利要求14所述的显示面板的制造方法，其中，所述步骤B包括：
    步骤b1、形成辅助供电电极和所述阳极；
    步骤b2、形成具有第一凹陷部和第二凹陷部的像素定义层，其中，所述第一凹陷部和所述第二凹陷部均贯穿所述像素定义层，所述第一凹陷部所在的位置与所述辅助供电电极所在的位置对应，所述第二凹陷部所在的位置与所述阳极所在的位置对应；
    步骤b3、在所述像素定义层上设置所述有机发光器件，其中，所述有机发光器件的至少一部分设置于所述第二凹陷部上，所述有机发光器件位于所述第二凹陷部上的部分与所述阳极接触；
    步骤b4、在所述第一凹陷部处和所述有机发光器件上设置所述阴极层，其中，所述阴极层包括所述第一阴极和所述第二阴极，所述第一阴极设置于所述第一凹陷部处，并且所述第一阴极与所述辅助供电电极连接，所述第二阴极设置于第二凹陷部处，并且所述第二阴极与所述阳极连接。
  16. 根据权利要求15所述的显示面板的制造方法，其中，在所述步骤b1之前，所述步骤B还包括：
    步骤b5、形成平坦化层；
    步骤b6、在所述平坦化层上设置有第一通孔和第二通孔；
    所述步骤b1包括：
    步骤b11、在所述平坦化层上和所述第一通孔中形成所述辅助供电电极，其中，所述辅助供电电极的至少一部分设置于所述平坦化层上，所述辅助供电电极的另一部分通过所述第一通孔与所述输电线连接；
    步骤b12、在所述平坦化层上和所述第二通孔中形成所述阳极，其中，所述阳极的至少一部分设置于所述平坦化层上，所述阳极的另一部分通过所述第二通孔与所述漏极连接；
    所述步骤b2为：
    在所述平坦化层上形成所述像素定义层。
  17. 根据权利要求16所述的显示面板的制造方法，其中，在步骤b3之后，以及在步骤b4之前，所述步骤B还包括：
    b7、利用激光束去除所述有机发光器件与所述第一凹陷部对应的部分，以在所述有机发光器件与所述第一凹陷部对应的位置处形成第三通孔，其中，所述辅助供电电极露出于所述第一凹陷部和所述第三通孔。
  18. 根据权利要求16所述的显示面板的制造方法，其中，在所述步骤b5之前，所述步骤B还包括：
    步骤b8、形成所述输电线。
  19. 根据权利要求16所述的显示面板的制造方法，其中，所述步骤A包括:
    步骤a1、在基板上依次设置遮光构件和缓冲层；
    步骤a2、在所述缓冲层上设置半导体构件；
    步骤a3、在所述半导体构件上设置第一绝缘层；
    步骤a4、在所述第一绝缘层上设置栅极；
    步骤a5、在所述缓冲层上设置第二绝缘层，其中，所述第二绝缘层覆盖所述半导体构件、所述第一绝缘层和所述栅极；
    步骤a6、在所述第二绝缘层上形成第四通孔和第五通孔；
    步骤a7、在所述第二绝缘层上设置源极、所述漏极。
  20. 根据权利要求19所述的显示面板的制造方法，其中，在所述步骤a4之后，以及在所述步骤a5之前，所述步骤A还包括：
    步骤a8、在所述半导体构件的两端边缘部中植入N+离子。
PCT/CN2018/084054 2018-03-07 2018-04-23 显示面板及其制造方法 Ceased WO2019169705A1 (zh)

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