WO2019169567A1 - 一种低压高速可编程均衡电路 - Google Patents

一种低压高速可编程均衡电路 Download PDF

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Publication number
WO2019169567A1
WO2019169567A1 PCT/CN2018/078204 CN2018078204W WO2019169567A1 WO 2019169567 A1 WO2019169567 A1 WO 2019169567A1 CN 2018078204 W CN2018078204 W CN 2018078204W WO 2019169567 A1 WO2019169567 A1 WO 2019169567A1
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WIPO (PCT)
Prior art keywords
resistor
amplifier stage
transistor
gain boosting
input
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PCT/CN2018/078204
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English (en)
French (fr)
Inventor
李发明
林永辉
洪明
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厦门优迅高速芯片有限公司
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Application filed by 厦门优迅高速芯片有限公司 filed Critical 厦门优迅高速芯片有限公司
Priority to PCT/CN2018/078204 priority Critical patent/WO2019169567A1/zh
Priority to US16/969,987 priority patent/US20200412316A1/en
Publication of WO2019169567A1 publication Critical patent/WO2019169567A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G5/00—Tone control or bandwidth control in amplifiers
    • H03G5/16—Automatic control
    • H03G5/165—Equalizers; Volume or gain control in limited frequency bands
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45098—PI types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G5/00—Tone control or bandwidth control in amplifiers
    • H03G5/16—Automatic control
    • H03G5/24—Automatic control in frequency-selective amplifiers
    • H03G5/28—Automatic control in frequency-selective amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45488—Indexing scheme relating to differential amplifiers the CSC being a pi circuit and a capacitor being used at the place of the resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45652—Indexing scheme relating to differential amplifiers the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G2201/00—Indexing scheme relating to subclass H03G
    • H03G2201/10—Gain control characterised by the type of controlled element

Definitions

  • the present invention relates to the field of electronic circuit technologies, and in particular, to a low voltage high speed programmable equalization circuit.
  • High-speed signal technology has many problems compared to general digital signals.
  • a key issue is the frequency-dependent transmission loss in all transmission media. It is mainly caused by skin effect and dielectric loss. The higher the frequency, the more obvious the skin effect and dielectric loss, and the greater the transmission loss.
  • This transmission loss causes the attenuation of the high-frequency component of the signal to be attenuated more than the low-frequency component, so that the signal ISI (inter-code interference) received by the receiver is severe, resulting in difficulty in clock data recovery and high BER (bit error rate).
  • the data transmission frequency and transmission distance are largely limited.
  • the equalization circuit is a method that can solve the problem of attenuation caused by transmission line loss in high-speed data transmission. Its main function is to offset or reduce the influence of nonlinearity of the cable on the data transmission error rate, which can significantly reduce the inter-code interference of data transmission and reduce the bit error rate. Due to its important role in high-speed data transmission, the equalization circuit becomes a key part of high-speed data transmission transceivers.
  • the equalization circuit is implemented by a high-speed differential amplifier with source-negative feedback.
  • the feedback consists of a fixed resistor and a capacitor.
  • the resistor is equivalent to an all-pass path
  • the capacitor is equivalent to a high-pass path.
  • This feedback consists of a source-negative feedback differential amplifier consisting of a resistor and a capacitor, which is equivalent to a split-path amplifier, an equivalent high-pass filter.
  • the current equalization circuit has the following problems: the negative feedback resistance and the capacitance of the equalization circuit are fixed. Once the equalization circuit is designed, since the capacitance value and the resistance value are fixed, the zero point and the pole of the transfer function are also fixed. The high frequency gain and low frequency gain are fixed. In this case, if the length of the cable changes, causing the high-frequency attenuation of the signal to change, the equalization circuit cannot be adjusted to compensate for the attenuation caused by cables of different lengths. If the compensation is not sufficient, the signal can not be recovered well, affecting the signal quality; if the compensation is excessive, the signal will be deformed and the signal quality will be affected.
  • the object of the present invention is to provide a low-voltage high-speed programmable equalization circuit, which can select an appropriate equalization compensation factor by setting a programmable equalization compensation factor to achieve adaptive adjustment.
  • a low-voltage high-speed programmable equalization circuit includes a gain boosting amplifier stage, a CML differential amplifier stage, and an emitter follower, wherein the input end of the gain boosting amplifier stage is an input terminal of the equalization circuit, and the output of the gain boosting amplifier stage The end is connected to the input end of the CML differential amplifier stage; the output end of the CML differential amplifier stage is connected to the input end of the emitter follower; and the output end of the emitter follower is the output end of the equalization circuit;
  • the gain boosting amplifier stage includes an input common mode voltage biasing unit, an input impedance matching unit, a purely resistive network path unit, a resistor-capacitor network high-pass path unit, a first differential amplifying circuit and a second differential amplifying circuit, and an input common mode voltage offset
  • the set unit is configured to set a bias voltage of the gain amplifier stage, and the input impedance matching unit is configured to match the input impedance of the gain amplifier stage with the impedance of the input module board connected to the chip;
  • the input end of the gain boosting amplifier stage is connected to the pure resistor network path unit,
  • the pure resistor network path unit is connected to the first differential amplifying circuit, and the first differential amplifying circuit is connected to the output end of the gain boosting amplifier stage;
  • the input end of the gain boosting amplifier stage is connected to the resistor-capacitor network high-pass path unit, and the resistor-capacitor network high-pass path unit is connected.
  • a second differential amplifying circuit
  • a variable current source is disposed in each of the first differential amplifying circuit and the second differential amplifying circuit, and the sum of the currents of the two variable current sources is kept constant.
  • the input common mode voltage biasing unit comprises a resistor R5 and a resistor R6, a resistor R5 and a resistor R6 are connected in series, one end of the resistor R5 is connected to the constant voltage power supply VDD, and one end of the resistor R6 is grounded;
  • the input impedance matching unit includes a resistor R3 and a resistor R4. One end of the resistor R3 is connected between the resistor R5 and the resistor R6, and the other end is connected to the input terminal INP of the gain boosting amplifier stage. One end of the resistor R4 is connected between the resistor R5 and the resistor R6. The other end is connected to the input terminal INN of the gain boosting amplifier stage;
  • the pure resistor network path unit includes a resistor R7, a resistor R8 and a resistor R9.
  • One end of the resistor R7 is connected to the input terminal INP of the gain boosting amplifier stage, and the other end is connected to one end of the resistor R9.
  • One end of the resistor R8 is connected to the input terminal INN of the gain boosting amplifier stage. The other end is connected to the other end of the resistor R9;
  • the first differential amplifying circuit comprises a transistor Q2, a transistor Q3, a resistor R13, a resistor R14 and a variable current source I2.
  • the base of the transistor Q2 is connected between the resistor R7 and the resistor R8, and the emitter passes through the variable current source I2.
  • Grounding, the collector is connected to the power supply VDD via the resistor R13, and the collector is also connected to the output terminal OUTN0 of the gain boosting amplifier stage;
  • the base of the transistor Q3 is connected between the resistor R8 and the resistor R9, and the emitter is connected via the variable current source I2.
  • Grounding, the collector is connected to the power supply VDD via the resistor R14, and the collector is also connected to the output terminal OUTP0 of the gain boosting amplifier stage;
  • the resistor-capacitor network high-pass path unit comprises a resistor R10, a resistor R11, a resistor R12, a capacitor C1 and a capacitor C2, and the resistor R10 and the capacitor C1 are connected in parallel, one end of which is connected to the input terminal INP of the gain boosting amplifier stage, and the other end of the resistor R12 is connected;
  • the resistor R11 and the capacitor C2 are connected in parallel, one end of which is connected to the input terminal INN of the gain boosting amplifier stage, and the other end is connected to the other end of the resistor R12;
  • the second differential amplifying circuit comprises a triode Q4, a triode Q5, a resistor R13, a resistor R14 and a variable current source I3.
  • the base connection resistor R12 of the transistor Q4 is connected to the resistor R10, one end of the capacitor C1, and the emitter is via a variable current source. After I3 is grounded, the collector is connected to the power supply VDD via the resistor R13.
  • the collector is also connected to the output terminal OUTN0 of the gain boosting amplifier stage; the base connection resistor R12 of the transistor Q5 is connected to the resistor R11 and one end of the capacitor C2, and the emitter is via the variable After the current source I3 is grounded, the collector is connected to the power supply VDD via the resistor R14, and the collector is also connected to the output terminal OUTP0 of the gain boosting amplifier stage.
  • the CML differential amplifier stage comprises a transistor Q6, a transistor Q7, a resistor R15, a resistor R16 and a current source I4.
  • the base of the transistor Q6 is connected to the input terminal INP1 of the CML differential amplifier stage, and the input terminal INP1 is connected to the output of the gain boosting amplifier stage.
  • the terminal INN1 is connected to the output terminal OUTN0 of the gain boosting amplifier stage, the emitter of the transistor Q7 is grounded via the current source I4, the collector is connected to the power source VDD via the resistor R16, and the collector is also connected to the output of the CML differential amplifier stage. End OUTP1.
  • the emitter follower comprises a transistor Q8, a transistor Q9, a current source I5, a current source I6, a base of the transistor Q8 is connected to an input terminal INP2 of the emitter follower, and the input terminal INP2 is connected to an output terminal OUTP1 of the CML differential amplification stage.
  • the collector of the transistor Q8 is connected to the power supply VDD, the emitter is grounded via the current source I5, and the emitter is also connected to the output terminal OUTP of the emitter follower; the base of the transistor Q9 is connected to the input terminal INN2 of the emitter follower, and The input terminal INN2 is connected to the output terminal OUTN1 of the differential amplifier stage; the collector of the transistor Q9 is connected to the power supply VDD, the emitter is grounded via the current source I5, and the emitter is also connected to the output terminal OUTN of the emitter follower.
  • the present invention uses the gain boosting amplifier stage to pass the input signal all the way through the pure resistance network all-pass path, and the other way through the resistor-capacitor network high-pass path, thereby achieving high-pass filtering and minimizing effective high-speed signal loss;
  • the two variable current sources of the first differential amplifying circuit and the second differential amplifying circuit in the gain boosting amplifier stage realize the equalization compensation size programmable, and adjust the ratio of the two variable current sources according to different cable lengths of different application scenarios, thereby realizing appropriate Balanced compensation to meet a variety of application needs; and will not affect the load capacity of high-speed signals.
  • the invention uses the CML differential amplification stage after the gain boosting amplifier stage, which can better suppress the power supply noise, make the high-speed transmission signal have better linearity, and provide a certain gain and bandwidth to ensure the high-speed signal normal transmission.
  • the invention adopts a transmitter-level follower as an output stage, on the one hand, realizes high-speed signal common-mode level shift, and on the other hand, improves the load capacity of high-speed signals.
  • the present invention uses a 1.8V power supply to reduce circuit power consumption, and circuit performance is small with process variation.
  • 1 is a circuit diagram of a prior art equalization circuit
  • FIG. 3 is a circuit diagram of a high speed signal differential amplification stage of the present invention.
  • FIG. 4 is a circuit diagram of a second stage CML differential amplification stage of the present invention.
  • Figure 5 is a circuit diagram of an emitter follower of the present invention.
  • the invention discloses a low-voltage high-speed programmable equalization circuit, which is mainly applied to a high-speed SFP+, XFP optical transceiver module.
  • the equalization circuit of the present invention uses a 1.8V low-voltage external power supply to reduce power. Power consumption, the circuit is based on a 0.18um SiGeBiCMOS process platform design.
  • Gainboost is a gain boosting amplification stage 1
  • CMLamp is a CML differential amplification stage 2
  • Emitterfollow is an emitter follower 3. As shown in FIG.
  • the low-voltage high-speed programmable equalization circuit of the present invention comprises a gain boosting amplifier stage 1, a CML differential amplifier stage 2, and an emitter follower 3, wherein the input end of the gain boosting amplifier stage 1 is an equalization circuit input end, and the gain
  • the output of the boosting amplifier stage 1 is connected to the input of the CML differential amplifier stage 2; the output of the CML differential amplifier stage 2 is connected to the input of the emitter follower 3; and the output of the emitter follower 3 is the output of the equalization circuit .
  • the gain boosting amplifier stage 1 includes an input common mode voltage biasing unit 11, an input impedance matching unit 12, a purely resistive network path unit 13, a resistor-capacitor network high-pass path unit 14, and a first differential amplifying circuit 15.
  • the second differential amplifying circuit 16 the input common mode voltage biasing unit 11 is configured to set the bias voltage of the gain boosting amplifier stage 1
  • the input impedance matching unit 12 is configured to match the input impedance of the gain boosting amplifier stage 1 and the input of the connection chip.
  • the impedance of the module board; the input of the gain boosting amplifier stage 1 is connected to the pure resistor network path unit 13, and the pure resistor network path unit 13 is connected to the first differential amplifying circuit 15, and the first differential amplifying circuit 15 is connected to the output of the gain boosting amplifier stage 1.
  • the input end of the gain boosting amplifier stage 1 is connected to the resistor-capacitor network high-pass path unit 14, the resistor-capacitor network high-pass path unit 14 is connected to the second differential amplifier circuit 16, and the second differential amplifier circuit 16 is connected to the output terminal of the gain boosting amplifier stage 1.
  • the input common mode voltage biasing unit 11 is composed of a resistor R5 and a resistor R6.
  • the resistor R5 and the resistor R6 are connected in series.
  • One end of the resistor R5 is connected to the constant voltage power supply VDD, and one end of the resistor R6 is grounded.
  • the input impedance matching unit 12 includes a resistor R3 and a resistor R4.
  • One end of the resistor R3 is connected between the resistor R5 and the resistor R6, and the other end is connected to the input terminal INP of the gain boosting amplifier stage 1.
  • One end of the resistor R4 is connected between the resistor R5 and the resistor R6.
  • the other end is connected to the input terminal INN of the gain boosting amplifier stage 1.
  • the resistor R3 and the resistor R4 are respectively 50 ⁇ , and constitute an input impedance of 100 ⁇ , which has the same impedance as the input module board connected to the chip, so that the input impedance matching effect is the best.
  • the pure resistor network path unit 13 includes a resistor R7, a resistor R8 and a resistor R9.
  • One end of the resistor R7 is connected to the input terminal INP of the gain boosting amplifier stage 1, and the other end is connected to one end of the resistor R9.
  • One end of the resistor R8 is connected to the input end of the gain boosting amplifier stage 1. INN, the other end is connected to the other end of the resistor R9.
  • the first differential amplifying circuit 15 comprises a transistor Q2, a transistor Q3, a resistor R13, a resistor R14 and a variable current source I2.
  • the base of the transistor Q2 is connected between the resistor R7 and the resistor R8, and the emitter is grounded via the variable current source I2.
  • the collector is connected to the power supply VDD via the resistor R13. At the same time, the collector is also connected to the output terminal OUTN0 of the gain boosting amplifier stage 1; the base of the transistor Q3 is connected between the resistor R8 and the resistor R9, and the emitter is connected via the variable current source I2. Grounding, the collector is connected to the power supply VDD via the resistor R14, and the collector is also connected to the output terminal OUTP0 of the gain boosting amplifier stage 1.
  • the resistor-capacitor network high-pass path unit 14 includes a resistor R10, a resistor R11, a resistor R12, a capacitor C1 and a capacitor C2.
  • the resistor R10 and the capacitor C1 are connected in parallel, one end of which is connected to the input terminal INP of the gain boosting amplifier stage 1 and the other end of the resistor R12.
  • the resistor R11 and the capacitor C2 are connected in parallel, one end of which is connected to the input terminal INN of the gain boosting amplifier stage 1, and the other end is connected to the other end of the resistor R12.
  • the second differential amplifying circuit 16 includes a triode Q4, a triode Q5, a resistor R13, a resistor R14, and a variable current source I3.
  • the base connection resistor R12 of the transistor Q4 is connected to the resistor R10, one end of the capacitor C1, and the emitter is via a variable current source I3.
  • the collector is connected to the power supply VDD via the resistor R13.
  • the collector is also connected to the output terminal OUTN0 of the gain boosting amplifier stage 1;
  • the base connection resistor R12 of the transistor Q5 is connected to the resistor R11 and one end of the capacitor C2, and the emitter is variable.
  • the collector is connected to the power supply VDD via the resistor R14, and the collector is also connected to the output terminal OUTP0 of the gain boosting amplifier stage 1.
  • the CML differential amplifier stage 2 includes a triode Q6, a triode Q7, a resistor R15, a resistor R16, and a current source I4.
  • the base of the transistor Q6 is connected to the input terminal INP1 of the CML differential amplifier stage 2, and the input terminal INP1 is connected.
  • the output of the transistor 1 is connected to the output terminal OUTN0 of the CML differential amplifier stage 2;
  • the pole is connected to the input terminal INN1 of the CML differential amplifier stage 2, and the input terminal INN1 is connected to the output terminal OUTN0 of the gain boosting amplifier stage 1.
  • the emitter of the transistor Q7 is grounded via the current source I4, and the collector is connected to the power source VDD via the resistor R16.
  • the collector is also connected to the output terminal OUTP1 of the CML differential amplifier stage 2.
  • the CML differential amplifier stage 2 combines two identical single-ended signal paths to process two differential phase signals, respectively. Compared to single-ended signal amplification stages, it has the following advantages: higher power supply noise rejection, greater output voltage swing, and higher linearity. Therefore, the use of CML differential amplifier stage 2, can better suppress power supply noise, make high-speed transmission signals have better linearity, and provide a certain gain and bandwidth to ensure the high-speed signal transmission.
  • the emitter follower 3 includes a transistor Q8, a transistor Q9, a current source I5, and a current source I6.
  • the base of the transistor Q8 is connected to the input terminal INP2 of the emitter follower 3, and the input terminal INP2 is connected to the CML differential.
  • the input terminal INN2 of the device 3 is connected to the output terminal OUTN1 of the CML differential amplifier stage 2; the collector of the transistor Q9 is connected to the power supply VDD, the emitter is grounded via the current source I5, and the emitter is also connected to the emitter follower.
  • the output of OUT 3 is OUTN.
  • the emitter follower 3 has a high input impedance, a low output impedance, and a voltage gain of approximately 1 to reduce the pre-stage source load as a post-stage input impedance. Since the DC output voltage follows the DC input voltage V BE , it is used for the unity gain level shift circuit.
  • the present invention combines the gain boosting amplifier stage 1, the CML differential amplifier stage 2, and the emitter follower 3.
  • the present invention passes the gain boosting amplifier stage 1 to make the input signal pass through the pure resistance network all-pass path, and the other pass through the resistor.
  • Capacitor network high-pass path to achieve high-pass filtering and minimize effective high-speed signal loss; and gain-enhanced two variable current sources of amplifier stage 1 to achieve equalization compensation size, to meet a variety of application requirements, and thus according to different applications Different cable lengths in the scene to achieve a suitable equalization compensation size.
  • adjusting the ratio of the two variable current sources does not affect the load capacity of the high speed signal.
  • the present invention employs the emitter-level follower 3 as an output stage, on the one hand, achieving high-speed signal common-mode level shifting, and on the other hand, improving the load-carrying capability of high-speed signals.
  • the invention uses a 1.8V power supply to reduce the power consumption of the circuit. Circuit performance is small with process variation.

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  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

一种低压高速可编程均衡电路，其包括增益提升放大级(1)、CML差分放大级(2)、发射极跟随器(3)，所述增益提升放大级(1)的输入端为均衡电路输入端，增益提升放大级(1)的输出端连接CML差分放大级(2)的输入端；所述CML差分放大级(2)的输出端连接发射极跟随器(3)的输入端；而发射极跟随器(3)的输出端为均衡电路的输出端。通过增益提升放大级(1)使输入信号一路通过纯电阻网络全通通路，另一路通过电阻电容网络高通通路，从而实现高通滤波，并使有效高速信号损耗降到最小；且增益提升放大级(1)中的两可变电流源实现均衡补偿大小可编程，根据不同应用场景不同电缆长度，调节两可变电流源的比例，从而实现合适的均衡补偿，满足多种应用需求。

Description

一种低压高速可编程均衡电路 技术领域
本发明涉及电子电路技术领域，具体涉及一种低压高速可编程均衡电路。
背景技术
高速信号技术相比一般的数字信号存在很多问题，一个关键的问题就是在所有的传输介质中都存在与频率相关的传输损耗。它主要是由趋肤效应和介质损耗引起的，频率越高，趋肤效应和介质损耗就越明显，导致的传输损耗就越大。这种传输损耗引起信号的高频分量的衰减比低频分量衰减大，使得接收机接收到的信号ISI（码间干扰）严重，从而导致难以进行时钟数据恢复和高的BER（误码率），在很大程度上限制了数据传输频率和传输距离。
均衡电路就是能解决高速数据传输中由于传输线损耗引起衰减问题的一种方法。其主要作用就是抵消或减小电缆的非线性对数据传输误码率的影响，它可以明显减小数据传输的码间干扰，减小误码率。由于其在高速数据传输中的重要作用，均衡电路成为高速数据传输收发机关键部分。
现有技术中，均衡电路用一个带源极负反馈的高速差分放大器实现，反馈由固定的电阻和电容组成，电阻相当于一条全通通路，电容相当于高通通路。这个反馈由电阻和电容组成的源极负反馈差分放大器就相当于分离路径放大器，等效高通滤波器。
但目前的均衡电路存在以下问题：均衡电路的负反馈电阻和电容是固定的，一旦均衡电路设计完成后，由于电容值和电阻值是固定的，其传输函数的零点和极点也被固定，其高频增益和低频增益就是固定的。在这种情况下，如果电缆长度发生变化，导致信号的高频衰减发生变化，这个均衡电路就不能随意调节来补偿各种不同长度电缆带来的衰减。如果补偿的不充分，信号不能得到很好的恢复，影响信号质量；如果补偿过度，则信号会变形，信号质量也会受到影响。
发明内容
本发明的目的在于提供一种低压高速可编程均衡电路，其通过设置可编程均衡补偿因子，可以选择合适的均衡补偿因子，达到自适应调节的目的。
为实现上述目的，本发明采用的技术方案是：
一种低压高速可编程均衡电路，所述均衡电路包括增益提升放大级、CML差分放大级、发射极跟随器，所述增益提升放大级的输入端为均衡电路输入端，增益提升放大级的输出端连接CML差分放大级的输入端；所述CML差分放大级的输出端连接发射极跟随器的输入端；而发射极跟随器的输出端为均衡电路的输出端；
所述增益提升放大级包括输入共模电压偏置单元、输入阻抗匹配单元、纯电阻网络通路单元、电阻电容网络高通通路单元、第一差分放大电路和第二差分放大电路，输入共模电压偏置单元用于设置增益放大级的偏置电压，输入阻抗匹配单元用于匹配增益放大级的输入阻抗与连接芯片的输入模块板的阻抗；增益提升放大级的输入端连接纯电阻网络通路单元，而纯电阻网络通路单元连接第一差分放大电路，第一差分放大电路连接增益提升放大级的输出端；增益提升放大级的输入端连接电阻电容网络高通通路单元，电阻电容网络高通通路单元连接第二差分放大电路，第二差分放大电路连接增益提升放大级的输出端；
所述第一差分放大电路和第二差分放大电路中均设有一可变电流源，两个可变电流源的电流总和保持恒定。
所述输入共模电压偏置单元包括电阻R5和电阻R6，电阻R5和电阻R6串联，电阻R5一端连接恒压电源VDD，电阻R6一端接地；
所述输入阻抗匹配单元包括电阻R3和电阻R4，电阻R3一端连接于电阻R5和电阻R6之间，另一端连接增益提升放大级的输入端INP；电阻R4一端连接于电阻R5和电阻R6之间，另一端连接增益提升放大级的输入端INN；
所述纯电阻网络通路单元包括电阻R7、电阻R8和电阻R9，电阻R7一端连接增益提升放大级的输入端INP，另一端连接电阻R9的一端；电阻R8一端连接增益提升放大级的输入端INN，另一端连接电阻R9的另一端；
所述第一差分放大电路包括三极管Q2、三极管Q3、电阻R13、电阻R14和可变电流源I2，三极管Q2的基极连接于电阻R7和电阻R8之间，发射极经可变电流源I2后接地，集电极经由电阻R13连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTN0；三极管Q3的基极连接于电阻R8和电阻R9之间，发射极经由可变电流源I2后接地，集电极经由电阻R14连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTP0；
所述电阻电容网络高通通路单元包括电阻R10、电阻R11、电阻R12、电容C1和电容C2，电阻R10和电容C1并联，其一端连接增益提升放大级的输入端INP，另一端电阻R12的一端；电阻R11和电容C2并联，其一端连接增益提升放大级的输入端INN，另一端连接电阻R12的另一端；
所述第二差分放大电路包括三极管Q4、三极管Q5、电阻R13、电阻R14和可变电流源I3，三极管Q4的基极连接电阻R12连接电阻R10、电容C1的一端，发射极经由可变电流源I3后接地，集电极经由电阻R13连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTN0；三极管Q5的基极连接电阻R12连接电阻R11、电容C2的一端，发射极经由可变电流源I3后接地，集电极经由电阻R14连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTP0。
所述CML差分放大级包括三极管Q6、三极管Q7、电阻R15、电阻R16和电流源I4，三极管Q6的基极连接CML差分放大级的输入端INP1，而该输入端INP1连接增益提升放大级的输出端OUTP0；三极管Q6的发射极经由电流源I4接地，集电极经由电阻R15连接电源VDD，同时，集电极还连接CML差分放大级的输出端OUTN1；三极管Q7的基极连接CML差分放大级的输入端INN1，而该输入端INN1连接增益提升放大级的输出端OUTN0，三极管Q7的发射极经由电流源I4接地，集电极经由电阻R16连接电源VDD，同时，集电极还连接CML差分放大级的输出端OUTP1。
所述发射极跟随器包括三极管Q8、三极管Q9、电流源I5、电流源I6，三极管Q8的基极连接发射极跟随器的输入端INP2,而该输入端INP2连接CML差分放大级的输出端OUTP1；三极管Q8的集电极连接电源VDD，发射极经由电流源I5接地，同时，发射极还连接发射极跟随器的输出端OUTP；三极管Q9的基极连接发射极跟随器的输入端INN2，而该输入端INN2连接差分放大级的输出端OUTN1；三极管Q9的集电极连接电源VDD，发射极经由电流源I5接地，同时，发射极还连接发射极跟随器的输出端OUTN。
采用上述方案后，本发明通过增益提升放大级使输入信号一路通过纯电阻网络全通通路，另一路通过电阻电容网络高通通路，从而实现高通滤波，并使有效高速信号损耗降到最小；且，增益提升放大级中第一差分放大电路和第二差分放大电路的两可变电流源实现均衡补偿大小可编程，根据不同应用场景不同电缆长度，调节两可变电流源的比例，从而实现合适的均衡补偿，满足多种应用需求；而且不会影响高速信号的带载能力。
本发明在增益提升放大级之后使用CML差分放大级，可以更好地抑制电源噪声，使高速传输信号有更好的线性度，并提供一定的增益和带宽，保证高速信号正常传输。本发明采用发射级跟随器作为输出级，一方面实现高速信号共模电平位移，另一方面提高高速信号的带载能力。
此外，本发明采用1.8V电源供电，降低电路功耗，电路性能随工艺偏差小。
附图说明
图1为现有技术的均衡电路的电路图；
图2为本发明均衡电路的功能框图；
图3为本发明高速信号差分放大级的电路图；
图4为本发明第二级CML差分放大级的电路图；
图5为本发明发射极跟随器的电路图。
具体实施方式
本发明揭示了一种低压高速可编程均衡电路，其主要应用于高速SFP+、XFP光收发模块，相比3.3V电源电压供电的传统电路结构，本发明均衡电路采用1.8V低压外部电源供电，降低功耗，电路基于0.18umSiGeBiCMOS工艺平台设计。
图2为本发明均衡电路的功能框图，图中，Gainboost为增益提升放大级1，CMLamp为CML差分放大级2，Emitterfollow为发射极跟随器3。如图2所示，本发明低压高速可编程均衡电路包括增益提升放大级1、CML差分放大级2、发射极跟随器3，其中，增益提升放大级1的输入端为均衡电路输入端，增益提升放大级1的输出端连接CML差分放大级2的输入端；CML差分放大级2的输出端连接发射极跟随器3的输入端；而发射极跟随器3的输出端为均衡电路的输出端。
其中，如图3所示，增益提升放大级1包括输入共模电压偏置单元11、输入阻抗匹配单元12、纯电阻网络通路单元13、电阻电容网络高通通路单元14、第一差分放大电路15和第二差分放大电路16，输入共模电压偏置单元11用于设置增益提升放大级1的偏置电压，输入阻抗匹配单元12用于匹配增益提升放大级1的输入阻抗与连接芯片的输入模块板的阻抗；增益提升放大级1的输入端连接纯电阻网络通路单元13，而纯电阻网络通路单元13连接第一差分放大电路15，第一差分放大电路15连接增益提升放大级1的输出端；增益提升放大级1的输入端连接电阻电容网络高通通路单元14，电阻电容网络高通通路单元14连接第二差分放大电路16，第二差分放大电路16连接增益提升放大级1的输出端。
上述输入共模电压偏置单元11由电阻R5和电阻R6构成，电阻R5和电阻R6串联，电阻R5一端连接恒压电源VDD，电阻R6一端接地。输入阻抗匹配单元12包括电阻R3和电阻R4，电阻R3一端连接于电阻R5和电阻R6之间，另一端连接增益提升放大级1的输入端INP；电阻R4一端连接于电阻R5和电阻R6之间，另一端连接增益提升放大级1的输入端INN。电阻R3和电阻R4分别为50Ω，组成100Ω的输入阻抗，和连接芯片的输入模块板阻抗相同，使输入阻抗匹配效果最好。
纯电阻网络通路单元13包括电阻R7、电阻R8和电阻R9，电阻R7一端连接增益提升放大级1的输入端INP，另一端连接电阻R9的一端；电阻R8一端连接增益提升放大级1的输入端INN，另一端连接电阻R9的另一端。第一差分放大电路15包括三极管Q2、三极管Q3、电阻R13、电阻R14和可变电流源I2，三极管Q2的基极连接于电阻R7和电阻R8之间，发射极经可变电流源I2后接地，集电极经由电阻R13连接电源VDD，同时，集电极还连接增益提升放大级1的输出端OUTN0；三极管Q3的基极连接于电阻R8和电阻R9之间，发射极经由可变电流源I2后接地，集电极经由电阻R14连接电源VDD，同时，集电极还连接增益提升放大级1的输出端OUTP0。
电阻电容网络高通通路单元14包括电阻R10、电阻R11、电阻R12、电容C1和电容C2，电阻R10和电容C1并联，其一端连接增益提升放大级1的输入端INP，另一端电阻R12的一端；电阻R11和电容C2并联，其一端连接增益提升放大级1的输入端INN，另一端连接电阻R12的另一端。第二差分放大电路16包括三极管Q4、三极管Q5、电阻R13、电阻R14和可变电流源I3，三极管Q4的基极连接电阻R12连接电阻R10、电容C1的一端，发射极经由可变电流源I3后接地，集电极经由电阻R13连接电源VDD，同时，集电极还连接增益提升放大级1的输出端OUTN0；三极管Q5的基极连接电阻R12连接电阻R11、电容C2的一端，发射极经由可变电流源I3后接地，集电极经由电阻R14连接电源VDD，同时，集电极还连接增益提升放大级1的输出端OUTP0。
上述增益提升放大级1中，第一差分放大电路15的可变电流源I2和第二差分放大电路16的可变电流源I3的电流总和保持恒定，可通过外置MCU（微处理器）控制调节两个差分放大电路的尾电流的比例，实现不同均衡补偿因子，调节零极点的位置，从而调节高频增益，实现高通滤波，然后再通过不同权重的差分放大电路进一步处理，从而实现高频信号增益提升的目的。比如I2+I3=a,当I2=0.1a时，I3=0.9a，由I2、I3不同比例，可实现不同的均衡补偿因子。
如图4所示，CML差分放大级2包括三极管Q6、三极管Q7、电阻R15、电阻R16和电流源I4，三极管Q6的基极连接CML差分放大级2的输入端INP1，而该输入端INP1连接增益提升放大级1的输出端OUTP0；三极管Q6的发射极经由电流源I4接地，集电极经由电阻R15连接电源VDD，同时，集电极还连接CML差分放大级2的输出端OUTN1；三极管Q7的基极连接CML差分放大级2的输入端INN1，而该输入端INN1连接增益提升放大级1的输出端OUTN0，三极管Q7的发射极经由电流源I4接地，集电极经由电阻R16连接电源VDD，同时，集电极还连接CML差分放大级2的输出端OUTP1。
CML差分放大级2将两条相同的单端信号路径结合起来，分别处理两个差动相位信号。相比单端信号放大级，有以下优点：更高的电源噪声抑制能力，更大的输出电压摆幅，更高的线性度。因此，使用CML差分放大级2，可以更好地抑制电源噪声，使高速传输信号有更好的线性度，并提供一定的增益和带宽，保证高速信号正常传输。
如图5所示，发射极跟随器3包括三极管Q8、三极管Q9、电流源I5、电流源I6，三极管Q8的基极连接发射极跟随器3的输入端INP2,而该输入端INP2连接CML差分放大级2的输出端OUTP1；三极管Q8的集电极连接电源VDD，发射极经由电流源I5接地，同时，发射极还连接发射极跟随器3的输出端OUTP；三极管Q9的基极连接发射极跟随器3的输入端INN2，而该输入端INN2连接CML差分放大级2的输出端OUTN1；三极管Q9的集电极连接电源VDD，发射极经由电流源I5接地，同时，发射极还连接发射极跟随器3的输出端OUTN。
发射极跟随器3具有高输入阻抗，低输出阻抗和近似为1的电压增益，以减小作为后级输入阻抗的前级信号源负载。因为直流输出电压跟随直流输入电压VBE变化，所以用于单位增益电平位移电路。
本发明将增益提升放大级1、CML差分放大级2、发射极跟随器3结合在一起，首先，本发明通过增益提升放大级1使输入信号一路通过纯电阻网络全通通路，另一路通过电阻电容网络高通通路，从而实现高通滤波，并使有效高速信号损耗降到最小；并增益提升放大级1的两可变电流源实现均衡补偿大小可编程，满足多种应用需求，从而可根据不同应用场景不同电缆长度，实现合适的均衡补偿大小。而且，调节两可变电流源的比例，不会影响高速信号的带载能力。
此外，本发明采用发射级跟随器3作为输出级，一方面实现高速信号共模电平位移，另一方面提高高速信号的带载能力。本发明采用1.8V电源供电，降低电路功耗。电路性能随工艺偏差小。
以上所述，仅是本发明实施例而已，并非对本发明的技术范围作任何限制，故凡是依据本发明的技术实质对以上实施例所作的任何细微修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (4)

  1. 一种低压高速可编程均衡电路，其特征在于：所述均衡电路包括增益提升放大级、CML差分放大级、发射极跟随器，所述增益提升放大级的输入端为均衡电路输入端，增益提升放大级的输出端连接CML差分放大级的输入端；所述CML差分放大级的输出端连接发射极跟随器的输入端；而发射极跟随器的输出端为均衡电路的输出端；
    所述增益提升放大级包括输入共模电压偏置单元、输入阻抗匹配单元、纯电阻网络通路单元、电阻电容网络高通通路单元、第一差分放大电路和第二差分放大电路，输入共模电压偏置单元用于设置增益放大级的偏置电压，输入阻抗匹配单元用于匹配增益放大级的输入阻抗与连接芯片的输入模块板的阻抗；增益提升放大级的输入端连接纯电阻网络通路单元，而纯电阻网络通路单元连接第一差分放大电路，第一差分放大电路连接增益提升放大级的输出端；增益提升放大级的输入端连接电阻电容网络高通通路单元，电阻电容网络高通通路单元连接第二差分放大电路，第二差分放大电路连接增益提升放大级的输出端；
    所述第一差分放大电路和第二差分放大电路中均设有一可变电流源，两个可变电流源的电流总和保持恒定。
  2. 根据权利要求1所述的一种低压高速可编程均衡电路，其特征在于：所述输入共模电压偏置单元包括电阻R5和电阻R6，电阻R5和电阻R6串联，电阻R5一端连接恒压电源VDD，电阻R6一端接地；
    所述输入阻抗匹配单元包括电阻R3和电阻R4，电阻R3一端连接于电阻R5和电阻R6之间，另一端连接增益提升放大级的输入端INP；电阻R4一端连接于电阻R5和电阻R6之间，另一端连接增益提升放大级的输入端INN；
    所述纯电阻网络通路单元包括电阻R7、电阻R8和电阻R9，电阻R7一端连接增益提升放大级的输入端INP，另一端连接电阻R9的一端；电阻R8一端连接增益提升放大级的输入端INN，另一端连接电阻R9的另一端；
    所述第一差分放大电路包括三极管Q2、三极管Q3、电阻R13、电阻R14和可变电流源I2，三极管Q2的基极连接于电阻R7和电阻R8之间，发射极经可变电流源I2后接地，集电极经由电阻R13连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTN0；三极管Q3的基极连接于电阻R8和电阻R9之间，发射极经由可变电流源I2后接地，集电极经由电阻R14连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTP0；
    所述电阻电容网络高通通路单元包括电阻R10、电阻R11、电阻R12、电容C1和电容C2，电阻R10和电容C1并联，其一端连接增益提升放大级的输入端INP，另一端电阻R12的一端；电阻R11和电容C2并联，其一端连接增益提升放大级的输入端INN，另一端连接电阻R12的另一端；
    所述第二差分放大电路包括三极管Q4、三极管Q5、电阻R13、电阻R14和可变电流源I3，三极管Q4的基极连接电阻R12连接电阻R10、电容C1的一端，发射极经由可变电流源I3后接地，集电极经由电阻R13连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTN0；三极管Q5的基极连接电阻R12连接电阻R11、电容C2的一端，发射极经由可变电流源I3后接地，集电极经由电阻R14连接电源VDD，同时，集电极还连接增益提升放大级的输出端OUTP0。
  3. 根据权利要求2所述的一种低压高速可编程均衡电路，其特征在于：所述CML差分放大级包括三极管Q6、三极管Q7、电阻R15、电阻R16和电流源I4，三极管Q6的基极连接CML差分放大级的输入端INP1，而该输入端INP1连接增益提升放大级的输出端OUTP0；三极管Q6的发射极经由电流源I4接地，集电极经由电阻R15连接电源VDD，同时，集电极还连接CML差分放大级的输出端OUTN1；三极管Q7的基极连接CML差分放大级的输入端INN1，而该输入端INN1连接增益提升放大级的输出端OUTN0，三极管Q7的发射极经由电流源I4接地，集电极经由电阻R16连接电源VDD，同时，集电极还连接CML差分放大级的输出端OUTP1。
  4. 根据权利要求3所述的一种低压高速可编程均衡电路，其特征在于：所述发射极跟随器包括三极管Q8、三极管Q9、电流源I5、电流源I6，三极管Q8的基极连接发射极跟随器的输入端INP2,而该输入端INP2连接CML差分放大级的输出端OUTP1；三极管Q8的集电极连接电源VDD，发射极经由电流源I5接地，同时，发射极还连接发射极跟随器的输出端OUTP；三极管Q9的基极连接发射极跟随器的输入端INN2，而该输入端INN2连接差分放大级的输出端OUTN1；三极管Q9的集电极连接电源VDD，发射极经由电流源I5接地，同时，发射极还连接发射极跟随器的输出端OUTN。
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