WO2019169514A1 - 一种高速随机数产生方法及装置 - Google Patents

一种高速随机数产生方法及装置 Download PDF

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WO2019169514A1
WO2019169514A1 PCT/CN2018/000397 CN2018000397W WO2019169514A1 WO 2019169514 A1 WO2019169514 A1 WO 2019169514A1 CN 2018000397 W CN2018000397 W CN 2018000397W WO 2019169514 A1 WO2019169514 A1 WO 2019169514A1
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entropy
random number
nodes
flip
output
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PCT/CN2018/000397
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French (fr)
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王云才
张琪琪
张建国
王安帮
李璞
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太原理工大学
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Priority to US16/486,241 priority Critical patent/US11216252B2/en
Publication of WO2019169514A1 publication Critical patent/WO2019169514A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes

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  • the present invention relates to the field of integrated circuits, and more particularly to a method and apparatus for generating high speed random numbers.
  • Random numbers have been used in scientific computing, digital communications, fiber sensing, radar ranging, and identity authentication.
  • in the field of secure communications with the rapid development of computer and network technologies, how to ensure information security is extremely important.
  • physical random numbers are not periodic and cannot be predicted, which is truly safe.
  • Physical random numbers are generally generated using physical random processes in the natural world (called physical entropy sources), such as circuit thermal noise, oscillator phase jitter, chaotic lasers, and so on.
  • the method of generating random numbers in circuit thermal noise is to use random statistical characteristics with good thermal noise of the circuit to generate random number sequences through sampling and quantization, but the amplitude of thermal noise itself is small, and it is necessary to use an amplifier for amplification, since the amplifier is not absolutely linearly amplified. Therefore, the randomness of the amplified noise signal will be poor;
  • the method of generating the random number by the oscillator phase jitter is to utilize the instability of the oscillator frequency, and the high frequency oscillator is sampled and quantized by the low frequency oscillator to generate a random number. Sequence, but the rate of random numbers generated is too low; the method of generating random numbers by chaotic lasers is to use the noise-like and wide-spectrum characteristics of chaotic lasers.
  • the signal intensity exhibits strong random fluctuations in the time domain, which can be generated as high-speed random numbers.
  • the use of autonomous Boolean networks to generate random numbers is a new method for generating physical random numbers in recent years. It utilizes the non-ideal characteristics of logic gate devices in autonomous Boolean networks (such as degradation effects, nonlinear time delays, and short pulse suppression).
  • the methods and devices for generating random numbers using autonomous Boolean networks mostly use a 3-input XOROR (XNOR) and a 3-input XOR (XOR) to form an autonomous Boolean network.
  • XNOR 3-input XOROR
  • XOR 3-input XOR
  • the purpose of the present invention is to solve the shortcomings of the existing random number generation method and device, which are complicated in structure and large in power consumption, and provide a high-speed, low-power physical random number generation technology and solution.
  • a high-speed random number generating method the apparatus used includes an entropy source module and an entropy sampling module;
  • the entropy source module (100) is composed of N nodes connected end to end to form a ring topology, which utilizes the non-ideal characteristics of the logic gates in the digital logic circuit and the influence of system noise, and the transmission delay between the logic gates. Different times, the output of each node exhibits chaotic dynamics as an entropy source; the N nodes include a node composed of XOR logical gates (102) and nodes (101) Ni composed of N-1 XOR logic gates.
  • N and i are integers, N value is equal to 3n, n is a positive integer, i ⁇ (1 ⁇ N-1); two input ends of each node are respectively connected to the output ends of the left and right adjacent nodes; N nodes The output is connected to the entropy sampling module (200) for sampling and quantization;
  • the entropy sampling module (200) uses a D flip-flop to sample and quantize the output signals of the respective nodes; the D flip-flops are N and are in one-to-one correspondence with N nodes, and the input of each D flip-flop is The end is connected to an output of a node of the entropy source module (100) corresponding thereto, and the clock signal input end of each D flip-flop is used for inputting a clock signal (300), and according to the input clock signal (300), the entropy source is Signal sampling, quantization, and finally each D flip-flop output outputs a sequence of random numbers with good random characteristics.
  • the invention comprises two parts of an entropy source module and an entropy sampling module, all of which are composed of digital logic devices, and has a simple structure and is easy to be integrated and manufactured; furthermore, the entropy source module of the invention is composed of a 2-input XOR gate (XNOR) and N - An autonomous Boolean network of 2-input XOR gates (XOR), using a 2-input logic gate compared to a 3-input XOROR (XNOR) and 3-input XOR gate (XOR) to form an autonomous Boolean network
  • the device can greatly reduce the power consumption level because a 3-input XOR gate (XNOR) or a 3-input XOR gate (XOR) requires two 2-input XOR gates or two 2-inputs, respectively.
  • XOR gates are cascaded, which means that the actual number of logic gate devices used in the present invention is about half of the three input logic gates in the case of a consistent number of nodes in the autonomous Boolean network; therefore, the power consumption of the device can also be reduced. About half.
  • the 2-input logic gate is about 1/2 of the 3-input logic gate; therefore, the random number generation rate can be increased by about 2 times.
  • the single-channel random number generation speed of the present invention is generated. Up to 1Gbps.
  • a high-speed random number generating device includes an entropy source module (100), an entropy sampling module (200), and an external clock for providing a clock signal (300);
  • the entropy source module (100) is composed of N nodes connected end to end to form a ring topology, and the N nodes comprise a node (102) composed of XOR logical gates and N-1 XOR logic gates.
  • the entropy sampling module (200) uses a D flip-flop to sample and quantize the output signals of the respective nodes; the D flip-flops are N and are in one-to-one correspondence with N nodes, and the input ends of each D flip-flop are connected thereto.
  • Corresponding entropy source module (100) the output end of one node, the clock signal input end of each D flip-flop is connected to an external clock; the output end of each D flip-flop is used to output a random number sequence with good random characteristics.
  • the entropy sampling module (200) uses a first-level D flip-flop to sample and quantize the output signals of each node. Since the entropy source module (100) is not driven by the clock signal, there is a setup and hold that does not satisfy the D flip-flop sampling and quantization. The event of time leads to the occurrence of metastability, which further increases the randomness of the system.
  • Each of the N nodes of the entropy source module can be output separately or simultaneously.
  • the entropy source module is an autonomous Boolean network composed of a digital logic gate and a ring topology, and is not driven by an external clock signal, and can generate a wide and flat chaotic signal.
  • the random number generating method and device are all composed of digital logic gates, the circuit structure is simple and easy to integrate, and the power consumption is very low, and is compatible with various programmable logic circuits.
  • the random number generating method and device can realize integrated miniaturization, and can be widely applied in the information security field such as secure communication.
  • the clock signal is provided by an external clock signal, and the clock signal is ⁇ 1 GHz.
  • the entropy sampling module is implemented by a D flip-flop, each D flip-flop has a clock signal input end connected to an external clock signal; and a signal input end of the D flip-flop is connected to an output end of each node of the entropy source module.
  • the generated random number sequence does not have periodicity and does not require post-processing.
  • 0 to 1 Gbit/s can be generated by the international random number industry test standard (NIST and Diehard statistical test) with good randomness. A random number of characteristics.
  • the system uses a 2-input XOR-OR gate and an XOR gate to form a ring topology.
  • an entropy source the system has a higher frequency than an entropy source composed of 3-input XOR gates and XOR gates. The power consumption is very low.
  • the entropy sampling module (200) of the system uses a first-level D flip-flop to sample and quantize the output signals of the respective nodes. Since the entropy source module (100) is not driven by the clock signal, there is a sampling error that does not satisfy the D flip-flop. The establishment and maintenance of time events lead to the occurrence of metastability, further increasing the randomness of the system.
  • the system uses digital logic gates, the circuit structure is simple, and it can be compatible with various programmable logic circuits, and has universal applicability and flexibility.
  • the random number generating method and device can realize integrated miniaturization, and can be widely applied in information security fields such as secure communication.
  • Figure 1 is a circuit configuration diagram of the apparatus of the present invention.
  • 100 entropy source module
  • 101 exclusive OR logic gate
  • 102 exclusive OR non-logic gate
  • 200 entropy sampling module
  • 300 clock signal.
  • Figure 2 is a schematic illustration of a Boolean fixed point of the apparatus of the present invention.
  • 3 is a sequence diagram of a 600 Mbps random number generated by the apparatus of the present invention.
  • 5 is a Diehard random number test result of a 600 Mbps random number generated by the apparatus of the present invention.
  • FIG. 1 is a circuit structural diagram of a method and apparatus for generating a high-speed random number according to the present invention. The specific steps of the method are as follows:
  • Step 1 Using the non-ideal characteristics of the logic gates in the digital logic circuit (such as degradation effect, nonlinear time delay and short pulse suppression, etc.) and the influence of system noise, the transmission delay between the logic gates is different, by N nodes
  • the constructed ring topology produces a broad and flat chaotic signal as the entropy source 100, where the N value is equal to 3n (n is a positive integer); the node 102 of the entropy source module 100 is an exclusive OR non-logic gate, and node 101 is an exclusive OR Logic gates, the two inputs of each node are respectively connected to the outputs of the left and right adjacent nodes.
  • the two inputs of the exclusive OR logic gate 102 are connected to the outputs of the exclusive OR logic gates 101N-1, 1011; the two inputs of the exclusive OR logic gate 1011 and the exclusive OR logic gates 102, 1012 The outputs are connected; the two inputs of the exclusive OR gate 101N-1 are connected to the outputs of the exclusive OR logic gates 102, 101N-2; the two inputs of the exclusive OR logic gate 101M and the exclusive OR logic gates The outputs of 101M-1 and 101M+1 are connected, wherein M is an integer whose value is greater than 1 and less than N-1;
  • N nodes in the entropy source module 100 can be used as an output terminal, and are connected to the input end of the entropy sampling module 200, that is, the output terminals of the XOR logic gate 102 and the XOR logic gate 101 can be used as an output terminal, and the entropy sampling module is connected. 200 input.
  • the entropy source module 100 is not driven by an external clock, and generates a wide and flat chaotic signal through a ring topology. Due to the non-ideal characteristics of the logic gates in the digital logic circuit and the influence of system noise, it is unpredictable.
  • Step 2 The output signal of the entropy source module 100 is extracted and quantized by the entropy sampling module 200 by using the external clock signal 300, and a random number sequence with good random characteristics is output.
  • the entropy sampling module 200 is all implemented by a first-level D flip-flop.
  • the D flip-flop has a clock signal input end connected to the external clock signal 300, and at the same time, the signal input end is connected to the output end of each node of the entropy source module 100. Since the entropy source module (100) is not driven by the clock signal, there are events that do not satisfy the setup and hold times of the D flip-flop sampling, quantization, resulting in metastability, which further increases the randomness of the system.
  • the above steps can be used to obtain a random number sequence with good random characteristics.
  • the random number rate of the device of the present invention is related to the frequency of the external clock signal, and the frequency range is ⁇ 1 GHz, and the generated random number can pass the international random number industry test without post-processing. Standard (NIST and Diehard statistical tests).
  • the high level represents 1 and the low level represents 0.
  • the exclusive OR logic gate 102 outputs 1
  • the exclusive OR logic gate 1011 outputs 1
  • the exclusive OR logic gate 1012 outputs
  • the exclusive OR logic gate 1013 outputs 1 "1101" is called the fixed point of the entropy source module.
  • the value of N is not equal to 3n (n is a positive integer)
  • the entropy source module has a fixed point, which finally outputs a steady state signal (high level or low level).
  • FIG. 4, and FIG. 5 are respectively a random sequence diagram of 600 Mbps generated by the apparatus of the present invention and test results of NIST and Diehard statistical tests.
  • the timing diagram when the amplitude is high level, the code is 1; When low, the code is 0.
  • the invention can be implemented on a programmable logic circuit such as a CPLD or an FPGA, and the device of the invention has the advantages of low cost, simple structure and easy integration, and low power consumption.
  • the invention can generate high-rate random numbers by parallel multiplexing, and can fully meet the application requirements of modern random numbers, especially in the information security field such as secure communication.

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Abstract

一种高速随机数产生方法及装置，包含熵源模块（100）和熵采样模块（200）两部分。所述熵源模块（100）是由数字逻辑门组成的自治布尔网络，该网络由一个异或非门（102）和N-1个异或门（101 N-1）组成，N值等于3n（n为正整数），熵源模块（100）可以产生频谱宽阔且平坦的混沌信号。熵采样模块（200）由D触发器构成，它对混沌信号进行采样、量化进而生成随机数序列。随机数序列可以通过随机数行业测试标准（NIST和Diehard统计测试），具有良好的随机统计特性。所述装置全部由数字逻辑门组成，电路结构简单、易于集成制造；且无需常规随机数产生装置所必须的后处理算法或电路，可以极大降低其功耗水平，可广泛应用在保密通信、密钥分发、数据加密等信息安全领域。

Description

一种高速随机数产生方法及装置 技术领域
本发明涉及集成电路领域，尤其是一种高速随机数产生方法及装置。
背景技术
随机数在科学计算、数字通信、光纤传感、雷达测距、身份认证等领域已有重要应用。尤其，在保密通信领域，随着计算机与网络技术的迅速发展，如何保证信息安全显得异常重要。
目前，很多随机数产生装置是使用计算机结合一些确定性数学算法(如线性同余方法等)来快速生成伪随机数，而伪随机数存在周期性，可以被预测，这些特点使得伪随机数发生器难以确保加密信息的安全。
与伪随机数不同，物理随机数无周期性、不可以被预测，是真正安全的。物理随机数一般是利用自然界的物理随机过程(称为物理熵源)来产生，例如电路热噪声、振荡器相位抖动、混沌激光等。
电路热噪声产生随机数的方法是利用电路热噪声良好的随机统计特性，通过采样、量化来产生随机数序列，但是热噪声自身的幅度较小，需要使用放大器进行放大，由于放大器并非绝对线性放大，因此放大后的噪声信号其随机性会变差；振荡器相位抖动产生随机数的方法是利用振荡器频率的不稳定性，通过低频振荡器对高频振荡器进行采样、量化来产生随机数序列，但这样产生的随机数速率过低；混沌激光产生随机数的方法是利用混沌激光的类噪声和宽频谱特性，信号强度在时域上呈现强烈的随机起伏变化，可以作为高速随机数产生的物理熵源，但混沌激光产生随机数的装置结构复杂，包含许多光学元件，不易集成；以上产生随机数的方法大部分需要后处理才能通过随机数测试，对随机数的产生和应用带来局限性。
利用自治布尔网络产生随机数是近年来出现的一种物理随机数产生新方法，它是利用自治布尔网络中逻辑门器件的非理想特性(如退化效应、非线性时间延迟和短脉冲抑制等)来产生物理随机过程(如相位噪声或混沌信号)，进而从中提取随机数序列的一类技术。目前利用自治布尔网络产 生随机数的方法和装置多采用3输入异或非门(XNOR)和3输入异或门(XOR)构成自治布尔网络，为了提高其随机数质量，都在其发明的结构中都加入了后处理电路；但是这样的解决方案，既增加了随机数产生装置的电路复杂性，同时提高了装置的功耗水平。
因此，发明一种结构简单、易于集成、功耗低、且产生随机数可通过随机数行业测试标准的高速随机数产生方法和技术具有极大的现实意义。
发明内容
本发明的目的是为了解决现有随机数产生方法和装置结构复杂、功耗大的缺点，提供一种高速、低功耗的物理随机数产生技术和解决方案。
本发明所述的一种高速随机数产生方法是采用以下技术方案实现的：
一种高速随机数产生方法，所用装置包括熵源模块和熵采样模块；
(1)所述熵源模块(100)是由N个节点首尾相连组成环状拓扑结构，利用数字逻辑电路中逻辑门的非理想性特性以及系统噪声的影响，各个逻辑门之间的传输延时不同，各个节点的输出呈现混沌动态，作为熵源；所述N个节点包括一个异或非逻辑门构成的节点(102)以及N-1个异或逻辑门构成的节点(101)N-i，其中N、i为整数，N值等于3n，n为正整数，，i∈(1～N-1)；每个节点的两个输入端分别连接左右相邻节点的输出端；N个节点的输出端连接到熵采样模块(200)，进行采样、量化；
(2)所述熵采样模块(200)采用D触发器对各个节点的输出信号进行采样、量化；所述D触发器为N个并与N个节点一一对应，每个D触发器的输入端连接与其对应的熵源模块(100)中一个节点的输出端，每个D触发器的时钟信号输入端均用于输入时钟信号(300)，并根据输入时钟信号(300)，将熵源信号采样、量化，最后每个D触发器输出端输出具有良好随机特性的随机数序列。
本发明包含熵源模块和熵采样模块两部分，全部由数字逻辑器件组成，结构简单且易于集成制造；此外，本发明的熵源模块是由1个2输入异或非门(XNOR)和N-1个2输入异或门(XOR)组成的自治布尔网络，相比采用3输入异或非门(XNOR)和3输入异或门(XOR)构成自治布尔网络，本 发明使用2输入逻辑门器件可以极大减小功耗水平，原因在于一个3输入异或非门(XNOR)或一个3输入异或门(XOR)原理上分别需要由两个2输入异或非门或两个2输入异或门来级联构成，这就意味着在自治布尔网络中节点数量一致的情况下，本发明实际的逻辑门器件使用数量约为3输入逻辑门的一半左右；因此装置功耗也可以降低约一半。最后，在器件传输延迟时间上，2输入逻辑门约是3输入逻辑门的1/2；因此，随机数产生速率可提高约2倍，在实际测试中，本发明的单路随机数产生速度最高可至1Gbps。
本发明所述的一种高速随机数产生装置是采用以下技术方案实现的：
一种高速随机数产生装置，包括熵源模块(100)、熵采样模块(200)和提供时钟信号(300)的外部时钟；
所述熵源模块(100)是由N个节点首尾相连组成环状拓扑结构，所述N个节点包括一个异或非逻辑门构成的节点(102)以及N-1个异或逻辑门构成的节点(101)N-i，其中N、i为整数，N值等于3n，n为正整数，，i∈(1～N-1)；每个节点的两个输入端分别连接左右相邻节点的输出端；N个节点的输出端连接到熵采样模块(200)；
所述熵采样模块(200)采用D触发器对各个节点的输出信号进行采样、量化；所述D触发器为N个并与N个节点一一对应，每个D触发器的输入端连接与其对应的熵源模块(100)中一个节点的输出端，每个D触发器的时钟信号输入端均连接外部时钟；每个D触发器的输出端用于输出具有良好随机特性的随机数序列。
熵采样模块(200)采用一级D触发器对各个节点的输出信号进行采样、量化，由于熵源模块(100)不受时钟信号驱动，所以存在不满足D触发器采样、量化的建立和保持时间的事件，导致出现亚稳态，进一步增加了系统的随机性。
熵源模块N个节点中各个节点可单独输出，也可同时输出。
所述熵源模块为由数字逻辑门组成环状拓扑结构的自治布尔网络，不受外部时钟信号驱动，可产生频谱宽阔且平坦的混沌信号。
所述随机数产生方法及装置全部由数字逻辑门组成，电路结构简单易 集成，并且功耗很低，可兼容各种不同的可编程逻辑电路。
所述随机数产生方法及装置可实现集成化小型化，可广泛应用在保密通信等信息安全领域。
进一步的，所述时钟信号由外部时钟信号提供，时钟信号≤1GHz。
进一步的，所述熵采样模块由D触发器实现，每个D触发器存在时钟信号输入端，连接外部时钟信号；D触发器的信号输入端与熵源模块的各个节点的输出端相连。
本发明所提供的一种高速随机数产生方法及装置，其优点与积极效果在于：
第一，所产生的随机数序列不存在周期性，无需后处理，通过调节采样时钟频率即可产生0～1Gbit/s可以通过国际随机数行业测试标准(NIST和Diehard统计测试)的具有良好随机特性的随机数。
第二，系统全部采用2输入异或非门和异或门构成环状拓扑结构，作为熵源，相对于采用3输入异或非门和异或门构成的熵源，具有更高的频率且功耗很低。
第三，系统所述熵采样模块(200)采用一级D触发器对各个节点的输出信号进行采样、量化，由于熵源模块(100)没有时钟信号驱动，所以存在不满足D触发器采样量化的建立和保持时间的事件，导致出现亚稳态，进一步增加了系统的随机性。
第四，系统全部采用数字逻辑门，电路结构简单，可兼容各种不同的可编程逻辑电路，具有普遍的适用性和灵活性。
第五，该随机数产生方法及装置可实现集成化小型化，可广泛应用在保密通信等信息安全领域。
附图说明
图1是本发明所述装置的电路结构图。
图中：100：熵源模块；101：异或逻辑门；102：异或非逻辑门；200：熵采样模块；300：时钟信号。
图2是本发明所述装置的布尔固定点示意图。
图3是本发明所述装置产生的600Mbps随机数序列图。
图4是本发明所述装置产生的600Mbps随机数的NIST随机数测试结果。
图5是本发明所述装置产生的600Mbps随机数的Diehard随机数测试结果。
具体实施方式
为了更加清楚明白地解释本发明的基本原理，结构和优点，以下结合附图，对本发明做出进一步详细说明。此处描述的具体实施内容仅仅用以解释本发明，并不用于限定本发明。
图1所示实施本发明所提供的一种高速随机数产生方法及装置的电路结构图，具体产生方法步骤如下：
步骤一、利用数字逻辑电路中逻辑门的非理想特性(如退化效应、非线性时间延迟和短脉冲抑制等)以及系统噪声的影响，各个逻辑门之间的传输延时不同，由N个节点构成的环形拓扑结构产生频谱宽阔且平坦的混沌信号，作为熵源100，其中N值等于3n(n为正整数)；熵源模块100的节点102为异或非逻辑门，节点101为异或逻辑门，每个节点的两个输入端分别连接左右相邻节点的输出端。
也就是说，异或非逻辑门102的两个输入端与异或逻辑门101N-1、1011的输出端相连接；异或逻辑门1011的两个输入端与异或非逻辑门102、1012的输出端相连接；异或逻辑门101N-1的两个输入端与异或非逻辑门102、101N-2的输出端相连接；异或逻辑门101M的两个输入端与异或逻辑门101M-1、101M+1的输出端相连接，其中M为整数，其值大于1且小于N-1；
熵源模块100中N个节点均可作为输出端，连接熵采样模块200的输入端，即异或非逻辑门102和异或逻辑门101的各个输出端均可作为输出端，连接熵采样模块200的输入端。
熵源模块100不受外部时钟驱动，通过环形拓扑结构产生频谱宽阔且平坦的混沌信号，由于数字逻辑电路中逻辑门的非理想特性以及系统噪声的影响，其具有不可预测性。
步骤二、利用外部时钟信号300对熵源模块100的输出信号，通过 熵采样模块200进行采样、量化，输出随机特性良好的随机数序列。
熵采样模块200全部由一级D触发器实现，D触发器存在时钟信号输入端，连接外部时钟信号300，同时，信号输入端与熵源模块100的各个节点的输出端相连。由于熵源模块(100)没有时钟信号驱动，所以存在不满足D触发器采样、量化的建立和保持时间的事件，导致出现亚稳态，进一步增加了系统的随机性。
通过熵采样模块200进行采样，可以得到随机特性良好的随机数序列。
实现以上步骤即可得到随机特性良好的随机数序列，本发明所述装置的随机数速率和外部时钟信号频率有关，频率范围≤1GHz，产生的随机数无需后处理即可通过国际随机数行业测试标准(NIST和Diehard统计测试)。
图2是本发明所述熵源模块N＝4时的每个节点的输出信号时序图(左为结构示意图，右为每个节点的输出信号时序图)。如图2所示，当熵源模块N＝4时，每个节点输出稳态信号，且可同时满足每个节点的布尔逻辑运算。高电平代表1，低电平代表0，如图2所示，异或非逻辑门102输出1，异或逻辑门1011输出1，异或逻辑门1012输出0，异或逻辑门1013输出1，“1101”即称之为熵源模块的固定点。当N值不等于3n(n为正整数)时，熵源模块均存在固定点，使其最终输出稳态信号(高电平或低电平)。
图3、图4、图5分别是本发明所述装置产生的600Mbps的随机序列图以及NIST和Diehard统计测试的测试结果，时序图中，幅值为高电平时，编码为1；幅值为低电平时，编码为0。
我们采集了1000组容量为1Mbit的600Mbps的随机数序列进行NIST测试。显著水平为0.01，要求每项测试的P-value值大于0.01，通过率大于0.9806。最终结果表明通过了该随机数测试标准，证明本方法产生的随机数随机性良好。
我们采集了1Gbit的600Mbps的随机数序列进行Diehard测试。显著水平为0.01，要求每项测试的P-value值大于0.01且小于0.99。最终结果表明通过了该随机数测试标准，证明本方法产生的随机数随机性良好。
本发明可在CPLD、FPGA等可编程逻辑电路上实现，而且，本发明所 述装置，成本低廉，结构简单容易集成，功耗很低。本发明可以通过并行多路产生高速率随机数，完全能够满足现代随机数的应用需求，尤其是保密通信等信息安全领域。
以上实施实例仅用具体实施说明本发明的基本原理和实现结构，在此基础上还可以做出若干改进和润饰，这种基于本发明的改进和润饰均包含在本发明的保护范围之内。

Claims (3)

  1. 一种高速随机数产生方法，其特征在于，所用装置包括熵源模块(100)和熵采样模块(200)；
    (1)所述熵源模块(100)是由N个节点首尾相连组成环状拓扑结构，利用数字逻辑电路中逻辑门的非理想性特性以及系统噪声的影响，各个逻辑门之间的传输延时不同，各个节点的输出呈现混沌动态，作为熵源；所述N个节点包括一个异或非逻辑门构成的节点(102)以及N-1个异或逻辑门构成的节点(101)N-i，其中N、i为整数，N值等于3n，n为正整数，，i∈(1～N-1)；每个节点的两个输入端分别连接左右相邻节点的输出端；N个节点的输出端连接到熵采样模块(200)，进行采样、量化；
    (2)所述熵采样模块(200)采用D触发器对各个节点的输出信号进行采样、量化；所述D触发器为N个并与N个节点一一对应，每个D触发器的输入端连接与其对应的熵源模块(100)中一个节点的输出端，每个D触发器的时钟信号输入端均用于输入时钟信号(300)，并根据输入时钟信号(300)，将熵源信号采样、量化，最后每个D触发器输出端输出具有良好随机特性的随机数序列。
  2. 如权利要求1所述的一种高速随机数产生方法，其特征在于，所述时钟信号(300)由外部时钟提供，时钟信号≤1GHz。
  3. 一种高速随机数产生装置，用于实现如权利要求2所述的方法，其特征在于，包括熵源模块(100)、熵采样模块(200)和提供时钟信号(300)的外部时钟；
    所述熵源模块(100)是由N个节点首尾相连组成环状拓扑结构，所 述N个节点包括一个异或非逻辑门构成的节点(102)以及N-1个异或逻辑门构成的节点(101)N-i，其中N、i为整数，N值等于3n，n为正整数，，i∈(1～N-1)；每个节点的两个输入端分别连接左右相邻节点的输出端；N个节点的输出端连接到熵采样模块(200)；
    所述熵采样模块(200)采用D触发器对各个节点的输出信号进行采样、量化；所述D触发器为N个并与N个节点一一对应，每个D触发器的输入端连接与其对应的熵源模块(100)中一个节点的输出端，每个D触发器的时钟信号输入端均连接外部时钟；每个D触发器的输出端用于输出具有良好随机特性的随机数序列。
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