WO2019134655A1 - 一种ldpc编码的方法、装置及数据发送的方法、装置 - Google Patents

一种ldpc编码的方法、装置及数据发送的方法、装置 Download PDF

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Publication number
WO2019134655A1
WO2019134655A1 PCT/CN2019/070200 CN2019070200W WO2019134655A1 WO 2019134655 A1 WO2019134655 A1 WO 2019134655A1 CN 2019070200 W CN2019070200 W CN 2019070200W WO 2019134655 A1 WO2019134655 A1 WO 2019134655A1
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ldpc
codebook
twenty
parity check
matrix
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PCT/CN2019/070200
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English (en)
French (fr)
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刘铮
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Definitions

  • the present application relates to the field of communications, such as a Low Density Parity Check Code (LDPC) encoding method, apparatus, LDPC encoding and data transmitting method, apparatus, and data transmission device.
  • LDPC Low Density Parity Check Code
  • Ethernet Passive Optical Network (EPON)/Gigabit-Capable Passive Optical Network (GPON) uplink channel and downlink channel usually use RS (255, 223) or RS (255, 239)
  • RS 255, 223
  • the downlink channel is a high-speed continuous service, and the main requirement is to obtain a higher coding gain.
  • a codebook with a larger block length can satisfy the service requirement of the downlink channel;
  • the uplink channel is a burst delay-sensitive service, and the main requirement is an optical network unit (Optical Network Unit (ONU) has a simple coding and a short end-to-end codec, so it can sacrifice a little coding gain and use a codebook with a smaller block length in exchange for shorter delay and lower complexity.
  • ONU Optical Network Unit
  • each of the uplink channel and the downlink channel is designed with an LDPC codec codebook, which requires an optical line terminal (OLT) and an ONU to design two different codec systems on the transmitting end and the receiving end, thereby increasing the system design. Difficulty.
  • the embodiment of the present application provides an LDPC encoding method, device, LDPC encoding and data transmitting method, device and data transmission device, so as to reduce system design difficulty.
  • An embodiment of the present application provides a method for LDPC encoding, including: acquiring a quasi-cyclic low-density parity check code QC-LDPC codebook, and determining a parity check matrix according to the QC-LDPC codebook; wherein, for an uplink channel and The downlink channel adopts the same QC-LDPC codebook; the parity bit is determined according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence.
  • the embodiment of the present application further provides an apparatus for LDPC encoding, including: a determining module, configured to obtain a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook; wherein, for an uplink channel and a downlink channel The same QC-LDPC codebook is used; the LDPC encoding module is configured to determine a parity bit according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence.
  • the embodiment of the present application further provides an LDPC encoder, including: a processor; a memory, configured to store the processor executable instructions; wherein the processor is configured to perform the following operations: acquiring a QC-LDPC codebook, Determining a parity check matrix according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, using the same QC-LDPC codebook; determining a parity bit according to the parity check matrix and the information sequence to be encoded, LDPC coding sequence.
  • the embodiment of the present application further provides a data transmission method, including: acquiring a QC-LDPC codebook, and determining a parity check matrix according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, adopting the same QC Determining a parity bit according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence; obtaining data to be transmitted according to the LDPC code sequence, and transmitting the to-be-sent data.
  • the embodiment of the present application further provides an apparatus for data transmission, including: a determining module, configured to acquire a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook; wherein, for an uplink channel and a downlink channel And adopting the same QC-LDPC codebook; the LDPC encoding module is configured to determine a parity bit according to the parity check matrix and the information sequence to be encoded to obtain an LDPC code sequence; and the sending module is configured to obtain a to be sent according to the LDPC code sequence. Data, the data to be sent is sent out.
  • a determining module configured to acquire a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook
  • the LDPC encoding module is configured to determine a parity bit according to the parity check matrix and the information sequence to be encoded to obtain an LDPC code sequence
  • the sending module is configured to obtain a to be sent according to the LD
  • the embodiment of the present application further provides a data transmission device, including: a processor; a transmission device configured to perform data transmission and reception communication according to control of the processor; and a memory configured to store the processor executable instruction;
  • the processor is configured to: obtain a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, the same QC-LDPC codebook is used;
  • the parity check matrix and the information sequence to be encoded determine a parity bit to obtain an LDPC code sequence; the data to be transmitted is obtained according to the LDPC code sequence, and the transmitting device is controlled to send the to-be-sent data.
  • the embodiment of the present application further provides a computer readable storage medium storing computer executable instructions, which are set to perform the LDPC encoding method in the embodiment of the present application.
  • the embodiment of the present application further provides a computer readable storage medium, where the computer executable instructions are set to execute the data sending method in the embodiment of the present application.
  • FIG. 1 is a flowchart of a method for LDPC encoding according to an embodiment of the present application
  • FIG. 2 is a flowchart of a method for data transmission according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of coding gain of a QC-LDPC codebook of 8*40*200 in the first embodiment
  • FIG. 4 is a schematic diagram of an apparatus for LDPC encoding according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an apparatus for data transmission according to an embodiment of the present application.
  • the method for LDPC encoding in the embodiment of the present application includes steps 101 and 102.
  • step 101 a Quasi Cyclic Low Density Parity Check Code (QC-LDPC) codebook is obtained, and a parity check matrix is determined according to the QC-LDPC codebook; wherein, for the uplink channel and The downlink channel uses the same QC-LDPC codebook.
  • QC-LDPC Quasi Cyclic Low Density Parity Check Code
  • the step includes: generating, for each unit value in the QC-LDPC codebook of the M rows and N columns, an identity matrix of Z rows and Z columns according to the lifting value Z, and the unit matrix according to the unit value. Perform a cyclic right shift to generate a parity check matrix of M*Z rows of N*Z columns and a submatrix size of Z.
  • step 102 a parity bit is determined according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence.
  • the same set of LDPC codebooks can be used for the uplink channel and the downlink channel, which reduces the complexity of the system design.
  • the method before the step 101, further includes: determining the QC-LDPC codebook according to the basic matrix coefficient and the lifting value.
  • the basic matrix coefficient includes the number of rows and the number of columns, and the promotion value is the size of the sub-matrix.
  • the base matrix coefficient is 8 rows and 40 columns, and the boost value is 200; or the base matrix coefficient is 6 rows and 26 columns, and the boost value is 512.
  • the QC-LDPC codebook is a codebook of 8*40*200, or a codebook of 6*26*512.
  • the number of bits is usually 18K or more.
  • This scheme has high computational complexity and a large delay in decoding processing, which is about 10us. It is unacceptable for high-speed services sensitive to delay.
  • the embodiment of the present application adopts a codebook of 8*40*200, or a codebook of 6*26*512, and the codebook length is limited to between 8000 and 12288 bits, and the complexity is only 2/3 of the 18K codebook. 1/2, the delay is 1/2 to 1/3 of the 18K codebook, which reduces the complexity and delay, and is applicable to both the downlink channel and the uplink channel.
  • the determining the QC-LDPC codebook according to the basic matrix coefficient and the boosting value Z comprises:
  • a QC-LDPC codebook whose bit error rate is reduced from 0.01 to 10 -12 or less is selected.
  • LDPC coding is used to reduce the bit error rate. Different codebooks have different effects on reducing the bit error rate. Computer simulation can be used to simulate multiple codebooks to determine the error rate from 0.01 to 10 - QC-LDPC codebook of 12 or less.
  • the QC-LDPC codebook used is:
  • This codebook is 8*40*200 codebook.
  • This codebook is a 6*26*512 codebook.
  • the method for data transmission in the embodiment of the present application includes step 201, step 202, and step 203.
  • step 201 a QC-LDPC codebook is obtained, and a parity check matrix is determined according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, the same QC-LDPC codebook is used.
  • step 202 a parity bit is determined according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence.
  • step 203 data to be transmitted is obtained according to the LDPC coding sequence, and the to-be-sent data is transmitted.
  • Steps 201 to 202 are the same as steps 101 to 102, and are not described again.
  • the obtaining the data to be sent according to the LDPC coding sequence includes: using the LDPC code sequence as data to be sent; or removing at least part of information bits in the LDPC code sequence.
  • the information bit portion is 20 columns
  • the removing the information bit portion of the LDPC coding sequence by at least one column as the data to be sent includes:
  • the first two columns in the information bit portion of the LDPC coding sequence are removed as data to be transmitted.
  • the information bit part is the first 20 columns, and the check digit part is the last 6 columns.
  • the information bit parts of the first two columns are not transmitted. This method is called puncturing. In this way, the code rate can be increased, and the code rate is increased from 0.77 to 0.83.
  • the parity check matrix that is, the H matrix size is 8 rows and 40 columns, and the sub-matrix size is 200; wherein the first 32 columns of the H matrix are information bits, the last 8 columns correspond to check bits, and the same codebook is used for the uplink channel and the downlink channel.
  • the complexity is only 1/2 of the 18K codebook.
  • the QC-LDPC codebook for 8*40*200 is:
  • the s and p are combined to obtain an LDPC coding sequence, and the encoding process is completed.
  • the LDPC code sequence is transmitted as data to be transmitted.
  • FIG. 3 it is a coding gain diagram of the above codebook, wherein EbN0 is a signal to noise ratio.
  • EbN0 is a signal to noise ratio.
  • the parity check matrix that is, the H matrix size is 6 rows and 26 columns, and the sub-matrix size is 512; wherein the first 20 columns of the H matrix are information bits, the last 6 columns correspond to check bits, and the support information length is 10K, and the code rate is 0.77. .
  • the same codebook is used for the uplink channel and the downlink channel, and the complexity is only 2/3 of the 18K codebook.
  • the 6*26*512 QC-LDPC codebook is:
  • the LDPC code sequence is transmitted as data to be transmitted.
  • the QC-LDPC codebook in the second embodiment is used.
  • the information bit portions of the first two columns are not transmitted, since the LDPC encoding is adopted, the information bit portions of the first two columns can still be decoded at the time of decoding, and the data is not affected. The effect of the transmission.
  • the embodiment of the present application further provides an apparatus for LDPC coding, which is configured to implement the foregoing embodiments and implementation manners, and has not been described again.
  • the term "module” may implement a combination of at least one of software and hardware for a predetermined function.
  • the devices described in the following embodiments can be implemented in software, hardware, or a combination of software and hardware, is also possible and conceivable.
  • the apparatus for LDPC encoding in the embodiment of the present application includes a determining module 41 and an LDPC encoding module 42.
  • the determining module 41 is configured to obtain a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, the same QC-LDPC codebook is used.
  • the LDPC encoding module 42 is configured to determine a parity bit according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence.
  • the apparatus further includes: a QC-LDPC codebook module configured to determine the QC-LDPC codebook according to the base matrix coefficient and the boost value.
  • the QC-LDPC codebook module is configured to select a QC-LDPC codebook that reduces the bit error rate from 0.01 to less than 10 -12 according to the base matrix coefficient and the boost value.
  • the base matrix coefficient is 8 rows and 40 columns, and the boost value is 200; or the base matrix coefficient is 6 rows and 26 columns, and the boost value is 512.
  • the determining module 41 is configured to: for each cell value in the QC-LDPC codebook of M rows and N columns, generate an identity matrix of Z rows and Z columns according to the lifting value Z, according to the cell value
  • the unit matrix is cyclically shifted to generate a parity check matrix of M*Z rows of N*Z columns and a submatrix size of Z.
  • the QC-LDPC codebook is:
  • the same set of LDPC codebooks can be used for the uplink channel and the downlink channel, which reduces the complexity of the system design.
  • the embodiment of the present application further provides an LDPC encoder, including: a processor; a memory, configured to store the processor executable instructions.
  • the processor is configured to: obtain a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, the same QC-LDPC codebook is used. And determining a parity bit according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence.
  • the processor is further configured to perform the following operations: before acquiring the QC-LDPC codebook, determining the QC-LDPC codebook according to the base matrix coefficient and the boost value.
  • the processor is further configured to perform the operation of selecting a QC-LDPC codebook that reduces the bit error rate from 0.01 to less than 10 -12 based on the base matrix coefficients and the boost values.
  • the base matrix coefficient is 8 rows and 40 columns, and the boost value is 200; or the base matrix coefficient is 6 rows and 26 columns, and the boost value is 512.
  • the processor is further configured to: perform, for each unit value in the QC-LDPC codebook of M rows and N columns, generate an identity matrix of Z rows and Z columns according to the lifting value Z, according to the The unit value cyclically shifts the unit matrix to generate a parity check matrix of M*Z rows N*Z columns and a submatrix size of Z.
  • the QC-LDPC codebook is:
  • the embodiment of the present application further provides a device for transmitting data, and the device is configured to implement the foregoing embodiments and implementation manners, and details are not described herein.
  • the term "module" may implement a combination of at least one of software and hardware for a predetermined function.
  • the devices described in the following embodiments may be implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • the apparatus for data transmission implemented by the present application includes a determining module 51, an LDPC encoding module 52, and a transmitting module 53.
  • the determining module 51 is configured to obtain a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, the same QC-LDPC codebook is used.
  • the LDPC encoding module 52 is configured to determine a parity bit according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence.
  • the sending module 53 is configured to obtain data to be sent according to the LDPC coding sequence, and send the to-be-sent data.
  • the determining module 51 is configured to: for each cell value in the QC-LDPC codebook of M rows and N columns, generate an identity matrix of Z rows and Z columns according to the lifting value Z, according to the cell value
  • the unit matrix is cyclically shifted to generate a parity check matrix of M*Z rows of N*Z columns and a submatrix size of Z.
  • N is the number of columns of the base matrix in the QC-LDPC codebook
  • Q is the number of columns of the check digit
  • Z is the boost value
  • H is the parity check matrix
  • s and p are combined to obtain the LDPC code sequence .
  • the sending module 53 is configured to: use the LDPC code sequence as data to be sent; or remove at least one column of information bits in the LDPC code sequence as data to be sent.
  • the QC-LDPC codebook is:
  • the same set of LDPC codebooks can be used for the uplink channel and the downlink channel, which reduces the complexity of the system design.
  • the embodiment of the present application further provides a data transmission device, including: a processor; a transmission device configured to perform data transceiving communication according to control of the processor; and a memory configured to store the processor executable instruction.
  • the processor is configured to: obtain a QC-LDPC codebook, and determine a parity check matrix according to the QC-LDPC codebook; wherein, for the uplink channel and the downlink channel, the same QC-LDPC codebook is used. And determining a parity bit according to the parity check matrix and the information sequence to be encoded, to obtain an LDPC code sequence; obtaining data to be transmitted according to the LDPC code sequence, and controlling the transmission device to send the to-be-sent data.
  • the processor is further configured to perform the following operations: before acquiring the QC-LDPC codebook, determining the QC-LDPC codebook according to the base matrix coefficient and the boost value.
  • the processor is further configured to perform the operation of selecting a QC-LDPC codebook that reduces the bit error rate from 0.01 to less than 10 -12 based on the base matrix coefficients and the boost values.
  • the base matrix coefficient is 8 rows and 40 columns, and the boost value is 200; or the base matrix coefficient is 6 rows and 26 columns, and the boost value is 512.
  • the processor is further configured to: perform, for each unit value in the QC-LDPC codebook of M rows and N columns, generate an identity matrix of Z rows and Z columns according to the lifting value Z, according to the The unit value cyclically shifts the unit matrix to generate a parity check matrix of M*Z rows N*Z columns and a submatrix size of Z.
  • the processor is further configured to: use the LDPC code sequence as data to be transmitted; or remove at least one column of information bits in the LDPC code sequence as data to be transmitted.
  • the information bit portion is 20 columns
  • the processor is further configured to perform the operation of removing the first two columns of the information bit portions of the LDPC code sequence as data to be transmitted.
  • the QC-LDPC codebook is:
  • the embodiment of the present application further provides a computer readable storage medium storing computer executable instructions, the computer executable instructions being set to perform the LDPC encoding method.
  • the embodiment of the present application further provides a computer readable storage medium storing computer executable instructions, the computer executable instructions being set to perform the data sending method.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.
  • ROM read-only memory
  • RAM random access memory
  • mobile hard disk a magnetic disk
  • optical disk a variety of media that can store program code.
  • modules or steps of the embodiments of the present application may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices. For example, they may be implemented in program code executable by a computing device such that they may be stored in a storage device for execution by a computing device and, in some instances, may be performed in a different order than that illustrated herein. Or the steps described, either separately as an integrated circuit module, or as a plurality of modules or steps in a single integrated circuit module. Thus, embodiments of the present application are not limited to any particular combination of hardware and software.

Abstract

本申请实施例公开了一种LDPC编码的方法、装置及数据发送的方法、装置，其中，所述LDPC编码的方法，包括：获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。

Description

一种LDPC编码的方法、装置及数据发送的方法、装置
本申请要求在2018年01月05日提交中国专利局、申请号为201810011064.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，例如一种低密度奇偶校验码(Low Density Parity Check Code，LDPC)的编码方法、装置、LDPC编码及数据发送的方法、装置和数据传输设备。
背景技术
以太网无源光网络(Ethernet Passive Optical Network，EPON)/吉比特容量无源光网络(Gigabit-Capable Passive Optical Network，GPON)上行信道与下行信道通常使用RS(255，223)或者RS(255，239)的编码方式，但是随着50Gbps EPON/GPON系统引进LDPC编码，下行信道与上行信道会根据各自的业务需求，设计两套独立的LDPC码本。下行信道是高速连续业务，主要需求是获得更高的编码增益，因此块长较大的码本可以满足下行信道的业务需求；上行信道是突发时延敏感业务，主要需求是光网络单元(Optical Network Unit，ONU)编码简单、端到端编解码时延短，因此可以稍微牺牲一点编码增益，采用块长较小的码本以换取更短的时延和更低的复杂度。
但是，上行信道和下行信道各自设计一套LDPC编解码码本，会要求光线路终端(Optical Line Terminal，OLT)和ONU在发射端、接收端设计两套不同的编解码系统，增加了系统设计的难度。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供了一种LDPC的编码方法、装置、LDPC编码及数据发送的方法、装置和数据传输设备，以降低系统设计难度。
本申请实施例提供了一种LDPC编码的方法，包括：获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
本申请实施例还提供了一种LDPC编码的装置，包括：确定模块，设置为获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；LDPC编码模块，设置为根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
本申请实施例还提供了一种LDPC编码器，包括：处理器；存储器，设置为存储所述处理器可执行指令；其中，所述处理器设置为执行以下操作：获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
本申请实施例还提供了一种数据发送的方法，包括：获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列；根据所述LDPC编码序列得到待发送数据，将所述待发送数据发送出去。
本申请实施例还提供了一种数据发送的装置，包括：确定模块，设置为获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；LDPC编码模块，设置为根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列；发送模块，设置为根据LDPC编码序列得到待发送数据，将所述待发送数据发送出去。
本申请实施例还提供了一种数据传输设备，包括：处理器；传输装置，设置为根据所述处理器的控制进行数据收发通信；存储器，设置为存储所述处理器可执行指令；其中，所述处理器设置为执行以下操作：获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列；根据LDPC编码序列得到待发送数据，控制所述传 输装置将所述待发送数据发送出去。
本申请实施例还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行本申请实施例中的LDPC编码的方法。
本申请实施例还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行本申请实施例中的数据发送方法。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本申请实施例的LDPC编码的方法的流程图；
图2为本申请实施例的数据发送的方法的流程图；
图3为示例实施例一中8*40*200的QC-LDPC码本的编码增益示意图；
图4为本申请实施例的LDPC编码的装置的示意图；
图5为本申请实施例的数据发送的装置的示意图。
具体实施方式
下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
如图1所示，本申请实施例的LDPC编码的方法，包括步骤101和步骤102。
在步骤101中，获取准循环低密度奇偶校验码(Quasi Cyclic Low Density Parity Check Code，QC-LDPC)码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本。
在一实施例中，本步骤包括：针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
在步骤102中，根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
在一实施例中，本步骤包括：选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；将s和p合并，得到LDPC编码序列。
在本申请实施例中，上行信道与下行信道可以使用同一套LDPC码本，降低了系统设计的复杂度。
在一实施例中，所述步骤101之前，还包括：根据基础矩阵系数和提升值确定QC-LDPC码本。
其中，基础矩阵系数包括行数和列数，提升值为子矩阵的大小。
在一实施例中，所述基础矩阵系数为8行40列，所述提升值为200；或者所述基础矩阵系数为6行26列，所述提升值为512。
也就是说，所述QC-LDPC码本为8*40*200的码本，或者，为6*26*512的码本。
对于LDPC的大码本方案，其比特数通常在18K或更多，这种方案计算复杂度高，译码处理时延较大，有10us左右，对于时延敏感的高速业务，是不可接受的。本申请实施例采用8*40*200的码本，或者，为6*26*512的码本，其码本长度限定在8000到12288比特之间，复杂度只是18K码本的2/3～1/2，时延是18K码本的1/2～1/3，降低了复杂度和时延，同时适用于下行信道和上行信道。
在一实施例中，所述根据基础矩阵系数和提升值Z确定QC-LDPC码本，包括：
根据基础矩阵系数和提升值，选择将误码率从0.01降至10 -12以下的QC-LDPC码本。
采用LDPC编码是为了降低误码率，不同的码本降低误码率的效果不同，可以采用计算机仿真的方式，对多个码本进行仿真实验，确定能够将误码率从0.01降至10 -12以下的QC-LDPC码本。
在一实施例中，采用的QC-LDPC码本为：
97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1
99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1
-1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1
105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1
70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1
68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1
69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1
81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
这种码本为8*40*200码本。
或者采用的QC-LDPC码本为：
0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1
410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1
37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1
21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1
259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0
353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
这种码本为6*26*512码本。
如图2所示，本申请实施例的数据发送的方法，包括步骤201，步骤202和步骤203。
在步骤201中，获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本。
在步骤202中，根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
在步骤203中，根据LDPC编码序列得到待发送数据，将所述待发送数据发送出去。
其中，步骤201～202与步骤101～102相同，不再赘述。
在一实施例中，所述步骤203中，所述根据LDPC编码序列得到待发送数据，包括：将所述LDPC编码序列作为待发送数据；或者将所述LDPC编码序列中的信息位部分去掉至少一列，作为待发送数据。
在一实施例中，所述信息位部分为20列，所述将所述LDPC编码序列中的信 息位部分去掉至少一列，作为待发送数据，包括：
将所述LDPC编码序列中信息位部分中的前两列去掉，作为待发送数据。
其中，针对6*26*512码本，信息位部分为前20列，校验位部分为后6列，传输数据时，最前2列的信息位部分不传输，这种方式称为凿孔，通过这种方式，能够提高码率，将码率从0.77提高到0.83。
下面以示例实施例进行说明。
示例实施例一
选择8*40*200的QC-LDPC码本，将误码率(Bit Error Rate，BER)从0.01纠正到10 -12以下。奇偶校验矩阵即H矩阵大小为8行40列，子矩阵大小为200；其中H矩阵的前32列为信息位，后8列对应于校验位，上行信道和下行信道使用同样的码本，复杂度只是18K码本的1/2。
8*40*200的QC-LDPC码本为：
97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1
99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1
-1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1
105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1
70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1
68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1
69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1
81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
将(40-8)*200＝6400bit的待编码信息序列作为一个矢量s，根据[s，p]*H T＝0，计算得到校验位p，p是一个8*200＝1600bit的矢量，将s和p合并，得到LDPC编码序列，完成编码过程。
传输数据时，将所述LDPC编码序列作为待发送数据，发送出去。
如图3所示，为采用上述码本的编码增益示意图，其中，EbN0为信噪比，从图中可以看出，当没有编码的原始数据的BER为0.01时，经过LDPC编码后，可以将BER纠正至10 -12以下。
示例实施例二
选择6*26*512的QC-LDPC码本，将BER从0.01纠正到10 -12以下。奇偶校验矩 阵即H矩阵大小为6行26列，子矩阵大小为512；其中H矩阵的前20列为信息位，后6列对应于校验位，支持信息长度为10K，码率为0.77。上行信道和下行信道使用同样的码本，复杂度只是18K码本的2/3。
6*26*512的QC-LDPC码本为：
0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1
410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1
37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1
21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1
259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0
353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
将(26-6)*512＝10240bit的待编码信息序列作为一个矢量s，根据[s，p]*H T＝0，计算得到校验位p，p是一个6*512＝3072bit的矢量，将s和p合并，得到LDPC编码序列，完成编码过程。
传输数据时，将所述LDPC编码序列作为待发送数据，发送出去。
示例实施例三
本示例实施例中，采用示例实施例二中的QC-LDPC码本，传输时，最前2列的信息比特部分不传输。信息比特512*20＝10240比特通过LDPC编码获得512*26＝13312比特；第512*2+1比特开始到末尾的所有比特是实际传输的比特，数目为512*24＝12288。支持信息长度为512*20＝10240(10K)；这样通过凿孔的方式，可以将码率从0.77提高为0.83。
需要说明的是，本示例实施例中，虽然最前2列的信息比特部分不传输，由于采用了LDPC编码，在解码时，仍然可以将最前2列的信息比特部分解码出来，并不会影响数据传输的效果。
本申请实施例还提供一种LDPC编码的装置，该装置设置为实现上述实施例及实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和硬件中至少一种的组合。尽管以下实施例所描述的装 置可以以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
如图4所示，本申请实施例的LDPC编码的装置，包括确定模块41和LDPC编码模块42。
确定模块41，设置为获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本。
LDPC编码模块42，设置为根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
在一实施例中，所述装置还包括：QC-LDPC码本模块，设置为根据基础矩阵系数和提升值确定QC-LDPC码本。
在一实施例中，所述QC-LDPC码本模块，设置为根据基础矩阵系数和提升值，选择将误码率从0.01降至10 -12以下的QC-LDPC码本。
在一实施例中，所述基础矩阵系数为8行40列，所述提升值为200；或者所述基础矩阵系数为6行26列，所述提升值为512。
在一实施例中，所述确定模块41，设置为：针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
在一实施例中，所述LDPC编码模块42，设置为：选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；将s和p合并，得到LDPC编码序列。
在一实施例中，所述QC-LDPC码本为：
97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1
99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1
-1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1
105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1
70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1
68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1
69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1
81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
或者
0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1
410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1
37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1
21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1
259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0
353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
在本申请实施例中，上行信道与下行信道可以使用同一套LDPC码本，降低了系统设计的复杂度。
本申请实施例还提供一种LDPC编码器，包括：处理器；存储器，设置为存储所述处理器可执行指令.
其中，所述处理器设置为执行以下操作：获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
在一实施例中，所述处理器还设置为执行以下操作：所述获取QC-LDPC码本之前，根据基础矩阵系数和提升值确定QC-LDPC码本。
在一实施例中，所述处理器还设置为执行以下操作：根据基础矩阵系数和提升值，选择将误码率从0.01降至10 -12以下的QC-LDPC码本。
在一实施例中，所述基础矩阵系数为8行40列，所述提升值为200；或者所述基础矩阵系数为6行26列，所述提升值为512。
在一实施例中，所述处理器还设置为执行以下操作：针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
在一实施例中，所述处理器还设置为执行以下操作：选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；将s和p合并，得到LDPC编码序列。
在一实施例中，所述QC-LDPC码本为：
97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1
99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1
-1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1
105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1
70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1
68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1
69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1
81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
或者
0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1
410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1
37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1
21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1
259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0
353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
本申请实施例还提供一种数据发送的装置，该装置设置为实现上述实施例及实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和硬件中至少一种的组合。尽管以下实施例所描述的装置可以以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
如图5所示，本申请实施的数据发送的装置，包括确定模块51，LDPC编码模块52和发送模块53。
确定模块51，设置为获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本。
LDPC编码模块52，设置为根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
发送模块53，设置为根据LDPC编码序列得到待发送数据，将所述待发送数据发送出去。
在一实施例中，所述确定模块51，设置为：针对M行N列的QC-LDPC码本中 每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
在一实施例中，所述LDPC编码模块52，设置为：选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；将s和p合并，得到LDPC编码序列。
在一实施例中，所述发送模块53，设置为：将所述LDPC编码序列作为待发送数据；或者将所述LDPC编码序列中的信息位部分去掉至少一列，作为待发送数据。
在一实施例中，所述QC-LDPC码本为：
97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1
99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1
-1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1
105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1
70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1
68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1
69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1
81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
或者
0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1
410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1
37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1
21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1
259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0
353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
在本申请实施例中，上行信道与下行信道可以使用同一套LDPC码本，降低了系统设计的复杂度。
本申请实施例还提供一种数据传输设备，包括：处理器；传输装置，设置为根据所述处理器的控制进行数据收发通信的；存储器，设置为存储所述处理器可执行指令。
其中，所述处理器设置为执行以下操作：获取QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的QC-LDPC码本；根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列；根据LDPC编码序列得到待发送数据，控制所述传输装置将所述待发送数据发送出去。
在一实施例中，所述处理器还设置为执行以下操作：所述获取QC-LDPC码本之前，根据基础矩阵系数和提升值确定QC-LDPC码本。
在一实施例中，所述处理器还设置为执行以下操作：根据基础矩阵系数和提升值，选择将误码率从0.01降至10 -12以下的QC-LDPC码本。
在一实施例中，所述基础矩阵系数为8行40列，所述提升值为200；或者所述基础矩阵系数为6行26列，所述提升值为512。
在一实施例中，所述处理器还设置为执行以下操作：针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
在一实施例中，所述处理器还设置为执行以下操作：选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；将s和p合并，得到LDPC编码序列。
在一实施例中，所述处理器还设置为执行以下操作：将所述LDPC编码序列作为待发送数据；或者将所述LDPC编码序列中的信息位部分去掉至少一列，作为待发送数据。
在一实施例中，所述信息位部分为20列，所述处理器还设置为执行以下操作：将所述LDPC编码序列中的信息位部分中的前两列去掉，作为待发送数据。
在一实施例中，所述QC-LDPC码本为：
97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1
99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1
-1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1
105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1
70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1
68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1
69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1
81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
或者
0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1
410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1
37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1
21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1
259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0
353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
本申请实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行所述LDPC编码的方法。
本申请实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行所述数据发送的方法。
在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的技术人员应该明白，上述的本申请实施例的模块或步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上。例如，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本申请实施例不限制于任何特定的硬件和软件结合。

Claims (29)

  1. 一种低密度奇偶校验码LDPC编码的方法，包括：
    获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的所述QC-LDPC码本；
    根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
  2. 如权利要求1所述的方法，所述获取QC-LDPC码本之前，还包括：
    根据基础矩阵系数和提升值确定所述QC-LDPC码本。
  3. 如权利要求2所述的方法，其中，所述根据基础矩阵系数和提升值确定所述QC-LDPC码本，包括：
    根据所述基础矩阵系数和提升值，选择将误码率从0.01降至10 -12以下的QC-LDPC码本。
  4. 如权利要求2所述的方法，其中，
    所述基础矩阵系数为8行40列，所述提升值为200；或者
    所述基础矩阵系数为6行26列，所述提升值为512。
  5. 如权利要求1所述的方法，其中，所述根据所述QC-LDPC码本确定奇偶校验矩阵，包括：
    针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
  6. 如权利要求1所述的方法，其中，所述根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列，包括：
    选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；
    将s和p合并，得到LDPC编码序列。
  7. 如权利要求1～6中任意一项所述的方法，其中，
    所述QC-LDPC码本为：
    97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1 99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1 -1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1
    105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1 70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1 68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1 69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1 81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
    或者所述QC-LDPC码本为：
    0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1 37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1 21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1 259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0 353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
    。
  8. 一种低密度奇偶校验码LDPC编码的装置，包括：
    确定模块，设置为获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的所述QC-LDPC码本；
    LDPC编码模块，设置为根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
  9. 如权利要求8所述的装置，其中，所述确定模块，设置为：
    针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
  10. 如权利要求8所述的装置，其中，所述LDPC编码模块，设置为：
    选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；
    将s和p合并，得到LDPC编码序列。
  11. 如权利要求8～10中任意一项所述的装置，其中，
    所述QC-LDPC码本为：
    97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1 99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1 -1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1 105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1 70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1 68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1 69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1 81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
    或者所述QC-LDPC码本为：
    0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1 37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1 21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1 259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0 353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
    。
  12. 一种低密度奇偶校验码LDPC编码器，包括：
    处理器；
    存储器，设置为存储所述处理器可执行指令；
    其中，所述处理器设置为执行以下操作：
    获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的所述QC-LDPC码本；
    根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列。
  13. 一种数据发送的方法，包括：
    获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的所述QC-LDPC码本；
    根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到低密度奇偶校验码LDPC编码序列；
    根据所述LDPC编码序列得到待发送数据，将所述待发送数据发送出去。
  14. 如权利要求13所述的方法，所述获取QC-LDPC码本之前，还包括：
    根据基础矩阵系数和提升值确定所述QC-LDPC码本。
  15. 如权利要求14所述的方法，其中，所述根据基础矩阵系数和提升值确定所述QC-LDPC码本，包括：
    根据基础矩阵系数和提升值，选择将误码率从0.01降至10 -12以下的QC-LDPC码本。
  16. 如权利要求14所述的方法，其中，
    所述基础矩阵系数为8行40列，所述提升值为200；或者
    所述基础矩阵系数为6行26列，所述提升值为512。
  17. 如权利要求13所述的方法，其中，所述根据所述QC-LDPC码本确定奇偶校验矩阵，包括：
    针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
  18. 如权利要求13所述的方法，其中，所述根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列，包括：
    选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；
    将s和p合并，得到LDPC编码序列。
  19. 如权利要求13所述的方法，其中，所述根据所述LDPC编码序列得到待发送数据，包括：
    将所述LDPC编码序列作为待发送数据；或者
    将所述LDPC编码序列中的信息位部分去掉至少一列，作为待发送数据。
  20. 如权利要求19所述的方法，其中，所述信息位部分为20列，所述将所述LDPC编码序列中的信息位部分去掉至少一列，作为待发送数据，包括：
    将所述LDPC编码序列中的信息位部分中的前两列去掉，作为待发送数据。
  21. 如权利要求13～20中任意一项所述的方法，其中，
    所述QC-LDPC码本为：
    97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1 99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1 -1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1 105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1 70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1 68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1 69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1 81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
    或者所述QC-LDPC码本为：
    0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1 37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1 21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1 259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0 353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
    。
  22. 一种数据发送的装置，包括：
    确定模块，设置为获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的所述QC-LDPC码本；
    低密度奇偶校验码LDPC编码模块，设置为根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到LDPC编码序列；
    发送模块，设置为根据LDPC编码序列得到待发送数据，将所述待发送数据发送出去。
  23. 如权利要求22所述的装置，其中，所述确定模块，设置为：
    针对M行N列的QC-LDPC码本中每个单元值，根据提升值Z生成Z行Z列的单位矩阵，根据所述单元值对所述单位矩阵进行循环右移位，生成M*Z行N*Z列，子矩阵大小为Z的奇偶校验矩阵。
  24. 如权利要求22所述的装置，其中，所述LDPC编码模块，设置为：
    选择(N-Q)*Z比特的待编码信息序列作为矢量s，根据[s，p]*H T＝0，计算得到校验位p，其中，N为所述QC-LDPC码本中基础矩阵的列数，Q为校验位的列数，Z为提升值，H为奇偶校验矩阵；
    将s和p合并，得到LDPC编码序列。
  25. 如权利要求22所述的装置，其中，所述发送模块，设置为：
    将所述LDPC编码序列作为待发送数据；或者
    将所述LDPC编码序列中的信息位部分去掉至少一列，作为待发送数据。
  26. 如权利要求22～25中任意一项所述的装置，其中，
    所述QC-LDPC码本为：
    97 -1 -1 49 -1 44 60 -1 24 -1 -1 44 -1 106 102 -1 -1 -1 123 -1 10 -1 41 16 -1 24 32 -1 43 21 -1 104 1 0 -1 -1 -1 -1 -1 -1 99 10 -1 50 -1 6 -1 -1 -1 101 29 49 97 -1 61 112 79 -1 -1 45 25 -1 44 -1 30 -1 -1 67 -1 -1 -1 97 -1 0 0 -1 -1 -1 -1 -1 -1 79 101 -1 -1 -1 121 26 -1 -1 59 -1 115 77 119 -1 113 -1 -1 -1 16 113 -1 101 8 -1 -1 77 -1 28 1 -1 0 -1 0 0 -1 -1 -1 -1 105 60 -1 123 13 85 -1 55 75 -1 -1 -1 -1 104 -1 113 -1 107 119 120 -1 107 -1 -1 -1 93 -1 107 38 -1 44 -1 -1 -1 -1 0 0 -1 -1 -1 70 34 107 -1 24 -1 117 -1 89 58 26 63 -1 -1 -1 111 105 85 -1 -1 -1 -1 61 86 -1 -1 43 -1 59 -1 77 -1 -1 -1 -1 -1 0 0 -1 -1 68 88 124 -1 83 -1 -1 42 -1 87 -1 -1 112 -1 -1 -1 -1 88 127 114 -1 89 -1 -1 82 85 42 -1 -1 30 -1 100 1 -1 -1 -1 -1 0 -1 -1 69 102 70 36 -1 -1 100 -1 82 -1 24 -1 -1 99 107 -1 -1 8 -1 36 -1 19 47 -1 71 22 8 -1 -1 20 -1 99 8 -1 -1 -1 -1 -1 0 -1 81 37 26 28 13 42 -1 -1 111 -1 22 -1 102 101 90 -1 -1 81 -1 108 13 45 44 -1 26 40 9 118 13 54 -1 98 22 -1 -1 -1 -1 -1 -1 0
    或者所述QC-LDPC码本为：
    0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 410 475 0 -1 0 0 0 0 0 0 0 -1 -1 0 0 0 -1 0 0 0 -1 0 0 -1 -1 -1 37 -1 332 0 10 65 -1 426 254 117 -1 0 0 -1 263 162 0 306 -1 501 256 -1 0 0 -1 -1 21 497 -1 390 -1 -1 -1 -1 -1 -1 -1 -1 62 -1 -1 -1 322 -1 -1 -1 -1 -1 -1 0 0 -1 259 374 406 96 -1 353 228 -1 -1 461 292 355 310 358 -1 144 339 -1 417 312 -1 -1 -1 -1 0 0 353 171 -1 258 70 -1 185 421 365 -1 448 337 260 29 302 -1 17 457 97 -1 0 -1 -1 -1 -1 0
    。
  27. 一种数据传输设备，包括：
    处理器；
    传输装置，设置为根据所述处理器的控制进行数据收发通信；
    存储器，设置为存储所述处理器可执行指令；
    其中，所述处理器设置为执行以下操作：
    获取准循环低密度奇偶校验码QC-LDPC码本，根据所述QC-LDPC码本确定奇偶校验矩阵；其中，对于上行信道和下行信道，采用相同的所述QC-LDPC码本；
    根据所述奇偶校验矩阵和待编码信息序列确定校验位，得到低密度奇偶校验码LDPC编码序列；
    根据所述LDPC编码序列得到待发送数据，控制所述传输装置将所述待发送数据发送出去。
  28. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行权利要求1-7任一项所述的低密度奇偶校验码LDPC编码的方法。
  29. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行权利要求13-21任一项所述的数据发送的方法。
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