WO2019130859A1 - Method for producing photoelectric conversion element, tool for plating, and plating apparatus - Google Patents

Method for producing photoelectric conversion element, tool for plating, and plating apparatus Download PDF

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Publication number
WO2019130859A1
WO2019130859A1 PCT/JP2018/041838 JP2018041838W WO2019130859A1 WO 2019130859 A1 WO2019130859 A1 WO 2019130859A1 JP 2018041838 W JP2018041838 W JP 2018041838W WO 2019130859 A1 WO2019130859 A1 WO 2019130859A1
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Prior art keywords
plating
photoelectric conversion
layer
conductive layer
conversion element
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PCT/JP2018/041838
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French (fr)
Japanese (ja)
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恒 宇津
足立　大輔
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株式会社カネカ
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Priority to JP2019562825A priority Critical patent/JP7337703B2/en
Publication of WO2019130859A1 publication Critical patent/WO2019130859A1/en

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/06—Suspending or supporting devices for articles to be coated
    • C25D17/08—Supporting racks, i.e. not for suspending
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the method further includes the step of forming the first conductive layer as N (where 2 ⁇ N) or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side. (10) The method for producing a photoelectric conversion device according to any one of (10) to (10).
  • the present invention is also a plating apparatus provided with the plating jig according to (13).
  • FIG. 1 is a plan view showing the surface side (light receiving surface side) of a photoelectric conversion element 100 formed by the manufacturing method of the present invention.
  • FIG. 2 is a cross-sectional view showing a cross section taken along line III-III in FIG.
  • the boundary is described between the semiconductor substrate 101 and the p-type semiconductor layer 103a and the n-type semiconductor layer 103b.
  • the semiconductor substrate 101 itself is an n-type semiconductor or p-type.
  • the semiconductor device may be a semiconductor and may have no boundary between the semiconductor substrate 101 and the p-type semiconductor layer 103a or between the semiconductor substrate 101 and the n-type semiconductor layer 103b.
  • a first conductive layer 107-1 is provided in the formation region of the collector electrode 107 on the first main surface side of the p-type semiconductor layer 103a.
  • the base electrode layer in the shape of a thin wire electrode including the bus bar electrode and the finger electrode shown in FIG. 1 is used as the first conductive layer 107-1.
  • a plating layer 107-2 is provided on the first main surface side of the first conductive layer 107-1.
  • the plated layer 107-2 and the first conductive layer 107-1 constitute a collector electrode including the surface side bus bar electrode and the finger electrode shown in FIG.
  • the semiconductor substrate 101 is an n-type semiconductor substrate.
  • a first transparent electrode layer 106a is included between the first conductive layer 107-1 and the p-type semiconductor layer 103a.
  • the back surface side of the n-type semiconductor layer 103 b is configured to further include a second transparent electrode layer 106 b and a back surface metal electrode as the second conductive layer 108.
  • the thickness of the single crystal silicon substrate used for the semiconductor substrate 101 is preferably 50 to 300 ⁇ m, more preferably 60 to 200 ⁇ m, and still more preferably 70 to 180 ⁇ m. By using a substrate with a film thickness in this range, the material cost can be further reduced.
  • the first main surface and the second main surface side of the semiconductor substrate 101 have a passivation layer.
  • the passivation layer can suppress carrier recombination and it may be of any type as long as it can terminate surface defects, but an intrinsic semiconductor layer, in particular, an intrinsic amorphous silicon layer is preferably used.
  • the film forming method of the p-type semiconductor layer 103 a is not particularly limited, for example, a CVD method (Chemical Vapor Deposition) can be used.
  • a CVD method Chemical Vapor Deposition
  • SiH 4 gas is used, and B 2 H 6 diluted with hydrogen is preferably used as the dopant addition gas.
  • the addition amount of the dopant impurity may be a very small amount, it is preferable to use a mixed gas diluted with SiH 4 or H 2 in advance.
  • the energy gap of the silicon-based thin film is obtained by alloying the silicon-based thin film by adding a gas containing different elements such as CH 4 , CO 2 , NH 3 , GeH 4 or the like at the time of forming the p-type semiconductor layer 103 a. You can change it. Further, in order to improve the light transmittance, a small amount of an impurity such as oxygen or carbon may be added. In that case, it can be formed by introducing a gas such as CO 2 and CH 4 in the CVD film forming.
  • the first principal surface side of the semiconductor substrate 101 is already the p-type semiconductor layer 103a, and the p-type semiconductor layer 103a is in the semiconductor substrate 101. Will be included in In this case, the step of forming the p-type semiconductor layer 103a is unnecessary.
  • Step of forming n-type semiconductor layer 103b is formed on the second main surface side, that is, the back surface side of the semiconductor substrate 101.
  • the step of forming the n-type semiconductor layer 103b may be performed before the step of forming the p-type semiconductor layer 103a described above, or may be performed after the step of forming the p-type semiconductor layer 103a.
  • amorphous silicon layer containing an amorphous component such as an amorphous silicon thin film or a microcrystalline silicon thin film.
  • P (phosphorus) or the like can be used as the dopant impurity.
  • the film forming method of the n-type semiconductor layer 103 b is not particularly limited, for example, a CVD method (Chemical Vapor Deposition) can be used.
  • a CVD method Chemical Vapor Deposition
  • SiH 4 gas is used, and PH 3 diluted with hydrogen is preferably used as the dopant addition gas.
  • the addition amount of the dopant impurity may be a very small amount, it is preferable to use a mixed gas diluted with SiH 4 or H 2 in advance.
  • the energy gap of the silicon-based thin film is obtained by alloying the silicon-based thin film by adding a gas containing different elements such as CH 4 , CO 2 , NH 3 , GeH 4 or the like at the time of forming the n-type semiconductor layer 103 b. You can change it. Further, in order to improve the light transmittance, a small amount of an impurity such as oxygen or carbon may be added. In that case, it can be formed by introducing a gas such as CO 2 and CH 4 in the CVD film forming.
  • the n-type semiconductor layer 103b is formed by diffusing an n-type dopant into the second main surface side of the semiconductor substrate 101 to make it n-type.
  • a first transparent electrode layer 106a is formed on the first principal surface side of the p-type semiconductor layer 103a by sputtering, MOCVD, etc., and a second transparent electrode layer is formed on the second principal surface side of the n-type semiconductor layer 103b.
  • the transparent electrode layer 106 b is formed.
  • the step of forming the first transparent electrode layer 106a may be after the step of forming the p-type semiconductor layer 103a, and may be before the step of forming the n-type semiconductor layer 103b.
  • the second transparent electrode layer 106b forming step may be after the n-type semiconductor layer 103b forming step, and may be before the p-type semiconductor layer 103a forming step.
  • transparent conductive metal oxides such as indium oxide, zinc oxide, tin oxide, titanium oxide, and composite oxides thereof can be used. . Further, it may be a non-metallic transparent conductive material such as graphene.
  • an indium-based composite oxide containing indium oxide as a main component as the first transparent electrode layer 106 a and the second transparent electrode layer 106 b.
  • a dopant added to indium oxide As an impurity used as a dopant, Sn, W, Ce, Zn, As, Al, Si, S, Ti etc. are mentioned.
  • the second conductive layer 108 is formed on the second transparent electrode layer 106 b.
  • the second conductive layer 108 may be a back surface metal electrode as shown in FIG. 2.
  • Examples of a method of forming the second conductive layer 108 include a sputtering method, a vapor deposition method, and a plating method. From the viewpoint of easy formation on almost the entire surface of the side, it is preferable to form by sputtering. In the case of forming a film on the back surface metal electrode by sputtering, it is preferable because it can be coated with high accuracy.
  • the concavo-convex portion can be covered with high precision, which is more preferable.
  • a material of such a back surface metal electrode Ti, Cr, Ni, Sn, Ag, Cu etc. are preferable.
  • the second conductive layer may use the second transparent electrode layer 106b (106b in FIG. 2 and 206b in FIG. 4) as it is as the second conductive layer, as shown by 208 in FIG. It may be a collector.
  • second transparent electrode layer 106 b is in contact with the plating power supply electrode on substantially the entire second main surface of photoelectric conversion element 100. Therefore, the in-plane uniformity of the mark overvoltage is high at the time of plating. Further, referring to FIG.
  • the thin wire electrode has mirror symmetry in the first conductive layer 207-1 and the second conductive layer 208, or the number of finger electrodes of the second conductive layer 208 is greater than that of the first conductive layer 207-1.
  • the current at the time of plating mainly moves vertically between the collecting electrodes, so that the in-plane uniformity becomes higher.
  • FIG. 4 the photoelectric conversion element 200, the semiconductor substrate 201, the intrinsic silicon based thin films 202a and 202b, the conductive silicon based thin films 203a and 203b, the collector electrode 207, and the plating layer 207-2 are illustrated.
  • Ni, Cu, Ag, Au, Pt, or an alloy thereof can be used as a material of the thin wire electrode forming the second conductive layer 208 formed of a thin wire electrode, but it can function as an underlayer in electrolytic plating. It is not particularly limited as long as it has a certain degree of conductivity.
  • a method of forming the second conductive layer 208 composed of fine line electrodes for example, using an inkjet method, a screen printing method, a wire bonding method, a spray method, a vacuum evaporation method, a sputtering method, an electrolytic plating method, an electroless plating method, etc. Can. From the viewpoint of cost and mass productivity, it is preferable to print the paste containing the material of the first conductive layer described above by screen printing.
  • a first conductive layer 107-1 is formed in the formation region of the collector electrode on the first main surface side of the first transparent electrode layer 106a. That is, the first conductive layer 107-1 is formed on the first transparent electrode layer 106a.
  • the first conductive layer 107-1 is a layer that functions as a conductive underlayer in the step of forming a plated layer 107-2 described later, and is a layer that becomes an electrode for depositing the plated layer 107-2.
  • the step of forming the first conductive layer 107-1 is performed after the step of forming the p-type semiconductor layer 103a, and when the first transparent electrode layer 106a is provided, it is performed after the step of forming the first transparent electrode layer 106a.
  • the step of forming the first conductive layer 107-1 may be performed before the step of forming the n-type semiconductor layer 102b.
  • the first conductive layer 107-1 for example, an inkjet method, a screen printing method, a wire bonding method, a spray method, a vacuum evaporation method, a sputtering method, an electrolytic plating method, an electroless plating method, etc. can be used. . From the viewpoint of cost and mass productivity, it is preferable to print the paste containing the material of the first conductive layer described above by screen printing.
  • the uncompleted photoelectric conversion element in which the first conductive layer 107-1 is formed is a diode in the direction perpendicular to the main surface, and the first conductive layer 107-1 to the second conductive layer 108 The direction is the forward direction of the diode.
  • the insulating layer 109 is formed on the first main surface side of the first transparent electrode layer 106 a to form an incomplete photoelectric conversion element 100 ⁇ / b> A.
  • the step of forming the insulating layer 109 may be performed either before or after the step of forming the first conductive layer 107-1 and may be performed before the step of forming the n-type semiconductor layer 103b.
  • the insulating layer 109 may be formed of a layer that can be removed by satisfying a predetermined condition, such as a photoresist material.
  • a predetermined condition such as a photoresist material.
  • light irradiation causes a structural change, which makes it easy to be dissolved by a specific chemical.
  • the photoresist material used to form the insulating layer 109 is not particularly limited as long as it has the above-mentioned properties, but a positive type novolac resin, a phenol resin etc., and a negative type acrylic resin etc. Can.
  • a removing solution for removing the insulating layer 109 for example, a solution containing tetramethyl ammonium hydroxide, alkyl benzene sulfonic acid, ethanolamines, sodium hydroxide or the like can be used.
  • a positive novolak resin is used as the photoresist material, and an aqueous sodium hydroxide solution is used as the removal solution.
  • the insulating layer 109 may be formed of an inorganic insulating film such as SiO, SiN, or SiON.
  • an inorganic insulating film such as SiO, SiN, or SiON.
  • CVD method film formation by the CVD method capable of precise film thickness control is preferable.
  • film quality control can be performed by controlling the material gas and film forming conditions.
  • the insulating layer 109 may be left in a completed product because light transmittance of the insulating film is good.
  • Step of Forming Plating Layer 107-2 the plating layer 107-2 is formed on the first main surface side of the first conductive layer 107-1.
  • the step of forming the plating layer 107-2 is performed after the step of forming the first conductive layer 107-1.
  • Ni, Cu, Ag, Au, Pt, or an alloy thereof can be used as a material of the plating layer 107-2.
  • Ni, Cu, Ag, Au, Pt, or an alloy thereof can be used as a material of the plating layer 107-2.
  • Cu is preferably used in terms of cost.
  • FIG. 8 is a schematic view showing an example of a state in which the incomplete photoelectric conversion element 100A is mounted on the substrate holder 114 at the time of plating.
  • the uncompleted photoelectric conversion element 100A is illustrated with the components other than the semiconductor substrate 101, the first conductive layer 107-1, and the second conductive layer 108 omitted for simplification.
  • the substrate holder 114 has a back plate 114-1, and further has a plating feeding electrode 117 and a plating feeding wire 118 connected to the plating feeding electrode 117 on the back plate.
  • the uncompleted photoelectric conversion element 100A is disposed on the plating feeding electrode 117, and the packing 114-2 is brought into close contact with both the back plate 114-1 and the uncompleted photoelectric conversion element 100A, and the frame 114-4 is fastened Fix with the tool 114-3.
  • the plating power supply electrode 117 and the second conductive layer 108 do not come in contact with the plating solution, and the plating power supply electrode 117 and the second conductive layer 108 are electrically connected to the first conductive layer 107-1 through the plating solution. Can be prevented from being connected.
  • a low resistance electric circuit such as a plating solution is formed between the plating power supply electrode 117 and the first conductive layer 107-1 when a voltage is applied during plating. A sufficient voltage is applied to cause current to flow in the forward direction of the diode formed of the PN junction of the incomplete photoelectric conversion element 100A.
  • the plating power supply electrode 117 and the second conductive layer 108 do not contact the plating solution, and the first conductive layer 107-1 contacts the plating solution. Any structure may be used as long as the condition is satisfied. For example, as shown in FIG. 10, when the substrate holder 214 is installed in a form to float on the surface of the plating solution 216, the back side of the substrate holder 214 is outside the plating solution 216, and the plating solution is There is no need to use a backboard since it does not come in contact with 216. Note that the substrate holder in FIG.
  • FIG. 10 is illustrated with packing and fasteners omitted for simplicity, and the incomplete photoelectric conversion element 200A is also illustrated with the exception of the semiconductor substrate and the first conductive layer 207-1. ing. Further, in FIG. 10, a plating apparatus 211, a plating tank 212, a plating electrode 213, a frame 214-4, a power supply 215, a plating power supply electrode 217, and a plating power supply wiring 218 are illustrated.
  • the plating feed electrode has a planar shape, and have an area equal to or larger than the area of the second conductive layer in the photoelectric conversion element 100.
  • the second conductive layer 108 using the back surface metal electrode shown in FIG. 3 or the above-mentioned second transparent electrode layer is used as the second conductive layer, the second entire surface of the photoelectric conversion element is substantially entirely A conductive layer is formed.
  • the planar plating power supply electrode having an area equal to or larger than the area of the second conductive layer is brought into contact so as to cover the entire second conductive layer, so that the photoelectric conversion element in the plane of the second conductive layer is supplied.
  • the influence of the potential difference caused by the electrical resistance in the direction can be suppressed, and a voltage is applied almost uniformly to the entire photoelectric conversion element.
  • the second conductive layer is formed of a thin wire electrode as shown in FIG. 4, it is preferable to contact the plating power supply electrode so as to cover the entire thin wire electrode in the second conductive layer 208.
  • the planar plating power supply electrode is preferably, for example, plate-like, but may have a pattern shape that covers only the thin wire electrode, or may be mesh-like.
  • the plating feed electrode it is preferable to use a bulk metal having a sufficient thickness so that the potential difference in the plating feed electrode does not become too large in the in-plane direction of the photoelectric conversion element. It is preferable to adjust the thickness according to the magnitude of the current value used in the process.
  • FIG. 9 is a conceptual view showing the step of forming the plating layer 107-2.
  • the incomplete photoelectric conversion element 100A after the step of forming the insulating layer 109 (FIG. 3) is immersed in the plating solution 116 in the plating tank 112.
  • a solution in which a metal salt is dissolved can be used as the plating solution 116, and specifically, a copper sulfate aqueous solution or the like in which copper sulfate is ionized can be used. That is, in the present embodiment, in the plating solution 116, copper ions and sulfate ions are ionized.
  • the substrate holder 114 in FIG. 9 is illustrated with packing and fasteners omitted for simplicity, and the incomplete photoelectric conversion element 100A is also illustrated with the exception of the semiconductor substrate and the first conductive layer 107-1. It shows.
  • the plating electrode 113 which is a conductor on a flat plate is disposed.
  • the plating electrode 113 is disposed to face the p-type base conductive layer 103 a.
  • the plating electrode 113 is formed of a single metal or metal alloy used for electrolytic plating. In the present embodiment, since copper sulfate is used as the plating solution 116, copper or the like can be used as the plating electrode 113.
  • the plating electrode 113 is connected to the positive electrode of the power source 115 and serves as an anode.
  • the plating electrode 113 has a size that covers substantially the entire surface of the semiconductor substrate of the incomplete photoelectric conversion element 100A.
  • the plating feed electrode 117 is connected to the negative electrode of the power supply 115 via the plating feed wire 118, and the second conductive layer 108 is fed through the plating feed electrode 117. At this time, the second conductive layer 108 and the first conductive layer 107-1 are electrically connected only by a diode including the n-type semiconductor layer 103b and the p-type semiconductor layer 103a.
  • the second conductive layer 108 and the first conductive layer 107-1 are not electrically connected to each other by the unnecessary conductive layer or the like in the configuration of the incomplete photoelectric conversion element 100A.
  • Both the plating power supply electrode 117 and the second conductive layer 108 are not electrically connected to the first conductive layer 107-1 via the plating solution 116.
  • the exposed surface of the first conductive layer 107-1 is shown in FIG.
  • the plated layer 107-2 is formed.
  • the diode configured to include the n-type semiconductor layer 103 b and the p-type semiconductor layer 103 a is a PN junction is illustrated, but the n-type semiconductor layer 103 b and the p-type semiconductor layer 103 a
  • the intrinsic semiconductor layer may be interposed therebetween, and the diode formed by the n-type semiconductor layer 103b, the intrinsic semiconductor layer, and the p-type semiconductor layer 103a may be a PIN junction.
  • the plating layer 108 on the According to the present invention, unlike the conventional method of manufacturing a solar cell in which feeding in plating is performed to the base electrode layer, the current applied during plating does not have to be increased stepwise, and the plating rate can be increased from the beginning. Manufacturing efficiency is increased. Furthermore, in the case where the plating voltage is applied unevenly on the first conductive layer 107-1, the portion where the mark overvoltage is low is unlikely to be plated.
  • the photoelectric conversion element 300 is shown.
  • a plating layer 307-2 is formed in contact with the transparent electrode layer 306a on the front surface side.
  • the second embodiment can be expected to reduce the manufacturing cost by adopting a structure in which the base electrode layer is not used as the first conductive layer.
  • the uncompleted photoelectric conversion element 300A in forming the photoelectric conversion element 300 is shown in FIG.
  • the first conductive layer 307-1 is formed of the first transparent electrode layer 306a, and is covered with the insulating layer 309 formed of the aforementioned photoresist material or the like.
  • the insulating layer 309 preferably has an opening, and the opening preferably has a pattern such as a thin wire electrode.
  • the other manufacturing method of the photoelectric conversion element in the present embodiment is manufactured by the same method as the manufacturing method according to the first embodiment.
  • the first conductive layer 307-1 is the first transparent electrode layer 306a
  • the height of the electrical resistance in the in-plane direction of the photoelectric conversion element makes the point as in the usual plating method.
  • the plating feeding electrode in contact with the second conductive layer 308 on the back surface side in a planar manner makes it possible to achieve high uniformity by interposing the diode formed of the PN junction of the incomplete photoelectric conversion element 300A.
  • a current can be supplied to the conductive layer 307-1 to form a uniform plating layer. 5 and 6, the incomplete photoelectric conversion element 300A, the semiconductor substrate 301, the intrinsic silicon-based thin films 302a and 302b, the conductive silicon-based thin films 303a and 303b, the second transparent electrode layer 306b, the collector electrode 307, and photoelectric conversion Unit 350 is shown.
  • FIG. 7 is a plan view showing the surface side of an incomplete photoelectric conversion element 400A formed by the manufacturing method of the present invention.
  • the incomplete photoelectric conversion element 400A four thin wire electrode regions capable of suggesting division into regions by dotted lines shown in the figure are formed by the first conductive layer 407-1, and a plurality of thin wire electrode regions are formed in each thin wire electrode region.
  • a bus bar electrode and a large number of finger electrodes provided to cross the bus bar electrode are included.
  • the design of the bus bar electrode and the finger electrode is not limited to that described above, and may be any design. Further, the bus bar electrode may not be provided, and only the finger electrode may be formed.
  • the thin wire electrode region may be a base electrode layer made of metal paste or the like, or the insulating layer may be a first transparent electrode layer having an opening on the thin wire electrode.
  • Each thin wire electrode region is isolated in appearance.
  • the base electrode layer is isolated in appearance and when the first conductive layer 407-1 is a first transparent electrode layer, the opening of the insulating layer Are isolated on the appearance.
  • the base electrode layer only needs to be isolated in appearance, and the first transparent electrode layer (not shown) formed on the semiconductor substrate 401 side from the base electrode layer It may be electrically connected.
  • the opening of the insulating layer may be isolated in appearance, and the first transparent electrode layer may be on the semiconductor substrate 401 side of the insulating layer, It may be formed over substantially the entire surface of the semiconductor substrate 401.
  • the plating layer formed after the plating step is isolated in appearance according to the first conductive layer 407-1.
  • four thin wire electrode regions that are isolated in appearance are formed, but in the present embodiment, the number of thin wire electrode regions is not limited as long as it is plural, and N (2 ⁇ N) Just do it.
  • the plating power supply electrode in planar contact with the second conductive layer on the back surface side of the uncompleted photoelectric conversion element 400A makes it possible to achieve uniformity by interposing the PN junction of the uncompleted photoelectric conversion element 400A. Therefore, current can flow to the first conductive layer 407-1 with high conductivity, and a uniform plating layer is formed.
  • the thin wire electrode region isolated in appearance is divided, for example, by the dotted line portion shown in the figure, and a plurality of photoelectric conversion elements are formed It is also good.
  • segment uncompleted photoelectric conversion element 400A after a plating process For example, laser dicing or blade dicing is mentioned. In particular, laser dicing is preferable because complicated shapes or curved surfaces can be cut out.
  • a plating layer is not formed in the cutting part of laser dicing or blade dicing because the plating layer is isolated on appearance in a thin wire
  • the difference from the conventional one will be described in detail.
  • the plating power supply is performed on the plating layer side, it is general that the base electrode layers are all connected in appearance and the plating layer is also formed in the cut portion There is a case. In such a case, the case of using copper or the like on the substantially entire surface as a plating layer is considered.
  • the plating layer is not formed, and the plating layer is also formed at the cut portion. Therefore, if laser dicing is performed for each plating layer (with the plating layer attached), plating by a laser When the copper of the layer melts and adheres to the semiconductor substrate at the cut surface or the like, the copper may diffuse into the semiconductor substrate and the characteristics of the photoelectric conversion element may be degraded.
  • the plating layer in the cut portion by not forming the plating layer in the cut portion, the characteristic deterioration of the photoelectric conversion element due to the diffusion of copper derived from the plating layer as described above is suppressed.
  • it can also prevent that a part of plating layer peels from a photoelectric conversion element by the physical interaction at the time of blade dicing and (following) cleavage.
  • the plurality of thin wire electrode regions as shown by dotted lines in FIG. 7 may be more than the number of photoelectric conversion elements to be finally formed, and the plating layer composed of a plurality of thin wire electrode regions isolated in appearance is one It may be formed on the photoelectric conversion element.
  • the other manufacturing method of the photoelectric conversion element according to the present embodiment is carried out in the same manner as the first embodiment.

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Abstract

Provided is a method for producing a photoelectric conversion element, which improves the production efficiency. The present invention is a method for producing a photoelectric conversion element that comprises a photoelectric conversion unit which has a first main surface and a second main surface that is on the reverse side of the first main surface. The photoelectric conversion unit sequentially comprises, from the first main surface side, at least a p-type semiconductor layer and an n-type semiconductor layer; and the photoelectric conversion element additionally comprises a first conductive layer on the first main surface side of the photoelectric conversion unit, while comprising a second conductive layer on the second main surface side of the photoelectric conversion unit. This method for producing a photoelectric conversion element comprises a plating layer formation step for forming a plating layer on the first conductive layer; and in the plating layer formation step, the plating is carried out in a state where a feeding electrode for plating and the second conductive layer are in area contact with each other, while preventing the feeding electrode for plating and the second conductive layer from coming into contact with a plating liquid.

Description

光電変換素子の製造方法及びめっき用治具、めっき装置Method of manufacturing photoelectric conversion element, plating jig, plating apparatus
　本発明は、光電変換素子の製造方法及びめっき用治具、めっき装置に関する。 The present invention relates to a method of manufacturing a photoelectric conversion element, a plating jig, and a plating apparatus.
　下記特許文献１には、以下の工程を含む太陽電池の製造方法が開示されている。まず、光電変換ユニットを形成した後に、光電変換ユニットの表面及び側面に第一透明電極層を形成する。その後、光電変換ユニットの裏面及び側面に第二透明電極層を形成する。その後、第二透明電極層上に金属層を形成する。その後、第一透明電極層上に下地電極層を形成する。その後、下地電極層、金属層をめっき液に浸し、金属層側から給電することにより、光電変換層の側面において金属層に電気的に接続された下地電極層と金属層とを同時にめっきする。その後、光電変換層の側面に形成された第一透明電極層、第二透明電極層、金属層、下地電極層を除去する。 The following Patent Document 1 discloses a method of manufacturing a solar cell including the following steps. First, after forming the photoelectric conversion unit, the first transparent electrode layer is formed on the surface and the side surface of the photoelectric conversion unit. Thereafter, the second transparent electrode layer is formed on the back surface and the side surface of the photoelectric conversion unit. Thereafter, a metal layer is formed on the second transparent electrode layer. Thereafter, a base electrode layer is formed on the first transparent electrode layer. Thereafter, the base electrode layer and the metal layer are immersed in a plating solution, and power is supplied from the metal layer side to simultaneously plate the base electrode layer and the metal layer electrically connected to the metal layer on the side surface of the photoelectric conversion layer. Thereafter, the first transparent electrode layer, the second transparent electrode layer, the metal layer, and the base electrode layer formed on the side surfaces of the photoelectric conversion layer are removed.
特開２０１５－８２６０３号公報JP, 2015-82603, A
　しかし、従来の太陽電池の製造方法では、めっきにおける給電を、めっき層側である下地電極層に点で接するように行うため、下地電極層の電気抵抗がある程度高くなると、めっきの給電部からの距離に応じて電位差が大きくなり、めっき電極の形成のされ方が不均一となる。このため、めっき時に印加する電流を段階的に増加させるという方法を用いることが一般的である。この場合、初期の低電流段階において、下地電極層における電位差が小さい状態でめっきを施すことにより、下地電極層全体に比較的均一に薄くめっき電極を形成することができる。これにより、下地電極の電気抵抗が全体的に低くなるため、次の段階で高電流を流しても電位差が大きくならず、めっきを均一に施すことができる。しかしながら、このように段階的にめっき速度を高める方法では製造効率が低くなるという課題がある。更には、下地電極層が透明電極層のみからなるような極端に電気抵抗の高い場合においては、均一なめっきを形成することが困難である。 However, in the conventional method of manufacturing a solar cell, since feeding in plating is performed in such a manner that the base electrode layer on the plating layer side is in contact with the point, if the electric resistance of the base electrode layer becomes high to some extent, The potential difference increases according to the distance, and the formation of the plating electrode becomes nonuniform. For this reason, it is common to use a method in which the current applied during plating is gradually increased. In this case, by plating in a state where the potential difference in the base electrode layer is small in the initial low current stage, a thin plating electrode can be formed relatively uniformly over the entire base electrode layer. As a result, the electric resistance of the base electrode as a whole is reduced, so that the potential difference does not increase even if a high current is applied in the next step, and plating can be performed uniformly. However, such a method of gradually increasing the plating rate has a problem that the manufacturing efficiency is lowered. Furthermore, it is difficult to form uniform plating in the case where the electrical resistance is extremely high, such as when the base electrode layer consists only of the transparent electrode layer.
　本発明者らは上記課題に鑑み鋭意検討した結果、所定のめっき方法を用いることにより、光電変換素子の製造効率が向上し、更に集電極が低コストで形成可能であることを見出し、本発明に至った。 MEANS TO SOLVE THE PROBLEM As a result of earnestly examining in view of the said subject, the present inventors discover that manufacture efficiency of a photoelectric conversion element improves by using a predetermined plating method, and also a collector can be formed at low cost, and this invention It came to
　したがって、本発明は、光電変換素子の製造効率が向上し、更に集電極が低コストで形成可能である、光電変換素子の製造方法を提供することを課題とする。 Therefore, this invention makes it a subject to provide the manufacturing method of a photoelectric conversion element which the manufacturing efficiency of a photoelectric conversion element improves, and also a collector can be formed at low cost.
　すなわち、本発明は、以下に関する。 That is, the present invention relates to the following.
　（１）本発明の第一は、第１主面と第１主面の裏面である第２主面とを備える光電変換ユニットを含む光電変換素子の製造方法であって、
　前記光電変換ユニットは第１主面側から第２主面側に向かって順に、少なくとも、ｐ型半導体層及びｎ型半導体層を備え、
　前記光電変換素子はさらに、前記光電変換ユニットの第１主面側に第一導電層を備え、前記光電変換ユニットの第２主面側に第二導電層を備え、
　前記第一導電層上にめっき層を形成するめっき層形成工程を備え、
　前記めっき層形成工程において、めっき給電用電極と前記第二導電層とを面状に接触させた状態で、かつ、めっき給電用電極および第二導電層をめっき液と接触させない状態で、めっきを行う、光電変換素子の製造方法である。 (1) A first aspect of the present invention is a method of manufacturing a photoelectric conversion element including a photoelectric conversion unit including a first main surface and a second main surface which is a back surface of the first main surface,
The photoelectric conversion unit includes at least a p-type semiconductor layer and an n-type semiconductor layer in order from the first main surface side to the second main surface side,
The photoelectric conversion device further includes a first conductive layer on the first main surface side of the photoelectric conversion unit, and a second conductive layer on the second main surface side of the photoelectric conversion unit,
And a plating layer forming step of forming a plating layer on the first conductive layer,
In the plating layer forming step, the plating is performed in a state in which the plating feeding electrode and the second conductive layer are in plane contact and the plating feeding electrode and the second conductive layer are not in contact with the plating solution. It is a manufacturing method of a photoelectric conversion element to carry out.
　この構成によって、第一導電層上に、均一にめっき層を形成することが可能となり、更には、めっき速度を高めて作製することが可能となることにより製造効率を高くすることが可能となる。 With this configuration, it becomes possible to form a plating layer uniformly on the first conductive layer, and furthermore, by making it possible to increase the plating rate to produce, it is possible to increase manufacturing efficiency. .
　（２）本発明は、また、前記めっき層形成工程において、前記第二導電層の面積以上の面積を有するめっき給電用電極を前記第二導電層に面状に接触させた状態でめっきを行う、前記（１）に記載の光電変換素子の製造方法である。この構成によって、めっき層の均一性を高めることが可能となる。 (2) The present invention also performs plating in a state in which a plating feeding electrode having an area equal to or larger than the area of the second conductive layer is brought into planar contact with the second conductive layer in the plating layer forming step. It is a manufacturing method of the photoelectric conversion element as described in said (1). This configuration makes it possible to improve the uniformity of the plating layer.
　（３）本発明は、また、前記第一導電層が第一透明電極層である、前記（１）又は（２）に記載の光電変換素子の製造方法である。この構成によって、下地電極層を省くことができ製造コストを低減することが可能となる。 (3) The present invention is also the method for producing a photoelectric conversion element according to (1) or (2), wherein the first conductive layer is a first transparent electrode layer. With this configuration, the base electrode layer can be omitted and the manufacturing cost can be reduced.
　（４）本発明は、また、前記光電変換素子は、さらに前記光電変換ユニットの第１主面側に第一透明電極層を備え、前記第一導電層が第一透明電極層の上に設けられている、前記（１）又は（２）に記載の光電変換素子の製造方法である。 (4) Further, according to the present invention, the photoelectric conversion device further includes a first transparent electrode layer on the first principal surface side of the photoelectric conversion unit, and the first conductive layer is provided on the first transparent electrode layer. It is a manufacturing method of the photoelectric conversion element as described in said (1) or (2).
　（５）本発明は、また、前記第一導電層がＮｉ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはこれらの合金からなる下地電極層である、前記（１）、（２）又は（４）に記載の光電変換素子の製造方法である。この構成によって、めっき層のパターニングを容易に実施することが可能となる。 (5) The present invention is also directed to (1), (2) or (4), wherein the first conductive layer is a base electrode layer composed of Ni, Cu, Ag, Au, Pt, or an alloy thereof. It is a manufacturing method of the photoelectric conversion element as described. This configuration makes it possible to easily carry out the patterning of the plating layer.
　（６）本発明は、また、前記第一導電層が細線電極である、、前記（１）～（５）のいずれか１項に記載の光電変換素子の製造方法である。この構成によって、めっき層のパターニングを容易に実施することが可能となる。 (6) The present invention is also the method for producing a photoelectric conversion element according to any one of (1) to (5), wherein the first conductive layer is a thin wire electrode. This configuration makes it possible to easily carry out the patterning of the plating layer.
　（７）本発明は、また、前記第一導電層は、少なくとも一部が絶縁層で覆われている、前記（１）～（６）のいずれか１項に記載の光電変換素子の製造方法である。この構成によって、めっき層のパターニングを容易に実施することが可能となる。 (7) The method according to any one of (1) to (6), wherein the first conductive layer is at least partially covered with an insulating layer. It is. This configuration makes it possible to easily carry out the patterning of the plating layer.
　（８）本発明は、また、前記第二導電層が第二透明電極層である、前記（１）～（７）のいずれか１項に記載の光電変換素子の製造方法である。この構成によって、めっき給電における均一性が向上し、めっき層の均一性を高めることが可能となる。 (8) The present invention is also the method of manufacturing a photoelectric conversion element according to any one of (1) to (7), wherein the second conductive layer is a second transparent electrode layer. With this configuration, the uniformity in plating power feeding can be improved, and the uniformity of the plating layer can be enhanced.
　（９）本発明は、また、前記光電変換素子は、さらに前記光電変換ユニットの第２主面側に第二透明電極層を備え、前記第二導電層が第二透明電極層の上に設けられている、前記（１）～（７）のいずれか１項に記載の光電変換素子の製造方法である。 (9) Further, according to the present invention, the photoelectric conversion device further includes a second transparent electrode layer on the second principal surface side of the photoelectric conversion unit, and the second conductive layer is provided on the second transparent electrode layer. It is a manufacturing method of the photoelectric conversion element according to any one of the above (1) to (7).
　（１０）本発明は、また、前記第二導電層が細線電極である、前記（１）～（９）のいずれか１項に記載の光電変換素子の製造方法である。この構成によって、めっき給電における均一性が向上し、めっき層の均一性を高めることが可能となる。 (10) The present invention is also the method of manufacturing a photoelectric conversion element according to any one of (1) to (9), wherein the second conductive layer is a thin wire electrode. With this configuration, the uniformity in plating power feeding can be improved, and the uniformity of the plating layer can be enhanced.
　（１１）さらに、第一導電層を、第１主面側から平面視した場合に外観上孤立するＮ個（ただし、２≦Ｎ）以上の細線電極領域として形成する工程を備える、前記（１）～（１０）のいずれか１項に記載の光電変換素子の製造方法である。この構成によって、半導体基板上に複数の光電変換素子を有する場合においても効率的にめっき層を形成することが可能となる。 (11) The method further includes the step of forming the first conductive layer as N (where 2 ≦ N) or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side. (10) The method for producing a photoelectric conversion device according to any one of (10) to (10). With this configuration, it is possible to efficiently form the plating layer even in the case where a plurality of photoelectric conversion elements are provided on the semiconductor substrate.
　（１２）さらに、第一導電層を、第１主面側から平面視した場合に外観上孤立するＮ個（ただし、２≦Ｎ）以上の細線電極領域として形成する工程を備え、
　さらに、第１主面側から平面視した場合に外観上孤立するＮ個以上の細線電極領域付きの光電変換素子を、めっき層が形成されていない部位において分割し、Ｎ個の光電変換素子を形成する工程を備える、前記（１）～（１０）のいずれか１項に記載の光電変換素子の製造方法である。この構成によって、複数の光電変換素子を効率的に作製することが可能となる。 (12) The method further includes the step of forming the first conductive layer as N (where 2 ≦ N) or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side,
Furthermore, the photoelectric conversion element with N or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side is divided at a portion where the plating layer is not formed, and N photoelectric conversion elements are obtained. It is a manufacturing method of the photoelectric conversion element according to any one of the above (1) to (10), including the forming step. With this configuration, it is possible to efficiently manufacture a plurality of photoelectric conversion elements.
　（１３）本発明は、また、前記（１）～（１２）のいずれか１項に記載の光電変換素子の製造方法に用いられる、めっき用治具であって、
　前記めっき層形成工程において、めっき給電用電極とめっき液とを接触させない状態で、かつ、めっき給電用電極と前記第二導電層とを面状に接触させた状態で、めっきを行うことが可能な、少なくとも、フレーム、パッキン、留め具、を備えるめっき用治具である。　この構成によって、効率的にめっきを実施することが可能となる。 (13) The present invention is also a plating jig used in the method of manufacturing a photoelectric conversion element according to any one of the above (1) to (12),
In the plating layer forming step, plating can be performed in a state in which the plating power supply electrode and the plating solution are not in contact with each other and in a state in which the plating power supply electrode and the second conductive layer are in planar contact. It is a plating jig provided with at least a frame, a packing, and a fastener. This configuration enables efficient plating.
　（１４）本発明は、また、前記（１３）に記載のめっき用治具を備えるめっき装置である。この構成によって、効率的にめっきを実施することが可能となる。 (14) The present invention is also a plating apparatus provided with the plating jig according to (13). This configuration enables efficient plating.
　本発明によれば、めっき層の均一性を向上させ、更には、めっき速度の高速化による製造効率向上を可能とする光電変換素子の製造方法を提供することができる。 According to the present invention, it is possible to provide a method of manufacturing a photoelectric conversion element capable of improving the uniformity of the plating layer and further improving the manufacturing efficiency by increasing the plating rate.
本発明の第１の実施形態に係る光電変換素子の表面側を示す平面図である。It is a top view which shows the surface side of the photoelectric conversion element which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る光電変換素子の断面模式図である。It is a cross-sectional schematic diagram of the photoelectric conversion element concerning the 1st Embodiment of this invention. 本発明の第１の実施形態に係る未完成な光電変換素子の断面模式図である。It is a cross-sectional schematic diagram of the incomplete photoelectric conversion element which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る光電変換素子において、裏面構造が異なる場合の断面模式図である。In the photoelectric conversion element which concerns on the 1st Embodiment of this invention, it is a cross-sectional schematic diagram in case back surface structures differ. 本発明の第２の実施形態に係る光電変換素子の断面模式図である。It is a cross-sectional schematic diagram of the photoelectric conversion element which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る未完成な光電変換素子の断面模式図であるIt is a cross-sectional schematic diagram of the incomplete photoelectric conversion element which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る光電変換素子の表面側を示す平面図である。It is a top view which shows the surface side of the photoelectric conversion element which concerns on the 3rd Embodiment of this invention. 本発明の実施形態に係るめっき用治具を示す断面模式図である。It is a cross section showing the plating jig concerning the embodiment of the present invention. 本発明の実施形態に係るめっき装置を示す断面模式図である。It is a cross section showing the plating device concerning the embodiment of the present invention. 本発明の実施形態に係るめっき装置を示す断面模式図である。It is a cross section showing the plating device concerning the embodiment of the present invention.
　（１）本発明の第一は、第１主面と第１主面の裏面である第２主面とを備える光電変換ユニットを含む光電変換素子の製造方法であって、
　前記光電変換ユニットは第１主面側から第２主面側に向かって順に、少なくとも、ｐ型半導体層及びｎ型半導体層を備え、
　前記光電変換素子はさらに、前記光電変換ユニットの第１主面側に第一導電層を備え、前記光電変換ユニットの第２主面側に第二導電層を備え、
　前記第一導電層上にめっき層を形成するめっき層形成工程を備え、
　前記めっき層形成工程において、めっき給電用電極と前記第二導電層とを面状に接触させた状態で、かつ、めっき給電用電極および第二導電層をめっき液と接触させない状態で、めっきを行う、光電変換素子の製造方法である。 (1) A first aspect of the present invention is a method of manufacturing a photoelectric conversion element including a photoelectric conversion unit including a first main surface and a second main surface which is a back surface of the first main surface,
The photoelectric conversion unit includes at least a p-type semiconductor layer and an n-type semiconductor layer in order from the first main surface side to the second main surface side,
The photoelectric conversion device further includes a first conductive layer on the first main surface side of the photoelectric conversion unit, and a second conductive layer on the second main surface side of the photoelectric conversion unit,
And a plating layer forming step of forming a plating layer on the first conductive layer,
In the plating layer forming step, the plating is performed in a state in which the plating feeding electrode and the second conductive layer are in plane contact and the plating feeding electrode and the second conductive layer are not in contact with the plating solution. It is a manufacturing method of a photoelectric conversion element to carry out.
　（２）本発明は、また、前記めっき層形成工程において、前記第二導電層の面積以上の面積を有するめっき給電用電極を前記第二導電層に面状に接触させた状態でめっきを行う、前記（１）に記載の光電変換素子の製造方法である。 (2) The present invention also performs plating in a state in which a plating feeding electrode having an area equal to or larger than the area of the second conductive layer is brought into planar contact with the second conductive layer in the plating layer forming step. It is a manufacturing method of the photoelectric conversion element as described in said (1).
　（３）本発明は、また、前記第一導電層が第一透明電極層である、前記（１）又は（２）に記載の光電変換素子の製造方法である。 (3) The present invention is also the method for producing a photoelectric conversion element according to (1) or (2), wherein the first conductive layer is a first transparent electrode layer.
　（４）本発明は、また、前記光電変換素子は、さらに前記光電変換ユニットの第１主面側に第一透明電極層を備え、前記第一導電層が第一透明電極層の上に設けられている、前記（１）又は（２）に記載の光電変換素子の製造方法である。 (4) Further, according to the present invention, the photoelectric conversion device further includes a first transparent electrode layer on the first principal surface side of the photoelectric conversion unit, and the first conductive layer is provided on the first transparent electrode layer. It is a manufacturing method of the photoelectric conversion element as described in said (1) or (2).
　（５）本発明は、また、前記第一導電層がＮｉ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはこれらの合金からなる下地電極層である、前記（１）、（２）又は（４）に記載の光電変換素子の製造方法である。 (5) The present invention is also directed to (1), (2) or (4), wherein the first conductive layer is a base electrode layer composed of Ni, Cu, Ag, Au, Pt, or an alloy thereof. It is a manufacturing method of the photoelectric conversion element as described.
　（６）本発明は、また、前記第一導電層が細線電極である、前記（１）～（５）のいずれか１項に記載の光電変換素子の製造方法である。 (6) The present invention is also the method for producing a photoelectric conversion element according to any one of (1) to (5), wherein the first conductive layer is a thin wire electrode.
　（７）本発明は、また、前記第一導電層は、少なくとも一部が絶縁層で覆われている、前記（１）～（６）のいずれか１項に記載の光電変換素子の製造方法である。 (7) The method according to any one of (1) to (6), wherein the first conductive layer is at least partially covered with an insulating layer. It is.
　（８）本発明は、また、前記第二導電層が第二透明電極層である、前記（１）～（７）のいずれか１項に記載の光電変換素子の製造方法である。 (8) The present invention is also the method of manufacturing a photoelectric conversion element according to any one of (1) to (7), wherein the second conductive layer is a second transparent electrode layer.
　（９）本発明は、また、前記光電変換素子は、さらに前記光電変換ユニットの第２主面側に第二透明電極層を備え、前記第二導電層が第二透明電極層の上に設けられている、前記（１）～（７）のいずれか１項に記載の光電変換素子の製造方法である。 (9) Further, according to the present invention, the photoelectric conversion device further includes a second transparent electrode layer on the second principal surface side of the photoelectric conversion unit, and the second conductive layer is provided on the second transparent electrode layer. It is a manufacturing method of the photoelectric conversion element according to any one of the above (1) to (7).
　（１０）本発明は、また、前記第二導電層が細線電極である、前記（１）～（９）のいずれか１項に記載の光電変換素子の製造方法である。 (10) The present invention is also the method of manufacturing a photoelectric conversion element according to any one of (1) to (9), wherein the second conductive layer is a thin wire electrode.
　（１１）さらに、第一導電層を、第１主面側から平面視した場合に外観上孤立するＮ個（ただし、２≦Ｎ）以上の細線電極領域として形成する工程を備える、前記（１）～（１０）のいずれか１項に記載の光電変換素子の製造方法である。 (11) The method further includes the step of forming the first conductive layer as N (where 2 ≦ N) or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side. (10) The method for producing a photoelectric conversion device according to any one of (10) to (10).
　（１２）さらに、第一導電層を、第１主面側から平面視した場合に外観上孤立するＮ個（ただし、２≦Ｎ）以上の細線電極領域として形成する工程を備え、
　さらに、第１主面側から平面視した場合に外観上孤立するＮ個以上の細線電極領域付きの光電変換素子を、めっき層が形成されていない部位において分割し、Ｎ個の光電変換素子を形成する工程を備える、前記（１）～（１０）のいずれか１項に記載の光電変換素子の製造方法である。 (12) The method further includes the step of forming the first conductive layer as N (where 2 ≦ N) or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side,
Furthermore, the photoelectric conversion element with N or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side is divided at a portion where the plating layer is not formed, and N photoelectric conversion elements are obtained. It is a manufacturing method of the photoelectric conversion element according to any one of the above (1) to (10), including the forming step.
　（１３）本発明は、また、前記（１）～（１２）のいずれか１項に記載の光電変換素子の製造方法に用いられる、めっき用治具であって、
　前記めっき層形成工程において、めっき給電用電極とめっき液とを接触させない状態で、かつ、めっき給電用電極と前記第二導電層とを面状に接触させた状態で、めっきを行うことが可能な、少なくとも、フレーム、パッキン、留め具、を備えるめっき用治具である。 (13) The present invention is also a plating jig used in the method of manufacturing a photoelectric conversion element according to any one of the above (1) to (12),
In the plating layer forming step, plating can be performed in a state in which the plating power supply electrode and the plating solution are not in contact with each other and in a state in which the plating power supply electrode and the second conductive layer are in planar contact. It is a plating jig provided with at least a frame, a packing, and a fastener.
　（１４）本発明は、また、前記（１３）に記載のめっき用治具を備えるめっき装置である。 (14) The present invention is also a plating apparatus provided with the plating jig according to (13).
　（第１の実施形態）
　本開示の第１の実施形態について、図面を用いて以下に説明する。 First Embodiment
A first embodiment of the present disclosure will be described below using the drawings.
　［光電変換素子１００］
　図１は、本発明の製造方法により形成する光電変換素子１００の表面側（受光面側）を示す平面図である。図２は、図１におけるＩＩＩ－ＩＩＩ線の断面を示す断面図である。 [Photoelectric conversion element 100]
FIG. 1 is a plan view showing the surface side (light receiving surface side) of a photoelectric conversion element 100 formed by the manufacturing method of the present invention. FIG. 2 is a cross-sectional view showing a cross section taken along line III-III in FIG.
　図１に示すように、光電変換素子１００は、複数のバスバー電極と、このバスバー電極と交差するように設けられた多数のフィンガー電極からなる集電極１０７を有している。
なお、バスバー電極およびフィンガー電極のデザインは前述のものに限定されず、どのようなものであってもよい。また、バスバー電極は有していなくてもよく、フィンガー電極のみ形成されていてもよい。本開示において、半導体基板、光電変換ユニット及び／又は光電変換素子１００の表面を第１主面と定義し、裏面を第２主面と定義する。 As shown in FIG. 1, the photoelectric conversion element 100 includes a plurality of bus bar electrodes and a collector electrode 107 including a plurality of finger electrodes provided so as to intersect the bus bar electrodes.
The design of the bus bar electrode and the finger electrode is not limited to that described above, and may be any design. Further, the bus bar electrode may not be provided, and only the finger electrode may be formed. In the present disclosure, the front surface of the semiconductor substrate, the photoelectric conversion unit, and / or the photoelectric conversion element 100 is defined as a first main surface, and the back surface is defined as a second main surface.
　図２に示すように、本実施形態における光電変換素子１００は半導体基板１０１を有する。半導体基板１０１は、その第１の主面側にｐ型半導体層（導電型シリコン系薄膜）１０３ａを有する。半導体基板１０１は、その第２の主面側にｎ型半導体層（導電型シリコン系薄膜）１０３ｂを有する。図２においては、第２の主面側を下側に表示し、第１の主面側を上側に表示している。 As shown in FIG. 2, the photoelectric conversion element 100 in the present embodiment has a semiconductor substrate 101. The semiconductor substrate 101 has a p-type semiconductor layer (conductive silicon-based thin film) 103 a on the first main surface side. The semiconductor substrate 101 has an n-type semiconductor layer (conductive silicon-based thin film) 103 b on the second main surface side. In FIG. 2, the second main surface side is displayed on the lower side, and the first main surface side is displayed on the upper side.
　この、ｐ型半導体層１０３ａとｎ型半導体層１０３ｂとの間において、ＰＮ接合が形成されている。 A PN junction is formed between the p-type semiconductor layer 103a and the n-type semiconductor layer 103b.
　なお、図２に示す例においては、半導体基板１０１とｐ型半導体層１０３ａ、ｎ型半導体層１０３ｂとの間に境界線を記載しているが、半導体基板１０１自体がｎ型半導体、若しくはｐ型半導体であり、半導体基板１０１とｐ型半導体層１０３ａとの間、若しくは半導体基板１０１とｎ型半導体層１０３ｂとの間に境界がない構成であってもよい。 In the example shown in FIG. 2, the boundary is described between the semiconductor substrate 101 and the p-type semiconductor layer 103a and the n-type semiconductor layer 103b. However, the semiconductor substrate 101 itself is an n-type semiconductor or p-type. The semiconductor device may be a semiconductor and may have no boundary between the semiconductor substrate 101 and the p-type semiconductor layer 103a or between the semiconductor substrate 101 and the n-type semiconductor layer 103b.
　ｐ型半導体層１０３ａにおける第１の主面側には、集電極１０７の形成領域に、第一導電層１０７－１が設けられている。本実施形態においては、第一導電層１０７－１として、図１に示したバスバー電極とフィンガー電極からなる細線電極形状の下地電極層を用いている。更に、第一導電層１０７－１における第１の主面側には、めっき層１０７－２が設けられている。このめっき層１０７－２、及び第一導電層１０７－１が、図１に示す表面側のバスバー電極とフィンガー電極からなる集電極を構成している。 A first conductive layer 107-1 is provided in the formation region of the collector electrode 107 on the first main surface side of the p-type semiconductor layer 103a. In the present embodiment, as the first conductive layer 107-1, the base electrode layer in the shape of a thin wire electrode including the bus bar electrode and the finger electrode shown in FIG. 1 is used. Furthermore, a plating layer 107-2 is provided on the first main surface side of the first conductive layer 107-1. The plated layer 107-2 and the first conductive layer 107-1 constitute a collector electrode including the surface side bus bar electrode and the finger electrode shown in FIG.
　本実施形態においては、半導体基板１０１がｎ型半導体基板である構成としている。また、第一導電層１０７－１とｐ型半導体層１０３ａとの間には、第一透明電極層１０６ａを含む。ｎ型半導体層１０３ｂの裏面側には、第二透明電極層１０６ｂと、第二導電層１０８として裏面金属電極とを更に含む構成としている。 In the present embodiment, the semiconductor substrate 101 is an n-type semiconductor substrate. In addition, a first transparent electrode layer 106a is included between the first conductive layer 107-1 and the p-type semiconductor layer 103a. The back surface side of the n-type semiconductor layer 103 b is configured to further include a second transparent electrode layer 106 b and a back surface metal electrode as the second conductive layer 108.
　なお、半導体基板１０１とｐ型半導体層１０３ａとの間に真性半導体層１０２ａを介在させる構成としてもよく、半導体基板１０１とｎ型半導体層１０３ｂとの間に真性半導体層１０２ｂを介在させる構成としてもよい。半導体基板１０１とｐ型半導体層１０３ａとの間、若しくは、半導体基板１０１とｎ型半導体層１０３ｂとの間に真性半導体１０２を介在させる場合、ｐ型半導体層１０３ａとｎ型半導体層１０３ｂとの間において、ＰＩＮ接合が形成される構成となる。本開示においては、上述したＰＮ接合の中にこのＰＩＮ接合も含まれることとする。また、本実施形態において、ｐ型半導体層１０３ａ、真性半導体層１０２ａ、半導体基板１０１、真性半導体層１０２ｂ及びｎ型半導体層１０３ｂが光電変換ユニット１５０を構成する。 Note that the intrinsic semiconductor layer 102a may be interposed between the semiconductor substrate 101 and the p-type semiconductor layer 103a, and the intrinsic semiconductor layer 102b may be interposed between the semiconductor substrate 101 and the n-type semiconductor layer 103b. Good. When the intrinsic semiconductor 102 is interposed between the semiconductor substrate 101 and the p-type semiconductor layer 103a or between the semiconductor substrate 101 and the n-type semiconductor layer 103b, between the p-type semiconductor layer 103a and the n-type semiconductor layer 103b. , And a PIN junction is formed. In the present disclosure, this PIN junction is also included in the above-described PN junction. Further, in the present embodiment, the p-type semiconductor layer 103 a, the intrinsic semiconductor layer 102 a, the semiconductor substrate 101, the intrinsic semiconductor layer 102 b, and the n-type semiconductor layer 103 b constitute a photoelectric conversion unit 150.
　［光電変換素子１００の製造方法］
　以下、本実施形態に係る光電変換素子１００の製造方法について、図２を用いて説明する。 [Method of Manufacturing Photoelectric Conversion Element 100]
Hereinafter, the manufacturing method of the photoelectric conversion element 100 which concerns on this embodiment is demonstrated using FIG.
　［半導体基板１０１準備ステップ］
　まず図２に示した半導体基板１０１を準備する。半導体基板１０１としては、例えば、単結晶シリコン基板、多結晶シリコン基板などのシリコン基板を用いることができる。結晶基板内のキャリア寿命の長さから単結晶シリコン基板が好ましい。シリコン基板としては、ｎ型シリコン基板とｐ型シリコン基板を用いることが出来る。とりわけ結晶基板内のキャリア寿命の長さから、ｎ型単結晶シリコン基板を用いることが好ましい。また、ｐ型単結晶シリコン基板で、光照射によってｐ型ドーパントであるＢ（ホウ素）が影響して再結合中心となるＬＩＤ（Ｌｉｇｈｔ　Ｉｎｄｕｃｅｄ　Ｄｅｇｒａｄａｔｉｏｎ）が起こる場合があるが、ｎ型ではより抑制される。本実施形態においては、半導体基板１０１としてｎ型単結晶シリコン基板を用いる。 [Semiconductor substrate 101 preparation step]
First, the semiconductor substrate 101 shown in FIG. 2 is prepared. As the semiconductor substrate 101, for example, a silicon substrate such as a single crystal silicon substrate or a polycrystalline silicon substrate can be used. A single crystal silicon substrate is preferable in view of the carrier lifetime in the crystal substrate. As a silicon substrate, an n-type silicon substrate and a p-type silicon substrate can be used. In particular, it is preferable to use an n-type single crystal silicon substrate in view of the carrier lifetime in the crystal substrate. In addition, in a p-type single crystal silicon substrate, there may be cases where LID (Light Induced Degradation), which is a recombination center, may be affected by light irradiation due to B (boron) that is a p-type dopant. Ru. In the present embodiment, an n-type single crystal silicon substrate is used as the semiconductor substrate 101.
　半導体基板１０１に用いる単結晶シリコン基板は、その膜厚が５０～３００μｍが好ましく、６０～２００μｍがより好ましく、７０～１８０μｍが更に好ましい。この範囲の膜厚の基板を用いることにより、より材料コストを低減することができる。 The thickness of the single crystal silicon substrate used for the semiconductor substrate 101 is preferably 50 to 300 μm, more preferably 60 to 200 μm, and still more preferably 70 to 180 μm. By using a substrate with a film thickness in this range, the material cost can be further reduced.
　半導体基板１０１は、光閉じ込めの観点から、光入射面側（受光面側、表面側）及び裏面側にテクスチャ構造と呼ばれる凹凸構造を有することが好ましい。 The semiconductor substrate 101 preferably has a concavo-convex structure called a texture structure on the light incident surface side (light receiving surface side, front surface side) and the back surface side from the viewpoint of light confinement.
　また、半導体基板１０１の第１の主面および第２の主面側は、パッシベーション層を有するものが好ましい。パッシベーション層はキャリア再結合を抑制することができ、表面欠陥を終端できれば種類を問わないが、真性半導体層、とりわけ、真性非晶質シリコン層が好ましく用いられる。 In addition, it is preferable that the first main surface and the second main surface side of the semiconductor substrate 101 have a passivation layer. The passivation layer can suppress carrier recombination and it may be of any type as long as it can terminate surface defects, but an intrinsic semiconductor layer, in particular, an intrinsic amorphous silicon layer is preferably used.
　［ｐ型半導体部１０３ａ形成ステップ］
　次に、半導体基板１０１の第１の主面側、即ち表面側に、ｐ型半導体層１０３ａを形成する。ｐ型半導体層１０３ａを形成する上で用いる材料としては、非晶質シリコン薄膜、微結晶シリコン（非晶質シリコンと結晶質シリコンとを含む）薄膜等、非晶質成分を含む非晶質シリコン層を含むことが望ましい。また、ドーパント不純物としては、Ｂ（ホウ素）などを用いることができる。 [Step for forming p-type semiconductor portion 103a]
Next, the p-type semiconductor layer 103 a is formed on the first main surface side, that is, the surface side of the semiconductor substrate 101. As a material used to form the p-type semiconductor layer 103a, amorphous silicon thin film, microcrystalline silicon (including amorphous silicon and crystalline silicon) thin film, and amorphous silicon containing an amorphous component It is desirable to include a layer. Further, B (boron) or the like can be used as the dopant impurity.
　ｐ型半導体層１０３ａの製膜方法は特に限定されないが、例えばＣＶＤ法（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）を使用することができる。ＣＶＤ法を用いる場合、ＳｉＨ４ガスを用い、ドーパント添加ガスとしては、水素希釈されたＢ２Ｈ６が好ましく用いられる。なお、ドーパント不純物の添加量は微量でよいため、予めＳｉＨ４やＨ２で希釈された混合ガスを用いることが好ましい。ｐ型半導体層１０３ａの製膜時に、ＣＨ４、ＣＯ２、ＮＨ３、ＧｅＨ４等の異種元素を含むガスを添加して、シリコン系薄膜を合金化することにより、シリコン系薄膜のエネルギーギャップを変更することもできる。また、光の透過性を向上させるために酸素や炭素といった不純物を微量添加しても良い。その場合、ＣＯ２やＣＨ４といったガスをＣＶＤ製膜の際に導入することにより形成することができる。 Although the film forming method of the p-type semiconductor layer 103 a is not particularly limited, for example, a CVD method (Chemical Vapor Deposition) can be used. When the CVD method is used, SiH 4 gas is used, and B 2 H 6 diluted with hydrogen is preferably used as the dopant addition gas. In addition, since the addition amount of the dopant impurity may be a very small amount, it is preferable to use a mixed gas diluted with SiH 4 or H 2 in advance. The energy gap of the silicon-based thin film is obtained by alloying the silicon-based thin film by adding a gas containing different elements such as CH 4 , CO 2 , NH 3 , GeH 4 or the like at the time of forming the p-type semiconductor layer 103 a. You can change it. Further, in order to improve the light transmittance, a small amount of an impurity such as oxygen or carbon may be added. In that case, it can be formed by introducing a gas such as CO 2 and CH 4 in the CVD film forming.
　なお、半導体基板１０１として、ｐ型多結晶シリコン基板を用いた場合、既に半導体基板１０１の第１の主面側はｐ型半導体層１０３ａとなっており、ｐ型半導体層１０３ａが半導体基板１０１内に含まれる構成となる。この場合、ｐ型半導体層１０３ａ形成ステップは不要となる。 When a p-type polycrystalline silicon substrate is used as the semiconductor substrate 101, the first principal surface side of the semiconductor substrate 101 is already the p-type semiconductor layer 103a, and the p-type semiconductor layer 103a is in the semiconductor substrate 101. Will be included in In this case, the step of forming the p-type semiconductor layer 103a is unnecessary.
　［ｎ型半導体層１０３ｂ形成ステップ］
　また、半導体基板１０１の第２の主面側、即ち裏面側に、ｎ型半導体層１０３ｂを形成する。なお、このｎ型半導体層１０３ｂ形成ステップは、上述したｐ型半導体層１０３ａ形成ステップの前に行ってもよく、ｐ型半導体層１０３ａ形成ステップの後に行ってもよい。 [Step of forming n-type semiconductor layer 103b]
In addition, the n-type semiconductor layer 103 b is formed on the second main surface side, that is, the back surface side of the semiconductor substrate 101. The step of forming the n-type semiconductor layer 103b may be performed before the step of forming the p-type semiconductor layer 103a described above, or may be performed after the step of forming the p-type semiconductor layer 103a.
　ｎ型半導体層１０３ｂを形成する上で用いる材料としては、非晶質シリコン薄膜、微結晶シリコン薄膜等、非晶質成分を含む非晶質シリコン層を含むことが望ましい。また、ドーパント不純物としては、Ｐ（リン）などを用いることができる。 As a material used to form the n-type semiconductor layer 103 b, it is preferable to include an amorphous silicon layer containing an amorphous component, such as an amorphous silicon thin film or a microcrystalline silicon thin film. In addition, P (phosphorus) or the like can be used as the dopant impurity.
　ｎ型半導体層１０３ｂの製膜方法は特に限定されないが、例えばＣＶＤ法（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）を使用することができる。ＣＶＤ法を用いる場合、ＳｉＨ４ガスを用い、ドーパント添加ガスとしては、水素希釈されたＰＨ３が好ましく用いられる。なお、ドーパント不純物の添加量は微量でよいため、予めＳｉＨ４やＨ２で希釈された混合ガスを用いることが好ましい。ｎ型半導体層１０３ｂの製膜時に、ＣＨ４、ＣＯ２、ＮＨ３、ＧｅＨ４等の異種元素を含むガスを添加して、シリコン系薄膜を合金化することにより、シリコン系薄膜のエネルギーギャップを変更することもできる。また、光の透過性を向上させるために酸素や炭素といった不純物を微量添加しても良い。その場合、ＣＯ２やＣＨ４といったガスをＣＶＤ製膜の際に導入することにより形成することができる。 Although the film forming method of the n-type semiconductor layer 103 b is not particularly limited, for example, a CVD method (Chemical Vapor Deposition) can be used. When the CVD method is used, SiH 4 gas is used, and PH 3 diluted with hydrogen is preferably used as the dopant addition gas. In addition, since the addition amount of the dopant impurity may be a very small amount, it is preferable to use a mixed gas diluted with SiH 4 or H 2 in advance. The energy gap of the silicon-based thin film is obtained by alloying the silicon-based thin film by adding a gas containing different elements such as CH 4 , CO 2 , NH 3 , GeH 4 or the like at the time of forming the n-type semiconductor layer 103 b. You can change it. Further, in order to improve the light transmittance, a small amount of an impurity such as oxygen or carbon may be added. In that case, it can be formed by introducing a gas such as CO 2 and CH 4 in the CVD film forming.
　なお、半導体基板１０１として、ｐ型多結晶シリコン基板を用いた場合、半導体基板１０１の第２の主面側にｎ型ドーパントを拡散させてｎ型化させることにより、ｎ型半導体層１０３ｂを形成してもよい。 Note that when a p-type polycrystalline silicon substrate is used as the semiconductor substrate 101, the n-type semiconductor layer 103b is formed by diffusing an n-type dopant into the second main surface side of the semiconductor substrate 101 to make it n-type. You may
　［第一透明電極層１０６ａ、第二透明電極層１０６ｂ形成ステップ］
　次に、スパッタ法や、ＭＯＣＶＤ法等によって、ｐ型半導体層１０３ａの第１の主面側に第一透明電極層１０６ａを形成し、ｎ型半導体層１０３ｂの第２の主面側に第二透明電極層１０６ｂを形成する。第一透明電極層１０６ａ形成ステップは、ｐ型半導体層１０３ａ形成ステップより後であればよく、ｎ型半導体層１０３ｂ形成ステップより前であってもよい。また、第二透明電極層１０６ｂ形成ステップは、ｎ型半導体層１０３ｂ形成ステップより後であればよく、ｐ型半導体層１０３ａ形成ステップより前であってもよい。 [Step of Forming First Transparent Electrode Layer 106a, Second Transparent Electrode Layer 106b]
Next, a first transparent electrode layer 106a is formed on the first principal surface side of the p-type semiconductor layer 103a by sputtering, MOCVD, etc., and a second transparent electrode layer is formed on the second principal surface side of the n-type semiconductor layer 103b. The transparent electrode layer 106 b is formed. The step of forming the first transparent electrode layer 106a may be after the step of forming the p-type semiconductor layer 103a, and may be before the step of forming the n-type semiconductor layer 103b. The second transparent electrode layer 106b forming step may be after the n-type semiconductor layer 103b forming step, and may be before the p-type semiconductor layer 103a forming step.
　第一透明電極層１０６ａ、第二透明電極層１０６ｂの構成材料としては、酸化インジウム、酸化亜鉛、酸化錫、酸化チタン、及びそれらの複合酸化物等の透明導電性金属酸化物を用いることができる。また、グラフェンのような非金属からなる透明導電性材料であってもよい。上述した構成材料の中でも、高い導電率と透明性の観点からは、酸化インジウムを主成分とするインジウム系複合酸化物を第一透明電極層１０６ａ、第二透明電極層１０６ｂとして用いることが好ましい。また、信頼性やより高い導電率を確保する為に、インジウム酸化物にドーパントを添加して用いることが更に好ましい。ドーパントとして用いる不純物としては、Ｓｎ，Ｗ，Ｃｅ，Ｚｎ，Ａｓ，Ａｌ，Ｓｉ，Ｓ，Ｔｉ等が挙げられる。 As a constituent material of the first transparent electrode layer 106a and the second transparent electrode layer 106b, transparent conductive metal oxides such as indium oxide, zinc oxide, tin oxide, titanium oxide, and composite oxides thereof can be used. . Further, it may be a non-metallic transparent conductive material such as graphene. Among the constituent materials described above, from the viewpoint of high conductivity and transparency, it is preferable to use an indium-based composite oxide containing indium oxide as a main component as the first transparent electrode layer 106 a and the second transparent electrode layer 106 b. Further, in order to secure the reliability and higher conductivity, it is more preferable to use a dopant added to indium oxide. As an impurity used as a dopant, Sn, W, Ce, Zn, As, Al, Si, S, Ti etc. are mentioned.
　［第二導電層形成ステップ］
　更に、第二導電層１０８を第二透明電極層１０６ｂ上に形成する。第二導電層１０８は図２に示されているような裏面金属電極でもよく、第二導電層１０８の形成方法としては、例えば、スパッタ法や蒸着法、めっき法などが挙げられるが、中でも裏面側のほぼ全面に容易に形成出来る観点から、スパッタ法により形成することが好ましい。裏面金属電極をスパッタ法により製膜する場合、精度よく被覆することができるため好ましい。特にヘテロ接合太陽電池などの結晶シリコン系太陽電池において一般的に用いられる凹凸構造付き基板を用いた場合、該凹凸部分にも精度よく被覆できるため、より好ましい。このような裏面金属電極の材料としては、Ｔｉ、Ｃｒ、Ｎｉ、Ｓｎ、Ａｇ、Ｃｕなどが好ましい。 [Step of forming second conductive layer]
Furthermore, the second conductive layer 108 is formed on the second transparent electrode layer 106 b. The second conductive layer 108 may be a back surface metal electrode as shown in FIG. 2. Examples of a method of forming the second conductive layer 108 include a sputtering method, a vapor deposition method, and a plating method. From the viewpoint of easy formation on almost the entire surface of the side, it is preferable to form by sputtering. In the case of forming a film on the back surface metal electrode by sputtering, it is preferable because it can be coated with high accuracy. In particular, when a substrate with a concavo-convex structure generally used in a crystalline silicon solar cell such as a heterojunction solar cell is used, the concavo-convex portion can be covered with high precision, which is more preferable. As a material of such a back surface metal electrode, Ti, Cr, Ni, Sn, Ag, Cu etc. are preferable.
　また、第二導電層は、第二透明電極層１０６ｂ（図２の１０６ｂ、図４の２０６ｂ）をそのまま第二導電層として使用してもよいし、図４の２０８の様に細線電極からなる集電極であってもよい。図２を参照して、第二導電層として第二透明電極層１０６ｂを用いる場合は、第二透明電極層１０６ｂが、光電変換素子１００の第２主面における略全面においてめっき給電用電極と接するため、めっき時において印過電圧の面内均一性が高くなる。また図４を参照して、第二導電層２０８として細線電極からなる集電極を用いた場合においても、半導体基板１０１や第一透明電極層２０６ａ（１０６ａ）および第二透明電極層２０６ｂ（１０６ｂ）により、細線電極のフィンガー電極間のキャリア移動距離程度であれば十分低抵抗を確保することができ、めっき時における印過電圧の面内均一性の高さを確保することができる。また、細線電極が第一導電層２０７－１と第二導電層２０８においてミラー対称を有しているか、第二導電層２０８のフィンガー電極の本数が第一導電層２０７－１のフィンガー電極よりも多い場合等においては、めっき時の電流は、主に集電極間を垂直に移動すると考えられるため、より面内均一性が高くなる。なお、図４において、光電変換素子２００、半導体基板２０１、真性シリコン系薄膜２０２ａ及び２０２ｂ、導電型シリコン系薄膜２０３ａ及び２０３ｂ、集電極２０７、めっき層２０７－２が図示されている。 Also, the second conductive layer may use the second transparent electrode layer 106b (106b in FIG. 2 and 206b in FIG. 4) as it is as the second conductive layer, as shown by 208 in FIG. It may be a collector. Referring to FIG. 2, in the case of using second transparent electrode layer 106 b as the second conductive layer, second transparent electrode layer 106 b is in contact with the plating power supply electrode on substantially the entire second main surface of photoelectric conversion element 100. Therefore, the in-plane uniformity of the mark overvoltage is high at the time of plating. Further, referring to FIG. 4, even in the case where a collecting electrode composed of fine line electrodes is used as second conductive layer 208, semiconductor substrate 101, first transparent electrode layer 206 a (106 a) and second transparent electrode layer 206 b (106 b) Accordingly, if the carrier movement distance between the finger electrodes of the thin wire electrode is about the same, a sufficiently low resistance can be secured, and the height of the in-plane uniformity of the imprinted overvoltage at the time of plating can be secured. In addition, the thin wire electrode has mirror symmetry in the first conductive layer 207-1 and the second conductive layer 208, or the number of finger electrodes of the second conductive layer 208 is greater than that of the first conductive layer 207-1. In many cases, it is considered that the current at the time of plating mainly moves vertically between the collecting electrodes, so that the in-plane uniformity becomes higher. In FIG. 4, the photoelectric conversion element 200, the semiconductor substrate 201, the intrinsic silicon based thin films 202a and 202b, the conductive silicon based thin films 203a and 203b, the collector electrode 207, and the plating layer 207-2 are illustrated.
　細線電極からなる第二導電層２０８を形成する細線電極の材料としては、例えばＮｉ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはこれらの合金等が使用できるが、電解めっき法における下地層として機能し得る程度の導電率を有していれば、特に限定されない。細線電極からなる第二導電層２０８の形成方法としては、例えば、インクジェット法、スクリーン印刷法、導線接着法、スプレー法、真空蒸着法、スパッタ法、電解めっき法、無電解めっき法などを用いることができる。コスト、および、量産性の観点からは上述の第一導電層の材料を含むペーストをスクリーン印刷法で印刷することが好ましい。 For example, Ni, Cu, Ag, Au, Pt, or an alloy thereof can be used as a material of the thin wire electrode forming the second conductive layer 208 formed of a thin wire electrode, but it can function as an underlayer in electrolytic plating. It is not particularly limited as long as it has a certain degree of conductivity. As a method of forming the second conductive layer 208 composed of fine line electrodes, for example, using an inkjet method, a screen printing method, a wire bonding method, a spray method, a vacuum evaporation method, a sputtering method, an electrolytic plating method, an electroless plating method, etc. Can. From the viewpoint of cost and mass productivity, it is preferable to print the paste containing the material of the first conductive layer described above by screen printing.
　［第一導電層１０７－１形成ステップ］
　図２を参照して、次に、第一透明電極層１０６ａの第１の主面側における集電極の形成領域に第一導電層１０７－１を形成する。すなわち、第一透明電極層１０６ａの上に第一導電層１０７－１を形成する。第一導電層１０７－１は、後述するめっき層１０７－２形成工程において、導電性の下地層として機能する層であり、めっき層１０７－２を析出させる電極となる層である。 [Step of Forming First Conductive Layer 107-1]
Referring to FIG. 2, next, a first conductive layer 107-1 is formed in the formation region of the collector electrode on the first main surface side of the first transparent electrode layer 106a. That is, the first conductive layer 107-1 is formed on the first transparent electrode layer 106a. The first conductive layer 107-1 is a layer that functions as a conductive underlayer in the step of forming a plated layer 107-2 described later, and is a layer that becomes an electrode for depositing the plated layer 107-2.
　第一導電層１０７－１形成ステップは、ｐ型半導体層１０３ａ形成ステップの後に行い、第一透明電極層１０６ａを設ける場合は第一透明電極層１０６ａ形成ステップの後に行う。第一導電層１０７－１形成ステップは、ｎ型半導体層１０２ｂ形成ステップよりも前に行ってもよい。 The step of forming the first conductive layer 107-1 is performed after the step of forming the p-type semiconductor layer 103a, and when the first transparent electrode layer 106a is provided, it is performed after the step of forming the first transparent electrode layer 106a. The step of forming the first conductive layer 107-1 may be performed before the step of forming the n-type semiconductor layer 102b.
　第一導電層１０７－１を形成する下地電極層の材料としては、例えばＮｉ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはこれらの合金等が使用できるが、電解めっき法における下地層として機能し得る程度の導電率を有していれば、特に限定されない。なお、本実施形態においては、第一導電層１０７－１は、第一透明電極層１０６ａよりも高い導電率を有していてもよいし、有していなくてもよい。 As a material of the base electrode layer for forming the first conductive layer 107-1, for example, Ni, Cu, Ag, Au, Pt, or an alloy thereof can be used, but the extent to which it can function as a base layer in the electrolytic plating method There is no particular limitation as long as it has the conductivity of In the present embodiment, the first conductive layer 107-1 may or may not have higher conductivity than the first transparent electrode layer 106a.
　第一導電層１０７－１の形成方法としては、例えば、インクジェット法、スクリーン印刷法、導線接着法、スプレー法、真空蒸着法、スパッタ法、電解めっき法、無電解めっき法などを用いることができる。コスト、および、量産性の観点からは上述の第一導電層の材料を含むペーストをスクリーン印刷法で印刷することが好ましい。 As a method of forming the first conductive layer 107-1, for example, an inkjet method, a screen printing method, a wire bonding method, a spray method, a vacuum evaporation method, a sputtering method, an electrolytic plating method, an electroless plating method, etc. can be used. . From the viewpoint of cost and mass productivity, it is preferable to print the paste containing the material of the first conductive layer described above by screen printing.
　ここで、第一導電層１０７－１が形成された未完成な光電変換素子は、その主面の垂線方向についてダイオードとなっており、第一導電層１０７－１から第二導電層１０８への方向がダイオードの順方向である。 Here, the uncompleted photoelectric conversion element in which the first conductive layer 107-1 is formed is a diode in the direction perpendicular to the main surface, and the first conductive layer 107-1 to the second conductive layer 108 The direction is the forward direction of the diode.
　［絶縁層１０９形成ステップ］
　次に、図３に示されているように第一透明電極層１０６ａの第１の主面側に絶縁層１０９を形成し未完成な光電変換素子１００Ａを形成する。絶縁層１０９形成ステップは、第一導電層１０７－１形成ステップの前後のどちらに行ってもよく、ｎ型半導体層１０３ｂ形成ステップの前に行ってもよい。 [Step of Forming Insulating Layer 109]
Next, as shown in FIG. 3, the insulating layer 109 is formed on the first main surface side of the first transparent electrode layer 106 a to form an incomplete photoelectric conversion element 100 </ b> A. The step of forming the insulating layer 109 may be performed either before or after the step of forming the first conductive layer 107-1 and may be performed before the step of forming the n-type semiconductor layer 103b.
　絶縁層１０９はフォトレジスト材料など、所定の条件を満たすことで除去可能な層により形成しても構わない。絶縁層１０９をフォトレジスト材料で形成した場合、光の照射によって構造変化を起こし、特定の薬品によって溶けやすくなる。 The insulating layer 109 may be formed of a layer that can be removed by satisfying a predetermined condition, such as a photoresist material. When the insulating layer 109 is formed of a photoresist material, light irradiation causes a structural change, which makes it easy to be dissolved by a specific chemical.
　本実施形態においては、絶縁層１０９は、後述するめっき層１０７－２形成工程において使用するめっき液に対する化学的安定性を有する材料を用いて形成する。このような材料を用いることにより、めっき層１０７－２形成工程の際に、絶縁層１０９が溶解しにくく、半導体基板１０１、ｐ型半導体層１０３ａ、ｎ型半導体層１０３ｂ等へのダメージが発生するのを抑制することができる。 In the present embodiment, the insulating layer 109 is formed using a material having chemical stability with respect to a plating solution used in the step of forming a plating layer 107-2 described later. By using such a material, the insulating layer 109 is difficult to dissolve in the step of forming the plating layer 107-2, and damage to the semiconductor substrate 101, the p-type semiconductor layer 103a, the n-type semiconductor layer 103b, and the like occurs. Can be suppressed.
　絶縁層１０９の形成に使用するフォトレジスト材料は、上述した性質を備えていれば特に限定されるものではないが、ポジ型ならノボラック樹脂、フェノール樹脂など、ネガ型ならアクリル樹脂などを使用することができる。 The photoresist material used to form the insulating layer 109 is not particularly limited as long as it has the above-mentioned properties, but a positive type novolac resin, a phenol resin etc., and a negative type acrylic resin etc. Can.
　また、絶縁層１０９を除去する除去液としては、例えば、テトラメチルアンモニウムハイドロオキサイド、アルキルベンゼンスルホン酸、エタノールアミン類、水酸化ナトリウムなどを含む溶液などを使用することができる。 Further, as a removing solution for removing the insulating layer 109, for example, a solution containing tetramethyl ammonium hydroxide, alkyl benzene sulfonic acid, ethanolamines, sodium hydroxide or the like can be used.
　本実施形態では、フォトレジスト材料として、ポジ型のノボラック樹脂を使用し、除去液として、水酸化ナトリウム水溶液を使用する。 In this embodiment, a positive novolak resin is used as the photoresist material, and an aqueous sodium hydroxide solution is used as the removal solution.
　絶縁層１０９は、ＳｉＯ、ＳｉＮ、ＳｉＯＮなどの無機絶縁膜により形成されていてもよい。無機絶縁膜を形成する方法は特に問わないが、精密な膜厚制御が可能なＣＶＤ法による製膜が好ましい。ＣＶＤ法であれば、材料ガスや製膜条件のコントロールで膜質制御が可能である。このような無機絶縁膜を使用する場合は、絶縁膜における光透過性が良いため、完成品において絶縁層１０９を残したままとしてもよい。 The insulating layer 109 may be formed of an inorganic insulating film such as SiO, SiN, or SiON. There is no particular limitation on the method of forming the inorganic insulating film, but film formation by the CVD method capable of precise film thickness control is preferable. In the case of the CVD method, film quality control can be performed by controlling the material gas and film forming conditions. In the case of using such an inorganic insulating film, the insulating layer 109 may be left in a completed product because light transmittance of the insulating film is good.
　［めっき層１０７－２形成ステップ］
　次に、第一導電層１０７－１の第１の主面側にめっき層１０７－２を形成する。めっき層１０７－２形成ステップは、第一導電層１０７－１形成ステップの後に行う。 [Step of Forming Plating Layer 107-2]
Next, the plating layer 107-2 is formed on the first main surface side of the first conductive layer 107-1. The step of forming the plating layer 107-2 is performed after the step of forming the first conductive layer 107-1.
　めっき層１０７－２の材料としては、例えばＮｉ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはこれらの合金等が使用できる。とりわけ、コストの観点から、Ｃｕが好適に用いられる。 As a material of the plating layer 107-2, for example, Ni, Cu, Ag, Au, Pt, or an alloy thereof can be used. Above all, Cu is preferably used in terms of cost.
　図８は、めっきを行う際の基板ホルダ１１４に未完成な光電変換素子１００Ａを装着した状態の一例を概略図として示している。ここで、未完成な光電変換素子１００Ａは、簡略化のため半導体基板１０１と第一導電層１０７－１、第二導電層１０８以外を省略して図示している。基板ホルダ１１４は背板１１４－１を有し、更に背板上に面状のめっき給電用電極１１７と、めっき給電用電極１１７に接続されるめっき給電用配線１１８を有している。めっき給電用電極１１７の上に未完成な光電変換素子１００Ａを配置し、パッキン１１４－２を、背板１１４－１と未完成な光電変換素子１００Ａの両方に密着させ、フレーム１１４－４と留め具１１４－３とで固定する。これにより、めっき給電用電極１１７と第二導電層１０８が、めっき液と接触せず、めっき給電用電極１１７と第二導電層１０８が、めっき液を介して第一導電層１０７－１と電気的に接続されることを防ぐことができる。このようにすることで、めっき時に電圧を印加した際に、めっき給電用電極１１７と第一導電層１０７－１との間にめっき液のような低抵抗な電気回路が形成されることを排除することができ、未完成な光電変換素子１００ＡのＰＮ接合からなるダイオードの順方向に電流を流すために十分な電圧が印加される。 FIG. 8 is a schematic view showing an example of a state in which the incomplete photoelectric conversion element 100A is mounted on the substrate holder 114 at the time of plating. Here, the uncompleted photoelectric conversion element 100A is illustrated with the components other than the semiconductor substrate 101, the first conductive layer 107-1, and the second conductive layer 108 omitted for simplification. The substrate holder 114 has a back plate 114-1, and further has a plating feeding electrode 117 and a plating feeding wire 118 connected to the plating feeding electrode 117 on the back plate. The uncompleted photoelectric conversion element 100A is disposed on the plating feeding electrode 117, and the packing 114-2 is brought into close contact with both the back plate 114-1 and the uncompleted photoelectric conversion element 100A, and the frame 114-4 is fastened Fix with the tool 114-3. Thus, the plating power supply electrode 117 and the second conductive layer 108 do not come in contact with the plating solution, and the plating power supply electrode 117 and the second conductive layer 108 are electrically connected to the first conductive layer 107-1 through the plating solution. Can be prevented from being connected. By doing this, it is excluded that a low resistance electric circuit such as a plating solution is formed between the plating power supply electrode 117 and the first conductive layer 107-1 when a voltage is applied during plating. A sufficient voltage is applied to cause current to flow in the forward direction of the diode formed of the PN junction of the incomplete photoelectric conversion element 100A.
　以上により基板ホルダ１１４を一例として説明したが、基板ホルダは、めっき給電用電極１１７と第二導電層１０８がめっき液と接触せず、かつ、第一導電層１０７－１がめっき液と接触するという条件を満たせば、どのような構造であっても構わない。例えば、図１０に示されているように、基板ホルダ２１４をめっき液２１６の液面に浮かせるような形で設置する場合は、基板ホルダ２１４の背面側はめっき液２１６の外にあり、めっき液２１６と接触しないため、背板を使用する必要はない。なお、図１０における基板ホルダは、簡単のためパッキンと留め具が省略されて図示してあり、未完成な光電変換素子２００Ａも半導体基板と第一導電層２０７－１以外は省略して図示している。また、図１０には、めっき装置２１１、めっき槽２１２、めっき電極２１３、フレーム２１４－４、電源２１５、めっき給電用電極２１７、めっき給電用配線２１８が図示されている。 Although the substrate holder 114 has been described above as an example, in the substrate holder, the plating power supply electrode 117 and the second conductive layer 108 do not contact the plating solution, and the first conductive layer 107-1 contacts the plating solution. Any structure may be used as long as the condition is satisfied. For example, as shown in FIG. 10, when the substrate holder 214 is installed in a form to float on the surface of the plating solution 216, the back side of the substrate holder 214 is outside the plating solution 216, and the plating solution is There is no need to use a backboard since it does not come in contact with 216. Note that the substrate holder in FIG. 10 is illustrated with packing and fasteners omitted for simplicity, and the incomplete photoelectric conversion element 200A is also illustrated with the exception of the semiconductor substrate and the first conductive layer 207-1. ing. Further, in FIG. 10, a plating apparatus 211, a plating tank 212, a plating electrode 213, a frame 214-4, a power supply 215, a plating power supply electrode 217, and a plating power supply wiring 218 are illustrated.
　また、めっき給電用電極は面状の形状をしており、光電変換素子１００における第二導電層の面積以上の面積を有することが好ましい。例えば、図３に示した裏面金属電極を用いた第二導電層１０８や、前述の第二透明電極層を第二導電層として用いた場合は、光電変換素子の裏面側の略全面に第二導電層が形成されている。この場合、第二導電層の面積以上の面積を有する面状のめっき給電用電極を、第二導電層全体を覆う様に接触させることにより、めっき給電時に第二導電層の光電変換素子面内方向における電気抵抗により生じる電位差の影響を抑制でき、光電変換素子全体に概ね均一に電圧が印加される。また、第二導電層が図４に示されているように細線電極から形成される場合は、第二導電層２０８における細線電極全体を覆う様にめっき給電用電極を接触させることが好ましい。 In addition, it is preferable that the plating feed electrode has a planar shape, and have an area equal to or larger than the area of the second conductive layer in the photoelectric conversion element 100. For example, when the second conductive layer 108 using the back surface metal electrode shown in FIG. 3 or the above-mentioned second transparent electrode layer is used as the second conductive layer, the second entire surface of the photoelectric conversion element is substantially entirely A conductive layer is formed. In this case, the planar plating power supply electrode having an area equal to or larger than the area of the second conductive layer is brought into contact so as to cover the entire second conductive layer, so that the photoelectric conversion element in the plane of the second conductive layer is supplied. The influence of the potential difference caused by the electrical resistance in the direction can be suppressed, and a voltage is applied almost uniformly to the entire photoelectric conversion element. When the second conductive layer is formed of a thin wire electrode as shown in FIG. 4, it is preferable to contact the plating power supply electrode so as to cover the entire thin wire electrode in the second conductive layer 208.
　面状のめっき給電用電極は、例えば板状であることが好ましいが、細線電極のみを覆うようなパターン形状を有していてもよく、また、メッシュ状であってもよい。また、めっき給電用電極としては、光電変換素子の面内方向においてめっき給電用電極内の電位差が大きくなり過ぎないように、十分な厚みを有しているバルクの金属を用いることが好ましく、めっき工程で用いる電流値の大きさに応じてその厚みを調整することが好ましい。 The planar plating power supply electrode is preferably, for example, plate-like, but may have a pattern shape that covers only the thin wire electrode, or may be mesh-like. In addition, as the plating feed electrode, it is preferable to use a bulk metal having a sufficient thickness so that the potential difference in the plating feed electrode does not become too large in the in-plane direction of the photoelectric conversion element. It is preferable to adjust the thickness according to the magnitude of the current value used in the process.
　図９は、このめっき層１０７－２形成ステップを示す概念図である。図９に示すめっき装置１１１において、めっき槽１１２内のめっき液１１６に、絶縁層１０９（図３）形成ステップ後の未完成な光電変換素子１００Ａを浸す。めっき液１１６としては、例えば金属塩を溶解したものを用いることができ、具体的には、硫酸銅が電離した硫酸銅水溶液などを用いることができる。即ち、本実施形態においては、めっき液１１６において、銅イオンと硫酸イオンが電離している。なお、図９における基板ホルダ１１４は、簡単のためパッキンと留め具が省略されて図示してあり、未完成の光電変換素子１００Ａも半導体基板と第一導電層１０７－１以外は省略して図示している。 FIG. 9 is a conceptual view showing the step of forming the plating layer 107-2. In the plating apparatus 111 shown in FIG. 9, the incomplete photoelectric conversion element 100A after the step of forming the insulating layer 109 (FIG. 3) is immersed in the plating solution 116 in the plating tank 112. For example, a solution in which a metal salt is dissolved can be used as the plating solution 116, and specifically, a copper sulfate aqueous solution or the like in which copper sulfate is ionized can be used. That is, in the present embodiment, in the plating solution 116, copper ions and sulfate ions are ionized. Note that the substrate holder 114 in FIG. 9 is illustrated with packing and fasteners omitted for simplicity, and the incomplete photoelectric conversion element 100A is also illustrated with the exception of the semiconductor substrate and the first conductive layer 107-1. It shows.
　めっき槽１１２内には、平板上の導電体であるめっき電極１１３が配置されている。めっき電極１１３は、ｐ型下地導電層１０３ａと対向するよう配置されている。めっき電極１１３は、電解めっきに用いられる金属単体又は金属合金で形成されたものである。本実施形態では、めっき液１１６として硫酸銅を使用しているため、めっき電極１１３として銅などを使用することができる。 In the plating tank 112, the plating electrode 113 which is a conductor on a flat plate is disposed. The plating electrode 113 is disposed to face the p-type base conductive layer 103 a. The plating electrode 113 is formed of a single metal or metal alloy used for electrolytic plating. In the present embodiment, since copper sulfate is used as the plating solution 116, copper or the like can be used as the plating electrode 113.
　めっき電極１１３は電源１１５の正極に接続されており、陽極となっている。めっき電極１１３は、未完成な光電変換素子１００Ａの半導体基板の略全面を覆う程度の大きさを有している。 The plating electrode 113 is connected to the positive electrode of the power source 115 and serves as an anode. The plating electrode 113 has a size that covers substantially the entire surface of the semiconductor substrate of the incomplete photoelectric conversion element 100A.
　電源１１５の負極には、めっき用給電配線１１８を介してめっき給電用電極１１７が接続され、このめっき給電用電極１１７を介して、第二導電層１０８が給電される。このとき、第二導電層１０８と第一導電層１０７－１とは、ｎ型半導体層１０３ｂとｐ型半導体層１０３ａとを含んで構成されるダイオードのみにより電気的に接続された状態である。 The plating feed electrode 117 is connected to the negative electrode of the power supply 115 via the plating feed wire 118, and the second conductive layer 108 is fed through the plating feed electrode 117. At this time, the second conductive layer 108 and the first conductive layer 107-1 are electrically connected only by a diode including the n-type semiconductor layer 103b and the p-type semiconductor layer 103a.
　すなわち、次の４つの条件が満たされた状態である。 That is, the following four conditions are satisfied.
　（１）第二導電層１０８と第一導電層１０７－１とが、未完成な光電変換素子１００Ａの構成に不要な導電性層等によって電気的に接続されていない。 (1) The second conductive layer 108 and the first conductive layer 107-1 are not electrically connected to each other by the unnecessary conductive layer or the like in the configuration of the incomplete photoelectric conversion element 100A.
　（２）第二導電層１０８に対する第一導電層１０７－１の電位差が順方向降下電圧以上になるよう電圧をかけた場合に、電流が、第二導電層１０８と第一導電層１０７－１を含んで構成されるダイオードを介して、第一導電層１０７－１にまで流れる。 (2) When a voltage is applied so that the potential difference of the first conductive layer 107-1 with respect to the second conductive layer 108 becomes equal to or higher than the forward drop voltage, the current flows through the second conductive layer 108 and the first conductive layer 107-1. Flow to the first conductive layer 107-1 via a diode configured to
　（３）めっき給電用電極１１７と等電位の給電部材が第一導電層１０７－１に接続されていない。 (3) The plating feed electrode 117 and a feed member of equal potential are not connected to the first conductive layer 107-1.
　（４）めっき給電用電極１１７と第二導電層１０８の両方が、めっき液１１６を介して第一導電層１０７－１と電気的に接続されていない。 (4) Both the plating power supply electrode 117 and the second conductive layer 108 are not electrically connected to the first conductive layer 107-1 via the plating solution 116.
　以上により、上述した第二導電層１０８と第一導電層１０７－１との間でダイオードの順方向に電流が流れるため、第一導電層１０７－１の露出する表面において、図２に示しためっき層１０７－２が形成される。 As described above, since the current flows in the forward direction of the diode between the above-described second conductive layer 108 and the first conductive layer 107-1, the exposed surface of the first conductive layer 107-1 is shown in FIG. The plated layer 107-2 is formed.
　このような製造方法により、第二導電層１０８と第一導電層１０７－１とを、光電変換素子１００の構成に不要な導電性層を形成することなく、めっき層１０７－２を形成することができる。 Forming the plating layer 107-2 without forming the second conductive layer 108 and the first conductive layer 107-1 without forming a conductive layer unnecessary for the configuration of the photoelectric conversion element 100 by such a manufacturing method Can.
　なお、本実施形態においては、ｎ型半導体層１０３ｂとｐ型半導体層１０３ａとを含んで構成されるダイオードがＰＮ接合の場合を例示したが、ｎ型半導体層１０３ｂとｐ型半導体層１０３ａとの間に真性半導体層が介在し、ｎ型半導体層１０３ｂ、真性半導体層、ｐ型半導体層１０３ａにより構成されるダイオードがＰＩＮ接合であってもよい。 In the present embodiment, the case where the diode configured to include the n-type semiconductor layer 103 b and the p-type semiconductor layer 103 a is a PN junction is illustrated, but the n-type semiconductor layer 103 b and the p-type semiconductor layer 103 a The intrinsic semiconductor layer may be interposed therebetween, and the diode formed by the n-type semiconductor layer 103b, the intrinsic semiconductor layer, and the p-type semiconductor layer 103a may be a PIN junction.
　以上の様にめっきを行うことにより、第一導電層１０７－１の光電変換素子面内方向における電気抵抗による電位差を大幅に抑制することが可能であり、第一導電層１０７－１上に均一にめっき層１０８を形成することが可能となる。本発明によると、めっきにおける給電を下地電極層に行う従来の太陽電池の製造方法のように、めっき時に印加する電流を段階的に増加させる必要がなく、最初からめっき速度を高めて作製できるため製造効率が高くなる。更には、第一導電層１０７－１上に不均一にめっき電圧が印加される場合であれば、印過電圧が低い箇所がめっき形成されにくい。このようなめっき形成がされにくい箇所の電気抵抗ロスを低減させようとすると、めっき時間を長くする必要があり、めっきがされやすいところのめっき層の幅が太くなるため、遮光ロスが増加する。以上により、本発明による製造方法を使用することで、均一なめっき層を形成することができ、集電時の電気抵抗ロスや遮光ロスが低減される。 By performing plating as described above, it is possible to significantly suppress the potential difference due to the electrical resistance in the in-plane direction of the photoelectric conversion element of the first conductive layer 107-1, and uniform on the first conductive layer 107-1. It is possible to form the plating layer 108 on the According to the present invention, unlike the conventional method of manufacturing a solar cell in which feeding in plating is performed to the base electrode layer, the current applied during plating does not have to be increased stepwise, and the plating rate can be increased from the beginning. Manufacturing efficiency is increased. Furthermore, in the case where the plating voltage is applied unevenly on the first conductive layer 107-1, the portion where the mark overvoltage is low is unlikely to be plated. If it is intended to reduce the electrical resistance loss in a portion where such plating formation is difficult, it is necessary to lengthen the plating time, and the width of the plating layer where plating is likely to be increased, so that the light shielding loss increases. As mentioned above, by using the manufacturing method by this invention, a uniform plating layer can be formed and the electrical resistance loss and light-shielding loss at the time of current collection are reduced.
　（第２の実施形態）
　本開示の第２の実施形態について、図５および図６を用いて以下に説明する。 Second Embodiment
A second embodiment of the present disclosure will be described below with reference to FIGS. 5 and 6.
　図５では、光電変換素子３００が示されている。光電変換素子３００は表面側の透明電極層３０６ａに接するようにめっき層３０７－２が形成されている。このように、第一導電層として下地電極層を使用しない構造とすることで、第２の実施形態は製造コストの低減が期待できる。図６に光電変換素子３００を形成する上での未完成の光電変換素子３００Ａを示す。未完成の光電変換素子３００Ａでは、第一導電層３０７－１が第一透明電極層３０６ａにより形成されており、前述のフォトレジスト材料などにより形成された絶縁層３０９で覆われている。絶縁層３０９は開口部を有し、開口部は細線電極などのパターンを有していることが好ましい。本実施形態における光電変換素子のその他の製造方法は、第１実施形態による製造方法と同様の方法で作製される。本実施形態のように、第一導電層３０７－１が第一透明電極層３０６ａである場合は、光電変換素子の面内方向における電気抵抗の高さから、通常のめっき方法のように点による接触方法を用いた給電では、面内均一性高くめっき層を形成することは困難である。これは第一導電層３０７－１である透明電極層３０６ａの面内方向における電気抵抗により、給電部から離れるにしたがって電位差が生じるためである。一方で、本発明によると、裏面側の第二導電層３０８に面状で接するめっき給電用電極により、未完成の光電変換素子３００ＡのＰＮ接合からなるダイオードを介することで、均一性高く第一導電層３０７－１に電流を流すことができ均一なめっき層が形成される。なお、図５及び６において、未完成の光電変換素子３００Ａ、半導体基板３０１、真性シリコン系薄膜３０２ａ及び３０２ｂ、導電型シリコン系薄膜３０３ａ及び３０３ｂ、第二透明電極層３０６ｂ、集電極３０７及び光電変換ユニット３５０が図示されている。 In FIG. 5, the photoelectric conversion element 300 is shown. In the photoelectric conversion element 300, a plating layer 307-2 is formed in contact with the transparent electrode layer 306a on the front surface side. As described above, the second embodiment can be expected to reduce the manufacturing cost by adopting a structure in which the base electrode layer is not used as the first conductive layer. The uncompleted photoelectric conversion element 300A in forming the photoelectric conversion element 300 is shown in FIG. In the uncompleted photoelectric conversion element 300A, the first conductive layer 307-1 is formed of the first transparent electrode layer 306a, and is covered with the insulating layer 309 formed of the aforementioned photoresist material or the like. The insulating layer 309 preferably has an opening, and the opening preferably has a pattern such as a thin wire electrode. The other manufacturing method of the photoelectric conversion element in the present embodiment is manufactured by the same method as the manufacturing method according to the first embodiment. As in the present embodiment, when the first conductive layer 307-1 is the first transparent electrode layer 306a, the height of the electrical resistance in the in-plane direction of the photoelectric conversion element makes the point as in the usual plating method. In feeding using a contact method, it is difficult to form a plating layer with high in-plane uniformity. This is because the electric resistance in the in-plane direction of the transparent electrode layer 306a which is the first conductive layer 307-1 causes a potential difference as it is separated from the feeding portion. On the other hand, according to the present invention, the plating feeding electrode in contact with the second conductive layer 308 on the back surface side in a planar manner makes it possible to achieve high uniformity by interposing the diode formed of the PN junction of the incomplete photoelectric conversion element 300A. A current can be supplied to the conductive layer 307-1 to form a uniform plating layer. 5 and 6, the incomplete photoelectric conversion element 300A, the semiconductor substrate 301, the intrinsic silicon-based thin films 302a and 302b, the conductive silicon-based thin films 303a and 303b, the second transparent electrode layer 306b, the collector electrode 307, and photoelectric conversion Unit 350 is shown.
　（第３の実施形態）
　本開示の第３の実施形態について、図７を用いて以下に説明する。 Third Embodiment
A third embodiment of the present disclosure will be described below with reference to FIG.
　図７は、本発明の製造方法により形成する未完成の光電変換素子４００Ａの表面側を示す平面図である。未完成の光電変換素子４００Ａは、図に記載の点線で領域分けを示唆可能な、４つの細線電極領域が第一導電層４０７－１により形成されており、それぞれの細線電極領域には複数のバスバー電極と、このバスバー電極と交差するように設けられた多数のフィンガー電極を有している。なお、バスバー電極およびフィンガー電極のデザインは前述のものに限定されず、どのようなものであってもよい。また、バスバー電極は有していなくてもよく、フィンガー電極のみ形成されていてもよい。細線電極領域は金属ペーストなどからなる下地電極層であってもよいし、絶縁層が細線電極上の開口部を有する第一透明電極層であってもよい。それぞれの細線電極領域は、外観上孤立している。第一導電層４０７－１が下地電極層である場合は、下地電極層が外観上孤立しており、第一導電層４０７－１が第一透明電極層である場合は、絶縁層の開口部が外観上孤立している。第一導電層４０７－１が下地電極層である場合は、下地電極層が外観上孤立していればよく、下地電極層より半導体基板４０１側に形成された不図示の第一透明電極層により電気的に接続されていてもよい。また、第一導電層４０７－１が第一透明電極層である場合は、絶縁層の開口部が外観上孤立していればよく、第一透明電極層が絶縁層の半導体基板４０１側において、半導体基板４０１の略全面に渡って形成されていてもよい。本実施形態における未完成の光電変換素子４００Ａにおいて、めっき工程後に形成されためっき層は、第一導電層４０７－１に従って外観上孤立している。なお、図７では、外観状孤立する４つの細線電極領域が形成されているが、本実施形態では、細線電極領域の数は複数である限り限定されず、Ｎ個（２≦Ｎ）であればよい。 FIG. 7 is a plan view showing the surface side of an incomplete photoelectric conversion element 400A formed by the manufacturing method of the present invention. In the incomplete photoelectric conversion element 400A, four thin wire electrode regions capable of suggesting division into regions by dotted lines shown in the figure are formed by the first conductive layer 407-1, and a plurality of thin wire electrode regions are formed in each thin wire electrode region. A bus bar electrode and a large number of finger electrodes provided to cross the bus bar electrode are included. The design of the bus bar electrode and the finger electrode is not limited to that described above, and may be any design. Further, the bus bar electrode may not be provided, and only the finger electrode may be formed. The thin wire electrode region may be a base electrode layer made of metal paste or the like, or the insulating layer may be a first transparent electrode layer having an opening on the thin wire electrode. Each thin wire electrode region is isolated in appearance. When the first conductive layer 407-1 is a base electrode layer, the base electrode layer is isolated in appearance and when the first conductive layer 407-1 is a first transparent electrode layer, the opening of the insulating layer Are isolated on the appearance. When the first conductive layer 407-1 is a base electrode layer, the base electrode layer only needs to be isolated in appearance, and the first transparent electrode layer (not shown) formed on the semiconductor substrate 401 side from the base electrode layer It may be electrically connected. When the first conductive layer 407-1 is the first transparent electrode layer, the opening of the insulating layer may be isolated in appearance, and the first transparent electrode layer may be on the semiconductor substrate 401 side of the insulating layer, It may be formed over substantially the entire surface of the semiconductor substrate 401. In the uncompleted photoelectric conversion element 400A in the present embodiment, the plating layer formed after the plating step is isolated in appearance according to the first conductive layer 407-1. In FIG. 7, four thin wire electrode regions that are isolated in appearance are formed, but in the present embodiment, the number of thin wire electrode regions is not limited as long as it is plural, and N (2 ≦ N) Just do it.
　本実施形態の様に、外観上孤立した複数の第一導電層４０７－１を有する場合、通常のめっき方法であれば各第一導電層にめっき給電を実施する必要があるため、細線電極領域の数が多い場合は、めっきを実施することが困難となる。本発明によると、未完成の光電変換素子４００Ａにおける裏面側の第二導電層に面状で接するめっき給電用電極により、未完成の光電変換素子４００ＡのＰＮ接合からなるダイオードを介することで、均一性高く第一導電層４０７－１に電流を流すことができ、均一なめっき層が形成される。 As in the present embodiment, in the case of having a plurality of first conductive layers 407-1 isolated in appearance, it is necessary to carry out plating power feeding to each first conductive layer if it is a usual plating method, so a thin wire electrode region If the number is large, it will be difficult to perform plating. According to the present invention, the plating power supply electrode in planar contact with the second conductive layer on the back surface side of the uncompleted photoelectric conversion element 400A makes it possible to achieve uniformity by interposing the PN junction of the uncompleted photoelectric conversion element 400A. Therefore, current can flow to the first conductive layer 407-1 with high conductivity, and a uniform plating layer is formed.
　本実施形態による光電変換素子は、未完成の光電変換素子４００Ａにおけるめっき工程後に、外観上孤立した細線電極領域を、例えば図に記載の点線部分で分割し、複数の光電変換素子が形成されてもよい。未完成の光電変換素子４００Ａをめっき工程後に分割する方法としては、特に限定されないが、例えばレーザーダイシングまたはブレードダイシングが挙げられる。特に、複雑な形状または曲面を切り出すことができることから、レーザーダイシングが好ましい。このように複数の光電変換素子に分割する場合、めっき層が細線電極領域において外観上孤立していることで、レーザーダイシングやブレードダイシングの切断部分にめっき層が形成されない。（逆に言うと、めっき層が形成されていない部分をレーザーダイシングやブレードダイシングで切断する。）従来との相違点について、詳しく説明する。　例えば、従来の通常の方法では、めっき層側にめっき給電を行う際に、下地電極層を全て外観上つなげて形成されていることが一般的であり、切断部分にもめっき層が形成される場合がある。このような場合において、銅などを略全面にめっき層として使用する場合を考える。その場合、めっき層が形成されていない部分が少なく、また、切断部分にもめっき層が形成されているため、めっき層ごと（めっき層が付いたまま）レーザーダイシングを行うと、レーザーによって、めっき層の銅が溶解して切断面などにおいて半導体基板に付着することで、半導体基板内へ拡散してしまい、光電変換素子の特性低下が生じるおそれが有る。しかしながら本発明の様に、切断部分にめっき層を形成しないことにより、前記のような、めっき層由来の銅の拡散による光電変換素子の特性低下が抑制される。また、切断部分にめっき層を形成しないことにより、ブレードダイシングや（引き続く）折り割り時における物理的な相互作用により、めっき層の一部が光電変換素子から剥がれることも防ぐことができる。 In the photoelectric conversion element according to the present embodiment, after the plating process in the incomplete photoelectric conversion element 400A, the thin wire electrode region isolated in appearance is divided, for example, by the dotted line portion shown in the figure, and a plurality of photoelectric conversion elements are formed It is also good. Although it does not specifically limit as a method to divide | segment uncompleted photoelectric conversion element 400A after a plating process, For example, laser dicing or blade dicing is mentioned. In particular, laser dicing is preferable because complicated shapes or curved surfaces can be cut out. Thus, when dividing | segmenting into several photoelectric conversion elements, a plating layer is not formed in the cutting part of laser dicing or blade dicing because the plating layer is isolated on appearance in a thin wire | line electrode area | region. (Conversely, the portion where the plating layer is not formed is cut by laser dicing or blade dicing.) The difference from the conventional one will be described in detail. For example, in the conventional method, when the plating power supply is performed on the plating layer side, it is general that the base electrode layers are all connected in appearance and the plating layer is also formed in the cut portion There is a case. In such a case, the case of using copper or the like on the substantially entire surface as a plating layer is considered. In that case, there are few portions where the plating layer is not formed, and the plating layer is also formed at the cut portion. Therefore, if laser dicing is performed for each plating layer (with the plating layer attached), plating by a laser When the copper of the layer melts and adheres to the semiconductor substrate at the cut surface or the like, the copper may diffuse into the semiconductor substrate and the characteristics of the photoelectric conversion element may be degraded. However, as described in the present invention, by not forming the plating layer in the cut portion, the characteristic deterioration of the photoelectric conversion element due to the diffusion of copper derived from the plating layer as described above is suppressed. Moreover, by not forming a plating layer in a cut part, it can also prevent that a part of plating layer peels from a photoelectric conversion element by the physical interaction at the time of blade dicing and (following) cleavage.
　図７に点線で示したような複数の細線電極領域は、最終的に形成する光電変換素子の数よりも多くてもよく、外観上孤立した複数の細線電極領域からなるめっき層が、一つの光電変換素子上に形成されていてもよい。 The plurality of thin wire electrode regions as shown by dotted lines in FIG. 7 may be more than the number of photoelectric conversion elements to be finally formed, and the plating layer composed of a plurality of thin wire electrode regions isolated in appearance is one It may be formed on the photoelectric conversion element.
　本実施形態による光電変換素子のその他の製造方法は、第１の実施形態と同様に実施される。 The other manufacturing method of the photoelectric conversion element according to the present embodiment is carried out in the same manner as the first embodiment.

Claims (14)

  1. 　第１主面と第１主面の裏面である第２主面とを備える光電変換ユニットを含む光電変換素子の製造方法であって、
    　前記光電変換ユニットは第１主面側から第２主面側に向かって順に、少なくとも、ｐ型半導体層及びｎ型半導体層を備え、
    　前記光電変換素子はさらに、前記光電変換ユニットの第１主面側に第一導電層を備え、前記光電変換ユニットの第２主面側に第二導電層を備え、
    　前記第一導電層上にめっき層を形成するめっき層形成工程を備え、
    　前記めっき層形成工程において、めっき給電用電極と前記第二導電層とを面状に接触させた状態で、かつ、めっき給電用電極および第二導電層をめっき液と接触させない状態で、めっきを行う、光電変換素子の製造方法。     A manufacturing method of a photoelectric conversion element including a photoelectric conversion unit including a first main surface and a second main surface which is a back surface of the first main surface,
    The photoelectric conversion unit includes at least a p-type semiconductor layer and an n-type semiconductor layer in order from the first main surface side to the second main surface side,
    The photoelectric conversion device further includes a first conductive layer on the first main surface side of the photoelectric conversion unit, and a second conductive layer on the second main surface side of the photoelectric conversion unit,
    And a plating layer forming step of forming a plating layer on the first conductive layer,
    In the plating layer forming step, the plating is performed in a state in which the plating feeding electrode and the second conductive layer are in plane contact and the plating feeding electrode and the second conductive layer are not in contact with the plating solution. The manufacturing method of a photoelectric conversion element to carry out.
  2. 　前記めっき層形成工程において、前記第二導電層の面積以上の面積を有するめっき給電用電極を前記第二導電層に面状に接触させた状態でめっきを行う、請求項１に記載の光電変換素子の製造方法。 The photoelectric conversion according to claim 1, wherein in the plating layer forming step, plating is performed in a state in which a plating feeding electrode having an area equal to or larger than the area of the second conductive layer is in planar contact with the second conductive layer. Method of manufacturing a device
  3. 　前記第一導電層が第一透明電極層である、請求項１又は２に記載の光電変換素子の製造方法。 The manufacturing method of the photoelectric conversion element of Claim 1 or 2 whose said 1st conductive layer is a 1st transparent electrode layer.
  4. 　前記光電変換素子は、さらに前記光電変換ユニットの第１主面側に第一透明電極層を備え、前記第一導電層が第一透明電極層の上に設けられている、請求項１又は２に記載の光電変換素子の製造方法。 The photoelectric conversion device further includes a first transparent electrode layer on the first principal surface side of the photoelectric conversion unit, and the first conductive layer is provided on the first transparent electrode layer. The manufacturing method of the photoelectric conversion element as described in-.
  5. 　前記第一導電層がＮｉ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、またはこれらの合金からなる下地電極層である、請求項１、２又は４に記載の光電変換素子の製造方法。 The manufacturing method of the photoelectric conversion element of Claim 1, 2 or 4 whose said 1st conductive layer is a base electrode layer which consists of Ni, Cu, Ag, Au, Pt, or these alloys.
  6. 　前記第一導電層が細線電極である、請求項１～５のいずれか１項に記載の光電変換素子の製造方法。 The method of manufacturing a photoelectric conversion element according to any one of claims 1 to 5, wherein the first conductive layer is a thin wire electrode.
  7. 　前記第一導電層は、少なくとも一部が絶縁層で覆われている、請求項１～６のいずれか１項に記載の光電変換素子の製造方法。 The method of manufacturing a photoelectric conversion element according to any one of claims 1 to 6, wherein at least a part of the first conductive layer is covered with an insulating layer.
  8. 　前記第二導電層が第二透明電極層である、請求項１～７のいずれか１項に記載の光電変換素子の製造方法。 The method for producing a photoelectric conversion element according to any one of claims 1 to 7, wherein the second conductive layer is a second transparent electrode layer.
  9. 　前記光電変換素子は、さらに前記光電変換ユニットの第２主面側に第二透明電極層を備え、前記第二導電層が第二透明電極層の上に設けられている、請求項１～７のいずれか１項に記載の光電変換素子の製造方法。 The photoelectric conversion device further includes a second transparent electrode layer on the second principal surface side of the photoelectric conversion unit, and the second conductive layer is provided on the second transparent electrode layer. The manufacturing method of the photoelectric conversion element of any one of these.
  10. 　前記第二導電層が細線電極である、請求項１～９のいずれか１項に記載の光電変換素子の製造方法。 The method for producing a photoelectric conversion element according to any one of claims 1 to 9, wherein the second conductive layer is a fine line electrode.
  11. 　さらに、第一導電層を、第１主面側から平面視した場合に外観上孤立するＮ個（ただし、２≦Ｎ）以上の細線電極領域として形成する工程を備える、請求項１～１０のいずれか１項に記載の光電変換素子の製造方法。 The method according to claim 1, further comprising the step of forming the first conductive layer as N (where 2 ≦ N) or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side. The manufacturing method of the photoelectric conversion element of any one term.
  12. 　さらに、第一導電層を、第１主面側から平面視した場合に外観上孤立するＮ個（ただし、２≦Ｎ）以上の細線電極領域として形成する工程を備え、
    　さらに、第１主面側から平面視した場合に外観上孤立するＮ個以上の細線電極領域付きの光電変換素子を、めっき層が形成されていない部位において分割し、Ｎ個の光電変換素子を形成する工程を備える、請求項１～１０のいずれか１項に記載の光電変換素子の製造方法。     And a step of forming the first conductive layer as N (where 2 ≦ N) or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side,
    Furthermore, the photoelectric conversion element with N or more thin wire electrode regions isolated in appearance when viewed in plan from the first main surface side is divided at a portion where the plating layer is not formed, and N photoelectric conversion elements are obtained. The method for producing a photoelectric conversion element according to any one of claims 1 to 10, comprising the step of forming.
  13. 　請求項１～１２のいずれか１項に記載の光電変換素子の製造方法に用いられる、めっき用治具であって、
    　前記めっき層形成工程において、めっき給電用電極とめっき液とを接触させない状態で、かつ、めっき給電用電極と前記第二導電層とを面状に接触させた状態で、めっきを行うことが可能な、少なくとも、フレーム、パッキン、留め具、を備えるめっき用治具。     A plating jig used for the method of manufacturing a photoelectric conversion element according to any one of claims 1 to 12,
    In the plating layer forming step, plating can be performed in a state in which the plating power supply electrode and the plating solution are not in contact with each other and in a state in which the plating power supply electrode and the second conductive layer are in planar contact. A plating jig provided with at least a frame, a packing, and a fastener.
  14. 　請求項１３に記載のめっき用治具を備えるめっき装置。 A plating apparatus comprising the plating jig according to claim 13.
PCT/JP2018/041838 2017-12-27 2018-11-12 Method for producing photoelectric conversion element, tool for plating, and plating apparatus WO2019130859A1 (en)

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