JP2016195188A - Method of manufacturing solar cell and method of manufacturing solar cell module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a solar cell which allows for formation of a collector electrode having a high aspect ratio by a plating method, by suppressing occurrence of plating scorch.SOLUTION: A method of manufacturing a solar cell has a step of forming a metal seed layer on one principal surface of a photoelectric conversion part, a step of forming a first plating layer on the metal seed layer, and a step of forming a second plating layer on the first plating layer. In the step of forming a metal seed layer, a finger seed layer constituting a finger electrode is formed. Assuming the current density when forming the first plating layer is DK, and the current density when forming the second plating layer is DK, the following relationship is satisfied preferably; DK<DK<40A/dm. In the step of forming the second plating layer, the second plating layer is formed while disposing an insulating shield plate on the principal surface normal of the photoelectric conversion part, so as to cover the end of the finger seed layer in the plating liquid.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a method for manufacturing a solar cell and a method for manufacturing a solar cell module.

  As energy problems and global environmental problems become more serious, solar cells are attracting attention as alternative energy alternatives to fossil fuels. In a solar cell, electric power is generated by taking out carriers (electrons and holes) generated by light irradiation to a photoelectric conversion unit made of a semiconductor junction or the like to an external circuit. In order to efficiently extract carriers generated in the photoelectric conversion unit to an external circuit, a collector electrode is provided on the photoelectric conversion unit of the solar cell.

  The region where the collecting electrode is formed on the light receiving surface side of the solar cell is a region where light does not enter the photoelectric conversion unit and does not contribute to power generation. Therefore, from the viewpoint of reducing the light-shielding loss due to the collector electrode, it is required to increase the ratio of the thickness to the line width (aspect ratio) of the collector electrode.

  Examples of a method for forming a collector electrode of a solar cell include a method of forming a silver paste or the like by pattern printing by a screen printing method, a method of forming a collector electrode by a plating method, or the like. Silver paste or the like contains a resin material and thus has low electrical conductivity, whereas a metal layer formed by plating has high electrical conductivity. Therefore, high efficiency of the solar cell can be expected by forming the collecting electrode by a plating method. For example, in Patent Documents 1 and 2, after a resist pattern having an opening corresponding to the shape of the collector electrode is formed on a seed layer that is a starting point of plating, a plating layer is formed in the resist opening, and the resist is removed. Is disclosed.

In addition to “isotropic plating” in which the plating layer is grown to the same extent in the width and thickness directions, the rate of growth in the thickness direction is larger than the rate in which the plating layer is grown in the width direction. “Anisotropic plating” is known. Patent Document 3 discloses a method of growing a plating layer anisotropically at a relatively high current density after the plating layer isotropically grown at a relatively low current density. In Patent Document 3, when plating is performed at a high current density, the plating solution is stirred using a paddle blade or the like. According to Patent Document 3, it is considered that the metal ion dilute layer formed on the surface of the plating layer is destroyed by stirring of the plating solution, and the plating layer is formed at the location where the metal ion dilute layer is destroyed. . In the example of Patent Document 3, after forming a plating layer having a thickness of 18 μm at a current density of 5 A / dm ² , a plating layer having a total thickness of 140 μm is formed at a current density of 50 A / dm ² .

JP-A-11-204361 JP-A-11-204337 JP 2014-80674 A

  According to the method described in Patent Document 3, it is said that the plating surface state, anisotropic growth, pattern spacing, and the like can be controlled with high accuracy, and a plating layer having a high aspect ratio can be formed. In order to form a collector electrode having a high aspect ratio, the present inventors considered forming a collector electrode of a solar cell by a plating method described in Patent Document 3. However, when the solar cell collecting electrode is formed by the plating method described in Patent Document 3, not only the plating layer does not grow uniformly in the thickness direction, but also a portion where the plating layer grows in the width direction occurs. It has been found. Furthermore, metal was deposited at unintended locations. The state in which the surface shape of the plating layer is not uniform is called “plating burn”.

  This invention is made | formed in view of the above, and it aims at providing the manufacturing method of the solar cell which can suppress the generation | occurrence | production of a plating burn and can form the collector electrode with a high aspect ratio by the plating method.

  The present invention relates to a method of manufacturing a solar cell that includes a photoelectric conversion unit and a collector electrode that is provided on one main surface of the photoelectric conversion unit and includes a plurality of finger electrodes. In the manufacturing method of the present invention, the step of forming a metal seed layer on one main surface of the photoelectric conversion unit and the first plating layer are formed on the metal seed layer in a state where the photoelectric conversion unit is immersed in a plating solution. And a step of forming a second plating layer on the first plating layer in a state where the photoelectric conversion part is immersed in the plating solution.

In the step of forming the metal seed layer, a finger seed layer constituting the finger electrode is formed. When DK ₁ is the first current density when forming the first plating layer and DK ₂ is the second current density when forming the second plating layer, DK ₁ <DK ₂ <40 A / dm ² is satisfied. Is preferred. In the step of forming the second plating layer, the second plating is performed in a state where an insulating shielding plate is disposed on the principal surface normal line of the photoelectric conversion unit so as to cover the end of the finger seed layer in the plating solution. A layer is formed.

The first current density DK ₁ preferably satisfies _{1 A} / dm ² ≦ DK ₁ ≦ 12 A / dm ² . The second current density DK ₂ preferably satisfies 15 A / dm ² ≦ DK ₂ ≦ 38 A / dm ² .

  In one embodiment, the collector electrode further includes a bus bar electrode connected to the finger electrode. In this case, in the step of forming the metal seed layer, a bus bar seed layer constituting the bus bar electrode is also formed. The bus bar seed layer is formed so that the width of the bus bar seed layer is larger than the width of the finger seed layer.

  In the embodiment, in the step of forming the first plating layer, it is preferable that the first plating layer is formed on the bus bar seed layer and the finger seed layer by supplying power to the bus bar seed layer. In this case, it is preferable to supply power by arranging a plurality of power supply points per bus bar seed layer.

  Also in the step of forming the first plating layer, it is preferable that the first plating layer is formed in a state where the shielding plate is arranged so as to cover the end portion of the finger seed layer in the plating solution.

  In one embodiment, the ends of the finger seed layer are connected. In the step of forming the second plating layer, the second plating layer may be formed in a state where the shielding plate is disposed so as to cover the metal seed layer connecting the end portions of the finger seed layer in the plating solution. preferable.

  In one embodiment, the photoelectric conversion unit has a silicon-based thin film and a transparent electrode layer in this order on one main surface of a conductive single crystal silicon substrate. In this case, a collecting electrode is formed on the transparent electrode layer.

  In one embodiment, an insulating layer is formed on a region where the metal seed layer is not formed on one main surface of the photoelectric conversion unit. The insulating layer may also be formed on the metal seed layer. In this case, the plating layer is electrically connected to the metal seed layer through the opening provided in the insulating layer.

  The present invention relates to a method for manufacturing a solar cell module in which a solar cell manufactured by the above-described manufacturing method is connected to another solar cell or an external circuit via a wiring member.

According to the present invention, after forming the first plating layer with a relatively low current density DK ₁ , the plating layer grows in the width direction by forming the second plating layer with a relatively high current density DK ₂ . The rate of growth in the thickness direction can be made larger than the rate of performing. Furthermore, when forming at least the second plating layer, the end of the metal seed layer constituting the finger electrode is shielded by the shielding plate against the electric field from the plating electrode, so that the electric field is applied to the end of the metal seed layer. Can be reduced. As a result, the occurrence of plating burn is suppressed and a collector electrode with a high aspect ratio can be formed.

It is a typical top view of the solar cell concerning one embodiment. It is a schematic plan view of a solar cell according to another embodiment. It is a conceptual diagram which shows one Embodiment of a photoelectric conversion part preparation process. It is a conceptual diagram which shows one Embodiment of a metal seed layer formation process. It is a conceptual diagram which shows one Embodiment of an insulating layer formation process. It is a conceptual diagram which shows one Embodiment of a 1st plating layer formation process. It is a conceptual diagram which shows one Embodiment of a 2nd plating layer formation process. It is a structure schematic diagram of a plating apparatus. It is a schematic plan view which shows an example of the state by which the edge part of the metal seed layer was shielded. It is a schematic plan view which shows the example which has arrange | positioned the feeding point to the both ends of each bus bar seed layer. It is a schematic top view which shows the example which has arrange | positioned the feeding point on each bus-bar seed layer so that the distance between feeding points may become equal. It is typical sectional drawing of the heterojunction solar cell which concerns on one Embodiment. It is a graph which shows the relationship between plating time and current density. It is an optical microscope photograph which shows the surface of the finger electrode of each Example and a comparative example.

  FIG. 1 is a schematic plan view of a solar cell according to an embodiment. As shown in FIG. 1, the solar cell of the present invention includes a collector electrode 7 on one main surface of a photoelectric conversion unit 50. In the example shown in FIG. 1, the collector electrode 7 includes a plurality of finger electrodes 7 a extending in parallel with each other at a predetermined interval, and a bus bar electrode 7 b that collects current collected by the finger electrodes 7 a. The finger electrode 7a is preferably formed so as to be substantially perpendicular to the extending direction of the bus bar electrode 7b. The bus bar electrode 7b is preferably formed to be wider than the finger electrode 7a and substantially perpendicular to the extending direction of the finger electrode 7a. The bus bar electrode may not be linear and may be non-linear such as zigzag. Even when the bus bar electrode is non-linear, the finger electrode is preferably formed so as to be substantially perpendicular to the extending direction of the bus bar electrode. “Substantially perpendicular” means that the angle formed by the finger electrode and the bus bar electrode is 85 degrees or more and 95 degrees or less. In particular, the bus bar electrode is preferably formed so that the angle formed by the finger electrode and the bus bar electrode is 90 degrees, that is, orthogonal to the finger electrode. Note that the bus bar electrode 7b is not necessarily required, and the collector electrode 7 may be constituted only by the finger electrodes 7a.

  FIG. 2 is a schematic plan view of a solar cell according to another embodiment. As shown in FIG. 2, it is preferable that the collector electrode 70 has the ends of a plurality of finger electrodes 70a connected by connecting electrodes 70c. As described above, when the end portions of the finger electrodes 70a are connected, electricity flows to the connecting electrode 70c, so that the electric field can be prevented from concentrating on the end portions of the finger electrodes 70a. In addition, when the end portions of the finger electrodes 70a are connected, electricity flows to the other electrodes through the connecting electrodes 70c even when a part of the finger electrodes 70a is disconnected. In said embodiment, the edge part of at least 1 set of finger electrode should just be connected, and it is preferable that the edge part of all the finger electrodes is connected. In addition, when the edge part of the finger electrode 70a is connected by the connection electrode 70c, the cross | intersection part of the finger electrode 70a and the connection electrode 70c is considered as the edge part of the finger electrode 70a.

[Method of forming collector electrode]
3-7 is a process conceptual diagram which shows one Embodiment of the method of forming the collector electrode 7 on the photoelectric conversion part 50. FIG. In this embodiment, first, the photoelectric conversion unit 50 is prepared (photoelectric conversion unit preparation step, FIG. 3). For example, in the case of a heterojunction solar cell, a photoelectric conversion unit including a silicon-based thin film and a transparent electrode layer is prepared on a conductive single crystal silicon substrate.

  A metal seed layer 71 is formed on one main surface of the photoelectric conversion unit 50 (metal seed layer forming step, FIG. 4).

  In the present embodiment, the insulating layer 9 is formed on a region (metal seed layer non-formation region) where the metal seed layer 71 is not formed on one main surface of the photoelectric conversion unit 50 (insulating layer forming step, FIG. 5). When a transparent electrode layer is formed on the surface of the photoelectric conversion part like a heterojunction solar cell, an insulating layer is formed on the transparent electrode layer in order to suppress metal deposition on the transparent electrode layer. It is preferable. In FIG. 5, the insulating layer 9 is also formed on the metal seed layer 71. In order to form a first plating layer 721 (described later) on the metal seed layer 71 by a plating method, it is necessary to make the metal seed layer 71 and the plating solution conductive. Therefore, an opening 9 h is provided in the insulating layer 9 on the metal seed layer 71.

  A first plating layer 721 is formed on the metal seed layer 71 by a plating method (first plating layer forming step, FIG. 6). Further, a second plating layer 722 is formed on the first plating layer 721 (second plating layer forming step, FIG. 7). In the present embodiment, the metal seed layer 71 is covered with the insulating layer 9, but the metal seed layer 71 is exposed at a portion where the opening 9 h is formed in the insulating layer 9. Therefore, the metal seed layer 71 is exposed to the plating solution, and metal can be deposited starting from the opening 9h.

In the present invention, after the first plating layer 721 at a relatively low current density DK ₁ is formed, the second plating layer 722 is formed at a relatively high current density DK _2. By forming the first plating layer 721 on the surface of the metal seed layer 71, the resistance of the underlayer for forming the second plating layer 722 can be lowered. Therefore, even when plating is performed at a high current density to form the second plating layer 722, it is possible to reduce the concentration of the electric field on a part of the metal seed layer 71 and to suppress the occurrence of plating burn.

  As described in Patent Document 3 mentioned above, the higher the current density during plating, the more the plating layer grows anisotropically, that is, the plating layer grows in the thickness direction rather than the width direction. Can do. Therefore, it is considered that a collector electrode having a high aspect ratio can be formed by plating the metal seed layer 71 at a high current density. However, when the metal seed layer 71 is plated at a high current density, the resistance of the metal seed layer 71 is higher than that of the plating layer 72, and thus a part of the metal seed layer 71, particularly the metal seed layer 71. The electric field tends to concentrate on the edge of the. As a result, the amount of metal deposition increases at locations where the electric field concentrates, and plating burns are likely to occur.

  In the present invention, at least the second plating layer 722 is formed with the end portion of the metal seed layer 71 shielded against the electric field from the plating electrode (anode). This can reduce the concentration of the electric field at the end of the metal seed layer 71.

  Hereinafter, each step will be described in detail.

(Metal seed layer formation process)
The metal seed layer 71 functions as a conductive underlayer when the plating layer is formed by a plating method. The metal seed layer 71 may be composed of a plurality of layers. The material of the metal seed layer 71 is not specifically limited, For example, silver, copper, aluminum, etc. can be used.

  The metal seed layer 71 can be formed by various printing methods such as an inkjet method, a screen printing method, a spray method, or a coating method. From the viewpoint of productivity, the screen printing method is preferable. In the screen printing method, a process of printing a conductive paste composed of metal particles and a resin binder by screen printing is preferably used.

  As shown in FIG. 1, when the collector electrode 7 including the finger electrode 7a and the bus bar electrode 7b is formed, as the metal seed layer 71, the finger seed layer constituting the finger electrode 7a and the bus bar seed constituting the bus bar electrode 7b A layer is formed.

  As shown in FIG. 2, when the collector electrode 70 in which the end portions of the plurality of finger electrodes 70a are connected by the connecting electrode 70c is formed, a finger seed layer in which the end portions are connected is formed. As described above, it is preferable to form the metal seed layer so that the end portions of the plurality of finger seed layers are connected from the viewpoint of preventing the concentration of the electric field on the end portion of the metal seed layer.

The film thickness d ₁ of the metal seed layer 71 is preferably 20 μm or less, more preferably 15 μm or less, and even more preferably 10 μm or less from the viewpoint of cost. On the other hand, from the viewpoint of setting the line resistance within a desired range, the thickness d ₁ of the metal seed layer 71 is preferably 0.5 μm or more, and more preferably 1 μm or more. When the collector electrode includes a finger electrode and a bus bar electrode, the thickness of the bus bar seed layer may be the same as the thickness of the finger seed layer, may be larger than the thickness of the finger seed layer, It may be smaller than the film thickness of the seed layer.

From the viewpoint of reducing the light-shielding loss, it is preferable that the width of the collecting electrode after forming the plating layer is as small as possible. By reducing the width W ₁ of the metal seed layer 71, it is possible to reduce the width W of the collector electrode 7 after plating layer formation. From the above, the width W ₁ of the metal seed layer 71 is preferably 5 to 200 μm, and more preferably 30 to 100 μm. When the collector electrode includes a finger electrode and a bus bar electrode, the width of the finger seed layer is preferably in the above range.

(First plating layer forming step)
The first plating layer 721 is formed by a plating method starting from the metal seed layer 71. The metal deposited as the first plating layer 721 is not particularly limited as long as it is a material that can be formed by plating. For example, copper, nickel, tin, aluminum, chromium, silver, gold, zinc, lead, palladium, or the like, or these Can be used.

  FIG. 8 is a conceptual diagram of a plating apparatus used for forming a plating layer. The substrate 12 on which the metal seed layer 71 is formed on the photoelectric conversion unit 50 and the anode 13 are immersed in the plating solution 16 in the plating tank 11. The anode 13 is disposed so as to face the metal seed layer 71 on the photoelectric conversion unit 50. The metal seed layer 71 on the substrate 12 is connected to the power source 15 via the substrate holder 14. An insulating shielding plate 20 is disposed between the substrate 12 and the anode 13.

  A metal can be deposited on the metal seed layer 71 by applying a voltage between the anode 13 and the substrate 12. At this time, the electric field from the anode 13 tends to concentrate on the end of the metal seed layer 71, and the tendency becomes more prominent as the applied voltage increases. Therefore, the shielding plate 20 is disposed between the substrate 12 and the anode 13, and the end of the metal seed layer 71 is shielded against the electric field from the anode 13, so that the electric field is concentrated on the end of the metal seed layer 71. Can be reduced.

  FIG. 9 is a schematic plan view illustrating an example of a state where the end portion of the metal seed layer is shielded. FIG. 9 is a plan view from the anode 13 side in the direction in which the photoelectric conversion unit 50 (substrate 12) and the anode 13 face each other. In the example illustrated in FIG. 9, the shielding plate 20 is disposed on the main surface normal line of the photoelectric conversion unit 50. Specifically, the shielding plate 20 is disposed so as to cover the end portion of the finger seed layer 71a and the end portion of the bus bar seed layer 71b in the direction in which the photoelectric conversion portion and the anode face each other.

  In the present invention, it is only necessary that at least the end portion of the finger seed layer is shielded, and the portions other than the end portion of the finger seed layer may be shielded or may not be shielded. Moreover, the edge part of a bus-bar seed layer may be shielded and does not need to be shielded. For example, when a solar cell is manufactured using a 6-inch square silicon wafer, a region of about 5 mm to 40 mm from the edge of the main surface may be shielded.

  In the case of forming the finger seed layer having the ends connected to each other, it is preferable that the metal seed layer connecting the ends of the finger seed layer is also shielded in addition to the ends of the finger seed layer.

  The shape and size of the shielding plate are not particularly limited as long as at least the end portion of the finger seed layer is shielded. Moreover, when an opening is provided in the shielding plate, the shape of the opening is not particularly limited. The material of the shielding plate is not particularly limited as long as it is an insulating material, but is preferably stable to the plating solution. For example, polyvinyl chloride, polypropylene, polyethylene, acrylic resin, fluorine resin, or the like is used. be able to.

  As long as the shielding plate 20 is disposed between the substrate 12 and the anode 13, the shielding plate 20 may or may not contact the substrate 12 (metal seed layer 71). Therefore, the shielding plate 20 is preferably not in contact with the substrate 12. The position where the shielding plate 20 is disposed between the substrate 12 and the anode 13 is not particularly limited. However, if the shielding plate 20 is too far from the substrate 12, a sufficient shielding effect cannot be obtained. There is a risk. Therefore, the distance between the shielding plate 20 and the substrate 12 (metal seed layer 71) (the distance represented by L in FIG. 8) is preferably about 0.5 to 5 cm.

  When performing plating using a plating apparatus, it is necessary to bring the electrode terminal into contact with the metal seed layer. When the collector electrode includes a finger electrode and a bus bar electrode, plating can be performed by supplying power to one or both of the finger seed layer and the bus bar seed layer, but at least plating is performed by supplying power to the bus bar seed layer. It is preferable. By supplying power to the bus bar seed layer, not only a plating layer can be formed on the bus bar seed layer but also a plating layer can be formed on the finger seed layer.

  The film thickness of the plating layer increases as the distance from the electrode terminal (feeding point) in contact with the metal seed layer increases, and the film thickness of the plating layer tends to decrease as the distance from the power supply point increases. Therefore, it is preferable to arrange a plurality of feeding points on the metal seed layer from the viewpoint of forming a plating layer having a uniform film thickness. When the collector electrode includes a finger electrode and a bus bar electrode, it is preferable to arrange a plurality of feeding points on each bus bar seed layer. If too many feeding points are arranged on the bus bar seed layer, there are many places where the plating layer is not formed. Therefore, it is preferable to arrange two to five feeding points on each bus bar seed layer.

  When arranging a plurality of feeding points on each bus bar seed layer, it is preferable to arrange the feeding points so that the distances between the feeding points are equal. In this case, as shown in FIG. 10, feeding points 17 may be arranged at both ends of each bus bar seed layer 71b, or as shown in FIGS. 11 (a) and 11 (b). The feeding point 17 may be arranged on an equal dividing point of each bus bar seed 71b layer so that the distance between them is equal. In the example shown in FIG. 11A, the feeding points 17 are arranged on two of the four equally divided points of each bus bar seed 71b layer so that the distances between the two feeding points 17 are equal. In the example shown in FIG. 11B, the feeding points 17 are arranged on three of the six equally divided points of each bus bar seed 71b layer so that the distances between the three feeding points 17 are equal. Has been. As described above, the thickness of the plating layer tends to decrease as the distance from the feeding point increases. For example, as shown in FIG. 10, when two feeding points are arranged at both ends of each bus bar seed layer, the distance from the feeding point to the farthest point is 1/2 of the length of the bus bar seed layer. On the other hand, as shown in FIG. 11A, when the feeding point is arranged on two of the four equally divided points of each bus bar seed layer, the distance from the feeding point to the farthest point is the length of the bus bar seed layer. 1/4 of this. Thus, it is preferable that a plurality of feeding points are arranged on the equally dividing points of each bus bar seed layer from the viewpoint that the distance to the feeding point can be reduced and the thickness of the plating layer can be made uniform.

  In the first plating layer forming step, it is preferable to grow the first plating layer 721 isotropically. That is, it is preferable that the first plating layer 721 is grown to the same extent in the thickness direction and the width direction. For this reason, the cross-sectional shape of the first plating layer 721 is preferably a shape in which the upper part is curved.

The current density DK ₁ when forming the first plating layer 721 is not particularly limited as long as it is smaller than the current density DK ₂ when forming the second plating layer 722. From the viewpoint of suppressing the occurrence of plating burn, the current density DK ₁ is preferably 12 A / dm ² or less, and more preferably 10 A / dm ² or less. On the other hand, from the viewpoint of increasing the metal deposition rate, the current density DK ₁ is preferably 1 A / dm ² or more, and more preferably 3 A / dm ² or more.

  The plating time in the first plating layer forming step is appropriately set according to the area of the collecting electrode, the current density, the cathode current efficiency, the set film thickness, etc., and can be, for example, about 10 to 60 seconds.

  The temperature of the plating solution in the first plating layer forming step can be, for example, about 20 to 40 ° C.

(Second plating layer forming step)
In the second plating layer forming step, the current density is higher than the current density when forming the first plating layer 721 while the substrate 12 is immersed in the plating solution 16 used to form the first plating layer. Plating is performed. Thereby, the 2nd plating layer 722 can be grown anisotropically.

  Although the details of the mechanism by which the plating layer grows anisotropically by plating at a high current density is not clear, for example, it is estimated as follows. In FIG. 6, the top of the first plating layer 721 is close to the anode, whereas the bottom of the first plating layer 721 (near the photoelectric conversion unit 50) is away from the anode. Therefore, in the initial stage of the second plating layer forming process, the electric field is more likely to concentrate on the top than on the bottom of the plating layer, and the plating layer grows from the vicinity of the top to the vicinity of the bottom. Here, since plating is performed at a higher current density than in the first plating layer forming step in the second plating layer forming step, the consumption rate of metal ions for forming the plating layer is large. Therefore, in the second plating layer forming step, the plating solution existing around the top so that the metal ion concentration in the plating solution existing near the top of the plating layer is rapidly reduced to compensate for the decrease in the metal ion concentration. The metal ions inside move toward the top of the plating layer. As a result, the plating layer further grows near the top, and thereafter consumption of metal ions and supplementation of metal ions from the surroundings are repeated. On the other hand, in the vicinity of the bottom of the plating layer, metal ions are difficult to be supplied, and the metal ion concentration remains low. As a result, the growth near the top of the plating layer is promoted and the growth near the bottom is suppressed. From the above, as shown in FIG. 7, the second plating layer 722 is considered to grow in the thickness direction rather than the width direction.

Current density DK ₂ at the time of forming the second plating layer 722 is greater than the current density DK ₁ for forming the first plating layer 721 is not particularly limited as long as it is less than 40A / dm ^2. From the viewpoint of suppressing the occurrence of plating burn, the current density DK ₂ is preferably 38 A / dm ² or less, more preferably 35 A / dm ² or less, and even more preferably 32 A / dm ² or less. On the other hand, from the viewpoint of growing a plated layer anisotropically, current density DK ₂ is, 15A / dm ² or more is preferable, 17A / dm ² or more, more preferably, 18A / dm ² or more is more preferable.

  The plating time in the second plating layer forming step is appropriately set according to the area of the collecting electrode, the current density, the cathode current efficiency, the set film thickness, etc., and can be, for example, about 100 to 300 seconds.

  The temperature of the plating solution in the second plating layer forming step can be, for example, about 20 to 40 ° C.

  When shifting from the first plating layer forming step to the second plating layer forming step, it is preferable to instantaneously switch the voltage applied between the anode 13 and the substrate 12 from a low voltage to a high voltage. Thereby, it becomes possible to suppress the growth of the plating layer in the width direction.

  In the above example, the case where the first plating layer 721 and the second plating layer 722 are formed in a state where the end portion of the finger seed layer 71a is shielded is described. However, the end portion of the metal seed layer 71 is shielded. Is not necessary when the first plating layer 721 is formed, but may be performed at least when the second plating layer 722 is formed. As described above, when shifting from the first plating layer formation step to the second plating layer formation step, it is preferable to instantaneously switch the voltage applied between the anode 13 and the substrate 12 from a low voltage to a high voltage, It is preferable that the first plating layer 721 is formed in a state where the end portion of the finger seed layer 71a is shielded in advance, and the second plating layer 722 is formed in that state.

  The composition of the plating solution used for forming the first plating layer and the second plating layer is not particularly limited. For example, in the case of copper plating, an acidic copper plating solution having a known composition mainly composed of copper sulfate, sulfuric acid, and water can be used as the plating solution. An additive may be added to the plating solution. Examples of the additive include an accelerator for promoting precipitation, an inhibitor for suppressing precipitation so as to obtain a uniform film thickness, and a smoothing agent for partially suppressing precipitation and smoothing the surface. And a brightener for imparting gloss to the plating layer.

(Insulating layer formation process)
In the example shown in FIG. 5, the insulating layer 9 is formed on the metal seed layer 71 and the metal seed layer non-formation region. As described above, when a transparent electrode layer is formed on the surface of the photoelectric conversion part as in a heterojunction solar cell, an insulating layer is formed on the transparent electrode layer in order to suppress metal deposition on the transparent electrode layer. Is preferably formed.

  The material of the insulating layer may be an inorganic insulating material or an organic insulating material. As the inorganic insulating material, for example, materials such as silicon oxide, silicon nitride, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide can be used. As the organic insulating material, for example, materials such as polyester, ethylene vinyl acetate copolymer, acrylic, epoxy, and polyurethane can be used. Among these, an inorganic insulating material is preferable, silicon oxide or silicon nitride is more preferable, and silicon oxide is particularly preferable.

  The insulating layer can be formed using a known method. For example, in the case of an inorganic insulating material such as silicon oxide or silicon nitride, a dry method such as a plasma CVD method or a sputtering method is preferably used. In the case of an organic insulating material, a wet method such as a spin coating method or a screen printing method is preferably used. In particular, the insulating layer is preferably formed by a plasma CVD method from the viewpoint of forming a film having a dense structure. In addition, for example, when the surface of the photoelectric conversion part has a texture structure (uneven structure) as in the heterojunction solar cell shown, the insulating layer is also a plasma from the viewpoint that the film can be accurately formed on the textured concave and convex parts It is preferably formed by a CVD method.

The film thickness of the insulating layer can be appropriately set according to the material and forming method of the insulating layer, and is preferably 1000 nm or less, more preferably 500 nm or less. In addition, by appropriately setting the optical characteristics and film thickness of the insulating layer in the region where the metal seed layer is not formed, the light reflection characteristics are improved, the amount of light introduced into the solar cell is increased, and the conversion efficiency is further improved. Is possible. Thus, from the viewpoint of imparting suitable antireflection properties to the insulating layer, the thickness d ₀ of the insulating layer 9 on the metal seed layer non-forming region is preferably 30 nm to 250 nm, and preferably 50 nm to 250 nm. More preferred. The film thickness of the insulating layer on the metal seed layer may be different from the film thickness of the insulating layer on the metal seed layer non-forming region.

  In order to form the first plating layer 721 on the metal seed layer 71 by plating, it is necessary to make the metal seed layer and the plating solution conductive. Therefore, it is necessary to provide the opening 9h in the insulating layer 9 on the metal seed layer 71. As a method of forming the opening in the insulating layer, a method of patterning the insulating layer using a resist can be given. Alternatively, the opening may be formed in the insulating layer by a method such as laser irradiation, mechanical drilling, or chemical etching.

In addition to the above, as a method for forming a plating layer through the opening of the insulating layer, the following technique or the like can be adopted.
After forming an insulating layer on the transparent electrode layer, providing a groove penetrating the insulating layer to expose the surface or side surface of the transparent electrode layer, and depositing a metal seed layer on the exposed surface of the transparent electrode layer by photoplating or the like Then, a plating layer is formed by plating using this metal seed layer as a starting point (see JP 2011-199045 A).
By forming the insulating layer on the uneven metal seed layer, the insulating layer becomes discontinuous, so that an opening is formed. A plating layer is formed by plating from this opening as a starting point (WO2011 / 045287).
After forming the insulating layer on the metal seed layer containing the low melting point material or at the time of forming the insulating layer, the low melting point material is thermally fluidized by heating to form an opening in the insulating layer on the metal seed layer. A plating layer is formed by plating as a starting point (WO2013 / 077038).
After forming the self-assembled monolayer as the insulating layer, the self-assembled monolayer on the metal seed layer is peeled off to form an opening in the insulating layer (the metal seed layer is exposed) ). A plating layer is formed by plating using the exposed metal seed layer as a starting point. Since the self-assembled monolayer is formed on the transparent electrode layer, deposition of the plating layer on the transparent electrode layer is suppressed (WO2014 / 097829).

  These methods are more advantageous in terms of material cost and process cost because it is not necessary to use a resist. Moreover, the contact resistance between a transparent electrode layer and a collector electrode can be reduced by providing a low-resistance metal seed layer.

Through the first plating layer forming step and the second plating layer forming step, the plating layer 72 including the first plating layer 721 and the second plating layer 722 is formed on the metal seed layer 71 as shown in FIG. Can do. As described above, the collector electrode 7 including the metal seed layer 71 and the plating layer 72 can be formed on one main surface of the photoelectric conversion unit 50. The thus formed collector electrode 7 has a uniform film thickness and a high aspect ratio. When the width and film thickness of the metal seed layer 71 are W ₁ and d ₁ , respectively, and the width and film thickness of the plating layer 72 are W ₂ and d ₂ , respectively, W ₂ −W ₁ <2 × d ₂ is satisfied. preferable. The film thickness d ₂ of the plating layer 72 means the distance between the top of the metal seed layer 71 and the top of the plating layer 72.

Thickness _{d 2} of the plating layer 72 is preferably from 5 to 30 [mu] m, 10 to 20 [mu] m is more preferable. Moreover, 10-220 micrometers is preferable, as for the width W ₂ of the plating layer 72, 35-120 micrometers is more preferable, and 40-100 micrometers is further more preferable.

Furthermore, when the insulating layer 9 is formed on the metal seed layer non-formation region, when the film thickness of the insulation layer 9 on the metal seed layer non-formation region is d ₀ , 100 × d ₀ <d ₁ + d ₂ It is preferable to satisfy.

(Other processes)
After forming the second plating layer, the current density when forming the second plating layer 722 while the substrate 12 is immersed in the plating solution 16 used to form the first plating layer and the second plating layer. Plating may be performed stepwise at a higher current density. In that case, the current density is preferably switched by instantaneously switching the voltage applied between the anode 13 and the substrate 12 from a low voltage to a high voltage. In addition, after the second plating layer is formed, the second plating layer 722 is formed while the substrate 12 is immersed in the plating solution 16 used to form the first plating layer and the second plating layer. Plating may be performed at a current density lower than the current density.

  Furthermore, even if the substrate is immersed in a plating solution different from the plating solution used to form the first plating layer and the second plating layer, a plating layer made of a metal different from the first plating layer and the second plating layer is formed. Good. For example, by forming a plating layer made of a material with high conductivity such as copper on a metal seed layer, and then forming a plating layer made of a material with excellent chemical stability such as tin, low resistance and chemical stability A collector electrode with excellent properties can be formed. When forming a plating layer composed of a plurality of types of metals, it is not necessary to perform the first plating layer forming step and the second plating layer forming step described above for all the metals, except for the plating layer formed on the metal seed layer, It may be formed by a conventional plating method.

  After forming the plating layer, it is preferable to provide a plating solution removing step to remove the plating solution remaining on the surface of the photoelectric conversion portion. Moreover, after forming a plating layer, an insulating layer removal process may be performed.

[Solar cell]
Hereinafter, the configuration of the solar cell will be described in more detail using the heterojunction solar cell as an example. A heterojunction solar cell is a crystalline silicon solar cell in which a diffusion potential is formed by having a silicon-based thin film having a band gap different from that of single crystal silicon on the surface of a conductive single crystal silicon substrate. The silicon-based thin film is preferably amorphous. In particular, a thin intrinsic amorphous silicon layer interposed between a conductive amorphous silicon thin film for forming a diffusion potential and a single crystal silicon substrate has the highest conversion efficiency. It is known as one of battery forms.

  FIG. 12 is a schematic cross-sectional view of a heterojunction solar cell according to an embodiment. The solar cell 101 shown in FIG. 12 has, as the photoelectric conversion unit 50, the conductive silicon thin film 3a and the transparent electrode layer 6a in this order on one surface of the substrate 1 (light incident side surface, light receiving surface). On the other surface of the substrate 1 (surface opposite to the light incident side, back surface), the conductive silicon-based thin film 3b and the transparent electrode layer 6b are provided in this order. The solar cell 101 preferably has intrinsic silicon-based thin films 2a and 2b between the substrate 1 and the conductive silicon-based thin films 3a and 3b, respectively.

  A collecting electrode 7 including a metal seed layer 71 and a plating layer 72 is formed on the transparent electrode layer 6 a on the light incident side. A back electrode 8 is formed on the transparent electrode layer 6b on the back side. In the example shown in FIG. 2, the insulating layer 9 is formed on the transparent electrode layer 6 a where the metal seed layer 71 is not formed, and an opening 9 h is formed between the metal seed layer 71 and the plating layer 72. An insulating portion 9 is formed.

  The conductivity type of the single crystal silicon substrate 1 may be n-type or p-type. When holes and electrons are compared, electrons have a higher mobility. Therefore, when the silicon substrate 1 is an n-type single crystal silicon substrate, the conversion characteristics are particularly high. The silicon substrate 1 has a texture on at least the first main surface side, preferably on both surfaces. The texture is formed using, for example, an anisotropic etching technique. The texture formed by anisotropic etching has a quadrangular pyramid uneven structure.

  Intrinsic silicon thin films 2a and 2b are preferably provided between single crystal silicon substrate 1 and conductive silicon thin films 3a and 3b. By providing an intrinsic silicon-based thin film on the surface of the single crystal silicon substrate, surface passivation can be effectively performed while suppressing diffusion of impurities into the single crystal silicon substrate. In order to effectively perform surface passivation of the single crystal silicon substrate 1, the intrinsic silicon thin films 2a and 2b are preferably intrinsic amorphous silicon thin films.

As a method for forming the intrinsic silicon-based thin films 2a and 2b, a plasma CVD method is preferable. As conditions for forming an intrinsic silicon-based thin film by plasma CVD, a substrate temperature of 100 to 300 ° C., a pressure of 20 to 2600 Pa, and a high frequency power density of 0.004 to 0.8 W / cm ² are preferably used. As a raw material gas used for forming a silicon-based thin film, a mixed gas of a silicon-containing gas such as SiH ₄ or Si ₂ H ₆ and H ₂ is preferably used.

  One of the conductivity types of the conductive silicon thin films 3a and 3b is p-type, and the other is n-type. Examples of the p-type or n-type conductive silicon thin films 3a and 3b include amorphous silicon, microcrystalline silicon (a material containing amorphous silicon and crystalline silicon), amorphous silicon alloy, and microcrystalline silicon alloy. Etc. are used. Examples of the silicon alloy include silicon oxide, silicon carbide, silicon nitride, and silicon germanium. Among these, the conductive silicon thin film is preferably an amorphous silicon thin film.

The conductive silicon-based thin films 3a and 3b are also preferably formed by plasma CVD, as with the intrinsic silicon-based thin films 2a and 2b. When the conductive silicon thin film is formed, PH ₃ or B ₂ H ₆ is used as a dopant gas for adjusting the conductive type (n-type or p-type). Since the addition amount of the conductivity determining impurity may be small, it is preferable to use a dopant gas diluted with SiH ₄ or H ₂ in advance. When forming a conductive silicon thin film, the energy gap can be changed by alloying the silicon thin film by adding a gas containing a different element such as CO ₂ , CH ₄ , NH ₃ , GeH _4. it can.

  Transparent electrode layers 6a and 6b are formed on the conductive silicon thin films 3a and 3b, respectively. The transparent electrode layers 6a and 6b are preferably composed mainly of a conductive oxide. As the conductive oxide, for example, zinc oxide, indium oxide, tin oxide or the like can be used alone or as a composite oxide. From the viewpoints of conductivity, optical characteristics, and long-term reliability, indium-based oxides are preferable, and indium tin oxide (ITO) as the main component is more preferably used. The film thickness of the transparent electrode layers 6a and 6b is preferably 10 nm or more and 140 nm or less from the viewpoints of transparency, conductivity, and light reflection reduction.

  These transparent electrode layers are formed by a dry process (PVD method such as CVD, sputtering, or ion plating). PVD methods such as sputtering and ion plating are preferable for forming a transparent electrode layer containing indium oxide as a main component.

  In the heterojunction solar cell, a metal collector electrode is formed on the transparent electrode layers 6a and 6b in order to effectively extract photogenerated carriers.

The collector 7 on the light incident side is formed in a predetermined pattern. The collector electrode 7 can be formed by the method described so far. As described above, when the width and thickness of the metal seed layer 71 are W ₁ and d ₁ , and the width and thickness of the plating layer 72 are W ₂ and d ₂ , respectively, W ₂ −W ₁ <2 × d ₂ It is preferable to satisfy. Further, when the insulating layer 9 is formed on the metal seed layer non-forming region, when the thickness of the insulating layer 9 on the metal seed layer non-forming region is d ₀ , 100 × d ₀ <d ₁ + d ₂ It is preferable to satisfy.

  The back electrode 8 on the back surface side may be patterned, or may be formed on substantially the entire surface of the transparent electrode layer. Examples of the method for forming the back electrode 8 include dry processes such as various PVD methods and CVD methods, paste application, plating methods, and the like. As the back electrode 8, it is desirable to use a material having a high reflectance of light in the near-infrared to infrared wavelength region and high conductivity and chemical stability. Examples of materials satisfying such characteristics include silver, copper, and aluminum.

  As described above, the case where the collector electrode 7 is provided on the light incident side of the heterojunction solar cell has been mainly described, but a similar collector electrode may be formed on the back surface side. Since a solar cell using a single crystal silicon substrate, such as a heterojunction solar cell, has a large amount of current, in general, power generation loss due to loss of contact resistance between the transparent electrode layer / collector electrode tends to be significant. On the other hand, in the present invention, since the collector electrode including the metal seed layer and the plating layer has a low contact resistance with the transparent electrode layer, it is possible to reduce power generation loss due to the contact resistance.

  The present invention also relates to a crystalline silicon solar cell other than a heterojunction solar cell, a solar cell using a semiconductor substrate other than silicon such as GaAs, a pin junction or a pn junction of an amorphous silicon thin film or a crystalline silicon thin film. Various types of organic thin film solar cells such as silicon-based thin film solar cells having a transparent electrode layer formed thereon, compound semiconductor solar cells such as CIS and CIGS, dye-sensitized solar cells and organic thin films (conductive polymers) Applicable to solar cells.

A crystalline silicon solar cell has a configuration in which a diffusion layer of reverse conductivity type (for example, n-type) is provided on one main surface of a single conductivity type (for example, p-type) crystalline silicon substrate, and the collector electrode is provided on the diffusion layer. Can be mentioned. Such a crystalline silicon solar cell is generally provided with a conductive layer such as a p ⁺ layer on the back side of one conductive layer. Examples of the silicon thin film solar cell include an amorphous silicon thin film solar cell having an amorphous intrinsic (i type) silicon thin film between a p type thin film and an n type thin film, and a p type thin film and an n type thin film. Examples thereof include a crystalline silicon-based semiconductor solar cell having a crystalline intrinsic silicon thin film between the thin film. A tandem thin film solar cell in which a plurality of pin junctions are stacked is also suitable.

  When the solar cell of the present invention is put into practical use, it is preferably sealed by a sealing material and modularized. The modularization of the solar cell is performed by an appropriate method. For example, a bus bar electrode is connected to the collector electrode via an interconnector such as a tab, so that a plurality of solar cells are connected in series or in parallel, and sealed by a sealing material and a glass plate to be modularized. Done.

  Hereinafter, the present invention will be specifically described with reference to examples relating to heterojunction solar cells. In addition, this invention is not limited to a following example.

Example 1
The heterojunction solar cell of Example 1 was manufactured as follows. An n-type single crystal silicon wafer having a plane orientation of (100), a size of 156 mm square, and a thickness of 200 μm is used as a single conductivity type single crystal silicon substrate, and this silicon wafer is made into a 2 wt% HF aqueous solution. After immersing for 3 minutes and removing the silicon oxide film on the surface, rinsing with ultrapure water was performed twice. This silicon substrate was immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 15 minutes, and the texture was formed by etching the surface of the wafer. Thereafter, rinsing with ultrapure water was performed twice. When the surface of the wafer was observed with an atomic force microscope (manufactured by AFM Pacific Nanotechnology), the surface of the wafer was in progress of etching, and a pyramidal texture with an exposed (111) plane was formed. .

The etched wafer was introduced into a CVD apparatus, and an i-type amorphous silicon film having a thickness of 5 nm was formed on the light incident side as an intrinsic silicon-based thin film 2a. The film formation conditions for the i-type amorphous silicon were: substrate temperature: 170 ° C., pressure: 100 Pa, SiH ₄ / H ₂ flow rate ratio: 3/10, and input power density: 0.011 W / cm ² . In addition, the film thickness of the thin film in a present Example measures the film thickness of the thin film formed on the glass substrate on the same conditions with a spectroscopic ellipsometer (brand name M2000, product made from JA Woollam Co., Ltd.). It is a value calculated from the film forming speed obtained by this.

On the i-type amorphous silicon layer 2a, a p-type amorphous silicon film having a thickness of 7 nm was formed as the reverse conductivity type silicon-based thin film 3a. The film forming conditions for the p-type amorphous silicon layer 3a were as follows: the substrate temperature was 170 ° C., the pressure was 60 Pa, the SiH ₄ / B ₂ H ₆ flow rate ratio was 1/3, and the input power density was 0.01 W / cm ² . . The B ₂ H ₆ gas flow rate mentioned above is the flow rate of the diluted gas diluted with H ₂ to a B ₂ H ₆ concentration of 5000 ppm.

Next, an i-type amorphous silicon layer having a thickness of 6 nm was formed as an intrinsic silicon-based thin film 2b on the back side of the wafer. The film formation conditions for the i-type amorphous silicon layer 2b were the same as those for the i-type amorphous silicon layer 2a. On the i-type amorphous silicon layer 2b, an n-type amorphous silicon layer having a thickness of 4 nm was formed as a one-conductivity-type silicon-based thin film 3b. The film forming conditions for the n-type amorphous silicon layer 3b were: substrate temperature: 170 ° C., pressure: 60 Pa, SiH ₄ / PH ₃ flow rate ratio: 1/2, input power density: 0.01 W / cm ² . The PH ₃ gas flow rate mentioned above is the flow rate of the diluted gas diluted with H ₂ to a PH ₃ concentration of 5000 ppm.

Indium tin oxide (ITO, refractive index: 1.9) was formed to a thickness of 100 nm as the transparent electrode layers 6a and 6b on the conductive silicon-based thin films 3a and 3b. Using indium oxide as a target, a transparent electrode layer was formed by applying a power density of 0.5 W / cm ² in an argon atmosphere at a substrate temperature of room temperature and a pressure of 0.2 Pa. On the transparent electrode layer 6b on the back surface side, silver was formed as a back surface metal electrode 8 with a film thickness of 500 nm by sputtering. A collector electrode 7 having a metal seed layer 71 and a plating layer 72 was formed on the transparent electrode layer 6a on the light incident side as follows. For the formation of the metal seed layer 71 and the plating layer 72, a method using a low melting point material described in the above-mentioned WO2013 / 077038 was adopted.

For the formation of the metal seed layer 71, a printing paste (viscosity = viscosity) containing a low melting point material (silver fine particles having a particle size D _L = 0.3 to 0.7 μm) as a conductive material and further containing an epoxy resin as a binder resin. 80 Pa · s) was used. This printing paste was screen-printed using a # 230 mesh screen plate having an opening width (L = 60 μm) corresponding to the collector electrode pattern, and dried at 130 ° C.

  The wafer on which the metal seed layer 71 is formed is put into a CVD apparatus, and a silicon oxide layer (refractive index: 1.7 to 1.9) is formed as an insulating layer 9 with a thickness of 100 nm by the plasma CVD method on the light incident surface side. Formed.

The film forming conditions of the insulating layer 9 were: substrate temperature: 135 ° C., pressure 133 Pa, SiH ₄ / CO ₂ flow rate ratio: 1/20, input power density: 0.05 W / cm ² (frequency 13.56 MHz). The wafer after the formation of the insulating layer was introduced into a hot-air circulating oven, and annealed at 180 ° C. for 20 minutes in an air atmosphere.

  The substrate 12 that has been annealed as described above was put into the plating tank 11 as shown in FIG. A shielding plate 20 (thickness: mm) made of polyvinyl chloride was disposed between the substrate 12 and the anode 13. A 100 mm square opening is formed in the shielding plate 20, and the distance L between the substrate 12 and the shielding plate 20 is about 1 cm. The entire periphery of the silicon wafer was insulated by the shielding plate 20.

  The plating solution 16 contains copper sulfate pentahydrate, sulfuric acid, and sodium chloride as a promoter in a solution prepared to have a concentration of 120 g / l, 130 g / l, and 70 mg / l, respectively. , To which an inhibitor, a smoothing agent and a brightener were added were used.

FIG. 13 is a graph showing the relationship between plating time and current density. Using the above plating solution, after the first plating layer forming step was performed for 30 seconds under the conditions of a temperature of 40 ° C. and a current density of 6.6 A / dm ² , the voltage was instantaneously changed to a temperature of 40 ° C. and a current density of 23 A / dm ^2. The second plating layer forming step was performed for 210 seconds under dm ² conditions. As a result, copper was deposited on the metal seed layer 71 as the plating layer 72 with a thickness of about 10 μm. Copper was hardly deposited in the region where the metal seed layer 71 was not formed.

  Thereafter, the silicon wafer on the outer periphery of the cell was removed with a width of 0.5 mm by a laser processing machine, and a heterojunction solar cell was produced.

(Example 2)
After the first plating layer forming step was performed for 30 seconds under the conditions of a temperature of 40 ° C. and a current density of 6.6 A / dm ² , the voltage was changed instantaneously, and the second plating was performed at a temperature of 40 ° C. and a current density of 35 A / dm ^2. The layer forming step was performed for 120 seconds. A heterojunction solar cell was produced in the same manner as in Example 1 except that the conditions for forming the second plating layer were changed.

(Comparative Example 1)
After the first plating layer forming step was performed for 30 seconds under the conditions of a temperature of 40 ° C. and a current density of 6.6 A / dm ² , the voltage was changed instantaneously, and the second plating was performed at a temperature of 40 ° C. and a current density of 44 A / dm ^2. The layer forming process was performed for 85 seconds. A heterojunction solar cell was produced in the same manner as in Example 1 except that the conditions for forming the second plating layer were changed.

(Comparative Example 2)
Without performing the first plating layer forming step, the second plating layer forming step was performed for 210 seconds at a temperature of 40 ° C. and a current density of 23 A / dm ² . A heterojunction solar cell was produced in the same manner as in Example 1 except that the first plating layer forming step was not performed.

(Comparative Example 3)
Without performing the first plating layer forming step, the second plating layer forming step was performed for 120 seconds at a temperature of 40 ° C. and a current density of 35 A / dm ² . A heterojunction solar cell was produced in the same manner as in Example 2 except that the first plating layer forming step was not performed.

  About the finger electrode of each Example and the comparative example, the center part and edge part of each finger electrode were observed using the optical microscope (OLS3000, Olympus company make). FIG. 14 is an optical micrograph showing the surface of the finger electrode according to each example and comparative example. In FIG. 14, the vertical direction of the paper is the electrode width direction, and the vertical direction of the paper is the electrode thickness direction.

  Furthermore, using the optical microscope photograph, the width of the center part and the end part of each finger electrode was measured, and the presence or absence of plating burn was evaluated. In the evaluation of the plating burn, “Yes” was given when the metal was deposited non-uniformly in the width direction of the electrode, and “None” was given when the metal was deposited almost uniformly. A summary of the above results is shown in Table 1.

  From FIG. 14 and Table 1, in Example 1 and Example 2 in which plating was performed at a high current density after plating was performed at a low current density, the width of the end portion of the finger electrode was slightly larger than the width of the central portion. It can be confirmed that the plating growth in the width direction can be suppressed. Moreover, in Example 1 and Example 2, there is no non-uniform metal precipitation in the width direction, and it can be confirmed that no plating burn has occurred.

  On the other hand, in Comparative Example 2 and Comparative Example 3 in which plating was performed only at a high current density without performing plating at a low current density, it was confirmed that plating growth in the width direction was larger than that in Example 1 and Example 2. it can. Furthermore, in Comparative Example 2 and Comparative Example 3, it can be confirmed that metal is deposited non-uniformly in the width direction and plating burns are generated. Generation | occurrence | production of the plating burn was confirmed notably in the center part rather than the edge part of a finger electrode. This is presumably because, in Comparative Example 2 and Comparative Example 3, the high current density plating was performed in a state where the entire periphery of the silicon wafer was insulated by the shielding plate, so that the electric field was concentrated at the center of the finger electrode.

  From the above results, it is considered that the plating layer can be anisotropically grown by plating at a high current density after plating at a low current density.

Further, in Comparative Example 1 in which the current density when forming the second plating layer is 44 A / dm ² , the plating growth in the width direction can be suppressed as in Example 1 and Example 2, but Unlike Example 1 and Example 2, it can be confirmed that metal is deposited non-uniformly in the width direction and plating burns are generated. From this result, if the current density at the time of forming the second plating layer is too high, plating burns are generated, and therefore the current density at the time of forming the second plating layer is preferably less than 40 A / dm ^2. Conceivable.

DESCRIPTION OF SYMBOLS 1 Conductive single crystal silicon substrate 2a, 2b Intrinsic silicon thin film 3a, 3b Conductive silicon thin film 6a, 6b Transparent electrode layer 7, 70 Collector electrode 7a, 70a Finger electrode 7b, 70b Bus bar electrode 70c Connection electrode 71 Metal seed layer 71a Finger seed layer 71b Bus bar seed layer 72 Plating layer 721 First plating layer 722 Second plating layer 8 Back electrode 9 Insulating layer 9h Opening 10 Plating apparatus 11 Plating tank 12 Substrate 13 Anode 14 Substrate holder 15 Power source 16 Plating solution 17 Feeding point 20 Shielding plate 101 Solar cell

Claims (12)

A method of manufacturing a solar cell comprising a photoelectric conversion unit and a collector electrode provided on one main surface of the photoelectric conversion unit and including a plurality of finger electrodes,
Forming a metal seed layer on one principal surface of the photoelectric conversion unit;
Forming a first plating layer on the metal seed layer in a state where the photoelectric conversion part is immersed in a plating solution;
A step of forming a second plating layer on the first plating layer in a state where the photoelectric conversion part is immersed in the plating solution,
In the step of forming the metal seed layer, a finger seed layer constituting the finger electrode is formed,
DK ₁ <DK ₂ <40 A / dm ² where DK ₁ is the first current density when forming the first plating layer and DK ₂ is the second current density when forming the second plating layer. Meet,
In the step of forming the second plating layer, an insulating shielding plate is disposed on the principal surface normal line of the photoelectric conversion unit so as to cover an end of the finger seed layer in the plating solution. A method for manufacturing a solar cell, wherein the second plating layer is formed. ^{2. The} method for manufacturing a solar cell according to claim 1, wherein the first current density DK ₁ satisfies _{1 A} / dm ² ≦ DK ₁ ≦ 12 A / dm ² . 3. The method for manufacturing a solar cell according to claim 1, wherein the second current density DK ₂ satisfies 15 A / dm ² ≦ DK ₂ ≦ 38 A / dm ² . The collector electrode further includes a bus bar electrode connected to the finger electrode,
In the step of forming the metal seed layer, a bus bar seed layer constituting the bus bar electrode is also formed,
The method for manufacturing a solar cell according to claim 1, wherein the bus bar seed layer is formed so that a width of the bus bar seed layer is larger than a width of the finger seed layer.   5. The sun according to claim 4, wherein in the step of forming the first plating layer, the first plating layer is formed on the bus bar seed layer and the finger seed layer by supplying power to the bus bar seed layer. A battery manufacturing method.   The method for manufacturing a solar cell according to claim 5, wherein power supply is performed by arranging a plurality of power supply points per one bus bar seed layer.   In the step of forming the first plating layer, the first plating layer is formed in a state where the shielding plate is disposed so as to cover an end portion of the finger seed layer in the plating solution. The manufacturing method of the solar cell of any one of 1-6. The ends of the finger seed layers are connected,
In the step of forming the second plating layer, the second plating layer is formed in a state where the shielding plate is disposed so as to cover the metal seed layer connecting the end portions of the finger seed layer in the plating solution. The manufacturing method of the solar cell of any one of Claims 1-7. The photoelectric conversion unit has a silicon-based thin film and a transparent electrode layer in this order on one main surface of a conductive single crystal silicon substrate,
The method for manufacturing a solar cell according to claim 1, wherein the collector electrode is formed on the transparent electrode layer.   The manufacturing method of the solar cell of any one of Claims 1-9 with which an insulating layer is formed on the area | region in which the said metal seed layer is not formed among the one main surfaces of the said photoelectric conversion part. The insulating layer is also formed on the metal seed layer,
The method for manufacturing a solar cell according to claim 10, wherein the first plating layer is electrically connected to the metal seed layer through an opening provided in the insulating layer. A solar cell is manufactured by the manufacturing method according to any one of claims 1 to 11,
A method for manufacturing a solar cell module, wherein the solar cell is connected to another solar cell or an external circuit via a wiring member.