CN205810839U

CN205810839U - Silica-based heterojunction solaode

Info

Publication number: CN205810839U
Application number: CN201620459734.0U
Authority: CN
Inventors: 张金隆; 杨茹媛; 陈坤贤
Original assignee: Yancheng Jinhesheng Photoelectric Technology Co Ltd
Current assignee: Yancheng Jinhesheng Photoelectric Technology Co Ltd
Priority date: 2016-05-19
Filing date: 2016-05-19
Publication date: 2016-12-14
Anticipated expiration: 2026-05-19

Abstract

The utility model discloses a kind of silica-based heterojunction solaode.Silica-based heterojunction solaode, comprise: a silica-based PN contact structure, there are two apparent surfaces, the most silica-based PN contact structure is made up of a p type semiconductor layer and a N-type semiconductor substrate, N-type semiconductor substrate has one first roughened surface and one second roughened surface, and the energy gap of p type semiconductor layer is different from the energy gap of N-type semiconductor substrate；Wherein, this first roughened surface and this second roughened surface have an irregular pyramid texture structure, and this pyramid width in this pyramid texture structure and the ratio of pyramid vertex of a cone height are between 2 to 0.8.This silica-based heterojunction solaode can have high-quality texture structure, improves its current characteristics and promotes the characteristic of photoelectric transformation efficiency.

Description

Silicon-based heterojunction solar cell

Technical Field

The present invention relates to a silicon-based heterojunction solar cell, and more particularly, to an IPA (isopropyl alcohol) -free temperature-varying textured alkali-etched silicon-based heterojunction solar cell.

Background

Accordingly, currently, due to international energy shortage, various viable alternative energy sources are continuously developed in various countries of the world, and among them, solar cells that generate electricity by solar energy are most spotlighted. At present, the conversion efficiency of a solar cell made of silicon crystal is reduced due to the limitation that the solar cell can only absorb solar energy of 1.1 ev or more, the loss caused by reflected light, the insufficient absorption capability of the material to the solar light, the carrier being trapped by defects in the material before being led out and failing, or the carrier being trapped by suspended bonds on the surface of the material to generate recombination. Therefore, the conversion efficiency of the currently commercially available crystalline silicon solar cell is only about 15%, which means that there is actually a considerable space for the high efficiency of the crystalline silicon solar cell. The basic principle of high efficiency of solar cells is to combine materials of power generation layers with different energy gaps to form a laminated structure.

Reference is made to U.S. publication No. 5,213,628, entitled: a Photovoltaic device (Photovoltaic device), which mainly discloses a solar cell combined with different energy gaps, and by adding an amorphous silicon intrinsic semiconductor, the carrier life of the solar cell is prolonged, the electron hole recombination probability is reduced, and the photocurrent conversion efficiency is improved.

Reference is made to U.S. publication No. 6,878,921, entitled: photovoltaic device and manufacturing method thereof. As shown In FIG. 1, a silicon-based heterojunction solar cell is disclosed, which uses indium tin oxide (In)₂O₃:SnO₂ITO) transparent conductive film is used as a current spreading layer to improve the current characteristics and the photoelectric conversion efficiency.

Reference is made to U.S. publication No. 6,207,890, entitled: a Photovoltaic device and a method for fabricating the same are disclosed, which mainly disclose a structure and a fabrication method of the Photovoltaic device. This patent discloses a anisotropic etching solution to form a pyramid structure on an N-type single crystal silicon substrate, and to make the bottom of the pyramid arc to increase the open-circuit voltage and short-circuit current. The method uses alkaline solution and IPA (isopropyl alcohol) as anisotropic etching solution to prevent bubbles from generating in the N-type semiconductor layer, the concentration of IPA will affect the surface tension of the liquid, and when the surface tension is less than 47 dyn/cm, the bubbles will remain on the semiconductor surface to reduce the efficiency.

Reference is made to U.S. publication No. 8,835,210, entitled: a Method of fabricating a photovoltaic module (solar cell) is disclosed, which includes forming a crystalline silicon substrate having a textured surface. The method is characterized in that the main surface of the crystalline silicon substrate is etched for the first time by using an etching solution, and then, the etching solution with higher concentration of etching components is used for etching for the second time, so that a texture structure is formed on the main surface of the crystalline silicon substrate.

However, the etching method disclosed in the above patent produces a pyramid-shaped structure in a monocrystalline silicon N-type semiconductor. However, the deep V-shaped groove appears at the bottom of the pyramid, which causes electron holes to generate recombination.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, an objective of the present invention is to provide a silicon-based heterojunction solar cell, which has a high-quality texture structure prepared by temperature-variable textured alkali etching without isopropyl alcohol (IPA), so as to improve the overall photoelectric conversion efficiency of the cell.

Another objective of the present invention is to provide a manufacturing method of a silicon-based heterojunction solar cell, which utilizes a high-quality texture structure prepared by IPA (isopropyl alcohol, IPA) -free variable temperature textured alkaline etching, thereby improving the overall photoelectric conversion efficiency of the cell.

The utility model provides a silica-based heterogeneous solar cell that connects contains:

a silicon-based PN junction structure having two opposite surfaces, wherein the silicon-based PN junction structure is composed of a P-type semiconductor layer and an N-type semiconductor substrate, and the N-type semiconductor substrate has a first roughened surface and a second roughened surface;

the first roughened surface and the second roughened surface are provided with a concave-convex pyramid textured structure, and the ratio of the pyramid width to the pyramid top height in the pyramid textured structure is between 2 and 0.8.

Preferably, the pyramid width of the pyramid textured structure is between 5 and 15 microns.

Preferably, the pyramidal textured structure has a pyramidal apex height of between 4 microns and 10 microns.

Preferably, the silicon-based heterojunction solar cell further comprises:

a first transparent conductive film disposed on a surface of the silicon-based PN junction structure; and

and a second transparent conductive film disposed on the other surface of the PN junction structure opposite to the first transparent conductive film.

Preferably, the refractive index of the first transparent conductive film is between 1.90 and 1.94, and the refractive index of the second transparent conductive film is between 1.90 and 1.94.

Therefore, the utility model discloses the effect that can reach contains:

1. alkaline etching without isopropyl alcohol (IPA) is used to prevent deterioration of the working environment due to volatilization of isopropyl alcohol.

2. By using a variable-temperature texturing alkali etching process, a high-quality texture structure in a relatively arc shape can be prepared, and the carrier recombination velocity is reduced;

3. the high-quality texture structure increases the light absorption, improves the output current density and further improves the photoelectric conversion efficiency;

4. provides a commercial mass production speed and reduces the cost of mass production process.

Drawings

FIG. 1 is a schematic cross-sectional view of a prior art silicon-based heterojunction solar cell;

fig. 2 is a schematic cross-sectional view of a heterojunction solar cell according to a first embodiment of the present invention;

FIG. 3 illustrates the disclosed pyramidal textured structure of the first and second roughened surfaces; and

fig. 4 is a schematic cross-sectional view of a heterojunction solar cell according to a second embodiment of the present invention.

[ notation ] to show

100 silicon-based heterojunction solar cells;

a 110 substrate;

111 a first roughened surface;

112 a second roughened surface;

120 a first intrinsic amorphous silicon layer;

130P-type semiconductor layer;

140 a second intrinsic amorphous silicon layer;

a 150N type semiconductor layer;

160 a first electrode;

170 a second electrode;

180 a first transparent conductive film;

190 a second transparent conductive film.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and can implement the present invention, but the embodiments are not to be construed as limiting the present invention.

Referring now to fig. 2, therein is shown a silicon-based heterojunction solar cell 100 structure according to a first embodiment of the present invention, comprising: a substrate 110; a semiconductor layer 130; a first transparent conductive film 180; a first electrode 160; a second transparent conductive film 190; and a second electrode 170. The substrate 110 further has a first roughened surface 111 and a second roughened surface 112.

The structure of the silicon-based heterojunction solar cell 100 mainly comprises a silicon-based PN junction structure having two opposite surfaces, wherein the silicon-based PN junction structure is composed of the substrate 110 and the semiconductor layer 130, and the energy gap of the substrate is different from the energy gap of the semiconductor layer.

The substrate 110 is selected from one of a P-type semiconductor single crystal substrate, an N-type semiconductor single crystal substrate, a P-type single crystal silicon substrate, and an N-type single crystal silicon substrate. Preferably, the substrate 110 is selected from a (100) plane N-type semiconductor silicon-based single crystal substrate, but is not limited thereto.

The substrate 110 is preferably selected from a (100) plane N-type semiconductor silicon-based single crystal substrate, and the slice damage layer is removed by isotropic etching using an alkaline mixture having an alkali concentration of more than 2% by mass before etching. The mass% of a particular substance is defined as the percentage of the mass of the particular substance in the bulk solution.

The substrate 110 has a thickness of 180 micrometers (μm) to 200 micrometers (μm) before etching and 160 micrometers (μm) to 180 micrometers (μm) after etching. In addition, the etching thins the thickness of the silicon substrate, and makes the average thickness of the substrate 110 after completion be between 70 micrometers (μm) and 120 micrometers (μm). Thereby providing a thinner and highly economical silicon-based heterojunction solar cell 100.

The first roughened surface 111 and the second roughened surface 112 of the substrate 110 are anisotropically etched to form a textured pyramid structure having protrusions and recesses, so that light confinement due to diffuse reflection of light is more effective. To form the first roughened surface 111 and the second roughened surface 112 of the pyramid-textured structure with the concavities and convexities, the main etching conditions include: the concentration of the etching solution, the etching temperature and the etching time are used to enable the pyramid textured structure with the concave and convex parts to present a relatively arc shape so as to improve the open-circuit voltage and the short-circuit current of the pyramid textured structure.

Referring now to fig. 3, a pyramidal textured structure of the first and second roughened surfaces is shown. By the etching process, the pyramid-textured structures of the first and second roughened surfaces 111 and 112 can be in a relatively arc shape. Referring to fig. 3, wherein the pyramid width (W) in the pyramid textured structure is between 5 micrometers (μm) and 15 micrometers (μm), and the pyramid apex height (H) in the pyramid textured structure is between 4 micrometers (μm) and 10 micrometers (μm). Preferably, the pyramid width is between 8 micrometers (μm) and 12 micrometers (μm), and the pyramid apex height is between 5 micrometers (μm) and 10 micrometers (μm). Preferably, the ratio of the pyramid width to the pyramid tip height (W/H) is between about 2 and about 0.8.

The anisotropic etching is performed by immersing the substrate 110 sliced along a (100) crystal plane in an alkaline mixture, wherein the substrate 110 is immersed in the alkaline mixture for an etching time of 10 minutes to 20 minutes, and an etching temperature is changed from a first temperature to a second temperature, wherein the first temperature is greater than or equal to the second temperature, the first temperature is between 80 ℃ and 95 ℃, and the second temperature is between 70 ℃ and 80 ℃. Preferably, the first temperature is between 82 ℃ and 87 ℃ and the second temperature is between 76 ℃ and 80 ℃. By gradually changing the etching temperature from a first temperature with a higher temperature at the beginning to a second temperature with a lower temperature at the end, the etching speed is also decreased from a faster speed.

The present invention is characterized in that the anisotropic etching process is performed in a temperature varying process from a high temperature to a low temperature. The alkaline mixed solution is mainly composed of 0.5 to 3 mass% of sodium hydroxide (NaOH) or 0.5 to 3 mass% of potassium hydroxide (KOH), 0.05 to 0.1 mass% of an additive is added, and the balance of the alkaline mixed solution is water. It is noted that at the beginning of the etching time, the alkaline mass% in the alkaline mixture is higher than at the end of the etching time, for example, at the beginning of the etching time, the alkaline mixture is mainly 0.8 mass% sodium hydroxide (NaOH), 0.06 mass% of an additive is added, and the rest is water; at the end of the etching time, the alkaline mixture is mainly 2 mass% sodium hydroxide (NaOH), 0.1 mass% of an additive is added, and the remainder is water by mass.

The pyramidal textured structure results from the etch rate of the (111) crystal planes being significantly less than other crystallographic orientations. Herein, mass% of a particular substance is defined as the percentage of the mass of the particular substance in the total solution. Note that if the alkali concentration of the alkali mixture exceeds 2 mass%, for example, isotropic etching is formed, and it is difficult to form a pyramid-shaped textured structure having many irregularities.

It is noted that the present invention is characterized in that the additive does not use an aqueous isopropanol solution. Since, when an aqueous isopropyl alcohol solution is used in the etching mixture, the working environment is deteriorated due to the volatilization of isopropyl alcohol. The utility model is characterized in that the additive is a surfactant of alcohol derivative. The additives may be, for example, the commercially available "ALKA-TEX" series of GP solar GmbH, the "Etch TAD 74" and "Etch TAD 72" of Nippon pure chemical.

The conductivity of the semiconductor layer 130 is relative to the conductivity of the substrate 110. For example, if the substrate 110 is selected from an N-type semiconductor substrate, the conductivity of the semiconductor layer 130 is a P-type semiconductor layer, and the thickness of the semiconductor layer 130 is between 8 micrometers (μm) and 20 micrometers (μm).

In one embodiment, the conductivity of the semiconductor layer 130 is a P-type semiconductor layer disposed on the substrate 110 having N-type semiconductor. In the present embodiment, the doping concentration of the semiconductor layer 130 is between 1018 and 1020 atomic/cubic centimeter. The semiconductor layer 130 has an oxygen content of 5 × 10¹⁸To 1X 10¹⁷Atom/cubic centimeter. Wherein,impurities (Impurities) are added to the original material to generate excess holes, and the holes form the majority carrier semiconductor, which is called a P-type semiconductor layer. Example (c): in the case of silicon or germanium semiconductors, when impurities of valence 3 atoms are doped into the intrinsic semiconductor, excess holes are formed, and the holes are the mode of current flow.

The semiconductor layer 130 may be formed by Plasma-enhanced chemical vapor deposition (PECVD), Hot-wire chemical vapor deposition (HW-CVD), or Very high frequency Plasma-enhanced chemical vapor deposition (VHF-PECVD), and silicon compound (silicon) gas such as silane (SH 4) and Hydrogen (Hydrogen, H), Argon (Argon, Ar) may be introduced as the process gas.

The doping method of the semiconductor layer 130 is mainly a process method that can be selected from a gas doping, a Thermal diffusion method (Thermal diffusion), a Solid Phase Crystallization (SPC) or an Excimer Laser Annealing (ELA). In addition, the semiconductor layer 130 is selected from one of amorphous silicon, amorphous silicon germanium, amorphous silicon carbide, and nanocrystalline silicon.

In one embodiment, the conductivity of the semiconductor layer 130 is a P-type amorphous silicon semiconductor layer disposed on the substrate 110 with N-type semiconductor single crystal silicon to form a PN junction structure. The first electrode 180 disposed on a surface of the PN junction structure; and the second electrode 190 disposed on the other surface of the PN junction structure opposite to the first electrode.

The first transparent conductive film 180 is disposed on one surface of the PN junction structure, and the second transparent conductive film 190 is disposed on the other surface of the PN junction structure opposite to the first electrode. Referring to the embodiment of fig. 2, the first transparent conductive film 180 is disposed on the surface of the semiconductor layer 130, and the second transparent conductive film 190 is disposed on the surface of the substrate 110 having N-type semiconductor single crystal silicon.

The first transparent conductive film 180 and the second transparent conductive film 190 can be made of indium oxide, tin oxide, zinc oxide, indium oxide containing impurities, tin oxide containing impurities, and zinc oxide containing impurities. For example, but not limited to, aluminum-doped zinc oxide (ZnO: Al), gallium-doped zinc oxide (ZnO: Ga), boron-doped zinc oxide (ZnO: B), zinc-doped indium oxide (In)₂O₃Zn), indium oxide (In) doped with boron₂O₃B), hydrogen-doped indium oxide (In)₂O₃H) or the composition thereof.

It should be noted that the present invention is technically characterized in that ion plasma is used to deposit the first transparent conductive film 180 and the second transparent conductive film 190, the plating rate is greater than 1.5 nm/s, and the preferred plating rate is between 1.6 nm/s and 5 nm/s; the process temperature is lower than 200 ℃, preferably between 50 ℃ and 150 ℃.

The refractive index of the first transparent conductive film 180 is between 1.90 and 1.94, and the thickness is between 50nm and 90nm, so that a better anti-reflection effect can be obtained. The refractive index of the second transparent conductive film 190 is between 1.90 and 1.94, and the thickness is between 50nm and 90nm, so that a better anti-reflection effect can be obtained.

The grain sizes of the first transparent conductive film 180 and the second transparent conductive film 190 are between 20 nm and 30 nm, and a better anti-reflection effect can be obtained. The sheet resistivity of the first transparent conductive film 180 and the second transparent conductive film 190 is between 0.1 Ω/□ and 50 Ω/□. Preferably, the sheet resistivity of the first transparent conductive film 180 and the second transparent conductive film 190 is between 1 Ω/□ and 8 Ω/□.

The first transparent conductive film 180 and the second transparent conductive film 190 can be formed by any one process selected from evaporation, sputtering, electroplating, wet chemical, chemical vapor deposition, printing, and arc discharge deposition, preferably by ion plasma deposition.

The first electrode 160 is disposed on the first transparent conductive film 180, and the second electrode 170 is disposed on the second transparent conductive film 190, so as to extract electric energy and improve photoelectric conversion efficiency. The materials of the first electrode 160 and the second electrode 170 may be nickel, gold, silver, titanium, copper, palladium, and aluminum. In a preferred embodiment, the material of the first electrode 160 and the second electrode 170 is silver. In the present embodiment, the thickness is between 100 nm and 900 nm.

The line widths of the first electrode 160 and the second electrode 170 are between 100 micrometers and 2000 micrometers. Although only two first electrodes 160 and two second electrodes 170 are shown in the drawings, the implementation is not limited to two, and preferably, the first electrodes 160 and the second electrodes 170 have at least two electrode lines, and the number of the electrode lines is between 2 and 20. The smaller the electrode line widths of the first electrode 160 and the second electrode 170 are, the larger the number of electrode lines is; conversely, when the electrode line width of the first electrode 160 and the second electrode 170 is larger, the number of electrode lines is smaller. Therefore, the light-transmissive open area not shielded by the first electrode 160 and the second electrode 170 is at least 95% or more.

The materials of the first electrode 160 and the second electrode 170 are selected from pure metals and metal compounds. The metal may include gold, silver, copper, nickel, aluminum, and alloys thereof, and the process may be selected from any one of evaporation, sputtering, electroplating, arc plasma deposition, wet chemical process, and printing. The thickness of the first electrode 160 and the second electrode 170 is between 100 nm and 900 nm, and the resistance value is between 0.1 Ω and 5 Ω. Preferably, the material of the first electrode 160 and the second electrode 170 is silver.

Referring now to fig. 4, therein is shown a heterojunction solar cell 100 according to a second embodiment of the present invention, comprising: a substrate 110; a first intrinsic amorphous silicon layer 120; a first semiconductor layer 130; a first transparent conductive film 180; a second intrinsic amorphous silicon layer 140; a second semiconductor layer 150; and a second transparent conductive film 190; and a second electrode 170. The substrate 110 further has a first roughened surface 111 and a second roughened surface 112.

The second embodiment is substantially similar to the first embodiment, and the major difference is that the heterojunction solar cell 100 further comprises: a first intrinsic amorphous silicon layer 120; a second intrinsic amorphous silicon layer 140 and a second semiconductor layer 150. That is, a first intrinsic amorphous silicon layer 120 is further included between the substrate 110 and the first semiconductor layer 130. A second intrinsic amorphous silicon layer 140 is further sequentially included between the substrate 110 and the second transparent conductive film 190; a second semiconductor layer 150. That is, the second intrinsic amorphous silicon layer 140 is included between the substrate 110 and the second semiconductor layer 150. The first semiconductor layer 130 has a thickness of between 8 micrometers (μm) and 20 micrometers (μm). The second semiconductor layer 150 has a thickness of between 8 micrometers (μm) and 20 micrometers (μm). The thickness of the first intrinsic amorphous silicon layer 120 is between 4 micrometers (μm) and 10 micrometers (μm). The thickness of the second intrinsic amorphous silicon layer 140 is between 4 micrometers (μm) and 10 micrometers (μm).

The substrate 110, the first roughened surface 111, the second roughened surface 112, the first transparent conductive film 180 and the second transparent conductive film 190 of the second embodiment are the same as the substrate 110, the first transparent conductive film 180 and the second transparent conductive film 190 of the first embodiment, and the first semiconductor layer 130 of the second embodiment is the same as the semiconductor layer 130 of the first embodiment. I.e., the features are the same as those described above in the first embodiment, and thus are not described again here.

The first intrinsic amorphous silicon layer 120 is disposed on the first roughened surface 111 of the substrate 110, and is disposed between the substrate 110 and the first semiconductor layer 130, and has a hydrogen content of 3% to 10%. The second intrinsic amorphous silicon layer 140 is disposed on the second roughened surface 112 of the substrate 110, is opposite to the other side of the substrate 110 opposite to the first intrinsic amorphous silicon layer 120, and is particularly disposed between the substrate 110 and the second semiconductor layer 150, and has a hydrogen content of 3% to 10%.

The first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 may be made of one of amorphous silicon, amorphous silicon germanium, nanocrystalline silicon, microcrystalline silicon germanium, polycrystalline silicon, and polycrystalline silicon germanium. In addition, the first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 can be used to form quantum confinement effect to improve electrical characteristics to increase the absorbable incident light spectral range.

The first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 are formed by Plasma-enhanced chemical vapor deposition (PECVD), Hot-wire chemical vapor deposition (HW-CVD), or Very high frequency Plasma-enhanced chemical vapor deposition (VHF-PECVD), and silicon compound (silicon) gas such as silane (silane, SH) is introduced into the silicon-enhanced chemical vapor deposition₄) And Hydrogen (Hydrogen, H), Argon (Argon, Ar) and the like are mixed as the process gas. In the preferred embodiment of the present invention, the thickness of the first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 is between 5 nm and 20 nm, and the hydrogen content is between 3% and 7%. Note that the difference in hydrogen content affects the photoelectric conversion characteristics. In addition, the first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 can also be used to fill up defects occurring at the junction of the P-type semiconductor layer 130 and the substrate 110 or at the junction of the N-type semiconductor layer 150 and the substrate 110, so as to increase the conversion efficiency.

When the first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 are subjected to plasma CVD, the frequency is about 13.56MHz or 40.68MHz, preferably about 40.68MHz, the reaction pressure is 5Pa or more and less than 300Pa, preferably 50Pa or more and less than 200Pa, and the RF or VHF power is about 1mW/cm ²Above and less than 500mW/cm²And at about 5mW/cm²Above and less than 100mW/cm²Preferably.

The temperature of the substrate 110 may be set to exceed 180 ℃ and be less than 220 ℃ when the first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 are deposited. By setting the formation temperature to a high temperature range, an intrinsic amorphous silicon thin film can be obtained which can suppress crystallization and reduce the occurrence of defects.

In the second embodiment, the conductivity of the first semiconductor layer 130 is a P-type amorphous silicon semiconductor layer, and is disposed on the substrate 110 having N-type semiconductor single crystal silicon to form a PN junction structure.

Therefore, the second semiconductor layer 150 is an N-type semiconductor layer and is disposed on the second intrinsic amorphous silicon layer 140. The second semiconductor layer 150 has a doping concentration of 10¹⁸To 10²⁰Atom/cubic centimeter, and oxygen content of 5 × 10¹⁸To 1X 10¹⁷Atom/cubic centimeter. The second semiconductor layer 150 is a semiconductor in which impurities added to an intrinsic material may generate excess electrons to form majority carriers. For example, in the case of silicon and germanium semiconductors, when impurities having a valence of 5 are doped into the intrinsic semiconductor, excess electrons are formed. Wherein the electron flow is mainly electron.

The doping of the second semiconductor layer 150 may be selected from thermal gas doping, excimer laser annealing, solid-phase crystallization, diffusion, or ion implantation. In one embodiment, the second semiconductor layer 150 is selected from one of amorphous silicon, amorphous silicon germanium, amorphous silicon carbide and nanocrystalline silicon.

Note that when the substrate is an N-type silicon substrate, the light-emitting Surface is a P-type semiconductor layer, and the N-type semiconductor layer and the second intrinsic amorphous silicon layer can form a Back Surface Field (BSF) effect. On the contrary, when the substrate is a P-type silicon substrate, the light-emitting surface is an N-type semiconductor layer, and the P-type semiconductor layer and the first intrinsic amorphous silicon layer can form an effect of a back surface electric field.

The utility model discloses a silicon-based heterogeneous junction solar cell 100's processing procedure, it contains following step:

the first step is: forming a first roughened surface and a second roughened surface on an N-type semiconductor substrate by anisotropic etching;

the second step is: depositing a P-type semiconductor layer on the first roughened surface of the N-type semiconductor substrate to form a silicon-based PN junction structure, wherein the energy gap of the P-type semiconductor layer is different from that of the N-type semiconductor substrate;

The third step is: depositing a first transparent conductive film on the P-type semiconductor layer;

the fourth step is: depositing a second transparent conductive film on the second roughened surface of the N-type semiconductor substrate; and

the fifth step is: and forming a first electrode on the first transparent conductive film and a second electrode on the second transparent conductive film for extracting the current of the silicon-based PN junction structure.

In the first step, the surface of the substrate 110 is contaminated with microorganisms such as termitomyces albuminosus microflora, organic substances, termitomyces albuminosus products, and the compound …. The substrate 110 must first be cleaned to obtain a clean surface. In addition, the substrate 110 is anisotropically etched to form the first and second roughened surfaces 111 and 112 for increasing the scattering rate of incident light, thereby increasing light-trapping efficiency and improving electrical characteristics.

The present invention is characterized in that the first roughened surface 111 and the second roughened surface 112 are anisotropically etched to form a pyramid-shaped textured structure having recesses and protrusions, the pyramid width of the pyramid-shaped textured structure is between 5 micrometers (μm) and 15 micrometers (μm), and the pyramid vertex height is between 4 micrometers (μm) and 10 micrometers (μm).

The utility model is characterized in that, the anisotropic etching process is carried out in a temperature changing process from high temperature to low temperature. The alkaline mixed solution is mainly composed of 0.5 to 3 mass% of sodium hydroxide (NaOH) or 0.5 to 3 mass% of potassium hydroxide (KOH), 0.05 to 0.1 mass% of an additive is added, and the balance of the alkaline mixed solution is water. It is noted that at the beginning of the etching time, the alkaline mass% in the alkaline mixture is higher than at the end of the etching time, for example, at the beginning of the etching time, the alkaline mixture is mainly 0.8 mass% sodium hydroxide (NaOH), 0.06 mass% of an additive is added, and the rest is water; at the end of the etching time, the alkaline mixture is mainly 2 mass% sodium hydroxide (NaOH), 0.1 mass% of an additive is added, and the remainder is water by mass.

The pyramidal textured structure results from the etch rate of the (111) crystal planes being significantly less than other crystallographic orientations. Herein, mass% of a particular substance is defined as the percentage of the mass of the particular substance in the total solution. Note that if the alkali concentration of the alkali mixture exceeds 2 mass%, for example, isotropic etching is formed, and it is difficult to form a plurality of pyramid-shaped textured structures having irregularities.

It is noted that the present invention is characterized in that the additive does not use an aqueous isopropanol solution. Since, when an aqueous isopropyl alcohol solution is used in the etching mixture, the working environment is deteriorated due to the volatilization of isopropyl alcohol. The utility model is characterized in that the additive is a surfactant of alcohol derivatives. The additives may be used, for example, in the "ALKA-TEX" series commercially available from GP solar GmbH, or "Etch TAD 74" and "Etch TAD 72" from Nippon pure chemical.

In one embodiment, the alkaline mixture comprises 0.2-2 mass% (preferably 0.5-1.5 mass%, more preferably less than 1 mass%) of sodium hydroxide and 0.05-0.1 mass% of an "ALKA-TEX" additive. The alkaline mixture solution can enable the substrate 110 with the (100) crystal face slices to form a plurality of pyramid textured structures with the concave and convex. The etching time of the substrate 110 immersed in the alkaline mixture is 15 minutes, and the etching temperature is decreased from the first temperature of 90 ℃ to the second temperature of 70 ℃ within the etching time.

The specific sequence of the first roughened surface 111 and the second roughened surface 112 to form the pyramid-shaped textured structure with the concavities and convexities is (1) H₂O rinse (room temperature), (2) NaOH/additive, (3) H₂O rinse (room temperature), (4) HCl/H₂O₂/H₂O (volume ratio 1: 1: 5, 80 ℃), (5) H₂O rinse (room temperature), (6) HF/H₂O (5 mass%, room temperature), and (7) H₂O rinse (room temperature). In step (2), the substrate 110 is immersed in the alkaline mixture for an etching time of 15 minutes, and the etching temperature is 90 ℃ at the beginning of etching, gradually decreases during etching, and reaches 70 ℃ at the end of etching. The temperature is gradually decreased from a set high temperature to a set low temperature, and the temperature is not necessarily linearly decreased as long as the temperature is gradually decreased.

In the second step, the silicon-based PN junction structure is composed of a P-type semiconductor layer and an N-type semiconductor layer. For example, in the first embodiment, the conductivity of the semiconductor layer 130 is a P-type amorphous silicon semiconductor layer disposed on the substrate 110 with N-type semiconductor single crystal silicon to form a PN junction structure.

For example, in the second embodiment, the first intrinsic amorphous silicon layer 120 is disposed on the first roughened surface 111, and is disposed between the substrate 110 and the first semiconductor layer 130, and the hydrogen content thereof is between 3% and 10%. The substrate 110 and the first semiconductor layer 130 form a PN junction structure. The second intrinsic amorphous silicon layer 140 is disposed on the second roughened surface 112 and between the substrate 110 and the second semiconductor layer 150, and has a hydrogen content of 3% to 10%.

The process of the first intrinsic amorphous silicon layer 120, the second intrinsic amorphous silicon layer 140, the P-type semiconductor layer and the N-type semiconductor layer is one of Plasma-enhanced chemical vapor deposition (PECVD), Hot-wire chemical vapor deposition (HW-CVD), and Very high frequency Plasma-enhanced chemical vapor deposition (VHF-PECVD).

In the chemical vapor deposition system, at least hydrogen and silane gases are introduced to deposit the first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 on the first roughened surface 111 and the second roughened surface 112, respectively, and the hydrogen content of the first intrinsic amorphous silicon layer 120 and the second intrinsic amorphous silicon layer 140 is between 3% and 10% by the ratio of the introduced hydrogen flow to the silane gas flow being between 1 time and 100 times.

In the process of manufacturing the P-type semiconductor layer, the oxygen content is between 5 × 10¹⁸To 1X 10¹⁷Between atom/cubic centimeter, it selects plasma enhanced chemical vapor deposition process, hot filament chemical vapor deposition process or ultrahigh frequency plasma enhanced chemical vapor deposition process as the main process method, and introduces silicon compound (Silicide) gas such as Silane (SH) ₄) And Hydrogen (Hydrogen, H), Argon (Argon, Ar) and the like are mixed as the process gas. Such as: matching silane gas and hydrogen gas to mix; mixing silane gas, hydrogen and argon; mixing silane gas, germane gas and hydrogen; any one of the group consisting of silane gas, germane gas, hydrogen gas and argon gas is performed. By changing the mixing ratio of silane and hydrogen and the introduced gas, the P-type semiconductor layer 130 can be made of amorphous silicon, amorphous silicon germanium, amorphous silicon carbide and nano-scaleOne of the crystalline silicon. In the embodiment of the present invention, the doping concentration of the P-type semiconductor layer is 10¹⁸To 10²⁰Atom/cubic centimeter.

In the process of manufacturing the N-type semiconductor layer, the oxygen content is 5 × 10¹⁸To 1X 10¹⁷Between atom/cubic centimeter, it selects plasma enhanced chemical vapor deposition process, hot filament chemical vapor deposition process or ultrahigh frequency plasma enhanced chemical vapor deposition process as the main process method, and introduces silicon compound (Silicide) gas such as Silane (SH)₄) And Hydrogen (Hydrogen, H), Argon (Argon, Ar) and the like are mixed as the process gas. Such as: matching silane gas and hydrogen gas to mix; mixing silane gas, hydrogen and argon; mixing silane gas, germane gas and hydrogen; silane gas, germane gas, hydrogen gas and argon gas. By changing the mixing ratio of silane and hydrogen and the introduced gas, the N-type semiconductor layer 150 can be one of amorphous silicon, amorphous silicon germanium, amorphous silicon carbide and nanocrystalline silicon. In the embodiment of the present invention, the doping concentration of the N-type semiconductor layer is 10 ¹⁸To 10²⁰Atom/cubic centimeter.

In the third step and the fourth step, the first transparent conductive film 180 and the second transparent conductive film 190 are respectively disposed on the first semiconductor layer 130 and the second semiconductor layer 150. The first transparent conductive film 180 and the second transparent conductive film 190 are formed by a process selected from the group consisting of evaporation, sputtering, electroplating, wet chemical, chemical vapor deposition, printing, and ion plasma deposition.

However, in order to obtain a better surface texture, the first transparent conductive film 180 and the second transparent conductive film 190 are formed by ion plasma deposition, and then the transparent conductive unit with the texture structure can be obtained without performing an etching step.

It should be noted that the present invention is technically characterized in that ion plasma is used to deposit the first transparent conductive film 180 and the second transparent conductive film 190, the plating rate is greater than 1.5nm/s, and the preferred plating rate is between 1.6 nm/s and 5 nm/s; the process temperature is lower than 200 ℃, preferably between 50 ℃ and 150 ℃. The transparent conductive film has a special function by using a low-temperature process, i.e. the film of the previous process is not heated and annealed.

It should be noted that the refractive index of the first transparent conductive film 180 is between 1.90 and 1.94, and the thickness is between 50nm and 90nm, so as to obtain a better anti-reflection effect. The refractive index of the second transparent conductive film 190 is between 1.90 and 1.94, and the thickness is between 50nm and 90nm, so that a better anti-reflection effect can be obtained.

In the fifth step, the first electrode 160 and the second electrode 170 are formed by any one of a group consisting of evaporation, sputtering, chemical vapor deposition, electroplating, wet chemical, printing, and arc-cathode/anode dc discharge deposition, and the material of the first electrode 160 and the second electrode 170 may be one or a combination of nickel, gold, silver, titanium, copper, palladium, and aluminum. The thickness of the first electrode 160 and the second electrode 170 is between 100 nm and 900 nm, and the resistance value is between 0.1 Ω and 5 Ω. Preferably, the material of the first electrode 160 and the second electrode 170 is silver. It should be noted that the different preparation methods of the first electrode 160 and the second electrode 170 also affect the quality of the photoelectric properties thereof.

In the embodiment of the present invention, the quality of the photoelectric characteristic of the silicon-based heterojunction solar cell 100 can be affected by the process of preparing zinc oxide as the first transparent conductive film 180 and the second transparent conductive film 190 by ion plasma deposition and matching with the different first intrinsic amorphous silicon layer 120, the P-type semiconductor layer 130, the second intrinsic amorphous silicon layer 140 and the N-type semiconductor layer 150. The transparent conductive film has a special function by using a low-temperature process, i.e. the film of the previous process is not heated and annealed.

Ion plasma deposition to achieve high plating rates at low temperaturesMainly controls other process parameters, including: gas flow, gas pressure ratio, and ion plasma current. In a preferred embodiment, the first transparent conductive film 180 and the second transparent conductive film 190 are formed by anodic ion plasma deposition. The gas flow ratio (argon: oxygen) is between 1:4 and 1:12, and a preferred gas flow ratio is between 1:6 and 1: 10; wherein the flow rate of oxygen is between 5 sccm and 30 sccm. The ion plasma current of the zinc target is between 20A and 150A, and the anode arc direct current discharge current of a preferred zinc target is between 50A and 100A; the pressure of the cavity is between 10^-3Trunnion (torr) to 10^-4Between torr.

In a preferred embodiment of the present invention, at least one process gas is subjected to a purification step to reduce the oxygen content of the process gas. Too much oxygen in the process gas will generate too many oxygen vacancies in the deposited thin film structure, resulting in a reduction of carrier mobility in the solar cell, and thus a reduction of power generation efficiency. By performing the step of purifying the gas, the oxygen concentration of the film grown in the preferred embodiment is less than 5 x 10 ¹⁸Atom/cubic centimeter. It should be noted that the structure and method disclosed in the present invention are not only suitable for a single unit cell, but also can be applied to a modularized solar cell process.

Compare in traditional silica-based heterogeneous junction surface silicon solar cell, the utility model provides a silica-based heterogeneous junction surface solar cell 100 has the advantage as follows:

the transparent conductive film with low cost is adopted, so that the production cost can be reduced.

The transparent conductive film does not need to be additionally provided with an etching procedure, and the processing time can be shortened.

The utilization of ultraviolet light can be effectively increased to improve the efficiency.

The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. Equivalent substitutes or changes made by the technical personnel in the technical field on the basis of the utility model are all within the protection scope of the utility model. The protection scope of the present invention is subject to the claims.

Claims

1. A silicon-based heterojunction solar cell, comprising:

2. The silicon-based heterojunction solar cell of claim 1, wherein said pyramid width of said pyramid textured structure is between 5 microns and 15 microns.

3. The silicon-based heterojunction solar cell of claim 1, wherein the pyramid apex height of said pyramid textured structure is between 4 microns and 10 microns.

4. The silicon-based heterojunction solar cell of claim 1, further comprising: