WO2019128763A1 - 一种极化码译码器及译码方法 - Google Patents

一种极化码译码器及译码方法 Download PDF

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Publication number
WO2019128763A1
WO2019128763A1 PCT/CN2018/121582 CN2018121582W WO2019128763A1 WO 2019128763 A1 WO2019128763 A1 WO 2019128763A1 CN 2018121582 W CN2018121582 W CN 2018121582W WO 2019128763 A1 WO2019128763 A1 WO 2019128763A1
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Prior art keywords
decoding
input end
path
paths
input
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PCT/CN2018/121582
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English (en)
French (fr)
Inventor
张玉伦
游治
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华为技术有限公司
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Publication of WO2019128763A1 publication Critical patent/WO2019128763A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a polarization code decoder and a decoding method.
  • channel coding can ensure interference against the transmission of information, and the information data is reliably transmitted to the receiving device.
  • the transmitting device needs to encode the information data to obtain coded bits, interleave the coded bits, map the interleaved bits into modulation symbols, and then process and transmit the modulation symbols through the communication channel. After receiving the modulation symbol, the receiving device decodes and restores the information data by the decoder.
  • the 3GPP selected Polar code is used for control channel coding of 5G enhanced mobile broadband (eMBB) services.
  • Polar code can achieve error correction performance better than known patterns such as Turbo code, convolutional code and LDPC code with its unique channel polarization characteristics and combined with verification and other auxiliary means.
  • the main decoding methods of the Polar code include a serial cancellation (SC) decoding method and a list sequential cancellation list (SCL) decoding method.
  • SC decoding method uses a log likelihood ratio (LLR) as a decision criterion, performs hard decision on each bit, and sequentially determines decoding in order of bit number from small to large.
  • LLR log likelihood ratio
  • the number L of paths of the polarization code decoder is usually preset.
  • the number of paths of the SCL4 decoder is 4, which is only used for SCL4 decoding, and the path of the SCL8 decoder.
  • the number is 8, which is only used for SCL8 decoding.
  • the structure of the polarization code decoder is not flexible and the applicability is poor. For example, when there are multiple sets of data to be decoded at the same time, this way The polarization code decoder cannot coordinate between delay and performance.
  • the present application provides a polarization code decoder and a decoding method for solving the technical problem that the structure of the polarization code decoder in the prior art is inflexible and has poor applicability.
  • the present application provides a polarization code decoder, the polarization code decoder comprising a decoding unit, a control unit communicatively coupled to the decoding unit, and the decoding unit includes m inputs And n paths, the m inputs are selectively connected to the n paths, m, n are integers, m ⁇ n;
  • the decoding unit is configured to receive a first control signal sent by the control unit, and perform the following operations according to the first control signal:
  • the p1 input terminals are configured to be connected in one-to-one correspondence with the p1 paths, and the first candidate set is input to the first input end through the first input end. a path of the connection; and configuring a path corresponding to the first input end to be decoded in an SC decoding mode, wherein the first input end is any one of p1 input ends, and p1 is less than or equal to An integer of m;
  • the first control signal is used to indicate the SCL w1 decoding mode, configuring the second input end to be connected with the w1 paths, and inputting the second candidate set to the second input end by using the second input end Corresponding to the connected w1 paths; and configuring the w1 paths corresponding to the second input end to be decoded in the SCL w1 decoding mode, and the second input end is any one of the p2 input terminals , p2 is an integer less than or equal to m.
  • the SC decoding mode or the SCL w1 decoding mode may be implemented according to the first control signal sent by the control unit, so that the polarization code decoder is implemented.
  • the performance is more diverse and more able to meet business needs.
  • the m inputs are selectively connected to the n paths, including:
  • the m inputs are selectively coupled to the n paths by a plurality of selectors.
  • the first control signal is used to indicate an SC coding mode or an SCL 2 coding mode
  • the m inputs are selectively connected to the n paths by a plurality of selectors, including:
  • the third input end and the fourth input end are selectively connected to the first path by the first selector, and the third input end is connected to the second path; the third input end and the fourth input end are Determining two of the m inputs, the first selector is one of the plurality of selectors, the first path and the second path being two of the n paths path;
  • the third input end is respectively connected to the first path and the second path; when the first selector is in the second state, the first A three input terminal is coupled to the second path, and the fourth input terminal is coupled to the first path.
  • the first control signal is used to indicate an SC coding mode or an SCL 4 coding mode
  • the m inputs are selectively connected to the n paths by a plurality of selectors, including:
  • the fifth input terminal is connected to the third path, and the fifth input end and the sixth input end are selectively connected to the fourth path by the second selector, and the fifth input end and the seventh input end pass
  • the third selector is selectively connected to the fifth path, and the fifth input end and the eighth input end are selectively connected to the sixth path by the third selector; the fifth input end, the sixth input end
  • the fourth input end and the eighth input end are four of the m input ends, and the second selector, the third selector, and the fourth selector are Three of the plurality of selectors, the third path, the fourth path, the fifth path, and the sixth path are four of the n paths;
  • the fifth input end is respectively associated with the third path, the fourth path, the fifth path, and the sixth path Connecting; when the second selector, the third selector, and the fourth selector are both in the second state, the fifth input is connected to the third path, and the sixth input is connected to the fourth path, The seventh input terminal is connected to the fifth path, and the eighth input terminal is connected to the sixth path.
  • the decoding unit is further configured to select p3 candidate sets from the p1 candidate sets, or select p3 candidate sets from the p2 candidate sets; p3 is smaller than P1 or an integer less than p2;
  • the control unit is further configured to: after the decoding unit selects the p3 candidate sets, send a second control signal to the decoding unit, where the second control signal is used to indicate an SCL w2 decoding mode.
  • w2 2 h2
  • h2 is an integer greater than or equal to 1; w2>w1;
  • the decoding unit is further configured to receive a second control signal sent by the control unit, and configure a ninth input end corresponding to the w2 paths according to the second control signal, and pass the ninth input end
  • the candidate set is input to the w2 paths corresponding to the ninth input end; and the w2 paths corresponding to the ninth input end are configured to be decoded in the SCL w2 decoding mode, where the ninth input end is Any of the p3 inputs.
  • the polarization code decoder of the embodiment of the present application is applied to the blind detection scenario, and only one polarization code decoder can be set to implement the first level decoding and the second level decoding.
  • it is required to separately provide a polarization code decoder for performing first-level decoding and a polarization code decoder for performing second-level decoding, which can effectively reduce chip area and reduce work. Consumption.
  • control unit before the control unit sends the second control signal to the decoding unit, the control unit is further configured to:
  • the second control signal is determined based on a signal to noise ratio.
  • the first control signal is used to indicate an SC coding mode, and the second control signal is used to indicate an SCL 2 coding mode; or the first control signal is used to indicate an SC translation a code mode, the second control signal is used to indicate an SCL 4 coding mode; or the first control signal is used to indicate an SC coding mode, and the second control signal is used to indicate an SCL 8 coding mode.
  • an embodiment of the present application provides a data transmission apparatus, where the data transmission apparatus includes a polarization code decoder in any of the above designs.
  • the embodiment of the present application further provides a polarization code decoder, where the polarization code decoder includes a decoding unit, a control unit communicatively coupled to the decoding unit, and the decoding unit includes m input terminals. And n paths, the m inputs are selectively connected to the n paths, m, n are integers, m ⁇ n;
  • the control unit is configured to send a first control signal to the decoding unit, where the first control signal is used to indicate a first coding mode or a second coding mode; wherein the first coding mode is Refers to decoding a candidate set by one path; the second coding mode refers to decoding a candidate set by two or more paths;
  • the decoding unit is configured to receive a first control signal sent by the control unit, and perform the following operations according to the first control signal:
  • the first control signal is used to indicate the first decoding mode, configure p1 inputs to be connected in one-to-one correspondence with p1 paths, and input the first candidate set to the first through the first input end
  • the input end corresponds to the connected path; and the first candidate set is decoded by the path corresponding to the first input end, the first input end is any one of the p1 input ends, p1 An integer less than or equal to m;
  • the first control signal is used to indicate the second decoding mode, configuring the second input end to be connected with the w1 paths, and inputting the second candidate set to the second through the second input end
  • the input end corresponds to the connected w1 paths; and the second candidate set is decoded by the w1 paths corresponding to the second input end, and the second input end is any one of p2 input ends
  • p2 is an integer less than or equal to m
  • w1 is an integer greater than 1 and w1 ⁇ n.
  • the first coding mode may specifically refer to an SC coding mode
  • the second coding mode may specifically refer to an SCL coding mode. Since the number of paths corresponding to one input in the SCL decoding mode is usually 2 h1 and h1 is an integer greater than or equal to 1, w1 can be equal to 2 h1 .
  • the decoding unit is further configured to select p3 candidate sets from the p1 candidate sets, or select p3 candidate sets from the p2 candidate sets; p3 is smaller than P1 or an integer less than p2;
  • the control unit is further configured to: after the decoding unit selects the p3 candidate sets, send a second control signal to the decoding unit, where the second control signal is used to indicate a third decoding mode
  • the third decoding mode refers to decoding a candidate set by two or more paths
  • the decoding unit is further configured to receive a second control signal sent by the control unit, and configure a ninth input end corresponding to the w2 paths according to the second control signal, and pass the ninth input end
  • the candidate set is input to the w2 paths corresponding to the ninth input end; and the third candidate set is decoded by the w2 paths corresponding to the ninth input end, and the ninth input end is p3
  • w2 is an integer greater than 1 and w2 ⁇ n.
  • the third decoding mode may specifically refer to an SCL decoding mode, so w2 may be equal to 2 h 2 , and h 2 is an integer greater than or equal to 1.
  • the decoding mode indicated by the first control signal is the first level decoding
  • the purpose is to filter the candidate set
  • the decoding mode indicated by the second control signal is the second level decoding.
  • the purpose is to obtain the final decoding result. Therefore, in order to make the final decoding result more accurate and reliable on the basis of ensuring the delay target, w2>w1 can be set.
  • the embodiment of the present application further provides a decoding method, where the decoding method is applied to a polar code decoder, where the polar code decoder includes m input ends and n paths, and the m The input end is selectively connected to the n paths, where m and n are integers, and m ⁇ n; the decoding method includes:
  • the first control signal is used to indicate a first coding mode or a second coding mode
  • the first control signal is used to indicate the first decoding mode, configure the p1 input terminals to be connected in one-to-one correspondence with the p1 paths, and input the first candidate set to the first input terminal through the first input end.
  • the first candidate set Corresponding to the connected path; and decoding, by the first input end, the first candidate set, wherein the first input end is any one of p1 input ends, and p1 is smaller than Or an integer equal to m;
  • the first control signal is used to indicate the second decoding mode, configuring the second input end to be connected with the w1 paths, and inputting the second candidate set to the second through the second input end
  • the input end corresponds to the connected w1 paths; and the second candidate set is decoded by the w1 paths corresponding to the second input end, and the second input end is any one of p2 input ends
  • p2 is an integer less than or equal to m
  • w1 is an integer greater than 1 and w1 ⁇ n.
  • the first coding mode may specifically refer to an SC coding mode
  • the second coding mode may specifically refer to an SCL coding mode
  • the method further includes:
  • p3 is an integer less than p1 or less than p2;
  • the second control signal is used to indicate a third coding mode; and the third coding mode is to decode a candidate set by two or more paths;
  • the third decoding mode may specifically refer to an SCL decoding mode, so w2 may be equal to 2 h 2 , and h 2 is an integer greater than or equal to 1.
  • a decoding method is further provided in the embodiment of the present application, where the decoding method is applied to a polar code decoder, where the polar code decoder includes m input ends and n paths, where the m The input ends are selectively connected to the n paths, m and n are integers, and m ⁇ n; the decoding method includes:
  • the first control signal is used to indicate a fourth coding mode; and the fourth coding mode is to decode a candidate set by w3 paths, and w3 is an integer greater than or equal to 1. ;
  • the fourth coding mode when w3 is 1, the fourth coding mode may be an SC coding mode, and when w3 is an integer greater than or equal to 2, the fourth coding mode may be an SCL coding mode.
  • the polarization code decoder provided by the embodiment of the present invention can realize different decoding modes through selective connection between the input end and the path, so that the performance and processing delay of the polarization code decoder are various. Therefore, through a decoder, different performance and different parallelism can be decoded, flexible selection in speed performance, and two-level decoding can be realized based on the decoder to accelerate the PDCCH blind detection process and effectively avoid In the prior art, multiple polarization code decoders are needed to achieve the processing delay problem, which greatly reduces chip area and power consumption.
  • FIG. 1 is a schematic diagram of a network architecture applicable to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a blind detection decoding process
  • FIG. 3 is a schematic diagram of a blind detection device in the prior art
  • FIG. 4 is a schematic structural diagram of a polarization code decoder according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a polarization code decoder according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of an SC decoding mode of a polarization code decoder according to an embodiment of the present disclosure
  • FIG. 5b is a schematic diagram of a SCL2 decoding mode of a polarization code decoder according to an embodiment of the present disclosure
  • FIG. 6 is another schematic diagram of a polarization code decoder according to an embodiment of the present disclosure.
  • 6a is a schematic diagram of a SCL4 decoding mode of a polarization code decoder according to an embodiment of the present disclosure
  • FIG. 7a is a schematic diagram of a coding mode and a data flow in a first possible implementation manner
  • FIG. 7b is a schematic diagram of a coding mode and a data flow in a second possible implementation manner
  • FIG. 7c is a schematic diagram of a coding mode and a data flow in a third possible implementation manner
  • FIG. 7 is a schematic flowchart of two-level decoding according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a data transmission apparatus according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a network architecture applicable to an embodiment of the present application.
  • the network architecture may include at least one network device 100 (only one shown) and one or more terminal devices 200 connected to the network device 100.
  • Network device 100 can be a device that can communicate with terminal device 200.
  • the network device 100 can be any device having a wireless transceiving function. Including but not limited to: a base station (eg, a base station NodeB, an evolved base station eNodeB, a base station in a fifth generation (5G) communication system, a base station or network device in a future communication system, an access node in a WiFi system , wireless relay node, wireless backhaul node, etc.
  • the network device 100 may also be a wireless controller in a cloud radio access network (CRAN) scenario.
  • CRAN cloud radio access network
  • the network device 100 may also be a network device in a 5G network or a network device in a future evolved network; it may also be a wearable device or an in-vehicle device or the like.
  • the network device 100 may also be a small station, a transmission reference point (TRP) or the like. Of course, no application is not limited to this.
  • the terminal device 200 is a device with wireless transceiving function that can be deployed on land, including indoors or outdoors, handheld, wearable or on-board; it can also be deployed on the water surface (such as a ship, etc.); it can also be deployed in the air (for example, an airplane, Balloons and satellites, etc.).
  • the terminal device may be a mobile phone, a tablet (Pad), a computer with wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and industrial control ( Wireless terminal in industrial control, wireless terminal in self driving, wireless terminal in remote medical, wireless terminal in smart grid, transportation safety A wireless terminal, a wireless terminal in a smart city, a wireless terminal in a smart home, and the like.
  • a terminal device may also be referred to as a user equipment (UE), an access terminal device, a UE unit, a UE station, a mobile station, a mobile station, a remote station, a remote terminal device, a mobile device, a UE terminal device, a terminal device, Wireless communication device, UE proxy or UE device, and the like.
  • UE user equipment
  • the communication system to which the above network architecture is applicable includes, but is not limited to, a 5G communication system.
  • a 5G communication system in addition to the interaction of the data itself, there is an instruction interaction between the network device 100 and the terminal device 200.
  • the network device 100 completes the scheduling of the terminal device 200 by instructions, and delivers the format information of the scheduling.
  • the network device 100 often does not send or send some scheduling signaling, and the terminal device 200 itself monitors whether there is scheduling according to certain rules.
  • the terminal device 200 needs to perform blind detection decoding without knowing the exact format.
  • the blind detection decoding process is mostly shown in Figure 2. First, all possible decoding parameters are listed. Each hypothesis based on the decoding parameters and the data to be decoded (demodulated soft values) is translated as a candidate set. The code, the decoding result is judged to be right or wrong by verification, and the process is continued until the correct decoding result is searched or the entire set is traversed or a certain preset condition is reached.
  • the blind detection device In the general blind detection hypothesis (5G blind detection parameters have not been determined), there may be 44 candidate sets, wherein different candidate sets are obtained according to different combinations of decoding parameters and data to be decoded.
  • the blind detection device needs to separately set a polarization code decoder for performing the first stage decoding (specifically, 3 SC decoders) and a polarization code decoder for performing second stage decoding (specifically, 2 SCL8 decoders), as shown in FIG. 3, due to the need to set multiple polarization code translations
  • the coder leads to a large chip area and high power consumption.
  • the embodiment of the present application provides a polarization code decoder for solving the problem that the structure of the polarization code decoder in the prior art is inflexible and has poor applicability. Further, since the polarization code decoder provided by the embodiment of the present application can implement multiple coding modes, the first level translation in the 5G PDCCH blind detection scenario can be realized by setting a polarization code decoder. The code and the second level of decoding, in order to meet the blind detection delay target, avoid the problem of large chip area and high power consumption.
  • the polarization code decoder 400 includes a decoding unit 401 and a control unit 402, where The unit 401 and the control unit 402 are communicatively connected, and the manner of implementing the communication connection may be various, and is not limited herein.
  • the decoding unit 401 includes m input terminals (as shown in FIG. 4, which are input terminal 0, input terminal 1, input terminal 2, ..., input terminal m-1) and n paths (as shown in FIG. 4, The path is 0, path 1, path 2, ..., path n-1), and the m inputs are selectively connected to the n paths.
  • the decoding unit 401 is configured to receive the first control signal sent by the control unit 402, and perform the following operations according to the first control signal:
  • the first control signal is used to indicate the SC decoding mode, configure the p1 input terminals to be connected in one-to-one correspondence with the p1 paths, and input the first candidate set (candidate) to the first through the first input end.
  • the input end corresponds to the connected path; and the path corresponding to the first input end is configured to be decoded in an SC decoding mode, and the first input end is any one of the p1 input ends, and p1 is An integer less than or equal to m.
  • the first control signal is used to indicate the SCL w1 decoding mode, configuring the second input end to be connected with the w1 paths, and inputting, by the second input terminal, the second candidate set (candidate) to the first
  • the two inputs are corresponding to the connected w1 paths; and the w1 paths corresponding to the second input are configured to be decoded in the SCL w1 decoding mode, and the second input is any of the p2 inputs
  • p2 is an integer less than or equal to m.
  • the decoding unit may further include: n cyclic redundancy check (CRC) sub-units, which are respectively connected to the n paths, and are used for verifying the decoding result of the path of the corresponding connection.
  • CRC cyclic redundancy check
  • a decoding result processing subunit connected to the n CRC subunits, configured to obtain a final decoding result according to the verification result of each CRC subunit, or to filter out p2 according to the verification result of each CRC subunit Candidate sets (see the description of the primary decoding and the two-level decoding later).
  • the value of m can be less than or equal to the value of n, thereby ensuring that each input end can be connected in the SC decoding mode. path.
  • 8 inputs can respectively connect 8 paths, if in SCL2 decoding mode, 4 of them can correspond respectively.
  • six of the inputs can respectively correspond to 12 (6*2) paths.
  • the value of m and the value of n can be reasonably set according to actual needs, and are not limited.
  • the value of the value of m may be less than or equal to n as an example.
  • the value of w1 is less than or equal to the value of n.
  • the value of w1 may be 2, 4, or 8.
  • the value of w1 is 2, the value of p2 is 4, that is, 4 inputs are connected to 8 paths; when the value of w1 is 4, the value of p2 is 2, that is, 2 inputs. The corresponding end is connected to 8 paths; when the value of w1 is 8, the value of p2 is 1, that is, 8 inputs are connected to 8 paths.
  • the SC decoding mode or the SCL w1 decoding mode may be implemented according to the first control signal sent by the control unit, so that the polarization code is decoded.
  • the performance of the device is more diverse and more suitable for business needs.
  • m inputs are selectively connected to n paths by one or more selectors.
  • the first control signal is used to indicate the SC coding mode or the SCL 2 coding mode.
  • the connection between the m inputs and the n paths may be: the third input and the fourth input. The end is selectively connected to the first path by the first selector, and the third input is connected to the second path; the third input end and the fourth input end are two of the m input ends Inputs, the first selector is one of the plurality of selectors, the first path and the second path are two of the n paths; wherein the first When the selector is in the first state, the third input end is respectively connected to the first path and the second path; when the first selector is in the second state, the third input end is A second path is connected, and the fourth input is connected to the first path.
  • the first state may be an active state. At this time, “1” in the selector is turned on; the second state may be in a non-working state, and at this time, “0” in the selector is turned on.
  • FIG. 5 one possible configuration of a polarization code decoder is illustrated.
  • 8 inputs and 8 paths are selectively connected by 4 selectors (selector 1, selector 2, selector 3, selector 4): input 0 and input 1 are selected 1 is connected to path 1, and input 0 is connected to path 0; input 2 and input 3 are connected to path 3 via selector 2, and input 2 is connected to path 2; input 4 and input 5 are selected
  • the device 3 is connected to the path 5, and the input terminal 4 is connected to the path 4; the input terminal 6 and the input terminal 7 are connected to the path 7 via the selector 4, and the input terminal 6 is connected to the path 6.
  • the decoding unit may control the selector 1, the selector 2, the selector 3, and the selector 4 to be in the first state or the second state by SCL2_En according to the first control signal.
  • the decoding unit may control the selector 1, the selector 2, the selector 3, and the selector 4 to be in the second state through SCL2_En.
  • the input terminal 0 and Path 0 is connected, input 1 is connected to path 1, ..., and input 7 is connected to path 7.
  • the decoding unit may configure each path to be decoded in an SC decoding mode.
  • the decoding unit may control the selector 1, the selector 2, the selector 3, and the selector 4 to be in the first state through SCL2_En.
  • the input terminal 0 and Path 0 is connected to path 1
  • input 2 is connected to path 2 and path 3
  • input 4 is connected to path 4 and path 5
  • input 6 is connected to path 6 and path 7.
  • the decoding unit may configure path 0 and path 1 to be decoded in SCL2 coding mode, configure path 2 and path 3 to be decoded in SCL2 coding mode, and configure path 4 and path 5 as SCL2 decoding.
  • the mode is decoded, and path 6 and path 7 are configured for decoding in the SCL2 decoding mode.
  • the polarization code decoder illustrated in FIG. 5 can work in the SC decoding mode or in the SCL2 decoding mode according to the first control signal, so that the performance of the polarization code decoder is relatively better. diversification.
  • the first control signal is used to indicate the SC coding mode or the SCL4 coding mode.
  • the connection manner between the m input terminals and the n paths may be: the fifth input end and the third path. Connecting, the fifth input end and the sixth input end are selectively connected to the fourth path by the second selector, and the fifth input end and the seventh input end pass the third selector and the fifth path Selectively connecting, the fifth input end and the eighth input end are selectively connected to the sixth path by a third selector; the fifth input end, the sixth input end, and the seventh input end And the eighth input end is four of the m input ends, and the second selector, the third selector, and the fourth selector are among the plurality of selectors a third selector, the third path, the fourth path, the fifth path, and the sixth path are four of the n paths; wherein the second selector, the second When the third selector and the fourth selector are both in the first state, the fifth input ends respectively a third path, a fourth path,
  • FIG. 6 another possible structure of the polarization code decoder is illustrated.
  • 8 inputs and 8 paths are selectively connected by 6 selectors (Selector 1, Selector 2, Selector 3, Selector 4, Selector 5, Selector 6):
  • Input Terminal 0 is connected to path 0, input 0 and input 1 are connected to path 1 through selector 1, input 0 and input 2 are connected to path 2 via selector 2, and input 0 and input 3 are passed through selector 3.
  • input 4 is connected to path 4
  • input 4 and input 5 are connected to path 5 via selector 4
  • input 4 and input 6 are connected to path 6 via selector 5, input 4 and input
  • the terminal 7 is connected to the path 7 via the selector 6.
  • the decoding unit may control the selector 1, the selector 2, the selector 3, the selector 4, the selector 5, and the selector 6 to be in the first state or the second state by SCL4_En according to the first control signal.
  • the decoding unit may control the selector 1, the selector 2, the selector 3, the selector 4, the selector 5, and the selector 6 to be in the second state by SCL4_En.
  • input 0 is connected to path 0
  • input 1 is connected to path 1
  • ... is connected to path 7.
  • the decoding unit may configure each path to be decoded in an SC decoding mode.
  • the decoding unit may control the selector 1, the selector 2, the selector 3, the selector 4, the selector 5, and the selector 6 to be in the first state by SCL4_En.
  • input 0 is connected to path 0, path 1, path 3, path 4, and input 4 is connected to path 5, path 6, path 7, path 8.
  • the decoding unit may configure path 0, path 1, path 3, and path 4 to be decoded in the SCL4 decoding mode, and configure path 5, path 6, path 7, and path 8 to be decoded in the SCL4 decoding mode. .
  • the polarization code decoder illustrated in FIG. 6 can work in the SC decoding mode or in the SCL4 decoding mode according to the first control signal, so that the performance of the polarization code decoder is relatively better. diversification.
  • FIG. 5 and FIG. 6 are only two possible examples. According to FIG. 5 and FIG. 6, by adjusting the number and connection manner of the selector between the m input terminals and the n paths, that is, Two different coding modes can be implemented (the polarization code decoder in FIG. 5 can implement the SC coding mode, the SCL2 coding mode, and the polarization code decoder in FIG. 6 can implement the SC coding mode, SCL4 Decoding mode). In other examples, one polarization decoder can also implement more than two coding modes.
  • the coding mode that can be implemented by the polarization code decoder in this application is not limited to the foregoing SC coding mode, SCL2 coding mode, SCL4 coding mode, and may also be SCL8 coding mode, SCL16 coding mode or SCL32.
  • the decoding mode and the like are not specifically enumerated here.
  • the polarization code decoder in the embodiment of the present application is split into n independent SC decoders; when configured in the SCL2 decoding mode, in this embodiment of the present application, The polarization code decoder is split into n/2 independent SCL2 decoders; when configured in the SCL4 decoding mode, the polarization code decoder in the embodiment of the present application splits into n/4 independent SCL4 a decoder; when configured in the SCL8 decoding mode, the polarization code decoder in the embodiment of the present application is split into n/8 independent SCL8 decoders; when configured in the SCL16 decoding mode, the present application is implemented.
  • the polarization code decoder in the example is split into n/16 independent SCL16 decoders; when configured in the SCL32 decoding mode, the polarization code decoder in the embodiment of the present application is split into n/32 independent SCL32 decoder.
  • one possible decoding mode is one-level decoding. Specifically, the decoding unit directly obtains the first control signal through the SC decoding mode or the SCLw1 decoding mode. The final decoding result.
  • Another possible decoding method is two-level decoding. Specifically, after performing SC decoding according to the first control signal, the decoding unit selects p3 candidate sets from the p1 candidate sets, or translates After performing the SCLw1 decoding according to the first control signal, the code unit selects p3 candidate sets from the p2 candidate sets (first stage decoding); and further, the control unit is further configured to select at the decoding unit.
  • the decoding result processing sub-unit in the decoding unit directly obtains the final decoding result according to the verification result of each CRC sub-unit.
  • the decoding result processing sub-unit in the decoding unit may filter the candidate set according to the path metric value of the different path, specifically, according to the p1 a path metric value of the p1 paths corresponding to the candidate set, selecting p3 candidate sets from the p1 candidate sets, or according to path metric values of p2*w1 paths corresponding to the p2 candidate sets, The p2 candidate sets select p3 candidate sets.
  • the decoding result processing sub-unit compares the path metric values of different paths with the path metric threshold, and then filters out the path metric value smaller than the path metric threshold.
  • the value of w2 may be set to be larger than the value of w1.
  • the polarization code decoder illustrated in FIG. 4 in the embodiment of the present application may have multiple possible implementation manners when performing two-level decoding, and several specific examples are listed below.
  • Figure 7a is a schematic diagram of a coding mode and a data flow in a first possible implementation.
  • the first-stage coding mode is an SC coding mode
  • p3 candidate sets are selected for second-level decoding
  • the second-level decoding mode is SCL 8 or SCL 16 or SCL 32 decoding mode.
  • FIG. 7b is a schematic diagram of a coding mode and a data flow in a second possible implementation manner.
  • the first-stage decoding mode is the SCL 2 decoding mode
  • p3 candidate sets are selected for second-level decoding
  • the second-level decoding mode is SCL 8 or SCL 16 Or SCL 32 decoding mode.
  • FIG. 7c is a schematic diagram of a coding mode and a data flow in a third possible implementation manner.
  • the first-stage decoding mode is the SCL 4 decoding mode
  • the p3 candidate sets are filtered for the second-level decoding
  • the second-level decoding mode is SCL 8 or SCL 16 .
  • SCL 32 decoding mode is SCL 32 decoding mode.
  • the second-level coding mode may be determined in advance, such as the SCL8 coding mode (in this case, the first-level coding mode may be the SC coding mode, the SCL2 coding mode, or the SCL4 coding mode). In this way, the decoding unit can directly decode using the SCL8 decoding mode.
  • the first control signal is used to indicate the SC decoding mode
  • the second control signal is used to indicate the SCL4 decoding mode (see the structure of the polarization code decoder shown in FIG. 6) as an example, which is specifically described in conjunction with FIG. 7d.
  • Step 700 Obtain p1 candidate sets from the set of candidate sets, and p1 is less than or equal to m.
  • m 8. If the candidate set of the candidate set set that has not been subjected to the first level decoding is greater than or equal to 8, the p1 may be equal to 8. If the candidate set of the candidate set set that has not been subjected to the first level decoding is less than 8, the p1 is equal to the candidate. The number of candidate sets in the set that have not been decoded by the first stage.
  • step 701 p1 candidate sets are input from m inputs.
  • Step 702 The decoding unit configures a connection manner between the input end and the path according to the first control signal, and configures an SC decoding mode for decoding (see FIG. 5a).
  • step 703 the p3 candidate sets are filtered out.
  • the filtered candidate set may be an input.
  • Step 704 The decoding unit configures a connection mode between the input end and the path according to the second control signal, and configures the SCL4 decoding mode for decoding (see FIG. 5b).
  • the selector 1, the selector 2, and the selection can be directly controlled by SCL4_En.
  • the selector 3, the selector 5, the selector 5 and the selector 6 are in the first state and perform SCL4 decoding; if the two candidate sets selected in step 703 are candidates for the candidate set 0 and the input 4 of the input terminal 0
  • the decoding unit needs to exchange candidate set 1 and parameter 0 for position, parameter 4 and parameter 5.
  • the position is exchanged such that input 0 inputs the parameter 1, input 4 inputs the parameter 5, and controls the selector 1, the selector 2, the selector 3, the selector 4, the selector 5, and the selector 6 to be in the first state by SCL4_En , SCL4 decoding. It should be understood that the operations described herein are only taken based on the polarization code decoder illustrated in FIG. 6. If the polarization code decoder is designed to have other structures, the decoding unit may not need to perform the exchange location. operating.
  • Step 705 Is there any candidate set in the candidate set set that has not been decoded by the first level, and if yes, executing step 700; if not, executing step 706.
  • the polarization code decoder illustrated in FIG. 6 has only eight input terminals, only one candidate set can be decoded by performing the above one-time flow. If the candidate set is 44, it is required. The above process needs to be performed 6 times, wherein, since there are only 4 candidate sets in the last time, in the first stage decoding, some input inputs are empty, which does not affect the execution of the embodiment of the present application, and is still filtered. Two candidate sets can be used for the second level decoding. That is to say, for 44 candidate sets, the polarization decoder needs to perform the above steps 701 to 704 cyclically six times.
  • Step 706 Obtain a final decoding result according to the decoded result of the selected candidate set.
  • step 705 After 44 candidate sets are decoded by the first stage, a total of 12 candidate sets are selected for second-level decoding. Thus, in step 705, according to the second of 12 candidate sets.
  • the level decoding result is the final decoding result.
  • the polarization code decoder in the embodiment of the present application may also provide two or more decoding modes, which are not limited. .
  • the polarization code decoder provided by the embodiment of the present application is not limited to the 5G NR scenario, and may be applied to any other communication system that uses the polarization code as the channel coding, and is not limited thereto.
  • the embodiment of the present application further provides a decoding method, where the decoding method can be applied to the polar code decoder described in the foregoing embodiment, where the decoding method includes:
  • the first control signal is used to indicate a first decoding mode or a second decoding mode; if the first control signal is used to indicate a first decoding mode, configuring p1 inputs and P1 paths are connected in a one-to-one correspondence, and the first candidate set is input to the path corresponding to the connection of the first input end through the first input end; and the first connection path is connected to the first through the first input end
  • the candidate set is decoded, the first input end is any one of the p1 input terminals, and p1 is an integer less than or equal to m; if the first control signal is used to indicate the second decoding mode And configuring the second input end to be connected with the w1 paths, and inputting, by the second input end, the second candidate set to the w1 paths corresponding to the second input end; and, by the second input
  • the second candidate set is decoded by the w1 paths corresponding to the connection, the second input is any input of the p2 input terminals, p2 is
  • the first coding mode may specifically refer to an SC coding mode
  • the second coding mode may specifically refer to an SCL coding mode
  • the method further includes:
  • the third decoding mode may specifically refer to an SCL decoding mode, so w2 may be equal to 2 h 2 , and h 2 is an integer greater than or equal to 1.
  • the embodiment of the present application further provides a data transmission device, which includes the polarization code decoder in any of the above designs.
  • FIG. 8 is a schematic structural diagram of a data transmission apparatus according to an embodiment of the present invention (for example, an access point or a base station, a communication device such as a station or a terminal, or a chip in the foregoing communication device, etc.).
  • data transfer device 800 can be implemented by bus 801 as a general bus architecture.
  • bus 801 can include any number of interconnecting buses and bridges.
  • the bus 801 connects various circuits together, including a processor 802, a storage medium 803, and a bus interface 804, wherein the processor may include the polarization code decoder described above in FIG. 4, FIG. 5 or FIG. .
  • the data transmission device 800 connects the receiver front end processing unit 805 or the like via the bus 801 using the bus interface 804.
  • the receiver front end processing unit 805 can be used to implement signal processing functions of the physical layer in the wireless communication network, and transmit and receive radio frequency signals through the antenna 807.
  • the user interface 806 can be connected to a user terminal such as a keyboard, display, mouse or joystick.
  • the bus 801 can also be connected to various other circuits, such as timing sources, peripherals, voltage regulators, or power management circuits, etc., which are well known in the art and therefore will not be described in detail.
  • data transfer device 800 can also be configured as a general purpose processing system, such as generally referred to as a chip, including: one or more microprocessors that provide processor functionality; and an external portion that provides at least a portion of storage medium 803 Memory, all of which are connected to other supporting circuits through an external bus architecture.
  • a general purpose processing system such as generally referred to as a chip, including: one or more microprocessors that provide processor functionality; and an external portion that provides at least a portion of storage medium 803 Memory, all of which are connected to other supporting circuits through an external bus architecture.
  • data transfer device 800 can be implemented using: an ASIC (application specific integrated circuit) having processor 802, bus interface 804, user interface 806; and at least a portion of storage medium 803 integrated in a single chip, or
  • the data transmission device 800 can be implemented using one or more FPGAs (Field Programmable Gate Arrays), PLDs (Programmable Logic Devices), controllers, state machines, gate logic, discrete hardware components, any other suitable A circuit, or any combination of circuits capable of performing the various functions described throughout the present invention.
  • FPGAs Field Programmable Gate Arrays
  • PLDs Programmable Logic Devices
  • controllers state machines, gate logic, discrete hardware components, any other suitable A circuit, or any combination of circuits capable of performing the various functions described throughout the present invention.
  • the processor 802 is responsible for managing the bus and general processing (including executing software stored on the storage medium 803).
  • Processor 802 can be implemented using one or more general purpose processors and/or special purpose processors. Examples of processors include microprocessors, microcontrollers, DSP processors, and other circuits capable of executing software.
  • Software should be interpreted broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
  • Storage medium 803 is shown separated from processor 802 in the following figures, however, those skilled in the art will readily appreciate that storage medium 803, or any portion thereof, may be located external to data transmission device 800.
  • storage medium 803 can include transmission lines, carrier waveforms modulated with data, and/or computer products separate from wireless nodes, all of which can be accessed by processor 802 through bus interface 804.
  • storage medium 803, or any portion thereof, may be integrated into processor 802, for example, may be a cache and/or a general purpose register.
  • the polarization code decoder in the processor 802 can perform the flow shown in FIG. 7d above, and details are not described herein again.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

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Abstract

一种极化码译码器及译码方法，极化码译码器包括译码单元、与译码单元通信连接的控制单元；译码单元包括m个输入端和n个路径，m个输入端与n个路径选择性连接；控制单元，用于向译码单元发送第一控制信号，第一控制信号用于指示SC译码模式或SCL w1译码模式；译码单元，用于接收控制单元发送的第一控制信号，并根据第一控制信号配置SC译码模式进行译码或配置SCLw1译码模式进行译码。由此可知，本申请提供的极化码译码器可通过输入端与路径的选择性连接实现不同的译码模式，从而通过一个译码器，可实现不同性能和不同并行度的译码，在速度性能方面实现灵活选择，并可以基于该译码器实现两级译码，加速PDCCH盲检测过程。

Description

一种极化码译码器及译码方法
本申请要求在2017年12月29日提交中华人民共和国知识产权局、申请号为201711490147.3、发明名称为“一种极化码译码器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，特别涉及一种极化码译码器及译码方法。
背景技术
在通信系统中，信道编码可以保证对抗信息发送中的干扰，将信息数据可靠地传输至接收设备。通常发送设备需要对信息数据进行编码以获取编码比特，对编码比特进行交织，将交织后的比特映射成调制符号，然后通过通信信道来处理和发送调制符号。接收设备接收到调制符号后，通过译码器进行译码并恢复成信息数据。
3GPP选定极化(Polar)码用于5G增强移动宽带(enhance mobile broadband，eMBB)业务的控制信道编码。Polar码以其特有的信道极化特性，再结合校验等辅助手段后，可以达到优于Turbo码、卷积码和LDPC码等已知的各种码型的纠错性能。Polar码的主要译码方法包括串行抵消(successive cancellation，SC)译码方法和列表串行抵消(successive cancellation list，SCL)译码方法。其中，SC译码方法以对数似然比(log likelihood ratio，LLR)为判决准则，对每一个比特进行硬判决，按比特序号从小到大的顺序依次判决译码。SCL译码方法是对SC译码方法的改进，其中，路径(List)的个数记为L(L>1)，当L＝1时，SCL译码方法退化为SC译码方法，当L≥2K时，SCL译码等价于最大似然译码。
现有技术中，极化码译码器的路径个数L通常是预先设定好，比如，SCL4译码器的路径个数为4，只用于进行SCL4译码，SCL8译码器的路径个数为8，只用于进行SCL8译码，采用此种方式，极化码译码器的结构不灵活，适用性较差，比如，当同时有多组待译码数据时，此种方式的极化码译码器无法在延时和性能间进行协调。
发明内容
本申请提供一种极化码译码器及译码方法，用于解决现有技术中的极化码译码器的结构不灵活，适用性较差的技术问题。
第一方面，本申请提供一种极化码译码器，所述极化码译码器包括译码单元、与所述译码单元通信连接的控制单元；所述译码单元包括m个输入端和n个路径，所述m个输入端与所述n个路径选择性连接，m、n为整数，m≤n；
所述控制单元，用于向所述译码单元发送第一控制信号，所述第一控制信号用于指示SC译码模式或SCL w1译码模式，w1＝2 h1，h1为大于或等于1的整数，w1≤n；
所述译码单元，用于接收所述控制单元发送的第一控制信号，并根据所述第一控制信号执行如下操作：
若所述第一控制信号用于指示SC译码模式，则配置p1个输入端与p1个路径一一对应连接，并通过第一输入端将第一候选集输入到所述第一输入端对应连接的路径；以及，将所述第一输入端对应连接的路径配置为SC译码模式进行译码，所述第一输入端为p1个 输入端中的任一输入端，p1为小于或等于m的整数；
若所述第一控制信号用于指示SCL w1译码模式，则配置第二输入端与w1个路径对应连接，并通过所述第二输入端将第二候选集输入到所述第二输入端对应连接的w1个路径；以及，将所述第二输入端对应连接的w1个路径配置为SCL w1译码模式进行译码，所述第二输入端为p2个输入端中的任一输入端，p2为小于或等于m的整数。
根据上述内容可知，由于m个输入端与n个路径选择性连接，因此可以根据控制单元发送的第一控制信号，实现SC译码模式或SCL w1译码模式，从而使得极化码译码器的性能较为多样化，更能满足业务需求。
在一种可能的设计中，所述m个输入端与所述n个路径选择性连接，包括：
所述m个输入端与所述n个路径通过多个选择器选择性连接。
在一种可能的设计中，所述第一控制信号用于指示SC译码模式或SCL 2译码模式；
所述m个输入端与所述n个路径通过多个选择器选择性连接，包括：
第三输入端和第四输入端通过第一选择器与第一路径选择性连接，且所述第三输入端与第二路径连接；所述第三输入端和所述第四输入端为所述m个输入端中的两个输入端，第一选择器为所述多个选择器中的一个选择器，所述第一路径和所述第二路径为所述n个路径中的两个路径；
其中，所述第一选择器处于第一状态时，所述第三输入端分别与所述第一路径、所述第二路径连接；所述第一选择器处于第二状态时，所述第三输入端与所述第二路径连接，所述第四输入端与所述第一路径连接。
在一种可能的设计中，所述第一控制信号用于指示SC译码模式或SCL 4译码模式；
所述m个输入端与所述n个路径通过多个选择器选择性连接，包括：
第五输入端与第三路径连接，所述第五输入端和所述第六输入端通过第二选择器与第四路径选择性连接，所述第五输入端和所述第七输入端通过第三选择器与第五路径选择性连接，所述第五输入端和所述第八输入端通过第三选择器与第六路径选择性连接；所述第五输入端、所述第六输入端、所述第七输入端和所述第八输入端为所述m个输入端中的四个输入端，所述第二选择器、所述第三选择器和所述第四选择器为所述多个选择器中的三个选择器，所述第三路径、所述第四路径、所述第五路径和所述第六路径为所述n个路径中的四个路径；
其中，所述第二选择器、所述第三选择器和所述第四选择器均处于第一状态时，第五输入端分别与第三路径、第四路径、第五路径、第六路径连接；所述第二选择器、所述第三选择器和所述第四选择器均处于第二状态时，第五输入端与第三路径连接，第六输入端与第四路径连接，第七输入端与第五路径连接，第八输入端与第六路径连接。
在一种可能的设计中，所述译码单元，还用于从所述p1个候选集中选择出p3个候选集，或者，从所述p2个候选集中选择出p3个候选集；p3为小于p1或小于p2的整数；
所述控制单元，还用于在所述译码单元选择出所述p3个候选集后，向所述译码单元发送第二控制信号，所述第二控制信号用于指示SCL w2译码模式，w2＝2 h2，h2为大于或等于1的整数；w2>w1；
所述译码单元，还用于接收所述控制单元发送的第二控制信号，并根据所述第二控制信号配置第九输入端与w2个路径对应连接，并通过所述第九输入端将候选集输入到所述第九输入端对应连接的w2个路径；以及，将所述第九输入端对应连接的w2个路径配置为 SCL w2译码模式进行译码，所述第九输入端为p3个输入端中的任一输入端。
根据上述内容可知，将本申请实施例的极化码译码器应用到盲检测场景中，只需设置一个极化码译码器即可实现第一级译码和第二级译码，相比于现有技术中需要分别设置用于执行第一级译码的极化码译码器和用于执行第二级译码的极化码译码器，能够有效减小芯片面积，降低功耗。
在一种可能的设计中，所述控制单元向所述译码单元发送第二控制信号之前，还用于：
根据信噪比确定所述第二控制信号。
在一种可能的设计中，所述第一控制信号用于指示SC译码模式，所述第二控制信号用于指示SCL 2译码模式；或者，所述第一控制信号用于指示SC译码模式，所述第二控制信号用于指示SCL 4译码模式；或者，所述第一控制信号用于指示SC译码模式，所述第二控制信号用于指示SCL 8译码模式。
第二方面，本申请实施例提供一种数据传输装置，所述数据传输装置包括上述任一种设计中的极化码译码器。
本申请实施例还提供一种极化码译码器，所述极化码译码器包括译码单元、与所述译码单元通信连接的控制单元；所述译码单元包括m个输入端和n个路径，所述m个输入端与所述n个路径选择性连接，m、n为整数，m≤n；
所述控制单元，用于向所述译码单元发送第一控制信号，所述第一控制信号用于指示第一译码模式或第二译码模式；其中，所述第一译码模式是指通过一个路径对一个候选集进行译码；所述第二译码模式是指通过两个或两个以上的路径对一个候选集进行译码；
所述译码单元，用于接收所述控制单元发送的第一控制信号，并根据所述第一控制信号执行如下操作：
若所述第一控制信号用于指示所述第一译码模式，则配置p1个输入端与p1个路径一一对应连接，并通过第一输入端将第一候选集输入到所述第一输入端对应连接的路径；以及，通过所述第一输入端对应连接的路径对所述第一候选集进行译码，所述第一输入端为p1个输入端中的任一输入端，p1为小于或等于m的整数；
若所述第一控制信号用于指示所述第二译码模式，则配置第二输入端与w1个路径对应连接，并通过所述第二输入端将第二候选集输入到所述第二输入端对应连接的w1个路径；以及，通过所述第二输入端对应连接的w1个路径对所述第二候选集进行译码，所述第二输入端为p2个输入端中的任一输入端，p2为小于或等于m的整数，w1为大于1的整数且w1≤n。
进一步地，第一译码模式具体可以是指SC译码模式，第二译码模式具体可以是指SCL译码模式。由于SCL译码模式中一个输入端对应的路径个数通常为2 h1，h1为大于或等于1的整数，因此w1可以等于2 h1。
在一种可能的设计中，所述译码单元，还用于从所述p1个候选集中选择出p3个候选集，或者，从所述p2个候选集中选择出p3个候选集；p3为小于p1或小于p2的整数；
所述控制单元，还用于在所述译码单元选择出所述p3个候选集后，向所述译码单元发送第二控制信号，所述第二控制信号用于指示第三译码模式；所述第三译码模式是指通过两个或两个以上的路径对一个候选集进行译码；
所述译码单元，还用于接收所述控制单元发送的第二控制信号，并根据所述第二控制信号配置第九输入端与w2个路径对应连接，并通过所述第九输入端将候选集输入到所述 第九输入端对应连接的w2个路径；以及，通过所述第九输入端对应连接的w2个路径对第三候选集进行译码，所述第九输入端为p3个输入端中的任一输入端，w2为大于1的整数且w2≤n。
进一步地，第三译码模式具体可以是指SCL译码模式，因此w2可以等于2 h2，h2为大于或等于1的整数。
本申请实施例中由于第一控制信号所指示的译码模式为第一级译码，其目的是为了筛选候选集，而第二控制信号所指示的译码模式为第二级译码，其目的是获取最终的译码结果，因此，为了在保证延迟目标的基础上，使得最终的译码结果更为准确可靠，可设置w2>w1。
本申请实施例还提供一种译码方法，所述译码方法应用于极性码译码器中，所述极性码译码器中包括m个输入端和n个路径，所述m个输入端与所述n个路径选择性连接，m、n为整数，m≤n；所述译码方法包括：
接收第一控制信号；所述第一控制信号用于指示第一译码模式或第二译码模式；
若所述第一控制信号用于指示第一译码模式，则配置p1个输入端与p1个路径一一对应连接，并通过第一输入端将第一候选集输入到所述第一输入端对应连接的路径；以及，通过所述第一输入端对应连接的路径对所述第一候选集进行译码，所述第一输入端为p1个输入端中的任一输入端，p1为小于或等于m的整数；
若所述第一控制信号用于指示所述第二译码模式，则配置第二输入端与w1个路径对应连接，并通过所述第二输入端将第二候选集输入到所述第二输入端对应连接的w1个路径；以及，通过所述第二输入端对应连接的w1个路径对所述第二候选集进行译码，所述第二输入端为p2个输入端中的任一输入端，p2为小于或等于m的整数，w1为大于1的整数且w1≤n。
进一步地，第一译码模式具体可以是指SC译码模式，第二译码模式具体可以是指SCL译码模式。
在一种可能的设计中，所述方法还包括：
从所述p1个候选集中选择出p3个候选集，或者，从所述p2个候选集中选择出p3个候选集；p3为小于p1或小于p2的整数；
接收第二控制信号，所述第二控制信号用于指示第三译码模式；所述第三译码模式是指通过两个或两个以上的路径对一个候选集进行译码；
根据所述第二控制信号配置第九输入端与w2个路径对应连接，并通过所述第九输入端将候选集输入到所述第九输入端对应连接的w2个路径；以及，通过所述第九输入端对应连接的w2个路径对第三候选集进行译码，所述第九输入端为p3个输入端中的任一输入端，w2为大于1的整数且w2≤n。
进一步地，第三译码模式具体可以是指SCL译码模式，因此w2可以等于2 h2，h2为大于或等于1的整数。本申请实施例中还提供一种译码方法，所述译码方法应用于极性码译码器中，所述极性码译码器中包括m个输入端和n个路径，所述m个输入端与所述n个路径选择性连接，m、n为整数，m≤n；所述译码方法包括：
接收第一控制信号；所述第一控制信号用于指示第四译码模式；所述第四译码模式是指通过w3个路径对一个候选集进行译码，w3为大于或等于1的整数；
配置p4个输入端中的任一输入端与w3个路径对应连接，并通过所述任一输入端将对 应的候选集输入到所述任一输入端对应连接的w3个路径；以及，通过所述任一输入端对应连接的w3个路径对所述候选集进行译码，p4为小于或等于m的整数。
具体来说，当w3为1时，所述第四译码模式可以为SC译码模式，当w3为大于或等于2的整数时，所述第四译码模式可以为SCL译码模式。
由上述内容可知，本申请实施例提供的极化码译码器可通过输入端与路径之间的选择性连接实现不同的译码模式，使得极化码译码器的性能和处理延迟较为多样化，从而通过一个译码器，可实现不同性能和不同并行度的译码，在速度性能方面实现灵活选择，并可以基于该译码器实现两级译码，加速PDCCH盲检测过程，有效避免现有技术中需要使用多个极化码译码器来实现处理延迟的问题，大幅降低芯片面积和功耗。
附图说明
图1为本申请实施例适用的一种网络架构示意图；
图2为盲检测译码流程示意图；
图3为现有技术中的盲检测设备示意图；
图4为本申请实施例提供的一种极化码译码器的结构示意图；
图5为本申请实施例提供的极化码译码器的一种示例图；
图5a为本申请实施例提供的极化码译码器的SC译码模式示意图；
图5b为本申请实施例提供的极化码译码器的SCL2译码模式示意图；
图6为本申请实施例提供的极化码译码器的另一种示例图；
图6a为本申请实施例提供的极化码译码器的SCL4译码模式示意图；
图7a为第一种可能的实现方式中的译码模式和数据流示意图；
图7b为第二种可能的实现方式中的译码模式和数据流示意图；
图7c为第三种可能的实现方式中的译码模式和数据流示意图；
图7d为本申请实施例提供的两级译码的流程示意图；
图8为本申请实施例提供的一种数据传输装置的结构示意图。
具体实施方式
下面结合说明书附图对本申请进行具体说明，方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。
图1为本申请实施例适用的一种网络架构示意图。该网络架构可以包括至少一个网络设备100(仅示出1个)以及与网络设备100连接的一个或多个终端设备200。
网络设备100可以是能和终端设备200通信的设备。网络设备100可以是任意一种具有无线收发功能的设备。包括但不限于：基站(例如，基站NodeB、演进型基站eNodeB、第五代(the fifth generation，5G)通信系统中的基站、未来通信系统中的基站或网络设备、WiFi系统中的接入节点、无线中继节点、无线回传节点)等。网络设备100还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。网络设备100还可以是5G网络中的网络设备或未来演进网络中的网络设备；还可以是可穿戴设备或车载设备等。网络设备100还可以是小站，传输节点(transmission reference point，TRP)等。当然不申请不限于此。
终端设备200是一种具有无线收发功能的设备可以部署在陆地上，包括室内或室外、 手持、穿戴或车载；也可以部署在水面上(如轮船等)；还可以部署在空中(例如飞机、气球和卫星上等)。所述终端设备可以是手机(mobile phone)、平板电脑(Pad)、带无线收发功能的电脑、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等等。本申请的实施例对应用场景不做限定。终端设备有时也可以称为用户设备(user equipment，UE)、接入终端设备、UE单元、UE站、移动站、移动台、远方站、远程终端设备、移动设备、UE终端设备、终端设备、无线通信设备、UE代理或UE装置等。
上述网络架构适用的通信系统包括但不限于5G通信系统，以5G通信系统为例，在5G通信系统中，网络设备100和终端设备200之间除了数据本身的交互外，还有指令的交互，网络设备100通过指令完成对终端设备200的调度，以及传递调度的格式信息。为了降低指令交互的开销，网络设备100常常不发送或者少发送某些调度信令，而由终端设备200按照一定规则自行监听是否存在调度。在监听过程中，终端设备200需要在不知道确切格式的情况下做盲检测译码。
盲检测译码流程大多如图2所示，首先列出所有可能的译码参数，根据译码参数和待译码数据(解调软值)组合成的每一种假设作为一个候选集来译码，译码结果通过校验来判断对错，持续这个过程直到搜索到正确的译码结果或遍历全部集合或达到某个预设条件。
在一般的盲检测假设中(5G盲检测参数尚未确定)，可能有44个候选集(candidate)，其中，不同的候选集是根据译码参数和待译码数据的不同组合得到的。为满足盲检测的延迟目标(比如4us)，一种实现方式为，盲检测设备先执行第一级译码，对C1(比如C1＝44)个候选集进行筛选，进而根据筛选出的C2种候选集执行第二级译码得到译码结果，C2<C1。然而，由于现有技术中的极化码译码器的结构不灵活，为实现这一过程，盲检测设备需要分别设置用于执行第一级译码的极化码译码器(具体可以为3个SC译码器)和用于执行第二级译码的极化码译码器(具体可以为2个SCL8译码器)，如图3所示，由于需要设置多个极化码译码器，从而导致芯片面积大，功耗高。
基于此，本申请实施例提供一种极化码译码器，用于解决现有技术中极化码译码器的结构不灵活，适用性较差的问题。进一步地，由于本申请实施例提供的极化码译码器可以实现多种译码模式，因此，通过设置一个极化码译码器即可实现5G的PDCCH盲检测场景中的第一级译码和第二级译码，从而在满足盲检测延迟目标的基础上，避免了芯片面积大、功耗高的问题。
图4为本申请实施例提供的一种极化码译码器的结构示意图，如图4所示，所述极化码译码器400包括译码单元401、控制单元402，其中，译码单元401和控制单元402通信连接，实现通信连接的方式可以有多种，此处不做限制。
译码单元401包括m个输入端(如图4所示，分别为输入端0、输入端1、输入端2、……、输入端m-1)和n个路径(如图4所示，分别为路径0、路径1、路径2、……、路径n-1)，所述m个输入端与所述n个路径选择性连接。
控制单元402，用于向所述译码单元401发送第一控制信号，所述第一控制信号用于指示SC译码模式或SCL w1译码模式，w1＝2 h1，h1为大于或等于1的整数，w1≤n。
译码单元401，用于接收所述控制单元402发送的第一控制信号，并根据所述第一控制信号执行如下操作：
若所述第一控制信号用于指示SC译码模式，则配置p1个输入端与p1个路径一一对应连接，并通过第一输入端将第一候选集(candidate)输入到所述第一输入端对应连接的路径；以及，将所述第一输入端对应连接的路径配置为SC译码模式进行译码，所述第一输入端为p1个输入端中的任一输入端，p1为小于或等于m的整数。
若所述第一控制信号用于指示SCL w1译码模式，则配置第二输入端与w1个路径对应连接，并通过所述第二输入端将第二候选集(candidate)输入到所述第二输入端对应连接的w1个路径；以及，将所述第二输入端对应连接的w1个路径配置为SCL w1译码模式进行译码，所述第二输入端为p2个输入端中的任一输入端，p2为小于或等于m的整数。
进一步地，译码单元中还可以包括：n个循环冗余校验(cyclic redundancy check,CRC)子单元，分别与n个路径对应连接，用于对对应连接的路径的译码结果进行校验；译码结果处理子单元，与n个CRC子单元连接，用于根据每个CRC子单元的校验结果得到最终的译码结果，或者，根据每个CRC子单元的校验结果筛选出p2个候选集(具体参见后文中一级译码和两级译码的描述)。
针对于m的取值和n的取值之间的关系，具体实施中，m的取值可以小于或等于n的取值，从而保证在SC译码模式下每个输入端都能对应连接一个路径。在一个示例中，m＝8，n＝8，若在SC译码模式下，8个输入端可以分别对应连接8个路径，若在SCL2译码模式下，其中的4个输入端可以分别对应连接8(4*2)个路径；在另一个示例中，m＝8，n＝12，若在SC译码模式下，8个输入端可以分别对应连接8个路径，若在SCL2译码模式下，其中的6个输入端可以分别对应连接12(6*2)个路径。
在其它的实施例中，m的取值也可以大于n的取值，比如，m＝8，n＝4，若在SC译码模式下，只能有其中的4个输入端分别对应连接4个路径，若在SCL2译码模式下，只能有其中的2个输入端分别对应连接4(2*2)个路径，由此可知，此种情形下可能会导致部分输入端未能被有效利用，但并不影响本申请实施例的实现。
根据以上内容，m的取值和n的取值可以根据实际需要进行合理设置，具体不做限定。本申请实施例中主要以m的取值可以小于或等于n的取值为例进行描述。
针对于p1的取值和m的取值之间的关系，具体实施中，以5G PDCCH盲检测场景为例，若具有44个候选集，m＝8，则需要进行6次SC译码方可遍历44个候选集；如此，进行前5次SC译码时，p1的取值可以和m的取值相同，即为8，而进行第6次SC译码时，由于仅剩余4个候选集，此时，p1的取值可以为4。需要说明的是，当p1的取值为4时，可以认为剩余的4个输入端输入为空，仍按照p1＝m时的情形来进行译码即可。
针对于w1的取值和n的取值之间的关系，具体实施中，w1的取值小于或等于n的取值，比如，n＝8时，w1的取值可以为2、4或8；进一步地，w1的取值为2时，p2的取值为4，即4个输入端对应连接到8个路径；w1的取值为4时，p2的取值为2，即2个输入端对应连接到8个路径；w1的取值为8时，p2的取值为1，即8个输入端对应连接到8个路径。
本申请实施例中，由于m个输入端与n个路径选择性连接，因此可以根据控制单元发 送的第一控制信号，实现SC译码模式或SCL w1译码模式，从而使得极化码译码器的性能较为多样化，更能满足业务需求。
具体来说，m个输入端与n个路径之间选择性连接的方式可以有多种。一种可能的实现方式为，m个输入端与n个路径通过一个或多个选择器进行选择性连接。
在一个示例中，第一控制信号用于指示SC译码模式或SCL 2译码模式，此时，m个输入端与n个路径之间的连接方式可以为：第三输入端和第四输入端通过第一选择器与第一路径选择性连接，且所述第三输入端与第二路径连接；所述第三输入端和所述第四输入端为所述m个输入端中的两个输入端，第一选择器为所述多个选择器中的一个选择器，所述第一路径和所述第二路径为所述n个路径中的两个路径；其中，所述第一选择器处于第一状态时，所述第三输入端分别与所述第一路径、所述第二路径连接；所述第一选择器处于第二状态时，所述第三输入端与所述第二路径连接，所述第四输入端与所述第一路径连接。具体实施中，第一状态可以为工作状态，此时，选择器中的“1”导通；第二状态可以为非工作状态，此时，选择器中的“0”导通。
基于该示例，参见图5，示意出了极化码译码器的一种可能的结构。如图5所示，8个输入端和8个路径通过4个选择器(选择器1、选择器2、选择器3、选择器4)进行选择性连接：输入端0和输入端1通过选择器1与路径1连接，且输入端0与路径0连接；输入端2和输入端3通过选择器2与路径3连接，且输入端2与路径2连接；输入端4和输入端5通过选择器3与路径5连接，且输入端4与路径4连接；输入端6和输入端7通过选择器4与路径7连接，且输入端6与路径6连接。译码单元可根据第一控制信号，通过SCL2_En控制选择器1、选择器2、选择器3和选择器4处于第一状态或第二状态。
若第一控制信号指示SC译码模式，则译码单元可通过SCL2_En控制选择器1、选择器2、选择器3和选择器4处于第二状态，此时，参见图5a，输入端0与路径0连接，输入端1与路径1连接，……，输入端7与路径7连接。进一步地，译码单元可将各个路径配置为SC译码模式进行译码。
若第一控制信号指示SCL2译码模式，则译码单元可通过SCL2_En控制选择器1、选择器2、选择器3和选择器4处于第一状态，此时，参见图5b，输入端0与路径0和路径1连接，输入端2与路径2和路径3连接，输入端4与路径4和路径5连接，输入端6与路径6和路径7连接。进一步地，译码单元可将路径0和路径1配置为SCL2译码模式进行译码，将路径2和路径3配置为SCL2译码模式进行译码，将路径4和路径5配置为SCL2译码模式进行译码，将路径6和路径7配置为SCL2译码模式进行译码。
根据上述内容可知，图5所示例出的极化码译码器可根据第一控制信号工作在SC译码模式下或工作在SCL2译码模式下，从而使得极化码译码器的性能较为多样化。
在另一个示例中，第一控制信号用于指示SC译码模式或SCL4译码模式，此时，m个输入端与n个路径之间的连接方式可以为：第五输入端与第三路径连接，所述第五输入端和所述第六输入端通过第二选择器与第四路径选择性连接，所述第五输入端和所述第七输入端通过第三选择器与第五路径选择性连接，所述第五输入端和所述第八输入端通过第三选择器与第六路径选择性连接；所述第五输入端、所述第六输入端、所述第七输入端和所述第八输入端为所述m个输入端中的四个输入端，所述第二选择器、所述第三选择器和所述第四选择器为所述多个选择器中的三个选择器，所述第三路径、所述第四路径、所述第五路径和所述第六路径为所述n个路径中的四个路径；其中，所述第二选择器、所述第 三选择器和所述第四选择器均处于第一状态时，第五输入端分别与第三路径、第四路径、第五路径、第六路径连接；所述第二选择器、所述第三选择器和所述第四选择器均处于第二状态时，第五输入端与第三路径连接，第六输入端与第四路径连接，第七输入端与第五路径连接，第八输入端与第六路径连接。
基于该示例，参见图6，示意出了极化码译码器的另一种可能的结构。如图6所示，8个输入端和8个路径通过6个选择器(选择器1、选择器2、选择器3、选择器4、选择器5、选择器6)进行选择性连接：输入端0与路径0连接，输入端0和输入端1通过选择器1与路径1连接，输入端0和输入端2通过选择器2与路径2连接，输入端0和输入端3通过选择器3与路径3连接；输入端4与路径4连接，输入端4和输入端5通过选择器4与路径5连接，输入端4和输入端6通过选择器5与路径6连接，输入端4和输入端7通过选择器6与路径7连接。译码单元可根据第一控制信号，通过SCL4_En控制选择器1、选择器2、选择器3、选择器4、选择器5和选择器6处于第一状态或第二状态。
若第一控制信号指示SC译码模式，则译码单元可通过SCL4_En控制选择器1、选择器2、选择器3、选择器4、选择器5、选择器6处于第二状态，此时，参见图5a，输入端0与路径0连接，输入端1与路径1连接，……，输入端7与路径7连接。进一步地，译码单元可将各个路径配置为SC译码模式进行译码。
若第一控制信号指示SCL4译码模式，则译码单元可通过SCL4_En控制选择器1、选择器2、选择器3、选择器4、选择器5、选择器6处于第一状态，此时，参见图6a，输入端0与路径0、路径1、路径3、路径4连接，输入端4与路径5、路径6、路径7、路径8连接。进一步地，译码单元可将路径0、路径1、路径3、路径4配置为SCL4译码模式进行译码，将路径5、路径6、路径7、路径8配置为SCL4译码模式进行译码。
根据上述内容可知，图6所示例出的极化码译码器可根据第一控制信号工作在SC译码模式下或工作在SCL4译码模式下，从而使得极化码译码器的性能较为多样化。
需要说明的是，上述图5和图6仅为两种可能的示例，根据图5和图6可知，通过调整m个输入端和n个路径之间的选择器的个数和连接方式，即可实现两种不同的译码模式(图5中的极化码译码器可实现SC译码模式、SCL2译码模式，图6中的极化码译码器可实现SC译码模式、SCL4译码模式)。在其它的示例中，一个极化译码器也可以实现两种以上的译码模式。进一步地，本申请中极化码译码器可以实现的译码模式不限于上述SC译码模式、SCL2译码模式、SCL4译码模式，还可以为SCL8译码模式、SCL16译码模式或SCL32译码模式等，此处不再具体列举。
可以理解的，当配置为SC译码模式时，本申请实施例中的极化码译码器分裂为n个独立的SC译码器；当配置为SCL2译码模式时，本申请实施例中的极化码译码器分裂为n/2个独立的SCL2译码器；当配置为SCL4译码模式时，本申请实施例中的极化码译码器分裂为n/4个独立的SCL4译码器；当配置为SCL8译码模式时，本申请实施例中的极化码译码器分裂为n/8个独立的SCL8译码器；当配置为SCL16译码模式时，本申请实施例中的极化码译码器分裂为n/16个独立的SCL16译码器；当配置为SCL32译码模式时，本申请实施例中的极化码译码器分裂为n/32个独立的SCL32译码器。
基于上述所描述的极化码译码器，一种可能的译码方式为一级译码，具体来说，译码单元根据第一控制信号，通过SC译码模式或SCLw1译码模式直接得到最终的译码结果。另一种可能的译码方式为两级译码，具体来说，译码单元根据第一控制信号，进行SC译 码后，从所述p1个候选集中选择出p3个候选集，或者，译码单元根据第一控制信号，进行SCLw1译码后，从所述p2个候选集中选择出p3个候选集(第一级译码)；进而，控制单元还用于在所述译码单元选择出所述p3个候选集后，向所述译码单元发送第二控制信号，所述第二控制信号用于指示SCL w2译码模式，w2＝2 h2；译码单元还用于接收所述控制单元发送的第二控制信号，并根据所述第二控制信号配置第二输入端(第二输入端为p3个输入端中的任一输入端)与w2个路径对应连接，并通过所述第二输入端将候选集输入到所述第二输入端对应连接的w2个路径；以及，将所述第二输入端对应连接的w2个路径配置为SCL w2译码模式进行译码，得到最终的译码结果(第二级译码)。
也就是说，若为一级译码方式，则译码单元中的译码结果处理子单元直接根据每个CRC子单元的校验结果得到最终的译码结果。若为两级译码方式，则在第一级译码中，译码单元中的译码结果处理子单元可以根据不同路径的路径度量值筛选候选集，具体来说，可以根据所述p1个候选集对应的p1个路径的路径度量值，从所述p1个候选集中选择出p3个候选集，或者，根据所述p2个候选集对应的p2*w1个路径的路径度量值，从所述p2个候选集中选择出p3个候选集；一种可能的实现方式中，译码结果处理子单元将不同路径的路径度量值与路径度量阈值进行比较，进而筛选出路径度量值小于路径度量阈值的路径对应的候选集，其中，路径度量阈值可根据实际情况进行设置；在第二级译码中，译码单元中的译码结果处理子单元根据筛选出的多个候选集的译码结果得到最终的译码结果。
进一步地，在两级译码方式中，由于进行第一级译码时，候选集的个数较多，且第一级译码的译码结果用于对候选集进行筛选，而进行第二级译码时，候选集的个数较少，且第二级译码的译码结果用于得到最终的译码结果，因此，本申请实施例中可设置w2的取值大于w1的取值，从而便于第一级译码和第二级译码的实现。
基于此，本申请实施例中图4所示意的极化码译码器在进行两级译码时，可以有多种可能的实现方式，下面具体列举几种。
图7a为第一种可能的实现方式中的译码模式和数据流示意图。如图7a所示，第一级译码模式为SC译码模式，第一级译码后筛选出p3个候选集进行第二级译码，第二级译码模式为SCL 8或SCL 16或SCL 32译码模式。
图7b为第二种可能的实现方式中的译码模式和数据流示意图。如图7b所示，第一级译码模式为SCL 2译码模式，第一级译码后筛选出p3个候选集进行第二级译码，第二级译码模式为SCL 8或SCL 16或SCL 32译码模式。
图7c为第三种可能的实现方式中的译码模式和数据流示意图。如图7c所示，第一级译码模式为SCL 4译码模式，第一级译码后筛选出p3个候选集进行第二级译码，第二级译码模式为SCL 8或SCL 16或SCL 32译码模式。
根据上述内容可知，针对不同的第一级译码模式，可能会存在两种或两种以上第二级译码模式。在一种可能的实现方式中，可以预先确定第二级译码模式，比如为SCL8译码模式(此时第一级译码模式可能为SC译码模式、SCL2译码模式或SCL4译码模式)，如此，译码单元可以直接采用SCL8译码模式进行译码。
下面以第一控制信号用于指示SC译码模式，第二控制信号用于指示SCL4译码模式(可参见图6所示意的极化码译码器的结构)为例，结合图7d具体描述两级译码的流程。如图7d所示，包括：
步骤700，从候选集集合中获取p1个候选集，p1小于或等于m。
此处，示例性地，m＝8。若候选集集合中尚未进行第一级译码的候选集大于或等于8个，则p1可以等于8，若候选集集合中尚未进行第一级译码的候选集小于8个，则p1等于候选集集合中尚未进行第一级译码的候选集的个数。
步骤701，从m个输入端输入p1个候选集。
步骤702，译码单元根据第一控制信号，配置输入端和路径之间的连接方式，并配置SC译码模式进行译码(参见图5a)。
步骤703，筛选出p3个候选集。
此处，译码单元中译码结果处理子单元根据p1个候选集对应的p1个路径的路径度量值，筛选出2(p3＝2)个候选集，比如，筛选出的候选集可以为输入端0的候选集0和输入端4的候选集4。
步骤704，译码单元根据第二控制信号配置输入端和路径之间的连接方式，并配置SCL4译码模式进行译码(参见图5b)。
此处，若步骤703中筛选出的两个候选集为输入端0的候选集0和输入端4的候选集4，则步骤704中，可以直接通过SCL4_En控制选择器1、选择器2、选择器3、选择器4、选择器5和选择器6处于第一状态，并进行SCL4译码；若步骤703中筛选出的两个候选集为输入端0的候选集0和输入端4的候选集4以外的其它参数，比如，输入端1的候选集1和输入端5的候选集5，则在步骤704中，译码单元需将候选集1和参数0交换位置、参数4和参数5交换位置，从而使得输入端0输入参数1、输入端4输入参数5，并通过SCL4_En控制选择器1、选择器2、选择器3、选择器4、选择器5和选择器6处于第一状态，进行SCL4译码。应理解，这里所描述的操作仅为基于图6所示意的极化码译码器而采取的方式，若极化码译码器设计为其它结构，则译码单元也可能无需执行交换位置的操作。
步骤705，候选集集合中是否还有尚未进行第一级译码的候选集，若是，则执行步骤700，若否，则执行步骤706。
需要说明的是，由于图6所示意出的极化码译码器仅具有8个输入端，因此执行上述一次流程仅能对8个候选集进行译码，若候选集为44个，则需要上述流程需要执行6次，其中，由于最后一次仅有4个候选集，则在第一级译码中，部分输入端输入为空，此时并不影响本申请实施例的执行，后续仍筛选出2个候选集进行第二级译码即可。也就是说，针对于44个候选集，极化译码器需循环执行6次上述步骤701至步骤704。
步骤706，根据筛选出的候选集的译码结果得到最终的译码结果。
此处，根据上述描述可知，44个候选集通过第一级译码后，共筛选出12个候选集进行第二级译码，如此，在步骤705中，可根据12个候选集的第二级译码结果得到最终的译码结果。
需要说明的是，上述仅示例性说明了一级译码方式和两级译码方式，本申请实施例中的极化码译码器也可以提供两级以上的译码方式，具体不做限定。
本申请实施例提供的极化码译码器并不局限于5G NR场景中，还可以应用于其它任何使用极化码做为信道编码的通信系统中，具体不做限定。
本申请实施例还提供一种译码方法，所述译码方法可以应用于上述实施例中所描述的极性码译码器中，所述译码方法包括：
接收第一控制信号；所述第一控制信号用于指示第一译码模式或第二译码模式；若所 述第一控制信号用于指示第一译码模式，则配置p1个输入端与p1个路径一一对应连接，并通过第一输入端将第一候选集输入到所述第一输入端对应连接的路径；以及，通过所述第一输入端对应连接的路径对所述第一候选集进行译码，所述第一输入端为p1个输入端中的任一输入端，p1为小于或等于m的整数；若所述第一控制信号用于指示所述第二译码模式，则配置第二输入端与w1个路径对应连接，并通过所述第二输入端将第二候选集输入到所述第二输入端对应连接的w1个路径；以及，通过所述第二输入端对应连接的w1个路径对所述第二候选集进行译码，所述第二输入端为p2个输入端中的任一输入端，p2为小于或等于m的整数，w1为整数且w1≤n。
进一步地，第一译码模式具体可以是指SC译码模式，第二译码模式具体可以是指SCL译码模式。
在一种可能的设计中，所述方法还包括：
从所述p1个候选集中选择出p3个候选集，或者，从所述p2个候选集中选择出p3个候选集；p3为小于p1或小于p2的整数；以及，接收第二控制信号，所述第二控制信号用于指示第三译码模式；根据所述第二控制信号配置第九输入端与w2个路径对应连接，并通过所述第九输入端将候选集输入到所述第九输入端对应连接的w2个路径；以及，通过所述第九输入端对应连接的w2个路径对第三候选集进行译码，所述第九输入端为p3个输入端中的任一输入端，w2为整数且w2≤n。进一步地，第三译码模式具体可以是指SCL译码模式，因此w2可以等于2 h2，h2为大于或等于1的整数。
本申请实施例还提供一种数据传输装置，该数据传输装置包括上述任一种设计中的极化码译码器。
图8为本发明实施方式中所提供的数据传输装置的结构示意图(例如接入点或基站、站点或者终端等通信装置，或者前述通信装置中的芯片等)。如下图8所示，数据传输装置800可以由总线801作一般性的总线体系结构来实现。根据数据传输装置800的具体应用和整体设计约束条件，总线801可以包括任意数量的互连总线和桥接。总线801将各种电路连接在一起，这些电路包括处理器802、存储介质803和总线接口804，其中，处理器可以包括上述图4、图5或图6中所描述的极化码译码器。可选的，数据传输装置800使用总线接口804将接收机前端处理单元805等经由总线801连接。接收机前端处理单元805可用于实现无线通信网络中物理层的信号处理功能，并通过天线807实现射频信号的发送和接收。用户接口806可以连接用户终端，例如：键盘、显示器、鼠标或者操纵杆等。总线801还可以连接各种其它电路，如定时源、外围设备、电压调节器或者功率管理电路等，这些电路是本领域所熟知的，因此不再详述。
可以替换的，数据传输装置800也可配置成通用处理系统，例如通称为芯片，该通用处理系统包括：提供处理器功能的一个或多个微处理器；以及提供存储介质803的至少一部分的外部存储器，所有这些都通过外部总线体系结构与其它支持电路连接在一起。
可替换的，数据传输装置800可以使用下述来实现：具有处理器802、总线接口804、用户接口806的ASIC(专用集成电路)；以及集成在单个芯片中的存储介质803的至少一部分，或者，数据传输装置800可以使用下述来实现：一个或多个FPGA(现场可编程门阵列)、PLD(可编程逻辑器件)、控制器、状态机、门逻辑、分立硬件部件、任何其它适合的电路、或者能够执行本发明通篇所描述的各种功能的电路的任意组合。
其中，处理器802负责管理总线和一般处理(包括执行存储在存储介质803上的软件)。 处理器802可以使用一个或多个通用处理器和/或专用处理器来实现。处理器的例子包括微处理器、微控制器、DSP处理器和能够执行软件的其它电路。应当将软件广义地解释为表示指令、数据或其任意组合，而不论是将其称作为软件、固件、中间件、微代码、硬件描述语言还是其它。
在下图中存储介质803被示为与处理器802分离，然而，本领域技术人员很容易明白，存储介质803或其任意部分可位于数据传输装置800之外。举例来说，存储介质803可以包括传输线、用数据调制的载波波形、和/或与无线节点分离开的计算机制品，这些介质均可以由处理器802通过总线接口804来访问。可替换地，存储介质803或其任意部分可以集成到处理器802中，例如，可以是高速缓存和/或通用寄存器。
处理器802中的极化码译码器可执行上述图7d所示意的流程，在此不再赘述。
可以替换的，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种极化码译码器，其特征在于，所述极化码译码器包括译码单元、与所述译码单元通信连接的控制单元；所述译码单元包括m个输入端和n个路径，所述m个输入端与所述n个路径选择性连接，m、n为整数，m≤n；
    所述控制单元，用于向所述译码单元发送第一控制信号，所述第一控制信号用于指示SC译码模式或SCL w1译码模式，w1＝2 h1，h1为大于或等于1的整数，w1≤n；
    所述译码单元，用于接收所述控制单元发送的第一控制信号，并根据所述第一控制信号执行如下操作：
    若所述第一控制信号用于指示SC译码模式，则配置p1个输入端与p1个路径一一对应连接，并通过第一输入端将第一候选集(candidate)输入到所述第一输入端对应连接的路径；以及，将所述第一输入端对应连接的路径配置为SC译码模式进行译码，所述第一输入端为p1个输入端中的任一输入端，p1为小于或等于m的整数；
    若所述第一控制信号用于指示SCL w1译码模式，则配置第二输入端与w1个路径对应连接，并通过所述第二输入端将第二候选集输入到所述第二输入端对应连接的w1个路径；以及，将所述第二输入端对应连接的w1个路径配置为SCL w1译码模式进行译码，所述第二输入端为p2个输入端中的任一输入端，p2为小于或等于m的整数。
  2. 根据权利要求1所述的极化码译码器，其特征在于，所述m个输入端与所述n个路径选择性连接，包括：
    所述m个输入端与所述n个路径通过多个选择器选择性连接。
  3. 根据权利要求2所述的极化码译码器，其特征在于，所述第一控制信号用于指示SC译码模式或SCL 2译码模式；
    所述m个输入端与所述n个路径通过多个选择器选择性连接，包括：
    第三输入端和第四输入端通过第一选择器与第一路径选择性连接，且所述第三输入端与第二路径连接；所述第三输入端和所述第四输入端为所述m个输入端中的两个输入端，第一选择器为所述多个选择器中的一个选择器，所述第一路径和所述第二路径为所述n个路径中的两个路径；
    其中，所述第一选择器处于第一状态时，所述第三输入端分别与所述第一路径、所述第二路径连接；所述第一选择器处于第二状态时，所述第三输入端与所述第二路径连接，所述第四输入端与所述第一路径连接。
  4. 根据权利要求2所述的极化码译码器，其特征在于，所述第一控制信号用于指示SC译码模式或SCL 4译码模式；
    所述m个输入端与所述n个路径通过多个选择器选择性连接，包括：
    第五输入端与第三路径连接，所述第五输入端和所述第六输入端通过第二选择器与第四路径选择性连接，所述第五输入端和所述第七输入端通过第三选择器与第五路径选择性连接，所述第五输入端和所述第八输入端通过第三选择器与第六路径选择性连接；所述第五输入端、所述第六输入端、所述第七输入端和所述第八输入端为所述m个输入端中的四个输入端，所述第二选择器、所述第三选择器和所述第四选择器为所述多个选择器中的三个选择器，所述第三路径、所述第四路径、所述第五路径和所述第六路径为所述n个路径中的四个路径；
    其中，所述第二选择器、所述第三选择器和所述第四选择器均处于第一状态时，第五输入端分别与第三路径、第四路径、第五路径、第六路径连接；所述第二选择器、所述第三选择器和所述第四选择器均处于第二状态时，第五输入端与第三路径连接，第六输入端与第四路径连接，第七输入端与第五路径连接，第八输入端与第六路径连接。
  5. 根据权利要求1所述的极化码译码器，其特征在于：
    所述译码单元，还用于从所述p1个候选集中选择出p3个候选集，或者，从所述p2个候选集中选择出p3个候选集；p3为小于p1或小于p2的整数；
    所述控制单元，还用于在所述译码单元选择出所述p3个候选集后，向所述译码单元发送第二控制信号，所述第二控制信号用于指示SCL w2译码模式，w2＝2 h2，h2为大于或等于1的整数；w2>w1；
    所述译码单元，还用于接收所述控制单元发送的第二控制信号，并根据所述第二控制信号配置第九输入端与w2个路径对应连接，并通过所述第九输入端将第三候选集输入到所述第九输入端对应连接的w2个路径；以及，将所述第九输入端对应连接的w2个路径配置为SCL w2译码模式进行译码，所述第九输入端为p3个输入端中的任一输入端。
  6. 根据权利要求5所述的极化码译码器，其特征在于，所述译码单元从所述p1个候选集中选择出p3个候选集，包括：所述译码单元根据所述p1个候选集对应的p1个路径的路径度量值，从所述p1个候选集中选择出p3个候选集；
    所述译码单元从所述p2个候选集中选择出p3个候选集，包括：所述译码单元根据所述p2个候选集对应的p2×w1路径的路径度量值，从所述p2个候选集中选择出p3个候选集。
  7. 根据权利要求5或6所述的极化码译码器，其特征在于，所述第一控制信号用于指示SC译码模式，所述第二控制信号用于指示SCL 8译码模式。
  8. 一种数据传输装置，其特征在于，所述数据传输装置包括权利要求1至权利要求7中任一项所述的极化码译码器。
  9. 一种译码方法，其特征在于，所述译码方法应用于极性码译码器，所述极性码译码器包括m个输入端和n个路径，所述m个输入端与所述n个路径选择性连接，m、n为整数，m≤n；所述译码方法包括：
    接收第一控制信号；所述第一控制信号用于指示第一译码模式或第二译码模式；
    若所述第一控制信号用于指示第一译码模式，则配置p1个输入端与p1个路径一一对应连接，并通过第一输入端将第一候选集输入到所述第一输入端对应连接的路径；以及，通过所述第一输入端对应连接的路径对所述第一候选集进行译码，所述第一输入端为p1个输入端中的任一输入端，p1为小于或等于m的整数；
    若所述第一控制信号用于指示所述第二译码模式，则配置第二输入端与w1个路径对应连接，并通过所述第二输入端将第二候选集输入到所述第二输入端对应连接的w1个路径；以及，通过所述第二输入端对应连接的w1个路径对所述第二候选集进行译码，所述第二输入端为p2个输入端中的任一输入端，p2为小于或等于m的整数，w1为大于1的整数且w1≤n。
  10. 根据权利要求9所述的译码方法，其特征在于，所述方法还包括：
    从所述p1个候选集中选择出p3个候选集，或者，从所述p2个候选集中选择出p3个候选集；p3为小于p1或小于p2的整数；
    接收第二控制信号，所述第二控制信号用于指示第三译码模式；
    根据所述第二控制信号配置第九输入端与w2个路径对应连接，并通过所述第九输入端将候选集输入到所述第九输入端对应连接的w2个路径；以及，通过所述第九输入端对应连接的w2个路径对第三候选集进行译码，所述第九输入端为p3个输入端中的任一输入端，w2为大于1的整数且w2≤n。
  11. 一种计算机可读存储介质，其特征在于，所述存储介质存储有指令，当所述指令在计算机上运行时，使得计算机实现执行上述权利要求9或10所述的方法。
  12. 一种计算机程序产品，其特征在于，所述计算机程序产品包含指令，当所述指令在计算机上运行时，使得计算机执行权利要求9或10所述的方法。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112994706A (zh) 2019-12-02 2021-06-18 深圳市中兴微电子技术有限公司 译码方法、装置、设备及存储介质
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184086A (zh) * 2011-05-11 2011-09-14 电子科技大学 一种Booth编码器及乘法器
CN106656212A (zh) * 2016-12-05 2017-05-10 东南大学 基于极化码的自适应连续消除译码方法及架构
CN106656213A (zh) * 2016-12-22 2017-05-10 东南大学 基于k段分解的低复杂度极化码折叠硬件构架的实现方法
CN107040262A (zh) * 2017-03-28 2017-08-11 北京航空航天大学 一种计算polar码SCL+ CRC译码的List预测值的方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9503126B2 (en) * 2012-07-11 2016-11-22 The Regents Of The University Of California ECC polar coding and list decoding methods and codecs
KR101496182B1 (ko) * 2013-12-16 2015-03-09 성균관대학교산학협력단 최소거리가 확장된 극 부호 생성 방법 및 장치
RU2571587C2 (ru) * 2014-04-10 2015-12-20 Самсунг Электроникс Ко., Лтд. Способ и устройство кодирования и декодирования данных в скрученном полярном коде
CN105281785B (zh) * 2015-10-22 2018-08-31 东南大学 一种列表连续消除极化码译码方法、装置
FR3050343B1 (fr) * 2016-04-15 2020-01-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Methode de decodage a inversion d'un code polaire
KR102621627B1 (ko) * 2016-06-01 2024-01-08 삼성전자주식회사 순환 중복 검사와 극 부호를 이용하는 부호화를 위한 장치 및 방법
US10361728B2 (en) * 2016-06-17 2019-07-23 Huawei Technologies Co., Ltd. Multiple-symbol combination based decoding for general polar codes
CN106487479B (zh) * 2016-09-27 2019-04-16 清华大学深圳研究生院 一种基于多位判决的极化码译码方法
CN107273088B (zh) * 2017-06-16 2020-04-24 山东科技大学 一种针对极化码的快速排序方法及装置
CN107359967B (zh) * 2017-07-17 2020-04-17 北京航空航天大学 一种基于极化码的降低pdcch盲检次数的盲检方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184086A (zh) * 2011-05-11 2011-09-14 电子科技大学 一种Booth编码器及乘法器
CN106656212A (zh) * 2016-12-05 2017-05-10 东南大学 基于极化码的自适应连续消除译码方法及架构
CN106656213A (zh) * 2016-12-22 2017-05-10 东南大学 基于k段分解的低复杂度极化码折叠硬件构架的实现方法
CN107040262A (zh) * 2017-03-28 2017-08-11 北京航空航天大学 一种计算polar码SCL+ CRC译码的List预测值的方法

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