WO2019128595A1 - 一种静电放电保护器件 - Google Patents

一种静电放电保护器件 Download PDF

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Publication number
WO2019128595A1
WO2019128595A1 PCT/CN2018/117585 CN2018117585W WO2019128595A1 WO 2019128595 A1 WO2019128595 A1 WO 2019128595A1 CN 2018117585 W CN2018117585 W CN 2018117585W WO 2019128595 A1 WO2019128595 A1 WO 2019128595A1
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electrostatic discharge
protection device
discharge protection
trench
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French (fr)
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汪广羊
孙俊
孙贵鹏
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00

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  • the present application relates to semiconductor design and fabrication processes, and in particular to an electrostatic discharge protection device.
  • CMOS technology As the level of integrated circuit manufacturing technology enters the deep sub-micron era of integrated circuit line width, the feature size of CMOS technology continues to shrink, the transistor's ability to withstand high voltage and high current is continuously reduced, and deep sub-micron CMOS integrated circuits are more susceptible to electrostatic shock. The failure causes the reliability of the product to decrease.
  • Electrostatic Discharge is a common phenomenon in the process of manufacturing, manufacturing, assembling, testing and transporting integrated circuit devices or chips.
  • the large current generated in a short period of time during electrostatic discharge causes fatal damage to the integrated circuit, which is an important problem causing failure in the production of integrated circuits.
  • the electrostatic discharge phenomenon (HBM) that occurs on the human body usually occurs within a few hundred nanoseconds, and the maximum current peak may reach several amps. In other modes, the electrostatic discharge occurs for a shorter period of time and the current is larger.
  • HBM electrostatic discharge phenomenon
  • Such a large current flows through the integrated circuit in a short period of time, and the power consumption will be severely exceeded by the maximum value that it can withstand, causing serious physical damage to the integrated circuit and causing its eventual failure.
  • the main purpose is to increase the electrostatic discharge withstand capability of the integrated circuit itself. For example, additional electrostatic protection devices or circuits are added to protect the internal circuits of the integrated circuit from electrostatic discharge damage, but the manufacturing cost is increased, which is not conducive to the improvement of device integration. .
  • an electrostatic discharge protection device including:
  • first gate region located in a peripheral region of the substrate and a first body region located around the first gate region, the first body region having a second type of doping
  • the first source region located within the first body region, the first source region having a second type of doping.
  • Figure 1 is a schematic cross-sectional view of a conventional electrostatic discharge protection device
  • FIG. 3 is a schematic cross-sectional view of an electrostatic discharge protection device in accordance with an embodiment of the present application.
  • FIG 4 is an equivalent circuit diagram of an electrostatic discharge protection device in accordance with an embodiment of the present application.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature. Thus, the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • Electrostatic Discharge is a common phenomenon in the process of manufacturing, manufacturing, assembling, testing and transporting integrated circuit devices or chips.
  • the large current generated in a short period of time during electrostatic discharge causes fatal damage to the integrated circuit, which is an important problem causing failure in the production of integrated circuits.
  • Double-diffused MOSFETs have strong current capability and their ESD capability has been neglected.
  • DMOS vertical double-diffused MOSFET
  • LDMOS lateral double-diffused MOSFET
  • the VDMOS transistor further includes a trench type double diffused transistor (TDMOS).
  • TDMOS trench type double diffused transistor
  • the source 101 and the drain 102 of the TDMOS transistor are respectively located on both sides of the semiconductor substrate, and generally the source 101 is located on the front side of the substrate.
  • the drain 102 is located on the back side of the substrate, and the gate 103 is formed in a trench extending between the source and the drain to form a vertical channel.
  • TDMOS transistors have less current limiting than conventional DMOS transistor structures, providing lower on-resistance values.
  • FIG. 2 is an equivalent circuit diagram of a conventional ESD protection device, showing the most fragile mode of the device's ESD protection. At this time, the source potential is raised, the DMOS is in the deep-off state, and the DMOS ESD protection capability.
  • an electrostatic discharge protection device including: a substrate having a first type of doping; a first gate region located in a peripheral region of the substrate and located at the a first body region around a gate region, the first body region having a second type of doping; and a first source region located within the first body region, the first source region having a second type of doping .
  • the electrostatic discharge protection device further includes: a second gate region located in an inner region of the substrate; and a second body region located around the second gate region, the second body region having a second type of doping; And a second source region in the second body region, the second source region having a first type of doping.
  • the depth of the second gate region is less than or equal to the depth of the first gate region.
  • the substrate includes a heavily doped body layer and a lightly doped epitaxial layer over the body layer, the first gate region, the first body region, and the first source region being located at the epitaxial layer In the layer.
  • the first gate region is formed in a first trench located within the substrate.
  • the second gate region is formed in a second trench located within the substrate.
  • the first trench is formed between adjacent first body regions, and the depth of the first body region is smaller than a depth of the first trench.
  • the depth of the first source region is less than the depth of the first trench.
  • the depth of the second trench is less than or equal to the depth of the first trench.
  • the inner region of the substrate is formed with a DMOS device.
  • the electrostatic discharge protection device provided by the present application can avoid uneven opening in the peripheral region, eliminate weak links, thereby improving the electrostatic discharge protection capability of the device, and has flexible structure and can realize protection under different voltages.
  • the application provides an electrostatic discharge protection device including a substrate having a first type of doping; a first gate region located in a peripheral region of the substrate; and a first body region located around the first gate region The first body region has a second type of doping; and a first source region located within the first body region, the first source region having a second type of doping.
  • the electrostatic discharge protection device suppresses the uneven opening of the NPN or the PNP by changing the doping type of the source region of the peripheral region, thereby eliminating the weak link that is prone to failure, thereby improving the electrostatic protection capability of the device.
  • the first type of doping is N-type doping
  • the second type of doping is P-type doping
  • the first type of doping is P-type doping
  • the second type of doping is N-type doping.
  • the main doping element of the P-type doping is one or more of trivalent dopants, such as boron
  • the main doping element of the N-type doping is one or more of pentavalent dopants. For example, phosphorus or arsenic.
  • the structure of the electrostatic discharge protection device will be described in detail with the first type doping being N-type doping and the second type doping being P-type doping.
  • the electrostatic discharge protection device includes a substrate having an N-type doping, the substrate including a heavily doped body layer 301 and a lightly doped epitaxial layer 302 over the body layer 301.
  • the substrate may comprise a semiconductor element, such as silicon or silicon germanium (SiGe) of single crystal, polycrystalline or amorphous structure, and may also comprise a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, arsenic. Indium, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductor or a combination thereof; may also be silicon-on-insulator (SOI) or the like. Further, the substrate may further include other materials such as a multilayer structure of an epitaxial layer or a buried oxide layer. Although a few examples of materials from which a substrate can be formed are described herein, any material that can be used as a semiconductor substrate falls within the scope of the present application.
  • a semiconductor element such as silicon or silicon germanium (SiGe) of single crystal, polycrystalline or amorphous structure
  • a mixed semiconductor structure such as silicon carbide, indium antimonide, lead telluride, arsenic. Indium, indium phos
  • the body layer 301 in this embodiment may be a silicon substrate, and the epitaxial layer 302 may be a lightly doped epitaxial layer grown on the body layer 301 by a process such as CVD (Chemical Vapor Deposition).
  • the thickness of the epitaxial layer 302 may be According to the specific application requirements of the device, the structure can be flexibly adjusted.
  • the body layer 301 has an N-type heavily doped as a common drain region of the device; the epitaxial layer 302 has an N-type light doping.
  • the doping concentrations of the specific body layer 301 and the epitaxial layer 302 are the same as those in the conventional art, and will not be further described herein.
  • a first gate region 303 is formed in a peripheral region of the substrate, and a first body region 304 is disposed around the first gate region 303, and a first source region 305 is formed in the first body region 304.
  • the first body region 304 has a second type of doping
  • the first source region 305 has a second type of doping.
  • the first body region 304 and the first source region 305 each have a P-type doping.
  • the first gate region 303 is formed in a first trench 306 located within the substrate, the first trench 306 having a depth less than a thickness of the epitaxial layer 302.
  • the epitaxial layer 302 may be etched first to form the first trench 306; after the first trench 306 is formed, a gate dielectric may be formed on the inner wall of the first trench 306 by thermal oxidation or CVD, PECVD, or the like. a layer, wherein the gate dielectric layer material may be one or any combination of SrTiO 3 , HfO 2 , ZrO 2 , silicon oxide; finally filling the gate region material in the first trench 306, the gate filled in this embodiment
  • the material of the zone is polysilicon.
  • the first trench 306 is formed between adjacent first body regions 304 having a depth greater than the depth of the first body region 304.
  • the first body region has a P-type doping.
  • the position of the first body region 304 is first defined by a photolithography process, followed by implanting P-type dopant ions around the first gate region 303 using an ion implantation process to form the first body region 304.
  • the P-type ions implanted therein may be boron ions
  • the dose may be 1.0E13/cm 2 -1.0E15/cm 2
  • the energy may be 50KeV-120KeV
  • ion activation may be performed
  • the ion activation temperature may be 800 degrees to 1000 degrees.
  • the ion activation time can be from 20 minutes to 60 minutes.
  • a first source region 305 is formed in the first body region 304, the first source region 305 having a P-type heavily doped.
  • a P-type ion may be implanted into the substrate by an ion implantation process to form the first source region 305.
  • the P-type ions implanted therein may be boron ions, and the implantation dose may be 1.0E15/cm 2 -1.0E16/cm 2 , and the energy may be 50KeV-120KeV.
  • the P-doped first source region 305 and the N-doped substrate form a diode, as shown in FIG. 4, so that even if the electric field strength between the deep first gate region 303 and the drain region is too high or is disturbed by the outside, a source region doped with N-type, a P-doped body region, and an N-type cannot be formed.
  • the uneven opening of the NPN type parasitic transistor formed by the doped substrate is not limited to the doping ions of the first source region 305 of the peripheral region from N to P.
  • the doping ions of the first source region 305 of the peripheral region are P-type.
  • the N-type the uneven opening of the PNP formed due to the excessive electric field strength between the first gate region 303 and the drain region can be avoided, thereby eliminating the weak link that is prone to failure.
  • a plurality of DMOS devices are further formed in the inner region of the substrate inside the peripheral region, specifically including: a second gate region 307, and a second body located around the second gate region 307.
  • a second source region 309 is formed in the second body region 308.
  • the depth of the second gate region 307 is smaller than the depth of the first gate region 303.
  • the depth of the second gate region 307 may also be equal to the depth of the first gate region 303, and the structure is flexible, and protection under different voltages can be realized.
  • the second body region 308 Since the bottom of the second gate region 307 located in the inner region is not a location susceptible to failure, the second body region 308 has a second type of doping, and the second source region 309 has a first type of doping. In this embodiment, the second body region 308 has a P-type doping, and the second source region 309 has an N-type doping.
  • the second gate region 307 is formed in a second trench 310 located within the substrate.
  • the depth of the second trench 310 is smaller than the depth of the first trench 306.
  • the depth of the second trench 310 may also be equal to the depth of the first trench 306.
  • the second trench 310 may be formed in the same process as the first trench 306.
  • a second body region 308 is formed around the second gate region 307, the second body region having a P-type doping.
  • the second body region 308 may be formed in the same process as the first body region 304, and the doping concentration may be the same as that of the first body region 304.
  • a second source region 309 is formed in the second body region 308, the second source region 309 having an N-type heavily doped.
  • An N-type dopant ion may be implanted into the substrate using an ion implantation process to form a second source region 309.
  • the N-type ions implanted therein may be phosphorus or arsenic, and the dose may be 1.0E15/cm 2 -1.0E16/cm 2 and the energy may be 50KeV-120KeV.
  • the electrostatic discharge protection device provided by the present application suppresses the uneven opening of the NPN or the PNP by changing the doping type of the source region in the peripheral region, thereby eliminating the weak link which is prone to failure, thereby improving the electrostatic protection capability of the device.

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Abstract

提供一种静电放电保护器件，包括：基底，基底具有第一类型掺杂；位于基底的外围区域中的第一栅区（303）以及位于第一栅区（303）周围的第一体区（304），第一体区（304）具有第二类型掺杂；以及位于第一体区（304）内的第一源区（305），第一源区（305）具有第二类型掺杂。

Description

一种静电放电保护器件 技术领域
本申请涉及半导体设计与制造工艺，具体而言涉及一种静电放电保护器件。
背景技术
随着集成电路制造工艺水平进入集成电路线宽的深亚微米时代，CMOS工艺特征尺寸不断缩小，晶体管对于高电压和大电流的承受能力不断降低，深亚微米CMOS集成电路更容易遭受到静电冲击而失效，从而造成产品的可靠性下降。
静电放电(Electrostatic Discharge，ESD)是集成电路器件或芯片在制造、生产、组装、测试及运送等过程中产生的一种常见现象。静电放电时会在短时间内产生的大电流，对集成电路产生致命的损伤，是集成电路生产应用中造成失效的重要问题。例如，对于发生在人体上的静电放电现象(HBM)，通常发生在几百个纳秒内，最大的电流峰值可能达到几个安培，其它模式静电放电发生的时间更短，电流也更大。如此大的电流在短时间内通过集成电路，产生的功耗会严重超过其所能承受的最大值，从而对集成电路产生严重的物理损伤并导致其最终失效。
为了解决该问题，在实际应用中主要从环境和电路本身两方面来解决。环境方面，主要是减少静电的产生和及时消除静电，例如，应用不易产生静电的材料、增加环境湿度、操作人员和设备接地等。电路方面，主要是增加集成电路本身的静电放电耐受能力，例如增加额外的静电保护器件或者电路来保护集成电路内部电路不被静电放电损害，但会增加制作成本，不利于器 件集成度的提高。
因此，需要对目前的所述ESD器件结构作出改进，有效避免静电放电所造成的集成电路的失效。
发明内容
本申请为了克服目前存在的至少一个问题，提供了一种静电放电保护器件，包括：
基底，所述基底具有第一类型掺杂；
位于所述基底的外围区域中的第一栅区以及位于所述第一栅区周围的第一体区，所述第一体区具有第二类型掺杂；以及
位于所述第一体区内的第一源区，所述第一源区具有第二类型掺杂。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为传统的静电放电保护器件的示意性剖面图；
图2为传统的静电放电保护器件的等效电路图；
图3为根据本申请一实施例的静电放电保护器件的示意性剖面图；
图4为根据本申请一实施例的静电放电保护器件的等效电路图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的 理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数 形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
静电放电(Electrostatic Discharge，ESD)是集成电路器件或芯片在制造、生产、组装、测试及运送等过程中产生的一种常见现象。静电放电时会在短时间内产生的大电流，对集成电路产生致命的损伤，是集成电路生产应用中造成失效的重要问题。
双扩散金属氧化物半导体场效应管(double-diffused MOSFET，DMOS)本身电流能力强，其ESD能力一直被忽略。DMOS主要有两种类型，即垂直双扩散金属氧化物半导体场效应管(vertical double-diffused MOSFET，VDMOS)和横向双扩散金属氧化物半导体场效应管(lateral double-diffused MOSFET，LDMOS)。VDMOS晶体管又包括沟槽型双扩散晶体管(TDMOS)，具体地，如图1所示，TDMOS晶体管的源极101和漏极102分别位于半导体衬底的两面，通常其源极101位于衬底正面，漏极102位于衬底背面，而栅极103形成于在源和漏之间延伸的沟槽中，以形成垂直的沟道。TDMOS晶体管相比普通的DMOS晶体管结构对电流的限制更少，从而提供了较低的导通电阻值。
采用DMOS作为静电保护器件时，其外围区域易发生失效。申请人经研究发现，失效的原因如下：一般来说，考虑到外围可靠性的原因，外围区域DMOS晶体管的沟槽都会做的比内部区域深，此处电场强度在整个器件中最强。图2为传统的静电放电保护器件的等效电路图，其中示出了器件的静电放电保护能力最脆弱的模式，此时源极电位抬起，DMOS处于深度关断状态，DMOS的静电放电保护能力被限制在漏极和栅极之间，使得此处电场强度变高，而又由于外围区域DMOS晶体管的沟槽处电场强度在整个器件中最强，就进一步导致此处电场强度过高，造成NPN的不均匀开启，从而在图1圆圈 所示的位置处(即图2所示的薄弱位置处)发生失效。除此之外，即使外围DMOS晶体管与内部DMOS晶体管的栅区沟槽深度相等，外界条件的突变也会引起该位置处NPN的不均匀开启而造成失效。
为了解决上述至少一个技术问题，本申请提出一种静电放电保护器件，包括：基底，所述基底具有第一类型掺杂；位于所述基底的外围区域中的第一栅区以及位于所述第一栅区周围的第一体区，所述第一体区具有第二类型掺杂；以及位于所述第一体区内的第一源区，所述第一源区具有第二类型掺杂。
所述静电放电保护器件还包括：位于所述基底的内部区域中的第二栅区以及位于所述第二栅区周围的第二体区，所述第二体区具有第二类型掺杂；以及位于所述第二体区中的第二源区，所述第二源区具有第一类型掺杂。所述第二栅区的深度小于或等于所述第一栅区的深度。
所述基底包括重掺杂的本体层和位于所述本体层之上的轻掺杂的外延层，所述第一栅区、所述第一体区和所述第一源区位于所述外延层中。
所述第一栅区形成于位于所述基底内的第一沟槽中。所述第二栅区形成于位于所述基底内的第二沟槽中。所述第一沟槽形成于相邻的所述第一体区之间，所述第一体区的深度小于所述第一沟槽的深度。所述第一源区的深度小于所述第一沟槽的深度。所述第二沟槽的深度小于或等于所述第一沟槽的深度。
所述基底的内部区域形成有DMOS器件。
本申请提供的静电放电保护器件，能够避免外围区域发生不均匀开启，消除了薄弱环节，从而提高了器件的静电放电保护能力，并且结构灵活，可以实现不同电压下的保护。
[示例性实施例]
下面参考图3和图4对本申请一实施例的静电放电保护器件的结构进行详细说明。
本申请提供静电放电保护器件，包括基底，所述基底具有第一类型掺杂；位于所述基底的外围区域中的第一栅区以及位于所述第一栅区周围的第一体区，所述第一体区具有第二类型掺杂；以及位于所述第一体区内的第一源区，所述第一源区具有第二类型掺杂。
所述静电放电保护器件通过改变外围区域源区的掺杂类型，抑制NPN或PNP的不均匀开启，消除了易发生失效的薄弱环节，从而提高了器件的静电保护能力。
在本实施例中，所述第一类型掺杂为N型掺杂，所述第二类型掺杂为P型掺杂；在另一实施例中，所述第一类型掺杂为P型掺杂，所述第二类型掺杂为N型掺杂。其中，P型掺杂的主要掺杂元素为三价掺杂剂中的一种或多种，例如硼，N型掺杂的主要掺杂元素为五价掺杂剂中的一种或多种，例如磷或砷。
下面，结合图3，以所述第一类型掺杂为N型掺杂，所述第二类型掺杂为P型掺杂来详细介绍所述静电放电保护器件的结构。
具体地，所述静电放电保护器件包括具有N型掺杂的基底，所述基底包括重掺杂的本体层301和位于所述本体层301之上的轻掺杂的外延层302。
其中，所述基底可以包括半导体元素，例如单晶、多晶或非晶结构的硅或硅锗(SiGe)，也可以包括混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合；也可以是绝缘体上硅(SOI)等。此外，所述基底还可以包括其它的材料，例如外延层或埋氧层的多层结构。虽然在此描述了可以形成基底的材料的几个示例，但是可以作为半导体基底的任何材料均落入本申请的范围内。
本实施例中的本体层301可为硅衬底，外延层302可为采用CVD(化学气相沉积)等工艺在本体层301上一次性生长的轻掺杂的外延层，外延层302的厚度可按照器件的具体应用要求确定，结构可以灵活调整。
所述本体层301具有N型重掺杂，其作为器件的共同漏区；所述外延层302具有N型轻掺杂。具体的本体层301和外延层302的掺杂浓度与传统技 术中的掺杂浓度相同，在此不再一一赘述。
在所述基底的外围区域中形成有第一栅区303，以及位于所述第一栅区303周围的第一体区304，所述第一体区304中形成有第一源区305。其中，所述第一体区304具有第二类型掺杂，所述第一源区305具有第二类型掺杂。本实施例中，所述第一体区304和所述第一源区305均具有P型掺杂。
作为示例，所述第一栅区303形成于位于所述基底内的第一沟槽306中，所述第一沟槽306的深度小于所述外延层302的厚度。示例性地，可首先刻蚀所述外延层302以形成第一沟槽306；形成第一沟槽306之后，可采用热氧化或CVD、PECVD等方法在第一沟槽306的内壁形成栅介质层，其中，栅介质层材料可为SrTiO 3、HfO 2、ZrO 2、氧化硅中的一种或任意组合；最后在第一沟槽306内填充栅区材料，本实施例中所填充的栅区材料为多晶硅。
第一沟槽306形成于相邻的第一体区304之间，其深度大于第一体区304的深度。所述第一体区具有P型掺杂。示例性地，首先通过光刻工艺定义出第一体区304的位置，接着采用离子注入工艺在第一栅区303周围注入P型掺杂离子，以形成所述第一体区304。其中注入的P型离子可以为硼离子，剂量可以为1.0E13/cm 2-1.0E15/cm 2，能量可以为50KeV-120KeV，然后进行离子激活，离子激活的温度可以为800度～1000度，离子激活的时间可以为20分钟-60分钟。
在第一体区304中形成有第一源区305，所述第一源区305具有P型重掺杂。本实施例中，可采用离子注入工艺在衬底中注入P型离子，以形成所述第一源区305。其中注入的P型离子可以为硼离子，注入的剂量可以为1.0E15/cm 2-1.0E16/cm 2，能量可以为50KeV-120KeV。
在本实施例中，通过将外围区域的第一源区305的掺杂离子由N型改变为P型，P型掺杂的第一源区305与N型掺杂的基底构成二极管，如图4所示，因而即使较深的第一栅区303和漏区之间电场强度过高或受到外界干扰，也无法形成由N型掺杂的源区、P型掺杂的体区和N型掺杂的基底所构成的的NPN型寄生晶体管的不均匀开启。
在其他实施例中，当所述第一类型掺杂为P型掺杂，所述第二类型掺杂为N型掺杂时，将外围区域的第一源区305的掺杂离子由P型改变为N型，则可以避免由于第一栅区303和漏区之间电场强度过高而形成的PNP的不均匀开启，从而消除了易发生失效的薄弱环节。
在本实施例中，在所述基底位于所述外围区域内侧的内部区域中还形成有若干DMOS器件，具体包括：第二栅区307，以及位于所述第二栅区307周围的第二体区308，所述第二体区308中形成有第二源区309。本实施例中，所述第二栅区307的深度小于所述第一栅区303的深度。在其他实施例中，所述第二栅区307的深度也可以与所述第一栅区303的深度相等，结构灵活，可以实现不同电压下的保护。
由于位于内部区域的所述第二栅区307的底部并非易发生失效的位置，因而所述第二体区308具有第二类型掺杂，所述第二源区309具有第一类型掺杂。本实施例中，所述第二体区308具有P型掺杂，所述第二源区309具有N型掺杂。
作为示例，所述第二栅区307形成于位于所述基底内的第二沟槽310中。在本实施例中，所述第二沟槽310的深度小于所述第一沟槽306的深度。在其他实施例中，所述第二沟槽310的深度也可以与所述第一沟槽306的深度相等。所述第二沟槽310可与第一沟槽306在同一道工序中形成。
第二体区308形成于第二栅区307周围，所述第二体区具有P型掺杂。所述第二体区308可与第一体区304在同一道工序中形成，其掺杂浓度也可与第一体区304相同。
在第二体区308中形成有第二源区309，所述第二源区309具有N型重掺杂。可采用离子注入工艺在衬底中注入N型掺杂离子，以形成第二源区309。其中注入的N型离子可以为磷或砷，注入的剂量可以为1.0E15/cm 2-1.0E16/cm 2，能量可以为50KeV-120KeV。
本申请所提供的静电放电保护器件通过改变外围区域源区的掺杂类型， 抑制NPN或PNP的不均匀开启，消除了易发生失效的薄弱环节，从而提高了器件的静电保护能力。
本申请已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本申请限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本申请并不局限于上述实施例，根据本申请的教导还可以做出更多种的变型和修改，这些变型和修改均落在本申请所要求保护的范围以内。本申请的保护范围由附属的权利要求书及其等效范围所界定。

Claims (20)

  1. 一种静电放电保护器件，包括：
    基底，所述基底具有第一类型掺杂；
    位于所述基底的外围区域中的第一栅区以及位于所述第一栅区周围的第一体区，所述第一体区具有第二类型掺杂；以及
    位于所述第一体区内的第一源区，所述第一源区具有第二类型掺杂。
  2. 根据权利要求1所述的静电放电保护器件，其中，所述静电放电保护器件还包括：
    位于所述基底的内部区域中的第二栅区以及位于所述第二栅区周围的第二体区，所述第二体区具有第二类型掺杂；以及
    位于所述第二体区中的第二源区，所述第二源区具有第一类型掺杂。
  3. 根据权利要求1所述的静电放电保护器件，其中，所述第一源区具有的所述第二类型掺杂为重掺杂。
  4. 根据权利要求3所述的静电放电保护器件，其中，所述第一源区的第二类型掺杂的剂量为1.0E15/cm 2-1.0E16/cm 2。
  5. 根据权利要求2所述的静电放电保护器件，其中，所述第二栅区的深度小于或等于所述第一栅区的深度。
  6. 根据权利要求1所述的静电放电保护器件，其中，所述基底包括重掺杂的本体层和位于所述本体层之上的轻掺杂的外延层，所述第一栅区、所述第一体区和所述第一源区位于所述外延层中。
  7. 根据权利要求6所述的静电放电保护器件，其中，所述基底的外围区域形成有第一沟槽，所述第一栅区形成于所述第一沟槽中，所述第一沟槽的深度小于所述外延层的厚度。
  8. 根据权利要求2所述的静电放电保护器件，其中，所述基底的外围区域形成有第一沟槽，所述第一栅区形成于所述第一沟槽中，所述基底的内部区域形成有第二沟槽，所述第二栅区形成于所述第二沟槽中。
  9. 根据权利要求8所述的静电放电保护器件，其中，所述第一沟槽形成于相邻的所述第一体区之间，所述第一体区的深度小于所述第一沟槽的深度。
  10. 根据权利要求8所述的静电放电保护器件，其中，所述第一源区的深度小于所述第一沟槽的深度。
  11. 根据权利要求8所述的静电放电保护器件，其中，所述第二沟槽的深度小于或等于所述第一沟槽的深度。
  12. 根据权利要求2所述的静电放电保护器件，其中，所述基底的内部区域形成有DMOS器件。
  13. 根据权利要求8所述的静电放电保护器件，其中，所述第一沟槽内壁形成有栅介质层，所述第一栅区的栅区材料填充于所述第一沟槽内。
  14. 根据权利要求13所述的静电放电保护器件，其中，所述栅区材料为多晶硅。
  15. 根据权利要求13所述的静电放电保护器件，其中，所述栅介质层的材料包括氧化硅。
  16. 根据权利要求1所述的静电放电保护器件，其中，所述第一体区的第二类型掺杂的剂量为1.0E13/cm 2-1.0E15/cm 2。
  17. 根据权利要求2所述的静电放电保护器件，其中，所述第二体区与所述第一体区的掺杂浓度相同。
  18. 根据权利要求2所述的静电放电保护器件，其中，所述第二源区具有的所述第一类型掺杂为重掺杂。
  19. 根据权利要求2所述的静电放电保护器件，其中，所述第二源区的第一类型掺杂的剂量为1.0E15/cm 2-1.0E16/cm 2。
  20. 根据权利要求2所述的静电放电保护器件，其中，所述基底包括半导体元素。
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US20140167218A1 (en) * 2012-12-19 2014-06-19 Shekar Mallikarjunaswamy Circuit configuration and manufacturing processes for vertical transient voltage suppressor (tvs) and emi filter
US20140363930A1 (en) * 2006-11-30 2014-12-11 Madhur Bobde Latch-up free vertical tvs diode array structure using trench isolation
CN106960841A (zh) * 2016-01-12 2017-07-18 联华电子股份有限公司 高压晶体管

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140363930A1 (en) * 2006-11-30 2014-12-11 Madhur Bobde Latch-up free vertical tvs diode array structure using trench isolation
CN103094272A (zh) * 2011-11-01 2013-05-08 上海华虹Nec电子有限公司 用于静电保护的沟槽型绝缘栅场效应管结构
US20140167218A1 (en) * 2012-12-19 2014-06-19 Shekar Mallikarjunaswamy Circuit configuration and manufacturing processes for vertical transient voltage suppressor (tvs) and emi filter
CN106960841A (zh) * 2016-01-12 2017-07-18 联华电子股份有限公司 高压晶体管

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