WO2019114429A1 - 像素驱动电路、像素电路和显示装置及其驱动方法 - Google Patents

像素驱动电路、像素电路和显示装置及其驱动方法 Download PDF

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Publication number
WO2019114429A1
WO2019114429A1 PCT/CN2018/112006 CN2018112006W WO2019114429A1 WO 2019114429 A1 WO2019114429 A1 WO 2019114429A1 CN 2018112006 W CN2018112006 W CN 2018112006W WO 2019114429 A1 WO2019114429 A1 WO 2019114429A1
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Prior art keywords
transistor
voltage
coupled
electrode
control
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PCT/CN2018/112006
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English (en)
French (fr)
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殷新社
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京东方科技集团股份有限公司
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Priority to US16/345,146 priority Critical patent/US11282451B2/en
Priority to EP18867321.4A priority patent/EP3726518A4/en
Publication of WO2019114429A1 publication Critical patent/WO2019114429A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an organic light emitting diode (OLED) pixel driving circuit and a driving method thereof, a pixel circuit, a display substrate, and a display device and a driving method thereof.
  • OLED organic light emitting diode
  • the magnitude of the current between the source and the drain of the driving transistor is controlled by changing the gate voltage of the driving transistor that directly drives the OLED to emit light to achieve a change in the luminance of the light.
  • the threshold voltage Vth of the amorphous silicon thin film transistor the Thin Film Transistor of the thin film transistor, TFT for short
  • the low temperature polysilicon and the oxide semiconductor TFT device differs. That is to say, there is a large difference in the threshold voltage Vth of the driving transistors in different pixel circuits. This results in two adjacent pixel circuits, even if the input luminance data is the same, but the display brightness can be seen by the human eye, that is, the brightness unevenness in a small range similar to the hourglass phenomenon.
  • the OLED is driven by current to emit light. The greater the drive current, the brighter the illumination. If the light-emitting diodes in the pixel circuit powered by the same power supply line ELVDD are illuminated, then the current at the power supply line ELVDD is the maximum current at the beginning. Then every time a pixel circuit is passed, the current will decrease. Thus, a voltage drop is generated on the power supply line ELVDD, that is, the supply voltage of the first row of pixel circuits and the supply voltage of the last row of pixel circuits are relatively large. This causes the brightness of the display to gradually become brighter or darker even if the same brightness data is input. This is called the IR drop of ELVDD.
  • the embodiments described herein provide a pixel driving circuit and a driving method thereof, a display substrate, and a display device and a driving method thereof.
  • a pixel driving circuit includes a reset circuit, a compensation and data writing circuit, a driving transistor, and an emission control circuit.
  • a reset circuit coupled to the first control terminal and the control electrode and the second electrode of the driving transistor, and configured to control the driving transistor according to the first control signal from the first control terminal and the third control signal from the third control terminal The voltage of the pole is reset.
  • the compensation and data writing circuit is coupled to the data line, the first control terminal, the second control terminal, the control electrode of the driving transistor, and the first voltage terminal, and is configured to receive the reference signal from the data line according to the first control signal And receiving a data signal from the data line according to the second control signal from the second control terminal, and applying a compensation voltage to the control electrode of the driving transistor according to the reference signal, the data signal, and the voltage of the first voltage terminal.
  • a control electrode of the driving transistor is coupled to the compensation and data writing circuit, the first electrode is coupled to the first voltage terminal, and the second electrode is coupled to the light emitting control circuit.
  • the illumination control circuit is coupled to the light emitting device and the third control terminal, and is configured to control the illumination device to emit light according to the third control signal.
  • the reset circuit includes a first transistor.
  • the first transistor of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the gate of the driving transistor.
  • the compensation and data write circuit includes a second transistor, a third transistor, a first capacitor, and a second capacitor.
  • the control electrode of the second transistor is coupled to the first control terminal, the first electrode of the second transistor is coupled to the data line, and the second electrode of the second transistor is coupled to the first end of the first capacitor and the first end of the second capacitor.
  • the control electrode of the third transistor is coupled to the second control terminal, the first electrode of the third transistor is coupled to the data line, and the second electrode of the third transistor is coupled to the first terminal of the second capacitor.
  • the second end of the first capacitor is coupled to the control electrode of the driving transistor.
  • the second end of the second capacitor is coupled to the first voltage end.
  • the illumination control circuit includes a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the third control terminal, the first electrode of the fourth transistor is coupled to the light emitting device, and the second electrode of the fourth transistor is coupled to the second electrode of the driving transistor.
  • a reference signal is provided through a data line during a blanking interval.
  • the voltage of the gate of the driving transistor is reset to be smaller than a difference between the voltage of the first voltage terminal and the absolute value of the threshold voltage of the driving transistor.
  • a pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor.
  • the control electrode of the driving transistor is coupled to the second electrode of the first transistor and the second terminal of the first capacitor, the first electrode of the driving transistor is coupled to the first voltage terminal and the second terminal of the second capacitor, and the second electrode of the driving transistor The first pole of the first transistor and the second pole of the fourth transistor are coupled.
  • the control electrode of the first transistor is coupled to the first control terminal.
  • the control electrode of the second transistor is coupled to the first control terminal, the first electrode of the second transistor is coupled to the data line, and the second electrode of the second transistor is coupled to the first end of the first capacitor and the first end of the second capacitor.
  • the control electrode of the third transistor is coupled to the second control terminal, the first electrode of the third transistor is coupled to the data line, and the second electrode of the third transistor is coupled to the first terminal of the second capacitor.
  • the control electrode of the fourth transistor is coupled to the third control terminal, and the first electrode of the fourth transistor is coupled to the light emitting device.
  • the data lines are configured to receive reference signals and data signals at different time periods.
  • the current flowing through the driving transistor when the light emitting device emits light is expressed as:
  • I represents the current flowing through the driving transistor
  • K represents the current constant associated with the driving transistor
  • C1 represents the capacitance value of the first capacitor
  • C2 represents the capacitance value of the second capacitor
  • C3 represents the parasitic capacitance value of the driving transistor
  • Vdata represents The voltage value of the data signal from the data line
  • Vref represents the voltage value of the reference signal from the data line.
  • the driving transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor are P-type transistors.
  • a pixel circuit comprising the pixel driving circuit and the light emitting device according to the first or second aspect of the present disclosure as described above.
  • the pixel driving circuit is coupled to one end of the light emitting device and configured to drive the light emitting device to emit light.
  • the other end of the light emitting device is connected to the second voltage terminal.
  • the light emitting device includes an organic light emitting diode.
  • a display substrate including a plurality of gate lines and a plurality of data lines, and a plurality of pixel circuits according to the third aspect of the present disclosure as described above arranged in an array .
  • each of the gate lines is connected to a second control terminal of the corresponding pixel circuit.
  • a display device comprising the display substrate according to the fourth aspect of the present disclosure as described above.
  • a driving method for driving the pixel driving circuit according to the second aspect of the present disclosure as described above.
  • a reference signal is input to the data line, and a first compensation voltage associated with the voltage of the first voltage terminal, the threshold voltage of the driving transistor, and the reference signal is generated in the compensation and data writing circuit.
  • Inputting a data signal to the data line inputting a second voltage to the second control terminal, and inputting a first voltage to the first control terminal to generate a third voltage and data signal associated with the first voltage terminal in the compensation and data writing circuit Voltage.
  • the second voltage is input to the third control terminal and the first voltage is input to the second control terminal, thereby driving the light emitting device to emit light based on the voltage of the first voltage terminal, the first compensation voltage, and the third voltage.
  • in the step of inputting a reference signal to the data line, and generating a first compensation voltage in the compensation and data writing circuit inputting the reference signal to the data line to the first control terminal and the third control terminal A second voltage is input to reset the voltage of the gate of the drive transistor. Next, a second voltage is input to the first control terminal, and a first voltage is input to the third control terminal to generate a first compensation voltage in the compensation and data writing circuit.
  • a reference signal is input to the data line and a first compensation voltage is generated in the compensation and data writing circuit.
  • the voltage of the gate of the driving transistor is reset to be smaller than a difference between the voltage of the first voltage terminal and the absolute value of the threshold voltage of the driving transistor.
  • a driving method for driving the display device for the fifth aspect of the present disclosure as described above.
  • the reference signals are simultaneously input to the data lines of the pixel circuits of all the rows.
  • the corresponding data signals are sequentially input to the data lines of the pixel circuits of each row.
  • the light-emitting devices of the pixel circuits of all the rows are simultaneously illuminated.
  • the light emitting device is driven to emit light for less than half of the time of scanning one frame of image.
  • the time to scan one frame of image includes three distinct phases: a blanking phase, a data writing phase, and a lighting phase.
  • a blanking phase reference signals are simultaneously input to the data lines of the pixel circuits of all rows.
  • the data writing phase the corresponding data signals are sequentially input to the data lines of the pixel circuits of each row.
  • the light-emitting phase the light-emitting devices of the pixel circuits of all the rows are simultaneously illuminated.
  • FIG. 1 is a schematic block diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 is an example circuit diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • Figure 3 is a timing diagram of signals for the pixel circuit shown in Figure 2;
  • FIG. 4 is an equivalent working circuit diagram of the pixel driving circuit in the pixel circuit shown in FIG. 2 in the second stage;
  • FIG. 5 is an equivalent working circuit diagram of the pixel driving circuit in the pixel circuit shown in FIG. 2 in the third stage;
  • FIG. 6 is an equivalent working circuit diagram of the pixel circuit shown in FIG. 2 in the fourth stage
  • FIG. 7 is a schematic flowchart of a driving method of driving a pixel driving circuit in a pixel circuit as shown in FIG. 1 or FIG. 2 according to an embodiment of the present disclosure
  • FIG. 8 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic flowchart of a driving method of driving the display device shown in FIG. 8 according to an embodiment of the present disclosure.
  • the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor
  • the conduction currents are opposite in direction, so in the embodiments of the present disclosure, the controlled intermediate end of the transistor is referred to as the control pole, the signal input terminal is referred to as the first pole, and the signal output terminal is referred to as the second pole.
  • the transistors employed in the embodiments of the present disclosure are primarily switching transistors.
  • terms such as "first" and "second” are used to distinguish one component (or a portion of the component) from another component (or another portion of the component).
  • FIG. 1 shows a schematic block diagram of a pixel circuit 100 in accordance with an embodiment of the present disclosure.
  • the pixel circuit 100 may include a pixel driving circuit 110 and a light emitting device 120.
  • the pixel driving circuit 110 may be connected to one end of the light emitting device 120 and may be configured to drive the light emitting device 120 to emit light.
  • the other end of the light emitting device 120 can be connected to the second voltage terminal ELVSS.
  • the pixel driving circuit 110 may include a reset circuit 111, a compensation and data writing circuit 112, a driving transistor Td, and an emission control circuit 113.
  • the reset circuit 111 may be coupled to the first control terminal Wth and the control electrode and the second electrode of the driving transistor Td, and may be configured to be based on the first control signal from the first control terminal Wth and the third control terminal EM The three control signals reset the voltage of the gate of the driving transistor Td.
  • the compensation and data writing circuit 112 can be coupled to the data line V1, the first control terminal Wth, the second control terminal G, the control electrode of the driving transistor Td, and the first voltage terminal ELVDD, and can be configured according to the first control signal Receiving a reference signal Vref from the data line V1, receiving a data signal Vdata from the data line V1 according to a second control signal from the second control terminal G, and according to the reference signal Vref, the data signal Vdata, and the first voltage terminal ELVDD
  • the voltage applies a compensation voltage to the gate electrode of the driving transistor Td.
  • the compensation voltage can be used to compensate for the difference in threshold voltage of the driving transistor Td and the voltage drop across the power supply line (ie, the first voltage terminal ELVDD).
  • the control electrode of the driving transistor Td may be coupled to the compensation and data writing circuit 112, the first electrode may be coupled to the first voltage terminal ELVDD, the second electrode may be coupled to the light emission control circuit 113, and may be configured to provide A current corresponding to a voltage between the first pole and the control pole of the driving transistor Td.
  • the light emission control circuit 113 may be coupled to the second electrode of the driving transistor Td, the light emitting device 120, and the third control terminal EM, and may be configured to control the light emitting device 120 according to the third control signal from the third control terminal EM.
  • the current supplied from the driving transistor Td emits light.
  • the compensation and data writing circuit 112 in the pixel driving circuit is capable of compensating for a threshold voltage difference of the driving transistor Td and a voltage drop across the power supply line (ie, the first voltage terminal ELVDD) in the pixel driving circuit, thereby Avoid the difference in brightness of the LEDs on the array substrate.
  • the data signal and the reference signal can be input time-sharing through the data line, so there is no need to additionally set the reference signal line outside the data line, thereby saving the layout space of the display panel.
  • FIG. 2 shows an example circuit diagram of a pixel circuit 100 in accordance with an embodiment of the present disclosure.
  • the reset circuit 111 may include a first transistor T1.
  • the control electrode of the first transistor T1 can be coupled to the first control terminal Wth, the first electrode of the first transistor T1 can be coupled to the second electrode of the driving transistor Td, and the second electrode of the first transistor T1 can be coupled to the driving transistor Td. Control pole.
  • the compensation and data writing circuit 112 may include a second transistor T2, a third transistor T3, a first capacitor C1, and a second capacitor C2.
  • the control electrode of the second transistor T2 can be coupled to the first control terminal W1, the first electrode of the second transistor T2 can be coupled to the data line V1, and the second electrode of the second transistor T2 can be coupled to the first end of the first capacitor C1. And a first end of the second capacitor C2.
  • the control electrode of the third transistor T3 can be coupled to the second control terminal G.
  • the first electrode of the third transistor T3 can be coupled to the data line V1, and the second electrode of the third transistor T3 can be coupled to the first end of the second capacitor C2. .
  • the second end of the first capacitor C1 can be coupled to the control electrode of the driving transistor Td.
  • the second end of the second capacitor C2 can be coupled to the first voltage terminal ELVDD.
  • the illumination control circuit 113 may include a fourth transistor T4.
  • the control electrode of the fourth transistor T4 can be coupled to the third control terminal EM, the first electrode of the fourth transistor T4 can be coupled to the light emitting device 120, and the second electrode of the fourth transistor T4 can be coupled to the second electrode of the driving transistor Td.
  • the light emitting device 120 may include an organic light emitting diode.
  • FIG. 3 shows a timing diagram of signals that can be used for the pixel circuit 100 shown in FIG. 2.
  • the phases I to IV represent the time when one frame of image is scanned.
  • the working process of the pixel circuit 100 shown in FIG. 2 will be described in detail below with reference to the timing chart shown in FIG. In the following description, assuming that all transistors are P-type transistors, the first voltage terminal ELVDD outputs a high level, and the second voltage terminal ELVSS outputs a low level.
  • the above-mentioned high level and low level refer to two preset voltages which are higher and lower with respect to each other, and those skilled in the art can set according to the selected device and the circuit structure adopted, and the present disclosure No restrictions.
  • G1 is used to control the third transistor T3 in the pixel circuit of the first row to input data Vdata1 to the pixel circuit of the first row
  • G2 is used to control the third transistor T3 in the pixel circuit of the second row so as to be second
  • the pixel circuit input data Vdata2, Gn of the row is used to control the third transistor T3 in the pixel circuit of the nth row to input data Vdatan to the pixel circuit of the nth row
  • G1080 is used to control the pixel circuit of the 1080th row.
  • the three transistors T3 are used to input data Vdata1080 to the pixel circuits of the 1080th line.
  • the second control terminal G in FIG. 2 may correspond to one of G1, G2, ..., G1080.
  • DE in FIG. 3 represents a valid data strobe signal from the transmitting end of the data signal for spacing each frame of the data signal.
  • the period in which DE is low indicates a blanking phase at which no data signal is supplied to the pixel circuit.
  • the period in which DE is high indicates a data valid period at which a data signal can be supplied to the pixel circuit.
  • the DE is connected to a panel driving panel that generates a data signal Vdata and a second control signal G for providing a reference for the timing of the data signal Vdata and the second control signal G.
  • the rising edge of DE indicates that the data signal Vdata1 for the pixel circuit of the first row and the second control signal G1 for controlling the pixel circuit of the first row can be started.
  • the start of the data signal Vdata1 for the pixel circuit of the first row and the second control signal G1 of the pixel circuit for controlling the first row may start from the rising edge of DE, and the delay of the rising edge with respect to DE may be at most one scan time. .
  • V1 Vref
  • Wth is at a low level
  • EM is at a low level
  • DE is at a low level.
  • a low level is input to the first control terminal Wth, thereby turning on the first transistor T1 and the second transistor T2.
  • the reference signal Vref is input to the data line V1, thereby starting to apply the reference signal Vref to the first end (ie, point A) of the first capacitor C1.
  • a low level is input to the third control terminal EM, thereby turning on the fourth transistor T4.
  • the voltage from the second voltage terminal ELVSS will be applied to the gate electrode (ie, point B) of the driving transistor Td via the light emitting device 120, the fourth transistor T4, and the first transistor T1.
  • the voltage of the gate electrode of the driving transistor Td can be set to be smaller than the difference between the voltage of the first voltage terminal ELVDD and the absolute value of the threshold voltage of the driving transistor Td.
  • the reference signal Vref is used to maintain the voltage of the first terminal of the first capacitor C1.
  • the first terminal voltage of the first capacitor C1 is constant to help set the voltage of the second terminal of the first capacitor C1, thereby resetting the voltage of the gate of the driving transistor Td.
  • V1 Vref
  • Wth is at a low level
  • EM is at a high level
  • DE is at a low level.
  • a high level is input to the third control terminal EM, thereby turning off the fourth transistor T4. Since the first control terminal Wth continues to remain low, the first transistor T1 and the second transistor T2 continue to be turned on. Since the voltage of the gate electrode of the driving transistor Td is set to be smaller than the difference between the voltage of the first voltage terminal ELVDD and the absolute value of the threshold voltage of the driving transistor Td, the driving transistor Td is turned on. Thus, as shown in FIG. 4, the driving transistor Td and the first transistor T1 can be equivalent to the diode D1 connected in parallel with each other and the parasitic capacitor (ie, gate-source capacitor) C3 of the driving transistor Td.
  • the voltage of the second terminal (ie, point B) of the first capacitor C1 is equal to the voltage of the first voltage terminal ELVDD minus the absolute value of the threshold voltage of the driving transistor Td. Since the data line V1 is input to the reference signal Vref, the voltage of the first end (ie, point A) of the first capacitor C1 is equal to the reference signal Vref.
  • -Vref associated with the voltage of the first voltage terminal ELVDD, the threshold voltage of the driving transistor Td, and the reference signal Vref is generated in the compensation and data writing circuit 112.
  • V1 Vdata
  • Wth is at a high level
  • EM is at a high level
  • DE is at a high level.
  • This stage includes sub-phases of writing data signals Vdata (i.e., Vdata1 ... Vdata1080) to the pixel circuits of each row, respectively.
  • the data signal Vdatan for the row of pixel circuits is input to the data line V1. Simultaneously inputting a low level to the second control terminal G of the row of pixel circuits 100 (Gn for the second control terminal of the nth row of pixels) to turn on the third transistor T3, thereby applying data to the first end of the second capacitor C2. Signal Vdata. A high level is input to the first control terminal Wth, thereby turning off the first transistor T1 and the second transistor T2. Since the first transistor T1 and the second transistor T2 are turned off, the voltage across the first capacitor C1 remains unchanged.
  • a third voltage ELVDD-Vdata associated with the voltage of the first voltage terminal ELVDD and the data signal Vdata is generated in the compensation and data writing circuit 112.
  • Wth is at a high level
  • EM is at a low level
  • DE is at a high level.
  • a high level is input to the second control terminal G, thereby turning off the third transistor T3.
  • a low level is input to the third control terminal EM, thereby turning on the fourth transistor T4.
  • the voltage at point A is VA
  • the voltage at point B is VB.
  • K is the current constant associated with the process parameters and geometry of the drive transistor Td.
  • the light emitting device 120 is driven to emit light based on the voltage of the first voltage terminal ELVDD, the first compensation voltage, and the third voltage. It can be seen from the equation (3) that the driving current I has no relationship with Vth and ELVDD, and therefore the pixel driving circuit of the embodiment of the present disclosure can compensate the threshold voltage Vth of the driving transistor Td and the power supply line (ie, the first voltage terminal ELVDD). The voltage drops to avoid their effects on the brightness of the LED.
  • the data signal Vdata is written to each row of pixel circuits in a time of about half a frame (half the time of scanning one frame of image), and in the fourth stage, in the half frame
  • the light emitting device 120 is driven to emit light for less than a half frame.
  • the drive current flowing through the driving transistor Td can be increased by increasing the voltage range of the data signal Vdata.
  • the drive current flowing through the driving transistor Td can also be increased by reducing the channel length of the driving transistor Td.
  • the reduction in the channel length of the driving transistor Td can reduce the wiring area of the pixel circuit for realizing a higher resolution display panel.
  • the first control signal and the third control signal are controlled by the voltage signal, and the first control signal and the third control signal simultaneously control all the pixels, it is not necessary to design a corresponding scanning circuit for the first control signal and the third control signal. In this way, the scanning circuitry around the display panel is reduced, which facilitates the narrow bezel design of the display panel.
  • the reference signal Vref may be provided through the data line V1 during the blanking phase.
  • the first phase and the second phase described above are in the blanking phase.
  • N-type transistors can also be used to implement the pixel circuit.
  • the elements in the pixel circuit and their connection manner can be appropriately changed.
  • the first voltage terminal ELVDD can output a low level
  • the second voltage terminal ELVSS can output a high level.
  • the high and low states of the levels of the first to third control signals are opposite to the levels of the corresponding signals in FIG.
  • the first control signal in FIG. 3 is at a low level in the first phase and the second phase
  • the first control signal is at a high level in the first phase and the second phase.
  • the transistors in the pixel circuit 100 as shown in FIG. 2 may also be partially P-type transistors and partially N-type transistors.
  • the voltages of the first to third control signals used for the pixel circuits in this alternative embodiment are set according to the specific structure of the pixel circuit.
  • FIG. 7 is a schematic flowchart of a driving method of driving a pixel driving circuit in the pixel circuit 100 shown in FIG. 1 or FIG. 2 according to an embodiment of the present disclosure.
  • step S702 in the first stage, the reference signal Vref is input to the data line V1, the second voltage is input to the first control terminal Wth and the third control terminal EM, thereby controlling the gate of the driving transistor Td.
  • the voltage is reset.
  • step S704 in the second phase, the second voltage is input to the first control terminal Wth, and the first voltage is input to the third control terminal EM, thereby generating a voltage with the first voltage terminal ELVDD in the compensation and data writing circuit 112. And a threshold voltage of the driving transistor Td and a first compensation voltage related to the reference signal Vref.
  • step S706 in the third stage, the data signal Vdata is input to the data line V1, the second voltage is input to the second control terminal G, and the first voltage is input to the first control terminal Wth, thereby being in the compensation and data writing circuit 112.
  • a third voltage associated with the voltage of the first voltage terminal ELVDD and the data signal Vdata is generated.
  • step S708 in the fourth stage, the second voltage is input to the third control terminal EM and the first voltage is input to the second control terminal G, thereby based on the voltage of the first voltage terminal ELVDD, the first compensation voltage, and the third voltage.
  • the light emitting device 120 is driven to emit light.
  • FIG. 8 shows a schematic structural view of a display device 800 according to an embodiment of the present disclosure.
  • Display device 800 can include display substrate 810.
  • the display substrate 810 may include a plurality of gate lines (which are connected to the corresponding second control terminals G1, G2, G3, . . . ) and a plurality of data lines (V1, V2, V3, . . . ) and are arranged in an intersection.
  • a plurality of pixel circuits 100 as shown in FIG. 1 are arranged in an array.
  • the pixel circuits 100 located in the same row are connected to the same gate line, and the pixel circuits 100 in the same column are connected to the same data line.
  • the display device provided by the embodiment of the present disclosure can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a wearable device, or a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a wearable device, or a navigator.
  • FIG. 9 is a schematic flowchart of a driving method of driving the display device 800 shown in FIG. 8 according to an embodiment of the present disclosure.
  • step S902 in the blanking phase, the reference signal Vref is simultaneously input to all of the data lines (V1, V2, V3, ...) for all the pixel circuits 100 to perform FIG. 7 for all the pixel circuits 100. Steps S702 and S704 in the middle.
  • step S904 in the data writing phase, the corresponding data signal Vdata is sequentially input to the corresponding data line for the pixel circuit 100 of each row to perform step S706 in FIG. 7 for the row pixel circuit 100.
  • step S906 in the light emitting phase step S708 in FIG. 7 is performed for all the pixel circuits 100 to simultaneously drive the light emitting device 120 to emit light.
  • the light emitting device 120 is driven to emit light for less than half the time of scanning one frame of image.

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Abstract

本公开的实施例提供一种像素驱动电路。该像素驱动电路包括复位电路、补偿和数据写入电路、驱动晶体管和发光控制电路。复位电路被配置为根据来自第一控制端的第一控制信号和来自第三控制端的第三控制信号，对驱动晶体管的控制极的电压进行复位。补偿和数据写入电路被配置为根据第一控制信号，接收来自数据线的参考信号，根据来自第二控制端的第二控制信号，接收来自数据线的数据信号，并根据参考信号、数据信号和第一电压端的电压，向驱动晶体管的控制极施加补偿电压。驱动晶体管的控制极耦接到补偿和数据写入电路，第一极耦接到第一电压端，第二极耦接到发光控制电路。发光控制电路被配置为根据第三控制信号，控制发光器件发光。

Description

像素驱动电路、像素电路和显示装置及其驱动方法
相关申请的交叉引用
本申请要求于2017年12月15日递交的中国专利申请第201711348064.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及一种有机发光二极管(Organic Light Emitting Diode，简称OLED)像素驱动电路及其驱动方法、像素电路、显示基板、以及显示装置及其驱动方法。
背景技术
在当前OLED阵列基板中，通过改变直接驱动OLED发光的驱动晶体管的栅极电压来控制驱动晶体管的源极与漏极之间电流的大小以实现发光亮度的变化。由于制作工艺的因素，非晶硅薄膜晶体管(薄膜晶体管的英文名称为Thin Film Transistor，简称TFT)、低温多晶硅和氧化物半导体TFT器件的阈值电压Vth存在差异。也就是说不同像素电路中的驱动晶体管的阈值电压Vth存在较大的差异。这就造成了对于相邻的两个像素电路，即使输入的亮度数据相同，但是显示亮度人眼能看出差异，也就是类似于沙漏现象的小范围内亮度不均匀现象。
OLED由电流驱动发光。驱动电流越大，发光的亮度就越亮。如果由同一条电源线ELVDD供电的像素电路中的发光二极管都被点亮的话，那么在电源线ELVDD上电流在开始的时候是最大电流。然后每经过一个像素电路，电流都将减少。这样，在电源线ELVDD上就产生了电压降，也就是说第一行像素电路的供电电压和最后一行像素电路的供电电压相差比较大。这样就造成即使输入相同的亮度数据，显示屏的亮度仍然会逐渐变亮或者变暗。这就是所谓的ELVDD的电压下降(IR drop)。
发明内容
本文中描述的实施例提供了一种像素驱动电路及其驱动方法、显示基板、以及显示装置及其驱动方法。
根据本公开的第一方面，提供了一种像素驱动电路。该像素驱动电路包括复位电路、补偿和数据写入电路、驱动晶体管和发光控制电路。复位电路耦接到第一控制端和驱动晶体管的控制极和第二极，并被配置为根据来自第一控制端的第一控制信号和来自第三控制端的第三控制信号，对驱动晶体管的控制极的电压进行复位。补偿和数据写入电路耦接到数据线、第一控制端、第二控制端、驱动晶体管的控制极和第一电压端，并被配置为根据第一控制信号，接收来自数据线的参考信号，根据来自第二控制端的第二控制信号，接收来自数据线的数据信号，并根据参考信号、数据信号和第一电压端的电压，向驱动晶体管的控制极施加补偿电压。驱动晶体管的控制极耦接到补偿和数据写入电路，第一极耦接到第一电压端，第二极耦接到发光控制电路。发光控制电路耦接到发光器件和第三控制端，并被配置为根据第三控制信号，控制发光器件发光。
在本公开的实施例中，复位电路包括第一晶体管。第一晶体管的控制极耦接第一控制端，第一晶体管的第一极耦接驱动晶体管的第二极，第一晶体管的第二极耦接驱动晶体管的控制极。
在本公开的实施例中，补偿和数据写入电路包括第二晶体管、第三晶体管、第一电容器和第二电容器。第二晶体管的控制极耦接第一控制端，第二晶体管的第一极耦接数据线，第二晶体管的第二极耦接第一电容器的第一端和第二电容器的第一端。第三晶体管的控制极耦接第二控制端，第三晶体管的第一极耦接数据线，第三晶体管的第二极耦接第二电容器的第一端。第一电容器的第二端耦接驱动晶体管的控制极。第二电容器的第二端耦接第一电压端。
在本公开的实施例中，发光控制电路包括第四晶体管。第四晶体管的控制极耦接第三控制端，第四晶体管的第一极耦接发光器件，第四晶体管的第二极耦接驱动晶体管的第二极。
在本公开的实施例中，在消隐阶段(Blanking Interval)，通过数据线提供参考信号。
在本公开的实施例中，驱动晶体管的控制极的电压被复位至小于第一电压端的电压与驱动晶体管的阈值电压的绝对值的差值。
根据本公开的第二方面，提供了一种像素驱动电路。该像素驱动电路包括驱动晶体管、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容器和第二电容器。驱动晶体管的控制极耦接第一晶体管的第二极和第一电容器的第二端，驱动晶体管的第一极耦接第一电压端和第二电容器的第二端，驱动晶体管的第二极耦接第一晶体管的第一极和第四晶体管的第二极。第一晶体管的控制极耦接第一控制端。第二晶体管的控制极耦接第一控制端，第二晶体管的第一极耦接数据线，第二晶体管的第二极耦接第一电容器的第一端和第二电容器的第一端。第三晶体管的控制极耦接第二控制端，第三晶体管的第一极耦接数据线，第三晶体管的第二极耦接第二电容器的第一端。第四晶体管的控制极耦接第三控制端，第四晶体管的第一极耦接发光器件。
在本公开的实施例中，数据线被配置为在不同的时段接收参考信号和数据信号。
在本公开的实施例中，发光器件发光时流过驱动晶体管的电流被表示为：
Figure PCTCN2018112006-appb-000001
其中，I表示流过驱动晶体管的电流，K表示与驱动晶体管有关的电流常数，C1表示第一电容器的电容值，C2表示第二电容器的电容值，C3表示驱动晶体管的寄生电容值，Vdata表示来自数据线的数据信号的电压值，Vref表示来自数据线的参考信号的电压值。
在本公开的实施例中，驱动晶体管、第一晶体管、第二晶体管、第三晶体管和第四晶体管为P型晶体管。
根据本公开的第三方面，提供了一种像素电路，包括如上所述的根据 本公开的第一方面或第二方面的像素驱动电路和发光器件。像素驱动电路与发光器件的一端连接，并被配置为驱动发光器件发光。发光器件的另一端连接到第二电压端。
在本公开的实施例中，发光器件包括有机发光二极管。
根据本公开的第四方面，提供了一种显示基板，其包括多条栅线和多条数据线，以及被排列成阵列状的多个如上所述的根据本公开的第三方面的像素电路。在该显示基板中，各条栅线连接到相应的像素电路的第二控制端。
根据本公开的第五方面，提供了一种显示装置，其包括如上所述的根据本公开的第四方面的显示基板。
根据本公开的第六方面，提供了一种用于驱动如上所述的根据本公开的第二方面的像素驱动电路的驱动方法。在该驱动方法中，向数据线输入参考信号，在补偿和数据写入电路中产生与第一电压端的电压、驱动晶体管的阈值电压及参考信号相关的第一补偿电压。向数据线输入数据信号，向第二控制端输入第二电压并且向第一控制端输入第一电压，以在补偿和数据写入电路中产生与第一电压端的电压及数据信号相关的第三电压。向第三控制端输入第二电压并且向第二控制端输入第一电压，从而基于第一电压端的电压、第一补偿电压和第三电压来驱动发光器件发光。
在本公开的实施例中，在向数据线输入参考信号，在补偿和数据写入电路中产生第一补偿电压的步骤中，向数据线输入参考信号、向第一控制端和第三控制端输入第二电压，以对驱动晶体管的控制极的电压进行复位。接着，向第一控制端输入第二电压，向第三控制端输入第一电压，以在补偿和数据写入电路中产生第一补偿电压。
在本公开的实施例中，在消隐阶段，向数据线输入参考信号，并在补偿和数据写入电路中产生第一补偿电压。
在本公开的实施例中，驱动晶体管的控制极的电压被复位至小于第一电压端的电压与驱动晶体管的阈值电压的绝对值的差值。
根据本公开的第七方面，提供了一种用于驱动如上所述的根据本公开 的第五方面的显示装置的驱动方法。在该驱动方法中，同时向所有行的像素电路的数据线输入参考信号。然后，依次向每一行的像素电路的数据线输入相应的数据信号。接着，同时驱动所有行的像素电路的发光器件发光。其中，发光器件被驱动以发光的时间小于扫描一帧图像的时间的一半。
在本公开的实施例中，扫描一帧图像的时间包括三个不同的阶段：消隐阶段、数据写入阶段和发光阶段。在消隐阶段，同时向所有行的像素电路的数据线输入参考信号。在数据写入阶段，依次向每一行的像素电路的数据线输入相应的数据信号。在发光阶段，同时驱动所有行的像素电路的发光器件发光。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是根据本公开的实施例的像素电路的示意性框图；
图2是根据本公开的实施例的像素电路的示例电路图；
图3是用于图2所示的像素电路的各信号的时序图；
图4是如图2所示的像素电路中的像素驱动电路在第二阶段的等效工作电路图；
图5是如图2所示的像素电路中的像素驱动电路在第三阶段的等效工作电路图；
图6是如图2所示的像素电路在第四阶段的等效工作电路图；
图7是根据本公开的实施例的驱动如图1或图2所示的像素电路中的像素驱动电路的驱动方法的示意性流程图；
图8是根据本公开的实施例的显示装置的示意性框图；
图9是根据本公开的实施例的驱动如图8所示的显示装置的驱动方法的示意性流程图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指这些部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
图1示出根据本公开的实施例的像素电路100的示意性框图。如图1所示，像素电路100可包括像素驱动电路110和发光器件120。像素驱动电路110可与发光器件120的一端连接，并可被配置为驱动发光器件120发光。发光器件120的另一端可连接到第二电压端ELVSS。
像素驱动电路110可包括复位电路111、补偿和数据写入电路112、驱动晶体管Td和发光控制电路113。复位电路111可耦接到第一控制端Wth和驱动晶体管Td的控制极和第二极，并可被配置为根据来自第一控制端Wth的第一控制信号和来自第三控制端EM的第三控制信号，对驱动晶体 管Td的控制极的电压进行复位。
补偿和数据写入电路112可耦接到数据线V1、第一控制端Wth、第二控制端G、驱动晶体管Td的控制极和第一电压端ELVDD，并可被配置为根据第一控制信号，接收来自数据线V1的参考信号Vref，根据来自第二控制端G的第二控制信号，接收来自数据线V1的数据信号Vdata，并根据参考信号Vref、数据信号Vdata和第一电压端ELVDD的电压，向驱动晶体管Td的控制极施加补偿电压。补偿电压可用于补偿驱动晶体管Td的阈值电压差异和电源线(即，第一电压端ELVDD)上的电压下降。
驱动晶体管Td的控制极可耦接到补偿和数据写入电路112，第一极可耦接到第一电压端ELVDD，第二极可耦接到发光控制电路113，并可被配置为提供与驱动晶体管Td的第一极和控制极之间的电压对应的电流。
发光控制电路113可耦接到驱动晶体管Td的第二极、发光器件120和第三控制端EM，并可被配置为根据来自第三控制端EM的第三控制信号，控制发光器件120根据由驱动晶体管Td提供的电流发光。
根据本公开实施例的像素驱动电路中的补偿和数据写入电路112能够补偿像素驱动电路中的驱动晶体管Td的阈值电压差异和电源线(即，第一电压端ELVDD)上的电压下降，从而避免阵列基板上的发光二极管的亮度差异。此外，通过数据线可以分时输入数据信号和参考信号，因此不需要在数据线之外再额外设置参考信号线，从而节省了显示面板的布局空间。
图2示出根据本公开的实施例的像素电路100的示例电路图。如图2所示，复位电路111可包括第一晶体管T1。第一晶体管T1的控制极可耦接第一控制端Wth，第一晶体管T1的第一极可耦接驱动晶体管Td的第二极，第一晶体管T1的第二极可耦接驱动晶体管Td的控制极。
补偿和数据写入电路112可包括第二晶体管T2、第三晶体管T3、第一电容器C1和第二电容器C2。第二晶体管T2的控制极可耦接第一控制端Wth，第二晶体管T2的第一极可耦接数据线V1，第二晶体管T2的第二极可耦接第一电容器C1的第一端和第二电容器C2的第一端。第三晶体管T3的控制极可耦接第二控制端G，第三晶体管T3的第一极可耦接数据 线V1，第三晶体管T3的第二极可耦接第二电容器C2的第一端。第一电容器C1的第二端可耦接驱动晶体管Td的控制极。第二电容器C2的第二端可耦接第一电压端ELVDD。
发光控制电路113可包括第四晶体管T4。第四晶体管T4的控制极可耦接第三控制端EM，第四晶体管T4的第一极可耦接发光器件120，第四晶体管T4的第二极可耦接驱动晶体管Td的第二极。
发光器件120可包括有机发光二极管。
图3示出可用于图2所示的像素电路100的各信号的时序图。其中，阶段Ⅰ至Ⅳ表示扫描一帧图像的时间。下面结合图3所示的时序图，对如图2所示的像素电路100的工作过程进行详细描述。在以下的描述中，假定所有晶体管都是P型晶体管，第一电压端ELVDD输出高电平，第二电压端ELVSS输出低电平。上述高电平与低电平是指相对于彼此而言较高和较低的两个预设电压，本领域技术人员可以根据所选用的器件及所采用的电路结构进行设置，本公开对此不做限制。G1用于控制第一行的像素电路中的第三晶体管T3，以便向第一行的像素电路输入数据Vdata1，G2用于控制第二行的像素电路中的第三晶体管T3，以便向第二行的像素电路输入数据Vdata2，Gn用于控制第n行的像素电路中的第三晶体管T3，以便向第n行的像素电路输入数据Vdatan，G1080用于控制第1080行的像素电路中的第三晶体管T3，以便向第1080行的像素电路输入数据Vdata1080。图2中的第二控制端G可对应于G1、G2、……、G1080中的一个。在这里，1080表示像素电路的总行数，其仅是一个示例，并不是限制性的。此外，图3中的DE表示有效数据选通信号，其来自数据信号的发送端，用于将每一帧数据信号间隔开。DE为低电平的期间表示消隐阶段，在该阶段不向像素电路提供数据信号。DE为高电平的期间表示数据有效期间，在该阶段可向像素电路提供数据信号。DE连接到产生数据信号Vdata和第二控制信号G的屏驱动板，用于为数据信号Vdata和第二控制信号G的时序提供参考。例如DE的上升沿指示能够开始输出用于第一行的像素电路的数据信号Vdata1和控制第一行的像素电路的第二控制信号G1。用于第一行的像 素电路的数据信号Vdata1和控制第一行的像素电路的第二控制信号G1的开始可以从DE的上升沿开始，其相对于DE的上升沿的延迟最多为一行扫描时间。
在第一阶段Ⅰ，V1＝Vref，Wth处于低电平，EM处于低电平，DE处于低电平。
向第一控制端Wth输入低电平，从而打开第一晶体管T1和第二晶体管T2。向数据线V1输入参考信号Vref，从而开始向第一电容器C1的第一端(即A点)施加参考信号Vref。向第三控制端EM输入低电平，从而打开第四晶体管T4。这样，来自第二电压端ELVSS的电压将经由发光器件120、第四晶体管T4和第一晶体管T1被施加到驱动晶体管Td的控制极(即B点)。通过设置第二电压端ELVSS的电压，可以使得驱动晶体管Td的控制极的电压被设置为小于第一电压端ELVDD的电压与驱动晶体管Td的阈值电压的绝对值的差值。在本阶段，参考信号Vref用于维持第一电容器C1的第一端的电压。这样，第一电容器C1的第一端电压恒定有助于设定第一电容器C1的第二端的电压，从而对驱动晶体管Td的控制极的电压进行复位。
在第二阶段Ⅱ(等效工作电路如图4所示)，V1＝Vref，Wth处于低电平，EM处于高电平，DE处于低电平。
向第三控制端EM输入高电平，从而关闭第四晶体管T4。由于第一控制端Wth继续保持低电平，第一晶体管T1和第二晶体管T2继续打开。由于驱动晶体管Td的控制极的电压被设置为小于第一电压端ELVDD的电压与驱动晶体管Td的阈值电压的绝对值的差值，驱动晶体管Td打开。这样，如图4所示，驱动晶体管Td和第一晶体管T1能够等效为相互并联的二极管D1和驱动晶体管Td的寄生电容器(即，栅源电容器)C3。因此，第一电容器C1的第二端(即B点)的电压等于第一电压端ELVDD的电压减去驱动晶体管Td的阈值电压的绝对值。由于数据线V1被输入参考信号Vref，第一电容器C1的第一端(即A点)的电压等于参考信号Vref。这样，在第一电容器C1上存储的电荷量为Q1＝C1×(ELVDD-|Vth|-Vref)， 在第二电容器C2上存储的电荷量为Q2＝C2×(ELVDD-Vref)，在寄生电容C3上存储的电荷量为Q3＝C3×|Vth|。因此，B点的电荷总量为QB＝Q1-Q3＝C1×(ELVDD-|Vth|-Vref)-C3×|Vth|。
在本阶段，在补偿和数据写入电路112中产生与第一电压端ELVDD的电压、驱动晶体管Td的阈值电压及参考信号Vref相关的第一补偿电压ELVDD-|Vth|-Vref。
在第三阶段Ⅲ(即，数据写入阶段，等效工作电路如图5所示)，V1＝Vdata，Wth处于高电平，EM处于高电平，DE处于高电平。
本阶段包括分别向每一行的像素电路写入数据信号Vdata(即，Vdata1……Vdata1080)的子阶段。
例如，对于第n行的像素电路(即，在第n子阶段)，向数据线V1输入用于该行像素电路的数据信号Vdatan。同时向该行像素电路100的第二控制端G(对于第n行像素的第二控制端为Gn)输入低电平以打开第三晶体管T3，从而向第二电容器C2的第一端施加数据信号Vdata。向第一控制端Wth输入高电平，从而关闭第一晶体管T1和第二晶体管T2。由于第一晶体管T1和第二晶体管T2关闭，第一电容器C1两端的电压保持不变。这样，在第一电容器C1上存储的电荷量保持为Q1＝C1×(ELVDD-|Vth|-Vref)，在第二电容器C2上存储的电荷量为Q2＝C2×(ELVDD-Vdata)。因此，B点的电荷总量仍然为QB＝Q1-Q3＝C1×(ELVDD-|Vth|-Vref)-C3×|Vth|，而A点的电荷总量为QA＝-Q1-Q2＝-C1×(ELVDD-|Vth|-Vref)-C2×(ELVDD-Vdata)。
在本阶段，在补偿和数据写入电路112中产生与第一电压端ELVDD的电压及数据信号Vdata相关的第三电压ELVDD-Vdata。
在第四阶段Ⅳ(即，发光阶段，等效工作电路如图6所示)，Wth处于高电平，EM处于低电平，DE处于高电平。
向第二控制端G输入高电平，从而关闭第三晶体管T3。向第三控制端EM输入低电平，从而打开第四晶体管T4。此时，假设A点的电压为VA，B点的电压为VB。则A点的电荷总量为Q’A＝-C1×(VB-VA)-C2× (ELVDD-VA),B点的电荷总量为Q’B＝C1×(VB-VA)-C3×(ELVDD-VB)。由于A点和B点的电荷量分别相对于上一阶段保持不变，即Q’A＝QA，Q’B＝QB，从而可以计算出B点的电压：
Figure PCTCN2018112006-appb-000002
将式(1)代入下列计算驱动电流I的式(2)中，可以得到式(3)。
I＝K(V GS-Vth) 2    (2)
Figure PCTCN2018112006-appb-000003
在式(2)和式(3)中，K为与驱动晶体管Td的工艺参数和几何尺寸有关的电流常数。
在本阶段，基于第一电压端ELVDD的电压、第一补偿电压和第三电压来驱动发光器件120发光。由式(3)可见，驱动电流I与Vth和ELVDD都没有关系，因此采用本公开实施例的像素驱动电路可以补偿驱动晶体管Td的阈值电压Vth和电源线(即，第一电压端ELVDD)上的电压下降，从而避免它们对发光二极管的亮度造成的影响。
此外，在本公开的实施例中，在第三阶段，在大约半帧(扫描一帧图像的时间的一半)的时间内向每一行像素电路写入数据信号Vdata，在第四阶段，在半帧或小于半帧的时间内驱动发光器件120发光。为了与在一帧时间内驱动发光器件发光的显示面板保持相同的亮度，需要增加流过驱动晶体管Td的驱动电流。可以通过提高数据信号Vdata的电压范围来增加流过驱动晶体管Td的驱动电流。例如，对于在一帧时间内驱动发光器件发光的显示面板来说，通过提高数据信号Vdata电压的驱动动态范围，可以降低驱动IC输出电压的精度要求。此外，在替代实施例中，在Vdata的精度满足要求的情况下，还可以通过减少驱动晶体管Td的沟道长度来增加流过驱动晶体管Td的驱动电流。驱动晶体管Td的沟道长度的减少能够减少像素电路的布线面积，以用于实现分辨率更高的显示面板。
由于第一控制信号和第三控制信号采用电压信号控制，并且第一控制 信号和第三控制信号同时控制所有像素，因此无需为第一控制信号和第三控制信号设计相应的扫描电路。这样，减少了显示面板周边的扫描电路，这有利于显示面板的窄边框设计。
在一个示例中，可以在消隐阶段，通过数据线V1提供参考信号Vref。换句话说，上述第一阶段和第二阶段处于消隐阶段。这样，有充足的时间可以将向第一电容器C1充电的时间设定为一个至几十个像素行扫描时间。这可以提高第一电容器C1的充电率，从而提高能够补偿驱动晶体管Td的阈值电压Vth的精度。
本领域的技术人员可知道，在一个实施例中，也可以都采用N型晶体管来实现像素电路。在该实施例中，可适当改变像素电路中的元件及其连接方式。第一电压端ELVDD可以输出低电平，第二电压端ELVSS可以输出高电平。第一至第三控制信号的电平的高低状态与图3中的相应信号的电平相反。例如，在图3中的第一控制信号在第一阶段和第二阶段处于低电平，而在本实施例中第一控制信号在第一阶段和第二阶段处于高电平。
在本实施例的另一替代实施例中，如图2所示的像素电路100中的晶体管也可以部分是P型晶体管，部分是N型晶体管。用于该替代实施例中的像素电路的第一至第三控制信号的电压根据像素电路的具体结构来设置。
图7是根据本公开的实施例的驱动如图1或图2所示的像素电路100中的像素驱动电路的驱动方法的示意性流程图。
在该驱动方法中，在步骤S702，在第一阶段，向数据线V1输入参考信号Vref、向第一控制端Wth和第三控制端EM输入第二电压，从而对驱动晶体管Td的控制极的电压进行复位。
在步骤S704，在第二阶段，向第一控制端Wth输入第二电压，向第三控制端EM输入第一电压，从而在补偿和数据写入电路112中产生与第一电压端ELVDD的电压、驱动晶体管Td的阈值电压及参考信号Vref相关的第一补偿电压。
在步骤S706，在第三阶段，向数据线V1输入数据信号Vdata，向第 二控制端G输入第二电压并且向第一控制端Wth输入第一电压，从而在补偿和数据写入电路112中产生与第一电压端ELVDD的电压及数据信号Vdata相关的第三电压。
在步骤S708，在第四阶段，向第三控制端EM输入第二电压并且向第二控制端G输入第一电压，从而基于第一电压端ELVDD的电压、第一补偿电压和第三电压来驱动发光器件120发光。
图8示出根据本公开的实施例的显示装置800的结构示意图。显示装置800可包括显示基板810。显示基板810可包括交叉设置的多条栅线(其连接到相应的第二控制端G1、G2、G3、……)和多条数据线(V1、V2、V3、……)，以及被排列成阵列状的多个如图1所示的像素电路100。位于同一行的像素电路100连接到同一个栅线，位于同一列的像素电路100连接到同一个数据线。本公开实施例提供的显示装置可以应用于任何具有显示功能的产品，例如，电子纸、移动电话、平板电脑、电视机、笔记本电脑、数码相框、可穿戴设备或导航仪等。
图9是根据本公开的实施例的驱动如图8所示的显示装置800的驱动方法的示意性流程图。
在该驱动方法中，在步骤S902，在消隐阶段，针对所有像素电路100，同时向所有数据线(V1、V2、V3、……)输入参考信号Vref，以针对所有像素电路100执行图7中的步骤S702和S704。
在步骤S904，在数据写入阶段，依次针对每一行的像素电路100，向相应的数据线输入相应的数据信号Vdata，以针对该行像素电路100执行图7中的步骤S706。
在步骤S906，在发光阶段，针对所有像素电路100，执行图7中的步骤S708以同时驱动发光器件120发光。发光器件120被驱动以发光的时间小于扫描一帧图像的时间的一半。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不 是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
以上对本公开的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。

Claims (19)

  1. 一种像素驱动电路，包括：复位电路、补偿和数据写入电路、驱动晶体管和发光控制电路，
    其中，所述复位电路耦接到第一控制端和所述驱动晶体管的控制极和第二极，并被配置为根据来自所述第一控制端的第一控制信号和来自第三控制端的第三控制信号，对所述驱动晶体管的控制极的电压进行复位；
    所述补偿和数据写入电路耦接到数据线、所述第一控制端、第二控制端、所述驱动晶体管的控制极和第一电压端，并被配置为根据所述第一控制信号，接收来自所述数据线的参考信号，根据来自第二控制端的第二控制信号，接收来自所述数据线的数据信号，并根据所述参考信号、所述数据信号和所述第一电压端的电压，向所述驱动晶体管的控制极施加补偿电压；
    所述驱动晶体管的控制极耦接到所述补偿和数据写入电路，第一极耦接到第一电压端，第二极耦接到所述发光控制电路；
    所述发光控制电路耦接到发光器件和第三控制端，并被配置为根据所述第三控制信号，控制所述发光器件发光。
  2. 根据权利要求1所述的像素驱动电路，其中，所述复位电路包括第一晶体管，
    其中，所述第一晶体管的控制极耦接所述第一控制端，所述第一晶体管的第一极耦接所述驱动晶体管的第二极，所述第一晶体管的第二极耦接所述驱动晶体管的控制极。
  3. 根据权利要求1或2所述的像素驱动电路，其中，所述补偿和数据写入电路包括第二晶体管、第三晶体管、第一电容器和第二电容器，
    其中，所述第二晶体管的控制极耦接所述第一控制端，所述第二晶体管的第一极耦接所述数据线，所述第二晶体管的第二极耦接所述第一电容器的第一端和所述第二电容器的第一端；
    所述第三晶体管的控制极耦接所述第二控制端，所述第三晶体管的第一极耦接所述数据线，所述第三晶体管的第二极耦接所述第二电容器的第 一端；
    所述第一电容器的第二端耦接所述驱动晶体管的控制极；以及
    所述第二电容器的第二端耦接所述第一电压端。
  4. 根据权利要求1至3中任一项所述的像素驱动电路，其中，所述发光控制电路包括第四晶体管，
    其中，所述第四晶体管的控制极耦接所述第三控制端，所述第四晶体管的第一极耦接所述发光器件，所述第四晶体管的第二极耦接所述驱动晶体管的第二极。
  5. 根据权利要求1至4中任一项所述的像素驱动电路，其中，在消隐阶段，通过所述数据线提供参考信号。
  6. 一种像素驱动电路，包括：驱动晶体管、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容器和第二电容器，
    其中，所述驱动晶体管的控制极耦接第一晶体管的第二极和第一电容器的第二端，所述驱动晶体管的第一极耦接第一电压端和第二电容器的第二端，所述驱动晶体管的第二极耦接第一晶体管的第一极和第四晶体管的第二极；
    所述第一晶体管的控制极耦接第一控制端；
    所述第二晶体管的控制极耦接所述第一控制端，所述第二晶体管的第一极耦接数据线，所述第二晶体管的第二极耦接所述第一电容器的第一端和所述第二电容器的第一端；
    第三晶体管的控制极耦接第二控制端，所述第三晶体管的第一极耦接所述数据线，所述第三晶体管的第二极耦接所述第二电容器的第一端；以及
    第四晶体管的控制极耦接第三控制端，第四晶体管的第一极耦接发光器件。
  7. 根据权利要求6所述的像素驱动电路，其中，所述数据线被配置为在不同的时段接收参考信号和数据信号。
  8. 根据权利要求6或7所述的像素驱动电路，其中，所述发光器件发 光时流过所述驱动晶体管的电流被表示为：
    Figure PCTCN2018112006-appb-100001
    其中，I表示流过所述驱动晶体管的电流，K表示与所述驱动晶体管有关的电流常数，C1表示所述第一电容器的电容值，C2表示所述第二电容器的电容值，C3表示所述驱动晶体管的寄生电容值，Vdata表示来自所述数据线的数据信号的电压值，Vref表示来自所述数据线的参考信号的电压值。
  9. 根据权利要求6所述的像素驱动电路，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管为P型晶体管。
  10. 一种像素电路，包括权利要求1-9中任一项所述的像素驱动电路和发光器件，其中，所述像素驱动电路与所述发光器件的一端连接，并被配置为驱动所述发光器件发光，所述发光器件的另一端连接到第二电压端。
  11. 根据权利要求10所述的像素电路，其中，所述发光器件包括有机发光二极管。
  12. 一种显示基板，包括：
    多条栅线和多条数据线；以及
    被排列成阵列状的多个根据权利要求10或11所述的像素电路，
    其中，各条栅线连接到相应的像素电路的第二控制端。
  13. 一种显示装置，包括根据权利要求12所述的显示基板。
  14. 一种用于驱动根据权利要求1-9中任一项所述的像素驱动电路的驱动方法，包括：
    向数据线输入参考信号，在所述补偿和数据写入电路中产生与所述第一电压端的电压、所述驱动晶体管的阈值电压及所述参考信号相关的第一补偿电压；
    向所述数据线输入数据信号，向第二控制端输入第二电压并且向第一控制端输入第一电压，以在所述补偿和数据写入电路中产生与所述第一电 压端的电压及所述数据信号相关的第三电压；以及
    向第三控制端输入第二电压并且向第二控制端输入第一电压，从而基于所述第一电压端的电压、所述第一补偿电压和所述第三电压来驱动所述发光器件发光。
  15. 根据权利要求14所述的驱动方法，其中，向数据线输入参考信号，在所述补偿和数据写入电路中产生所述第一补偿电压包括：
    向数据线输入参考信号、向第一控制端和第三控制端输入第二电压，以对所述驱动晶体管的控制极的电压进行复位；以及
    向第一控制端输入第二电压，向第三控制端输入第一电压，以在所述补偿和数据写入电路中产生所述第一补偿电压。
  16. 根据权利要求15所述的驱动方法，其中，在消隐阶段，向数据线输入参考信号，并在所述补偿和数据写入电路中产生所述第一补偿电压。
  17. 根据权利要求14-16中任一项所述的驱动方法，其中，所述驱动晶体管的控制极的电压被复位至小于所述第一电压端的电压与所述驱动晶体管的阈值电压的绝对值的差值。
  18. 一种用于驱动根据权利要求13所述的显示装置的驱动方法，包括：
    同时向所有行的像素电路的数据线输入参考信号；
    依次向每一行的像素电路的数据线输入相应的数据信号；以及
    同时驱动所有行的像素电路的发光器件发光，
    其中，所述发光器件被驱动以发光的时间小于扫描一帧图像的时间的一半。
  19. 根据权利要求18所述的驱动方法，其中，所述扫描一帧图像的时间包括三个不同的阶段：消隐阶段、数据写入阶段和发光阶段；
    其中，在所述消隐阶段，同时向所有行的像素电路的数据线输入参考信号；在所述数据写入阶段，依次向每一行的像素电路的数据线输入相应的数据信号；在所述发光阶段，同时驱动所有行的像素电路的发光器件发光。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112309332B (zh) * 2019-07-31 2022-01-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板和显示面板
EP4068257B1 (en) * 2019-11-29 2024-05-22 BOE Technology Group Co., Ltd. Pixel driving circuit, driving method therefor and display device
CN111402807B (zh) * 2020-04-29 2021-10-26 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及其驱动方法
CN115482769A (zh) * 2021-05-31 2022-12-16 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示基板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070279337A1 (en) * 2006-06-01 2007-12-06 Lg Philips Lcd Co., Ltd. Organic light-emitting diode display device and driving method thereof
CN103927975A (zh) * 2013-12-30 2014-07-16 上海天马微电子有限公司 一种有机发光显示器的像素补偿电路及方法
CN104361857A (zh) * 2014-11-04 2015-02-18 深圳市华星光电技术有限公司 有机发光显示器像素驱动电路
CN105575331A (zh) * 2015-11-25 2016-05-11 友达光电股份有限公司 像素电压补偿电路
CN108447446A (zh) * 2018-04-10 2018-08-24 京东方科技集团股份有限公司 像素电路、显示面板及其驱动方法
CN108665852A (zh) * 2018-07-23 2018-10-16 京东方科技集团股份有限公司 像素电路、驱动方法、有机发光显示面板及显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560479B1 (ko) 2004-03-10 2006-03-13 삼성에스디아이 주식회사 발광 표시 장치 및 그 표시 패널과 구동 방법
KR100698699B1 (ko) * 2005-08-01 2007-03-23 삼성에스디아이 주식회사 데이터 구동회로와 이를 이용한 발광 표시장치 및 그의구동방법
EP1938300A2 (en) * 2005-10-12 2008-07-02 Koninklijke Philips Electronics N.V. Transistor control circuits and control methods, and active matrix display devices using the same
KR100833757B1 (ko) * 2007-01-15 2008-05-29 삼성에스디아이 주식회사 유기 전계 발광 표시 장치 및 영상 보정 방법
JP2008292786A (ja) 2007-05-25 2008-12-04 Sony Corp 表示装置、表示装置の駆動方法および電子機器
KR101645404B1 (ko) 2010-07-06 2016-08-04 삼성디스플레이 주식회사 유기 전계발광 표시장치
CN103839520B (zh) * 2014-02-28 2017-01-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
US9778800B2 (en) * 2014-06-27 2017-10-03 Boe Technology Group Co., Ltd. Pixel circuit, display panel and display apparatus
KR102150039B1 (ko) * 2014-07-14 2020-09-01 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
CN204029330U (zh) * 2014-07-22 2014-12-17 京东方科技集团股份有限公司 像素驱动电路、阵列基板及显示装置
CN104809989A (zh) * 2015-05-22 2015-07-29 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN106409227A (zh) * 2016-12-02 2017-02-15 武汉华星光电技术有限公司 像素电路及其驱动方法和有机发光显示器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070279337A1 (en) * 2006-06-01 2007-12-06 Lg Philips Lcd Co., Ltd. Organic light-emitting diode display device and driving method thereof
CN103927975A (zh) * 2013-12-30 2014-07-16 上海天马微电子有限公司 一种有机发光显示器的像素补偿电路及方法
CN104361857A (zh) * 2014-11-04 2015-02-18 深圳市华星光电技术有限公司 有机发光显示器像素驱动电路
CN105575331A (zh) * 2015-11-25 2016-05-11 友达光电股份有限公司 像素电压补偿电路
CN108447446A (zh) * 2018-04-10 2018-08-24 京东方科技集团股份有限公司 像素电路、显示面板及其驱动方法
CN108665852A (zh) * 2018-07-23 2018-10-16 京东方科技集团股份有限公司 像素电路、驱动方法、有机发光显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3726518A4 *

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